Heteroepitaxial wafer and method for manufacturing same

Abstract

The present invention provides a heteroepitaxial wafer which is obtained by epitaxially growing a silicon germanium layer on a silicon single crystal substrate and epitaxially growing a silicon layer on the silicon germanium layer, and which is characterized in that the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer satisfies [film thickness (nm)] < 1.4 × 107 × [Ge (%)]-4.5. As a result, provided is a heteroepitaxial wafer free of trapped metallic impurities.

Description

Heteroepitaxial wafer and manufacturing method thereof

[0001] The present invention relates to a heteroepitaxial wafer and a method for producing the same.

[0002] Silicon wafers fabricated by the Czochralski (CZ) method are primarily used as substrates for fabricating semiconductor integrated circuits. In particular, cutting-edge logic devices utilize a Gate All Around (GAA) structure, which is a currently used FinFET structure with a channel layer surrounded by electrodes on four sides, to suppress short-channel effects. This structure utilizes a silicon germanium epitaxial wafer (hereinafter sometimes referred to as a heteroepitaxial wafer) in which several pairs of silicon germanium (SiGe) epitaxial layers (hereinafter simply referred to as silicon germanium layers) and silicon epitaxial layers (hereinafter simply referred to as silicon layers) are stacked on a silicon single crystal substrate (sometimes referred to as a silicon wafer or simply a silicon substrate).

[0003] Incidentally, a wafer such as this, in which a layer of a different material (for example, a silicon germanium layer) is epitaxially grown on a substrate (for example, a silicon single crystal substrate), is generally called a heteroepitaxial wafer.

[0004] At this time, the difference in etching rate between the silicon germanium layer and the silicon layer is utilized to etch away the silicon germanium layer, thereby using the silicon layer as a channel layer. Therefore, it is necessary to increase the difference in etching rate between the silicon germanium layer and the silicon layer, and to achieve this, it is effective to increase the germanium concentration in the silicon germanium layer. In this case, the thickness of the silicon germanium layer needs to be the same as the thickness of the electrode layer surrounding the channel portion in the GAA structure, and an optimal thickness is designed for each device. Specifically, the silicon germanium layer is formed by forming an insulating film and electrode metal around the silicon layer that will become the channel layer after etching. Therefore, the thickness of the silicon germanium layer needs to be approximately the same as the thickness of the electrode metal layer.

[0005] On the other hand, because the covalent bond radius of germanium is larger than that of silicon, the lattice constant of the silicon germanium layer is larger than that of the silicon layer or silicon substrate. This causes a lattice mismatch between the silicon germanium layer and the silicon layer or silicon substrate. This lattice mismatch becomes larger as the germanium concentration increases. It is also known that the lattice mismatch introduces misfit dislocations (hereinafter sometimes simply referred to as dislocations) at the interface between the silicon germanium layer and the silicon layer or silicon substrate.

[0006] When the germanium concentration in the silicon germanium layer is constant, dislocations occur above a certain silicon germanium layer thickness. This thickness is called the critical film thickness for dislocation generation (hereinafter referred to as the first critical film thickness). Figure 1 of Patent Document 1 shows the first critical film thickness at each film formation temperature, and the lower the film formation temperature, the thicker the first critical film thickness becomes.

[0007] However, even in silicon germanium wafers formed to a thickness equal to or less than the first critical thickness, dislocations may occur when the wafer is subsequently subjected to a heat treatment for the device. These dislocations act as trapping sites for metal impurities (hereinafter sometimes referred to as gettering sites), and if unexpected contamination occurs during the device process, they can cause poor device characteristics.

[0008] Furthermore, FIG. 2 of Patent Document 2 shows that the first critical film thickness at which misfit dislocations occur at a heterointerface varies depending on the plane orientation. In this case as well, dislocations may occur when a silicon germanium wafer formed to a thickness equal to or less than the first critical film thickness is subjected to a subsequent device heat treatment.

[0009] When the silicon germanium layer has a relatively thin thickness of, for example, about 5 to 30 nm, the critical film thickness at which metal impurities are captured by subsequent heat treatment (hereinafter referred to as the second critical film thickness) is thicker than the first critical film thickness in Patent Documents 1 and 2. The reason for this is that even if dislocations that serve as capture sites are generated, their density is low, and the density of capture sites for metal impurities is also low, making it difficult for metal to be captured.

[0010] When the germanium concentration of the silicon germanium layer is the same, the lower the film formation temperature of the silicon germanium layer, the less likely misfit dislocations occur after the epitaxial process, and the thicker the first critical film thickness as described in Patent Documents 1 and 2 becomes.

[0011] In contrast to this, the critical film thickness referred to in the present invention means a second critical film thickness at which metal impurities are captured by dislocations generated during additional heat treatment such as device heat treatment carried out after the epitaxial process.

[0012] What is important here is the density of dislocations that act as trapping sites for metal impurities.

[0013] When the germanium concentration in the silicon germanium layer is low, the film stress is also small and the density of dislocations generated by the additional heat treatment after the epitaxial process is low. As a result, the density of metal trapping sites is also low and metal impurities are not trapped.

[0014] On the other hand, when the germanium concentration in the silicon germanium layer is high, the film stress is also large and the density of dislocations that occur increases, which increases the density of metal trapping sites and makes it easier for metal impurities to be trapped.

[0015] For the above reasons, the first critical film thickness at which dislocations occur after the epitaxial process and the second critical film thickness at which metal impurities are trapped after the additional heat treatment are completely different.

[0016] It is important to note that the deterioration of device characteristics is caused by the capture of metal impurities. Metal impurities captured during additional heat treatment after the epitaxial process have a distribution in the depth direction, and metals are also contained in the most important channel layer. Generally, metal impurities form deep levels and become carrier recombination or generation centers, thereby deteriorating device characteristics.

[0017] JP-A-2009-59939 JP-A-5-326398

[0018] As described above, heteroepitaxial wafers, such as silicon germanium wafers, are required not to capture metal impurities and degrade device characteristics even when subjected to device heat treatment. However, conventionally, even if dislocations are not observed immediately after the epitaxial growth process, there has been a problem in that dislocations are generated and metal impurities are captured by heat treatment such as device heat treatment.

[0019] The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide a heteroepitaxial wafer in which metal impurities are not trapped.

[0020] In order to solve the above-mentioned problems, the heteroepitaxial wafer of the present invention is a heteroepitaxial wafer in which a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer are epitaxially grown, respectively, and the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer is as follows: film thickness (nm)<1.4×10 ７ ×[Ge (%)] －４．５ is.

[0021] A heteroepitaxial wafer having such a silicon germanium layer thickness and such a germanium concentration in the silicon germanium layer will not trap metal impurities.

[0022] Furthermore, it is preferable that even if the heteroepitaxial wafer is subjected to a device heat treatment, impurities are not captured at either the interface between the silicon single crystal substrate and the silicon germanium layer or the interface between the silicon germanium layer and the silicon layer.

[0023] A heteroepitaxial wafer that does not trap impurities at the interface even when subjected to such device heat treatment can more reliably prevent the trapping of metal impurities.Furthermore, a heteroepitaxial wafer that does not trap metal impurities even when subjected to device heat treatment can prevent the deterioration of device characteristics due to the trapping of metal impurities even when subjected to heat treatment for device fabrication.

[0024] It is also preferable that the silicon germanium layer has a thickness of 3 to 140 nm and a germanium concentration of 10 to 30%.

[0025] A heteroepitaxial wafer having such a silicon germanium layer thickness and germanium concentration can more reliably prevent metal impurities from being captured.

[0026] It is also preferable that a plurality of pairs of the silicon germanium layer and the silicon layer are formed.

[0027] Such a heteroepitaxial wafer having a plurality of pairs of silicon germanium layers and silicon layers formed thereon prevents metal impurities from being trapped at the interface between each silicon germanium layer and silicon layer, making it easily applicable to cutting-edge logic devices using a GAA structure formed by stacking several pairs of silicon germanium layers and silicon layers, and ensuring that metal impurities are not trapped.

[0028] The present invention also provides a heteroepitaxial wafer manufacturing method in which a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer are epitaxially grown, and the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer is set to: film thickness (nm)<1.4×10 ７ ×[Ge (%)] －４．５ The silicon germanium layer is epitaxially grown as a silicon-germanium layer.

[0029] With such a film thickness and germanium concentration of the silicon germanium layer, it is possible to manufacture a heteroepitaxial wafer in which metal impurities are not captured even when a device heat treatment is applied.

[0030] In the heteroepitaxial wafer of the present invention, by defining the relationship between the film thickness of the silicon germanium layer and the germanium concentration of the silicon germanium layer, metal impurities are not trapped. Furthermore, in the heteroepitaxial wafer in which metal impurities are not trapped even when a device heat treatment is applied, deterioration of device characteristics due to the trapped metal impurities can be prevented even when a heat treatment is applied for device fabrication.

[0031] Furthermore, the manufacturing method of the present invention makes it possible to easily and reliably manufacture a heteroepitaxial wafer in which metal impurities are not captured even when a device heat treatment is applied.

[0032] 1 is a schematic diagram of a heteroepitaxial wafer according to an embodiment of the present invention; FIG. 2 is a graph showing the depth profile of germanium concentration and nickel concentration after heat treatment when the germanium concentration in the silicon germanium layer is different; FIG. 3 is a graph showing the depth profile of germanium concentration and nickel concentration after heat treatment when the film thickness of the silicon germanium layer is different; FIG. 4 is a graph showing the relationship between the germanium concentration and film thickness of the silicon germanium layer to prevent nickel capture after heat treatment; FIG. 5 is a graph showing the depth profile of germanium concentration and nickel concentration after heat treatment when the heat treatment temperature is different; FIG. 6 is a graph showing the depth profile of germanium concentration and nickel concentration after heat treatment when the silicon germanium layer is 15 nm thick and has a germanium concentration of 20%; and FIG. 7 is a graph showing the depth profile of germanium concentration and metal impurity concentration after heat treatment when the metal impurities are different.

[0033] The present invention will be described in detail below, but the present invention is not limited thereto.

[0034] As described above, in a device using the GAA structure, it is required that dislocations caused by lattice mismatch between the silicon germanium layer and the silicon layer or silicon single crystal substrate do not occur even when the device is subjected to heat treatment.

[0035] The present inventors have conducted extensive research into this problem and have found the relationship between the film thickness and germanium concentration of a silicon germanium layer in which capture of metal impurities (gettering phenomenon) occurs after heat treatment of the device, thereby completing the present invention.

[0036] That is, the present invention provides a heteroepitaxial wafer in which a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer are epitaxially grown, and the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer is as follows: film thickness (nm)<1.4×10 ７ ×[Ge (%)] －４．５ The heteroepitaxial wafer is characterized in that:

[0037] The following description will be made with reference to the drawings.

[0038] 1 is a schematic diagram of a heteroepitaxial wafer according to one embodiment of the present invention, which includes a silicon single crystal substrate 1, a silicon germanium layer 2, and a silicon layer 3. The silicon germanium layer 2 is epitaxially grown on the silicon single crystal substrate 1, and the silicon layer 3 is epitaxially grown on the silicon germanium layer 2.

[0039] Here, it is necessary that the film thickness of the silicon germanium layer 2 and the germanium concentration of the silicon germanium layer 2 satisfy the above formula 1. If formula 1 is satisfied, the heteroepitaxial wafer will not trap metal impurities.

[0040] Furthermore, if the heteroepitaxial wafer does not trap metal impurities even when subjected to device heat treatment, it is possible to prevent deterioration of device characteristics due to the trapping of metal impurities even when heat treatment is performed for device fabrication.

[0041] The circumstances under which Equation 1 was discovered will now be described in detail.

[0042] (Experiment 1) A silicon germanium layer was epitaxially grown on a p-type silicon substrate having a diameter of 300 mm and a resistivity of 10 Ω cm, with a target thickness of 50 nm and a target germanium concentration of 15, 20, or 30%, and then a silicon layer having a thickness of 50 nm was epitaxially grown.

[0043] Thereafter, evaluation was performed by X-ray topography, but no misfit dislocations were found in any of the wafers after the epitaxial growth process.

[0044] After that, each wafer was contaminated with nickel (Ni) as a metal impurity from the back side, and then heated at 850°C for 11 min. ２ This heat treatment at 850° C. for 11 minutes was determined to be a time sufficient for nickel to diffuse through the thickness of the wafer (775 μm) based on the diffusion coefficient of nickel.

[0045] The depth-direction concentration distribution of germanium and nickel was then measured using SIMS from the epitaxial layer side of each wafer. The results are shown in Figure 2. The three graphs in Figure 2, from left to right, show the target germanium concentrations of 15, 20, and 30%. The horizontal axis of Figure 2 represents depth from the epitaxial layer side, and the vertical axis represents nickel concentration on the left and germanium concentration on the right.

[0046] 2, the rising portion of the germanium concentration at a depth of 50 nm corresponds to the interface between the silicon layer and the silicon germanium layer, and the falling portion of the germanium concentration at a depth of 100 nm corresponds to the interface between the silicon germanium layer and the silicon substrate. In both graphs, the nickel concentration is high at each interface, indicating that nickel is trapped at the interface.

[0047] Here, the criterion for determining that nickel has been captured is whether or not a concentration equal to or higher than the lower detection limit is detected by SIMS analysis.

[0048] (Experiment 2) Furthermore, on a p-type silicon substrate having a diameter of 300 mm and a resistivity of 10 Ω cm, a silicon germanium layer was epitaxially grown to target thicknesses of 20, 60, 130, and 140 nm and germanium concentrations of 10 and 20%, and then a silicon layer having a thickness of 50 nm was epitaxially grown.

[0049] Thereafter, evaluation was performed by X-ray topography, but no misfit dislocations were found in any of the wafers after the epitaxial growth process.

[0050] After that, each wafer was contaminated with nickel from the backside, and then heated at 850°C for 11 min. ２ This heat treatment of 850° C. / 11 min was the same as in Experiment 1, and was set to a time sufficient for nickel to diffuse through the thickness of the wafer (775 μm) based on the diffusion coefficient of nickel.

[0051] The depth-direction concentration distribution of germanium and nickel was then measured using SIMS from the epitaxial layer side of each wafer. The results are shown in Figure 3. The four graphs in Figure 3, from left to right, show the cases where the target silicon germanium layer thicknesses were 20, 60, 130, and 140 nm, and all show the cases where the target germanium concentration was 20%. The horizontal axis of Figure 3 represents depth from the epitaxial layer side, and the vertical axis represents nickel concentration on the left and germanium concentration on the right.

[0052] As shown in FIG. 3, when the target germanium concentration is 20%, nickel is captured in the falling portion of the germanium concentration (the interface between the silicon germanium layer and the silicon substrate) when the thickness of the silicon germanium layer is 60 nm or more. However, when the germanium concentration is 10% (not shown), nickel is not captured even when the thickness of the silicon germanium layer is 140 nm.

[0053] By performing Experiments 1 and 2 as described above, it is possible to determine the conditions for the germanium concentration and film thickness of the silicon germanium layer under which nickel is not captured even after device heat treatment. Specifically, as shown in Figure 4, the germanium concentration and film thickness of the experimental silicon germanium layer were plotted, and conditions under which nickel was captured were indicated by x and conditions under which nickel was not captured by o, and Equation 1 was obtained as an equation representing the boundary conditions. In other words, this shows that if the germanium concentration and film thickness of the silicon germanium layer satisfy Equation 1, devices can be fabricated without nickel being captured even after device heat treatment.

[0054] (Experiment 3) In addition, a silicon germanium layer was epitaxially grown on a p-type silicon substrate having a diameter of 300 mm and a resistivity of 10 Ω cm, with a target thickness of 50 nm and a target germanium concentration of 20%, and then a silicon layer was epitaxially grown to a thickness of 50 nm. The second critical thickness of the silicon germanium layer calculated from Equation 1 was 20 nm.

[0055] Thereafter, evaluation was carried out by X-ray topography, but no misfit dislocations were found at the stage after the epitaxial growth process.

[0056] After that, the wafer was contaminated with nickel from the rear side, and then heated at 650°C for 30 min in a ２ , 850℃ / 11min / N ２ , 1000℃ / 6min / N ２ The heat treatment time at each temperature was determined based on the diffusion coefficient of nickel so that nickel could be sufficiently diffused through the thickness of the wafer (775 μm).

[0057] After that, the concentration distribution of germanium and nickel in the depth direction was measured from the epitaxial layer side of each wafer by SIMS. The results are shown in Figure 5. The three graphs in Figure 5, from the left, show the conditions of the additional heat treatment: 650°C / 30 min / N ２ , 850℃ / 11min / N ２ , 1000℃ / 6min / N ２ In FIG. 5, the horizontal axis represents the depth from the epitaxial layer side, and the vertical axis represents the nickel concentration on the left and the germanium concentration on the right.

[0058] 5, under all heat treatment conditions, the nickel concentration was high at the portion where the germanium concentration rises (at the interface between the silicon layer and the silicon germanium layer) and at the portion where the germanium concentration falls (at the interface between the silicon germanium layer and the silicon substrate), indicating that nickel was trapped at the interface. This is because the silicon germanium layer had a thickness of 50 nm that was greater than the second critical thickness of 20 nm (i.e., did not satisfy Equation 1).

[0059] On the other hand, when a similar experiment was carried out with the silicon germanium layer having a target thickness of 15 nm and a target germanium concentration of 20%, nickel was not captured at any of the heat treatment temperatures. ２ This shows the case of other conditions (650°C / 30min / N ２ , 1000℃ / 6min / N ２ This is because the thickness of the silicon germanium layer, 15 nm, is smaller than the second critical thickness of 20 nm (i.e., formula 1 is satisfied).

[0060] From the above, it was found that Equation 1 holds regardless of differences in the additional heat treatment conditions.

[0061] (Experiment 4) In addition, metal impurities other than nickel (cobalt (Co), copper (Cu), titanium (Ti), and molybdenum (Mo)) were also investigated. A silicon germanium layer was epitaxially grown on a p-type silicon substrate with a diameter of 300 mm and a resistivity of 10 Ω cm, aiming for a thickness of 50 nm and a germanium concentration of 30%, and then a silicon layer with a thickness of 50 nm was epitaxially grown. The second critical thickness of the silicon germanium layer calculated from Equation 1 in this case was 3 nm.

[0062] Thereafter, evaluation was carried out by X-ray topography, but no misfit dislocations were found at the stage after the epitaxial growth process.

[0063] Thereafter, the wafers contaminated with cobalt from the rear surface side and the wafers contaminated with copper were subjected to additional heat treatment at 850° C. for a time sufficient for the diffusion length of each to diffuse through the thickness of the wafer.

[0064] Similar experiments were also carried out for titanium and molybdenum, except that because these elements diffuse slowly, they were contaminated from the front side rather than the back side, and then heat-treated at 850°C.

[0065] The depth-wise concentration distribution of germanium and various metal impurities was then measured using SIMS from the epitaxial layer side of each wafer. The results are shown in Figure 7. The four graphs in Figure 7 show the results for metal impurities of cobalt, copper, titanium, and molybdenum, respectively. The horizontal axis of Figure 7 represents depth from the epitaxial layer side, and the vertical axis represents the metal impurity concentration on the left and the germanium concentration on the right.

[0066] 7, for any metal impurity, the concentration of the metal impurity is high at the portion where the germanium concentration rises (at the interface between the silicon layer and the silicon germanium layer) and at the portion where the germanium concentration falls (at the interface between the silicon germanium layer and the silicon substrate), and it was found that any metal impurity is captured. This is because the thickness of the silicon germanium layer, 50 nm, is thicker than the second critical thickness of 3 nm (i.e., does not satisfy Equation 1).

[0067] On the other hand, when a similar experiment was conducted with a silicon germanium layer thickness of 15 nm and a germanium concentration of 20%, no metal impurities were captured. When the metal impurity was nickel, the results were the same as those shown in Figure 6 of Experiment 3 above. Incidentally, similar results were obtained when the metal impurity was cobalt, copper, titanium, or molybdenum. This is because the second critical thickness of the silicon germanium layer calculated from Equation 1 in this case is 20 nm, and the silicon germanium layer thickness of 15 nm is smaller than the second critical thickness of 20 nm (i.e., Equation 1 is satisfied).

[0068] The above demonstrates the effectiveness of Equation 1. If the film thickness and germanium concentration of the silicon germanium layer satisfy Equation 1, a heteroepitaxial wafer in which metal impurities are not trapped can be fabricated. In addition, as described above, Equation 1 remains valid even if the heat treatment temperature or the type of metal impurities changes.

[0069] As described above, in the prior art (e.g., Patent Document 1), it is possible to determine the condition (first critical film thickness) of the silicon germanium layer for preventing the occurrence of misfit dislocations in the epitaxial process, whereas in the present invention, it is possible to determine the condition (second critical film thickness) of the silicon germanium layer for preventing the capture of metal impurities from being formed using Equation 1.

[0070] By using this formula 1, it is possible to prevent metal impurities from being trapped due to misfit dislocations in a heteroepitaxial wafer that has been subjected to a heat treatment in a device process. That is, by forming a silicon germanium layer so as to satisfy the condition of formula 1, metal impurities are not trapped even when a heat treatment is performed in a device process, and deterioration of device characteristics can be prevented.

[0071] Here, the thickness of the silicon germanium layer is preferably 3 nm or more, which allows the thickness of the silicon germanium layer to be made approximately the same as the thickness (3 nm or more) of the electrode metal region around the channel when fabricating a GAA structure for suppressing the short channel effect, for example, and allows the GAA structure to be fabricated without any problems.

[0072] Furthermore, the germanium concentration is more preferably 10% or more, which makes it possible to increase the difference in etching rate between the silicon germanium layer and the silicon layer, and therefore, when the silicon layer is used as a channel layer, the silicon germanium layer can be easily removed by etching.

[0073] In this case, the growth rate of the silicon germanium layer decreases as the germanium concentration increases, and the thickness that can be formed in a practical time decreases. In consideration of this, it is preferable that the silicon germanium layer has a thickness of 140 nm or less and a germanium concentration of 30% or less.

[0074] As a result, the thickness of the silicon germanium layer can be set to, for example, 3 to 140 nm.

[0075] The germanium concentration can be 10 to 30%.

[0076] Although not shown, it is more preferable to form a plurality of pairs of silicon germanium layers and silicon layers, which prevents metal impurities from being trapped at the interface between each silicon germanium layer and silicon layer, making it possible to easily apply the present invention to cutting-edge logic devices using a GAA structure formed by stacking several pairs of silicon germanium layers and silicon layers, and to prevent metal impurities from being trapped.

[0077] As described above, the present invention provides a method for producing a heteroepitaxial wafer in which a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer are epitaxially grown, and the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer is set to the following: film thickness (nm)<1.4×10 ７ ×[Ge (%)] －４．５ By using a method for epitaxially growing a silicon germanium layer as the first step, it is possible to reliably manufacture a heteroepitaxial wafer that does not trap impurities at the interface even when subjected to device heat treatment.

[0078] The present invention will be specifically explained below with reference to examples, but the present invention is not limited to these examples.

[0079] [Example 1] A silicon germanium layer was formed on a silicon single crystal substrate with a diameter of 300 mm, n-type, and resistivity of 10 Ω cm under the conditions of a germanium concentration of 20% and a film thickness of 5 nm, so as to satisfy the condition of Equation 1. The second critical film thickness calculated from Equation 1 at this germanium concentration is 20 nm. After that, nickel was contaminated from the back side, and the silicon germanium layer was deposited at 850°C / 11 min / N ２After the heat treatment, the concentration of germanium and nickel in the depth direction was analyzed from the surface side by SIMS. As a result, no capture of nickel was confirmed. This is because the thickness of the silicon germanium layer, 5 nm, is smaller than the second critical thickness of 20 nm (i.e., formula 1 is satisfied).

[0080] [Example 2] A silicon germanium layer was formed on a silicon single crystal substrate with a diameter of 300 mm, n-type resistivity of 10 Ω cm, with a target germanium concentration of 10% and a target thickness of 110 nm. The second critical thickness calculated from Equation 1 at this germanium concentration is 440 nm. After that, nickel was contaminated from the back side, and the silicon germanium layer was grown at 850°C / 11 min / N ２ After the heat treatment, the concentration of germanium and nickel in the depth direction was analyzed from the surface side by SIMS. The results showed that nickel was not captured. This is because the thickness of the silicon germanium layer, 110 nm, is smaller than the second critical thickness of 440 nm (i.e., formula 1 is satisfied).

[0081] Example 3: A silicon germanium layer was formed on a 300 mm diameter, n-type, 10 Ω-cm silicon single crystal substrate under conditions of a germanium concentration of 15% and a film thickness of 12 nm. The germanium concentration and film thickness in this case were below the first critical film thickness for film formation at 900°C in the prior art (Patent Document 1), and no misfit dislocations occurred after the heteroepitaxial process. Furthermore, the second critical film thickness calculated from Equation 1 at this germanium concentration was 71 nm.

[0082] Then, from the back side, nickel was contaminated and the temperature was 850°C / 11 min / N ２ After the heat treatment, the concentration of germanium and nickel in the depth direction was analyzed from the surface side by SIMS. The results showed that nickel was not captured. This is because the thickness of the silicon germanium layer, 12 nm, is smaller than the second critical thickness of 71 nm (i.e., formula 1 is satisfied).

[0083] [Comparative Example 1] A silicon germanium layer was formed on a 300 mm diameter, n-type, 10 Ω-cm silicon single crystal substrate under conditions of a germanium concentration of 25% and a film thickness of 30 nm. In this case, the germanium concentration and film thickness were below the first critical film thickness for film formation at 550°C in the prior art (Patent Document 1), and no misfit dislocations occurred after the heteroepitaxial process. Furthermore, the second critical film thickness calculated from Equation 1 at this germanium concentration was 7 nm.

[0084] Then, from the back side, nickel was contaminated and the temperature was 850°C / 11 min / N ２ After the heat treatment, the concentration of germanium and nickel in the depth direction was analyzed from the surface side by SIMS. The results showed that nickel was captured. This is because the thickness of the silicon germanium layer, 30 nm, is larger than the second critical thickness of 7 nm (i.e., formula 1 is not satisfied).

[0085] Here, the mechanism by which nickel (metal impurity) is captured when formula 1 is not satisfied is presumed to be that the strain energy generated between the silicon germanium layer and the silicon layer is converted into dislocations by the heat treatment at 850°C, and these dislocations become apparent as capture sites for the metal impurities.

[0086] From the above, it was shown that in Examples 1 to 3 of the present invention, which satisfy Formula 1, nickel (metallic impurities) was not captured, while in Comparative Example 1, which does not satisfy Formula 1, nickel (metallic impurities) was captured.

[0087] The present invention encompasses the following aspects: [1]: A heteroepitaxial wafer in which a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer are epitaxially grown, respectively, wherein the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer is: film thickness (nm)<1.4×10 ７ ×[Ge (%)] －４．５[2]: The heteroepitaxial wafer according to [1] above, characterized in that, even when the heteroepitaxial wafer is subjected to a device heat treatment, impurities are not captured at the interface between the silicon single crystal substrate and the silicon germanium layer, or at the interface between the silicon germanium layer and the silicon layer. [3]: The heteroepitaxial wafer according to [1] or [2] above, characterized in that the silicon germanium layer has a film thickness of 3 to 140 nm and a germanium concentration of 10 to 30%. [4]: ​​The heteroepitaxial wafer according to any one of [1] to [3] above, characterized in that the silicon germanium layer and the silicon layer are formed in pairs. [5]: A method for manufacturing a heteroepitaxial wafer in which a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer are epitaxially grown, respectively, wherein the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer is set to: film thickness (nm)<1.4×10 ７ ×[Ge (%)] －４．５ a silicon germanium layer formed on the substrate by epitaxial growth;

[0088] The present invention is not limited to the above-described embodiments. The above-described embodiments are merely examples, and any configuration that is substantially identical to the technical idea described in the claims of the present invention and that provides similar effects is included within the technical scope of the present invention.

Claims

1. A heteroepitaxial wafer in which a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer are epitaxially grown, the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer being: film thickness (nm) < 1.4 × 10 ７ ×[Ge (%)] －４．５ A heteroepitaxial wafer comprising:

2. The heteroepitaxial wafer according to claim 1, characterized in that, even when the heteroepitaxial wafer is subjected to a device heat treatment, impurities are not captured at either the interface between the silicon single crystal substrate and the silicon germanium layer or the interface between the silicon germanium layer and the silicon layer.

3. The heteroepitaxial wafer according to claim 1, wherein the silicon germanium layer has a thickness of 3 to 140 nm and a germanium concentration of 10 to 30%.

4. The heteroepitaxial wafer according to any one of claims 1 to 3, characterized in that the silicon germanium layer and the silicon layer are formed in a plurality of pairs.

5. A method for producing a heteroepitaxial wafer in which a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer are epitaxially grown, the method comprising the steps of: ７ ×[Ge (%)] －４．５ and epitaxially growing the silicon germanium layer as a heteroepitaxial layer.