Fault-tolerant quantum error correction device, fault-tolerant quantum error correction method, fault-tolerant quantum error correction program, and quantum computer

Abstract

This fault-tolerant quantum error correction device comprises: a quantum circuit that includes a plurality of physical quantum bits; an encoding unit that encodes the physical quantum bits to generate logical quantum bits; and an error correction unit that performs error correction using the logical quantum bits of a quantum error correction code. The quantum error correction code is a concatenated code obtained by concatenating a plurality of quantum codes. As the size of the concatenated code increases, the ratio between the size of the logical quantum bits forming the concatenated code and the size of the physical quantum bits approaches a finite value.

Description

Fault-tolerant quantum error correction device, fault-tolerant quantum error correction method, fault-tolerant quantum error correction program, and quantum computer

[0001] The present invention relates to a fault-tolerant quantum error correction device, a fault-tolerant quantum error correction method, a fault-tolerant quantum error correction program, and a quantum computer.

[0002] Known quantum error correction or fault-tolerant quantum computing (FTQC) technologies include protocols using quantum low-density parity-check codes (LDPC) such as surface codes (see, for example, Non-Patent Documents 1 to 3), protocols using concatenated codes such as 7-qubit codes (see, for example, Non-Patent Documents 4 and 5), and protocols using quantum expander codes (see, for example, Non-Patent Documents 6 to 8).

[0003] Kitaev, A. Y. Quantum computations: algorithms and error correction. Russian Mathematical Surveys 52, 1191 (1997).https: / / doi.org / 10.1070 / rm1997v052n06abeh002155Kitaev, A. Fault-tolerant quantum computation by anyons. Ann. Phys. 303, 2 (2003).http: / / www.sciencedirect.com / science / article / pii / S0003491602000180Bravyi, S. B. & Kitaev, A. Y. Quantum codes on a lattice with boundary (1998).https: / / arxiv.org / abs / quant-ph / 9811052Steane, A. M. Error correcting codes in quantum theory. Phys. Rev. Lett. 77, 793 (1996).https: / / link.aps.org / doi / 10.1103 / PhysRevLett.77.793Steane, A. Multiple-particle interference and quantum error correction. Proceedings of the Royal Society of London. Series A: Mathematical, Physical and Engineering Sciences 452, 2551 (1996).https: / / royalsocietypublishing.org / doi / abs / 10.1098 / rspa.1996.0136Kovalev, A. A. & Pryadko, L. P. Fault tolerance of quantum low-density parity check codes with sublinear distance scaling. Phys. Rev. A 87, 020304 (2013).https: / / link.aps.org / doi / 10.1103 / PhysRevA.87.020304Fawzi, O., Grospellier, A. & Leverrier, A. Constant overhead quantum fault tolerance with quantum expander codes. Commun. ACM 64, 106-114 (2020).https: / / doi.org / 10.1145 / 3434163Gottesman, D. Fault-tolerant quantum computation with constant overhead. Quantum Info. Comput. 14,1338-1372 (2014).https: / / www.rintonpress.com / journals / doi / QIC14.15-16-5.htmlAharonov, D. & Ben-Or, M. Fault-tolerant quantum computation with constant error rate. SIAM J. Com-put. 38, 1207{1282 (2008).https: / / doi.org / 10.1137 / S0097539799359385.

[0004] Fault tolerance is essential for achieving scalable quantum computing and accelerating classical computing. Fault-tolerant protocols mitigate the effects of errors by simulating the original circuit on the logical qubits of a quantum error-correcting code using an appropriate number of physical qubits. Here, "simulation" refers to virtually reproducing an idealized model on a computer. Specifically, the idealized model is, for example, the original circuit, and the computer that reproduces it is, for example, a noisy quantum computer. Conventional fault-tolerant protocols include those that use quantum low-density parity-check (LDPC) codes such as surface codes (see, for example, Non-Patent Documents 1-3) and those that use concatenated codes such as 7-qubit codes (see, for example, Non-Patent Documents 4 and 5). These techniques can suppress the error rate on the logical qubits.

[0005] However, to suppress errors using conventional protocols, the ratio of physical qubits per logical qubit must be large. However, the number of physical qubits available in quantum devices is very limited, and space overhead is a major obstacle to achieving quantum computing. In this regard, quantum low-density parity-check (LDPC) code methods require a sufficiently large code distance to reduce the error rate, resulting in significant space overhead. Furthermore, concatenated codes, such as 7-qubit codes, require an increased level of concatenation to reduce the error rate, which also results in significant space overhead.

[0006] On the other hand, a method that has recently attracted attention is one that uses quantum expander codes (a group of quantum LDPC codes in which the ratio (rate) of logical qubits per physical qubit does not asymptotically become zero) (see, for example, Non-Patent Documents 6 to 8). This method has the advantage of being able to suppress the space overhead to a certain constant. However, unlike conventional protocols, the protocol of this method requires sequential gate implementation, which has the disadvantage that the time overhead increases polynomially.

[0007] As described above, conventional quantum error correction techniques have a trade-off between spatial overhead and time overhead. The present invention has been made in consideration of these issues, and its purpose is to realize a quantum error correction technique that can suppress both spatial overhead and time overhead.

[0008] In order to solve the above problems, a fault-tolerant quantum error correction device according to one embodiment of the present invention includes a quantum circuit including a plurality of physical quantum bits, an encoding unit that encodes the physical quantum bits to generate logical quantum bits, and an error correction unit that performs error correction using the logical quantum bits of the quantum error correction code. The quantum error correction code is a concatenated code formed by concatenating a plurality of quantum codes, and as the size of the concatenated code increases, the ratio of the size of the logical quantum bits to the size of the physical quantum bits that form the concatenated code approaches a finite value.

[0009] In one embodiment, the concatenated code increases in physical qubit size as the logical qubit size increases.

[0010] In one embodiment of the fault-tolerant quantum error correction device, the concatenated code is a quantum code whose physical quantum bit size is 2. ｒ -1, logical qubit size is 2 ｒ −2r−1, a quantum Hamming code with a code distance of 3 (r is a natural number).

[0011] In one embodiment of the fault-tolerant quantum error correction device, the concatenated code is a quantum code whose physical quantum bit size is 2. ｒ -1, logical qubit size is 2 ｒ −2tr−1, and the code distance is 2t+1 (r and t are natural numbers).

[0012] In one embodiment of the fault-tolerant quantum error correction device, the space overhead is bounded by a constant and the time overhead varies quasi-logarithmically as the size of the quantum error correction code increases.

[0013] In one embodiment, the fault-tolerant quantum error correction device includes an efficient decoder constructed by mathematically inductively using each decoder of the quantum codes used in the concatenation.

[0014] In one embodiment of a fault-tolerant quantum error correction device, an efficient decoder uses classical Hamming codes to correct bit-flip and phase-flip errors from the syndromes of the Z-stabilizer and X-stabilizer generators, respectively.

[0015] In one embodiment of the fault-tolerant quantum error correction device, the quantum error correction code is a transposition of the code-concatenated fault-tolerant protocol into a protocol for a two-dimensional geometry, or a one-dimensional geometry, or in general a D-dimensional geometry.

[0016] Another aspect of the present invention is a fault-tolerant quantum error correction method for performing quantum error correction in a quantum circuit including a plurality of physical quantum bits. The method includes an encoding step of encoding the physical quantum bits to generate logical quantum bits, and an error correction step of performing error correction using the logical quantum bits of the quantum error correction code. The quantum error correction code is a concatenated code formed by concatenating a plurality of quantum codes. As the size of the concatenated code increases, the ratio of the size of the logical quantum bits forming the concatenated code to the size of the physical quantum bits approaches a finite value.

[0017] Yet another aspect of the present invention is a fault-tolerant quantum error correction program. This program causes a computer to execute an encoding step of encoding physical quantum bits to generate logical quantum bits, and an error correction step of performing error correction using the logical quantum bits of the quantum error correction code. The error correction code is a concatenated code formed by concatenating multiple quantum codes. As the size of the concatenated code increases, the ratio between the size of the logical quantum bits and the size of the physical quantum bits that form the concatenated code approaches a finite value.

[0018] Yet another aspect of the present invention is a quantum computer, which includes the fault-tolerant quantum error correction device described above.

[0019] Any combination of the above components, and any transformation of the present invention into an apparatus, method, system, recording medium, computer program, etc., are also valid aspects of the present invention.

[0020] According to the present invention, it is possible to realize a quantum error correction technique that can suppress both spatial overhead and time overhead.

[0021] Q relating to the embodiment （Ｌ） and Q （Ｌ－１）4 is a diagram showing the relationship between 1 qubit and 2 qubits. It is a diagram showing the overhead factors of a concatenated code and a 7-qubit code according to an embodiment. It is a diagram showing the compilation of a fault-tolerant protocol according to an embodiment. It is a diagram showing an original circuit of 14 qubits (W(M)=14). It is a diagram showing an example of a corresponding level 2 circuit (L=2, K(L)=7) obtained from the original circuit of FIG. 4. It is a diagram showing gate teleportation to realize a 1-qubit Clifford gate. Based on gate teleportation, a Clifford gate U is inserted into two level 1 registers. Ｃ 1 shows a level-l two-register Clifford gate abbreviation for applying R ｙ Magic state R for executing (±π / 4) ｙ This is a diagram showing gate teleportation assisted by (±π / 4) |0>. This is a diagram showing the same circuit as gate teleportation assisted by |0>, which is the trivial identity operation 1. UR is added to the level l register. ｙ R at level l based on gate teleportation for applying (±π / 4) gates ｙ 1 illustrates (±π / 4) gate abbreviation. 2 illustrates a level-l measurement gadget for measuring on all qubit Z-basis in a level-l register. 3 illustrates a level-l initial state preparation gadget for preparing logic states in an encoded level-l register. 4 illustrates a level-l initial state preparation gadget for preparing logic states in an encoded level-l register.

[0022] The present invention will be described below based on preferred embodiments with reference to the drawings. In the embodiments and modified examples, identical or equivalent components, steps, and members are designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. The dimensions of the components in the drawings are enlarged or reduced as appropriate for ease of understanding. Some components that are not important for explaining the embodiments are omitted from the drawings. Terms including ordinal numbers such as "first" and "second" are used to describe various components, but these terms are used only to distinguish one component from another and do not limit the components.

[0023] This embodiment is a technique for realizing quantum error correction in which spatial overhead is kept constant (hereinafter also referred to as "constant spatial overhead") by concatenating multiple small-sized quantum codes without using quantum LDPC codes. As an example, this embodiment is a technique for concatenating different quantum Hamming codes as the concatenation level of the concatenated code increases. As a result, a low-overhead protocol is realized that simultaneously achieves constant spatial overhead and quasi-polylogarithmic time overhead. Unlike existing constant spatial overhead protocols, this protocol realizes fault-tolerant quantum computing even when the decoder execution time is not constant. This makes it possible to realize error correction in large-scale quantum computing while suppressing both spatial overhead and time overhead.

[0024] Quantum error correction is one of the fundamental technologies of quantum computers, which can speed up computations in the presence of inherent noise compared to conventional classical computations.

[0025] To solve a computational problem with an M-bit input, quantum computing can utilize quantum circuits with polynomial size, O(Poly(M)), in width and depth. However, if these quantum circuits are implemented directly on physical qubits, noise-induced errors can corrupt the quantum computation results. Fault-tolerant protocols mitigate the effects of errors by using an appropriate number of physical qubits to simulate the original circuit on the logical qubits of a quantum error-correcting code. As mentioned above, conventional fault-tolerant protocols use quantum low-density parity-check codes (LDPCs) such as surface codes or concatenated codes such as 7-qubit codes to suppress the error rate on the logical qubits. However, neither of these existing techniques addresses the tradeoff between space and time overhead.

[0026] As an example of solving this problem, we first describe a fault-tolerant protocol that simulates a circuit of size O(Poly(M)) with a constant space overhead of O(1) and a quasi-logarithmic polynomial time overhead. This time overhead is smaller than the polynomial overhead of conventional constant space overhead protocols using quantum expander codes (Non-Patent Documents 6-8). This is important because it enables high-speed quantum computation without significant polynomial slowdown. In analyzing the time overhead, we take into account the waiting time (non-zero) for classical computation during the execution of the fault-tolerant protocol. The novelty of the protocol of this embodiment lies in the use of concatenated codes with non-zero rates composed of sequences of different quantum codes, rather than quantum LDPC codes.

[0027] [Concatenated Codes with Non-Zero Rates] The key technique for realizing constant spatial overhead in this embodiment is to create a concatenated code Q with non-zero rates from L different quantum codes. （Ｌ） Here, L represents the total number of connections.

[0028] Conjunction sign Q （Ｌ） is introduced as follows: N ｒ , N ｒ =2 ｒ Define it as -1. Then, Cｒ (r=2, 3, ...) is the block length N ｒ bits, dimension (N ｒ -r) bit, distance 3 Hamming code [N ｒ , N ｒ -r, 3]. Quantum Hamming code Q ｒ (r=3, 4, ...) is C ｒ and C ｒ Calderbank-Shor-Stean code (CSS) [[N ｒ , K. ｒ , 3]]. This is the physical qubit N ｒ =2 ｒ -1 (i.e., code size is N ｒ ), logical qubit K ｒ = N ｒ -2r, distance 3 [[N ｒ , K. ｒ , 3]]. The concatenation at each level l∈{1,...,L} has a parameter r ｌ = l + 2, which starts with a 7-qubit code at level 1 and uses the quantum Hamming code sequence Q ３ , Q ４ , and so on. The rate is K in the limit of l → ∞. ｒｌ / N ｒｌ →It becomes 1.

[0029] Next, for l = L, L-1, ..., 1, Q （Ｌ） By inductively defining Q （Ｌ） Constructs. （Ｌ） and N （Ｌ） Q （Ｌ） Let K be the number of logical qubits and physical qubits. （Ｌ） =exp(O(L ２ )), N （Ｌ） =exp(O(L ２ )) becomes. Q （Ｌ） K （Ｌ） The collection of logical qubits is called the level 1 register. The physical qubit is called the level 0 register (or level 0 qubit).

[0030] In Figure 1, （Ｌ） and Q （Ｌ－１）In FIG. 1, we show the inductive relationship between L different quantum Hamming codes Q ｒ１ , Q ｒ２ …, Q ｒＬ For each connection level l∈{L, L−1, ..., 1}, we inductively assign the qubits of the register at level l to K （ｌ－１） Q ｒｌ Using the code block, N ｒｌ The distance 3 code Q is encoded into quantum bits of registers of level (l-1). ｒｌ can correct one error per code block, and this pattern can recover the encoded level l register even if all the qubits in one of the level (l-1) registers contain correlated errors.

[0031] In particular, Q in the level l register （Ｌ） K （Ｌ） =K （Ｌ－１） ×K ｒｌ The quantum bits are ｒｌ K of qubits （Ｌ－１） Then, divide each K （Ｌ－１） ∈{1, ..., K （Ｌ－１）}, K ｒｌ k from each of the level (l-1) registers （Ｌ－１） Choose the qubit, k （Ｌ－１） K in the th block ｒｌ The quantum bits are expressed as a quantum Hamming code Q ｒｌ As the logical qubits of ｒｌ This concatenated code is designed so that the encoded level l register can be restored even if all the qubits in the level (l-1) register have correlated errors. In this way, （Ｌ） , K. （Ｌ） , 3 Ｌ ]]Concatenation code Q （Ｌ） It should be noted that the error suppression ability of this code, unlike quantum LDPC codes, is not characterized solely by the code distance since it is due to the concatenated structure.

[0032] Next, Q （Ｌ）But in the limit of L → ∞, it asymptotically becomes 1 / η ∞ (>0) where η ∞ is a finite asymptotic overhead factor (i.e., the inverse of the rate R(L)).

[0033] FIG. 2 shows the overhead factors of the concatenated code according to this embodiment and the 7-qubit code. The circle plots represent the concatenated code according to this embodiment, and the cross plots represent the 7-qubit code. As shown in FIG. 2, the overhead factor diverges to infinity in the case of conventional concatenated codes and quantum LDPC codes. In contrast, the overhead factor of the concatenated code according to this embodiment asymptotically approaches a constant of 36 (η ∞ < 36). However, in this example, η ∞ Note that is not necessarily optimized. For example, Q ３ Instead, Q １０ By starting the concatenation from [7 Ｌ , 1, 3 Ｌ ], the Q （Ｌ） The overhead factor advantage is several orders of magnitude larger.

[0034] The construction of concatenated codes with non-zero rates described above can, in principle, be applied to other code sequences that approach 1 sufficiently quickly. For example, the above results can be applied to other code sequences with a parameter r ｌ It can also be applied to the concatenation of quantum Hamming codes with r ≒ log(l). ｌ While the time overhead can be reduced compared to the case of = l + 2, the space overhead may be increased by a constant factor.

[0035] The concatenation of more general augmented code sequences can also be performed using the same code parameter r ｌ can be used to provide a family of concatenated codes with non-zero rates. ｒ -1, 2 ｒThere is a quantum Bose-Chaudhuri-Hocquenghem code (quantum BCH code) with r = -1 - 2tr, 2t + 1 (r and t are natural numbers). This is a CSS code for the classical BCH code and its dual code. Since this has a larger code distance than the quantum Hamming code, it is possible that higher performance error correction can be achieved as L increases.

[0036] [Efficient decoder] Q （Ｌ） Although it is not a quantum LDPC code, it can have an efficient decoder. An efficient decoder is essential for realizing fault-tolerant quantum computing, but is generally difficult to construct. In fault-tolerant quantum computing with constant space overhead, no quantum LDPC code had such an efficient decoder until an efficient decoder for quantum expander codes was developed.

[0037] In the protocol of this embodiment, for each level l, Q ｒｌ has an efficient decoder. In particular, to correct bit-flip and phase-flip errors from the syndromes of the Z-stabilizer and X-stabilizer generators, respectively, the classical Hamming code C ｒｌ Similar to conventional hard-decision decoders, we can use efficient decoders for Q ｒｌ By recursively using the decoder of （Ｌ） Using parallel classical computation, the decoding of ｒｌ )), which is log-polynomial with respect to the problem size M. It is therefore small compared to the depth of the original circuit, i.e., O(poly(M)). In particular, we have found that even when the decoder has such a non-zero execution time, our fault-tolerant protocol has a threshold.

[0038] [Fault-tolerant protocol] The concatenated code Q （Ｌ） is used to build a fault-tolerant protocol.

[0039] M-bit string (i １ , ..., i Ｍ ) ∈ {0, 1} Ｍ We use an original circuit of qubits of width W(M) and depth D(M) to solve a series of computational problems with inputs represented by: where width and depth behave polynomially in M, i.e., W(M) = O(poly(M)), D(M) = O(poly(M)).

[0040] In the original circuit (i １ , ..., i Ｍ ), the initial state of M qubits The rest of the original circuit is determined by M, independent of the inputs.

[0041] The original circuit consists of Clifford gates X, Y, Z, H, S, CNOT, CZ, and non-Clifford gate R. ｙ It is described by a gate set of (±π / 4), and ends with measurements of all qubits in the Z basis.

[0042] The original circuit is then simulated by sampling from the output probability distribution within a predetermined error ε. Based on the original circuit, the present protocol inductively defines a circuit at level l (lε{L, L−1, ..., 0}) consisting of level l elementary operations on level l registers, where level 0 circuits are circuits on physical qubits. The set of level L elementary operations consists of a measurement operation, an H-gate operation, a CNOT-gate operation, a CZ-gate operation, a Pauli-gate operation, an initial state preparation operation, a Clifford state preparation operation, a magic state preparation operation, and a wait operation.

[0043] By combining these basic operations, the protocol of this embodiment performs Clifford unitary on two registers and performs non-Clifford gate R on each register by gate teleportation. ｙ Perform the (±π / 4) operation.

[0044] FIG. 3 shows how the fault-tolerant protocol of this embodiment is compiled.

[0045] First, the original circuit is compiled into a level-L circuit, where the required concatenation level L depends on M and ε.

[0046] Furthermore, for each l = L, L-1, ..., 1, we compile the level-l circuit into a corresponding level-(l-1) circuit using level-l gadgets (i.e., level-(l-1) circuits to perform level-l elementary operations).

[0047] Unlike conventional protocols, our protocol uses registers instead of qubits as units. The gadgets used in this compilation are designed to meet appropriate conditions for fault tolerance. To keep the overall space overhead constant, each level l gadget is designed to use a fixed number of level (l-1) additional auxiliary registers per encoded level l register.

[0048] [Existence of a Threshold] The novelty of the protocol of this embodiment is that different codes Q ｒ１ , …, Q ｒＬ A concatenated code Q constructed from a sequence of （Ｌ） However, as the size of this set of codes increases, the existence of a threshold may become non-trivial.

[0049] Previously, proofs of the threshold theorem for concatenated codes assumed that the same codes were concatenated. （ｌ） The level l register for ｒｌ It is coded into level (l-1) registers, and as the concatenation level increases, ｒｌ However, the number of elementary operations at level (l-1) per gadget at level l grows polynomially (i.e., O(poly(N ｒｌ )) It can be proven that a threshold exists even when the

[0050] The analysis in this embodiment addresses a setting where the execution time of the classical computation in the decoder may also increase. Threshold analyses of existing constant-space-overhead protocols assume that the decoder must execute in zero time. It was unclear whether constant-space-overhead fault-tolerant quantum computation is possible when the execution time of the classical computation is non-zero and increases. Large-scale fault-tolerant quantum computation requires large-sized LDPC codes for error suppression. Because the decoder execution time of such large-sized quantum LDPC codes is long, waiting for this results in the physical qubits experiencing many errors during the waiting time. This situation violates the essential assumption for the existence of a threshold (i.e., the assumption that the physical error rate is constant during error correction). As a result, quantum LDPC code protocols may fail to correct large-scale, general classes of errors.

[0051] It should be noted that even in conventional protocols using quantum LDPC codes, such as 2D surface codes, the requirement that the execution time of classical computations not increase remains. In this case, the decoder must process the syndrome data stream at the rate at which it is received, even as the code distance increases. In contrast, concatenated codes Q （Ｌ） The protocol of the present embodiment, based on

[0046] , enables fault-tolerant quantum computation with constant space overhead even with finite computational resources.

[0052] In this setup, we assume that the circuit on the physical qubit follows a conventional local stochastic error model, where errors in the level-0 circuit are proportional to the physical error rate p ０ At each operation position in the level 0 circuit, there is a probability p ０ There may be defects at s positions. Errors may include adversarial errors and correlated errors. However, the probability that errors occur simultaneously at s positions is p ０ ｓ can be suppressed.

[0053] Hereinafter, each level l elementary operation in a level l circuit is referred to as a level l position. We can show that a fault also occurs at a level L position in an error level L circuit of the protocol of this embodiment according to the local probability error model. Furthermore, similar to conventional concatenated codes, we can prove the following proposition regarding double exponential error suppression at L:

[0054] [Proposition 1] (Error suppression by concatenation of quantum Hamming codes) Under a local stochastic error model, there exists a non-zero threshold constant p ｔｈ Concatenated code Q with 0 （ｌ） It is possible to explicitly construct a fault-tolerant protocol using p ０ <p ｔｈ ), quantum Hamming code Q （ｌ） The concatenated protocol reduces the logical error rate to Ｌ =exp(-O(2 Ｌ )) can be suppressed in the form of

[0055] A practical threshold can be obtained by slightly modifying the protocol of this embodiment. For example, （ｌ） By encoding each level 0 qubit into a constant size surface code logical qubit, the same threshold as the surface code can be achieved. When the noise of the physical qubit is biased, a particularly high threshold can be achieved by using the surface code. Compared to conventional protocols, the surface code and the code Q of this embodiment （ｌ） Concatenation with has the advantages of constant space overhead, large decoder speedups, and the existence of a threshold even for non-zero time decoders.

[0056] As shown in the following proposition, the significance of the protocol of this embodiment is that it can simultaneously achieve a constant space overhead and a quasi-logarithmic polynomial time overhead compared to the original circuit.

[0057] [Proposition 2] (Overhead due to quantum Hamming code concatenation)

[0058] Under the local stochastic error model, the concatenated code Q with concatenation level L = Θ(log(log(M / ε)))（ｌ） Using this, the original circuit with a width of W(M) qubits and a depth of D(M) can be converted to the depth of a fault-tolerant circuit, with a maximum of W(M) × O(1) physical qubits and D(M) × exp((O(log ２ We can explicitly construct fault-tolerant protocols that simulate within error ε>0 on all variational distances in running time (log(M / ε)), where W(M) = O(poly(M)) and D(M) = O(poly(M)).

[0059] These overheads include gate teleportation and the overhead for preparing the auxiliary state required for error correction. Unlike previous analyses of existing constant-space overhead protocols, the execution time also includes wait operations for non-zero-time classical computations in the decoder and gate teleportation.

[0060] As long as existing constant-space-overhead protocol techniques are used, it has been difficult to simultaneously achieve these space and time overheads. Existing protocols rely on conventional concatenated codes to prepare auxiliary states for gate teleportation, making it impossible to implement parallel gates for all logical qubits within a constant space overhead. Therefore, serial gate implementations incur polynomially large time overheads when implementing parallel gates in the original circuit.

[0061] In contrast, the protocol of this embodiment uses Q （ｌ） Full parallelism can be achieved by applying a gate to all logical qubits of Q at once. （ｌ） Thanks to the non-zero rate of , all auxiliary states required for gate teleportation can be prepared in parallel within a constant space overhead. As a result, the protocol of this embodiment has a significant advantage in terms of time overhead compared to conventional protocols with constant space overhead.

[0062] In particular, we aim to eliminate the architectural time overhead O(poly(N （ｌ） We found that even with the presence of )), a threshold exists. This may be imposed by constraints such as nearest-neighbor interactions in two-dimensional geometry, limited classical computational resources in the decoder, or insufficient parallelism in preparing auxiliary states used for gate teleportation and error correction. The suppression of logical error rates is much faster than the increase in code size. Therefore, concatenated codes in our protocol tolerate time overhead at higher concatenation levels by simply waiting, such as by executing an identity gate. This unique property of concatenated codes contrasts with quantum LDPC codes, which must be decoded at least once within a fixed time to avoid error accumulation. Therefore, our protocol can be implemented on a variety of architectures.

[0063] For example, the procedure described in [9] allows us to rewrite a code-concatenated fault-tolerant protocol into a protocol for two-dimensional (or one-dimensional) geometry. We can show that a threshold exists for such a rewrite, even with polynomial time overhead. Note, however, that if the original circuit contains two-qubit gates on any pair of qubits, then a protocol on such a 2D architecture to simulate the original circuit will incur a polynomial-long time overhead.

[0064] In the above embodiment, the quantum codes forming the concatenated code are described as quantum Hamming codes or quantum BCH codes. However, the concatenated code is not limited to this, and may be formed using, for example, C4 / C6 codes.

[0065] As described above, according to this embodiment, it is possible to construct a fault-tolerant quantum computing protocol that simultaneously achieves constant space overhead and quasi-logarithmic polynomial time overhead. An important technical feature is the use of a concatenated code composed of a sequence of quantum Hamming codes. By utilizing the concatenation of quantum Hamming codes, the technology of this embodiment provides an efficient decoder, a space-saving and high-speed protocol for simulating universal quantum computing, and a threshold that suppresses errors doubly exponentially as the concatenation level increases.

[0066] Example 1 Figure 4 shows an original circuit with 14 qubits (W(M)=14). Figure 5 shows the corresponding level 2 circuit (L=2, K （Ｌ） = 7) is shown below.

[0067] The original circuit consists of a set of Clifford gates X, Y, Z, H, S, CNOT, and CZ, and a set of non-Clifford gates R. ｙ (±π / 4). The W(M) quantum bits in the original circuit are (W(M) / K （Ｌ） ) qubits in Level-L registers, and for each Level-L register, add 8 + 2 = 10 auxiliary Level-L registers. Of these 10, 8 are used for Level-L abbreviation and Level-L basic operations as shown, and the remaining 2 are used for error correction. The Pauli gates at the input of the original circuit are compiled into Level-L Pauli gate operations. Next, the part of the original circuit consisting only of Clifford gates is compiled into Level-L two-register Clifford gate U Ｃ compiled into a single use of R ｙ The depth 1 part of the original circuit with (±π / 4) gates is R ｙ (±π / 4) Gate abbreviation UR ｙ (±π / 4) is compiled into a single use. Abbreviations that operate on all level L registers can be performed in parallel.

[0068] [Example 2] Figure 6 shows gate teleportation for realizing a one-qubit Clifford gate. Figure 7 shows a Clifford gate U in two level l registers based on gate teleportation. Ｃ 1 shows a level-1 two-register Clifford gate abbreviation for applying

[0069] This implementation uses the state 7 is assisted by the auxiliary level L register B １ , B ２ , B ３ , B ４ The tensor product of the Pauli operator is given by the measurement result. is calculated and applied as an error correction for quantum teleportation by two-level l Pauli gate operation.

[0070] [Example 3] In FIG. ｙ Magic state R for executing (±π / 4) ｙ (±π / 4) |0〉. Figure 9 shows the same circuit as the gate teleportation assisted by |0〉, which is the trivial identity operation 1. Figure 10 shows the UR ｙ R at level l based on gate teleportation for applying (±π / 4) gates ｙ (±π / 4) gate abbreviation. ｙ (±π / 4) is R ｙ (π / 4), R ｙ (-π / 4), and any tensor product of 1.

[0071] This implementation uses two auxiliary level registers, A １ and A ２ Assisted by Register A １ and A ２ is created by preparing the magic state and the initial state. and Prepared by UR ｙFor each quantum bit for which (±π / 4) acts as a trivial identity operation 1, A １ and A ２ A SWAP gate is applied between ｙ The application of (±π / 4) gates is avoided. These SWAP gates are implemented together as a two-register Clifford gate abbreviation in Figures 6 and 7. ｙ (π / 4) and gate teleportation is performed to apply the identity operation 1. Conditional on the measurement result, a level 1 Clifford gate for error correction, i.e., an HZ gate, is applied. R ｙ To achieve (-π / 4), after error correction by the HZ gate, an additional Clifford gate R ｙ The circuit of Figure 8 is used, applying (-π / 4) = ZH. Error correction HZ gate and additional Clifford gate R ｙ Each of (-π / 4) is implemented by the two-register Clifford gate abbreviation of FIGS. 6 and 7, and A ２ It operates trivially above and is discarded at the end.

[0072] Example 4 FIG. 11 shows a level-l measurement gadget for measuring all qubits in a level-l register in the Z basis.

[0073] This gadget is realized by a transversal level (l-1) measurement operation followed by an efficient decoder. The classical computation of this decoder is O(log(N ｒｌ )), so before using the measurement results, ｒｌ )) level (l-1) of the wait operation needs to be performed.

[0074] [Example 5] In FIG. 12, the logic state is stored in the coded level 1 register. 1 shows a level 1 initial state preparation gadget for preparing the

[0075] This gadget is a Clifford Unitary U ｅｎｃｏｄｅ By executing In this level (l-1) stabilizer circuit, the preparation operation is performed on the N ｒｌ This is performed sequentially using the auxiliary level (l-1) registers added to each set of level (l-1) registers. Note that most of the auxiliary level (l-1) registers other than those used in this preparation are omitted in FIG. 12. Next, K （ｌ－１） For each of the code blocks, Q ｒｌ the logical Z operator of the logical qubits of ｒｌ The verification is performed by measuring all Z generators of the stabilizer of . If the verification does not detect any errors, the gadget will Otherwise, this prepared state is discarded and the gadget executes the part between the dashed lines as shown, outputting the prepared logic in the second run without verification. Output.

[0076] The embodiments of the present invention have been described in detail above. These embodiments are merely examples, and it will be understood by those skilled in the art that various modifications and changes are possible within the scope of the claims of the present invention, and that such modifications and changes also fall within the scope of the claims of the present invention. Therefore, the descriptions and drawings in this specification should be treated as illustrative rather than restrictive.

[0077] Any combination of the above-described embodiments and modifications is also useful as an embodiment of the present invention. A new embodiment resulting from the combination has the combined effects of each of the combined embodiments and modifications.

Claims

1. A fault-tolerant quantum error correction device comprising: a quantum circuit including a plurality of physical quantum bits; an encoding unit that encodes the physical quantum bits to generate logical quantum bits; and an error correction unit that performs error correction using the logical quantum bits of a quantum error correction code, wherein the quantum error correction code is a concatenated code formed by concatenating a plurality of quantum codes, and the ratio of the size of the logical quantum bits forming the concatenated code to the size of the physical quantum bits approaches a finite value as the size of the code increases.

2. A fault-tolerant quantum error correction device as described in claim 1, characterized in that the size of the physical quantum bits of the concatenated code increases as the size of the logical quantum bits increases.

3. The concatenated code has a physical quantum bit size of 2 ｒ -1, the size of the logical quantum bit is 2 ｒ 2. The fault-tolerant quantum error correction device according to claim 1, wherein the quantum Hamming code has a code distance of −2r−1 and a code distance of 3 (r is a natural number).

4. The concatenated code has a physical quantum bit size of 2 ｒ -1, the size of the logical quantum bit is 2 ｒ 2. The fault-tolerant quantum error correction device according to claim 1, wherein the quantum BCH code has a code distance of 2t+1 (r and t are natural numbers) and a bit length of r=−2tr−1.

5. A fault-tolerant quantum error correction device as described in claim 1, characterized in that as the size of the quantum error correction code increases, the space overhead is kept constant and the time overhead varies quasi-logarithmically polynomially.

6. A fault-tolerant quantum error correction device according to claim 1, further comprising an efficient decoder in which each decoder used in the concatenation is constructed inductively.

7. A fault-tolerant quantum error correction device as claimed in claim 6, wherein the efficient decoder uses classical Hamming codes to correct bit-flip errors and phase-flip errors from the syndromes of the Z-stabilizer generator and the X-stabilizer generator, respectively.

8. The fault-tolerant quantum error correction device of claim 1, wherein the quantum error correction code is a rewrite of a fault-tolerant protocol of concatenated codes into a protocol for a two-dimensional geometry, a one-dimensional geometry or generally a D-dimensional geometry.

9. A method for performing fault-tolerant quantum error correction in a quantum circuit including a plurality of physical quantum bits, comprising: an encoding step of encoding the physical quantum bits to generate logical quantum bits; and an error correction step of performing error correction using the logical quantum bits of a quantum error correcting code, wherein the quantum error correcting code is a concatenated code formed by concatenating a plurality of quantum codes, and the ratio of the size of the logical quantum bits forming the concatenated code to the size of the physical quantum bits approaches a finite value as the size of the code increases.

10. A fault-tolerant quantum error correction program that causes a computer to execute an encoding step of encoding physical quantum bits to generate logical quantum bits, and an error correction step of performing error correction using the logical quantum bits of a quantum error correction code, wherein the quantum error correction code is a concatenated code formed by concatenating a plurality of quantum codes, and the concatenated code is characterized in that as the size of the code increases, the ratio of the size of the logical quantum bits that form the concatenated code to the size of the physical quantum bits approaches a finite value.

11. A quantum computer including the fault-tolerant error correction device of claim 1.