Semiconductor substrate manufacturing method, semiconductor substrate manufacturing device, and template substrate

Abstract

This semiconductor substrate manufacturing method includes: (i) a step for preparing a template substrate that has a growth suppression region and first and second seed regions, wherein the growth suppression region includes a first region and a second region, and a third region that has a different light reflectance from the first and second regions; (ii) a step for growing first and second semiconductor parts according to a predetermined growth condition; (iii) a step for irradiating at least the third region of the semiconductor substrate with first light; and (iv) a step for changing the predetermined growth condition on the basis of second light which is the reflected light from the semiconductor substrate.

Description

Semiconductor substrate manufacturing method, semiconductor substrate manufacturing apparatus, and template substrate

[0001] The present disclosure relates to a method for manufacturing a semiconductor substrate.

[0002] Patent Document 1 discloses a technique for forming a GaN (gallium nitride) based semiconductor layer on a GaN based substrate or a heterogeneous substrate (for example, a sapphire substrate) using an ELO (Epitaxial Lateral Overgrowth) method.

[0003] Japanese Patent Application Publication No. 2013-251304

[0004] A method for manufacturing a semiconductor substrate in one aspect of the present disclosure includes the steps of: preparing a template substrate having a growth inhibition region and first and second seed regions adjacent to each other via the growth inhibition region, wherein the growth inhibition region includes a first region adjacent to the first seed region and a second region adjacent to the second seed region, and a third region located between the first and second regions and having a different optical reflectivity than the first and second regions; growing a first semiconductor portion and a second semiconductor portion above the growth inhibition region under predetermined growth conditions; irradiating first light onto at least the third region of the template substrate and the semiconductor substrate including the first semiconductor portion and the second semiconductor portion; and changing the predetermined growth conditions based on second light, which is reflected light from the semiconductor substrate.

[0005] Furthermore, a template substrate in one aspect of the present disclosure is a template substrate for growing a nitride semiconductor, and has a growth-inhibition region and first and second seed regions adjacent to each other via the growth-inhibition region, and the growth-inhibition region includes a first region adjacent to the first seed region, a second region adjacent to the second seed region, and a third region located between the first and second regions and having a different optical reflectivity from the first and second regions.

[0006] FIG. 1 is a cross-sectional view showing a configuration of a semiconductor substrate in an embodiment of the present disclosure. FIG. 2 is a flowchart showing a manufacturing method of a semiconductor substrate in an embodiment of the present disclosure. FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor substrate in an embodiment of the present disclosure. FIG. 4 is a graph showing a schematic time change in intensity of second light from a semiconductor substrate. FIG. 5 is a cross-sectional view showing an example of a configuration of a semiconductor portion having a sloped region. FIG. 6 is a plan view showing an example of a mask pattern. FIG. 7 is a cross-sectional view showing an example of a configuration of a base substrate. FIG. 8 is a cross-sectional view showing an example of a configuration of an underlayer portion. FIG. 9 is a schematic view showing a configuration of an apparatus for manufacturing a semiconductor substrate in an embodiment of the present disclosure. FIG. 10 is a cross-sectional view showing a manufacturing method of a semiconductor substrate in Example 1. FIG. 11 is a cross-sectional view showing a configuration of a semiconductor substrate in an example of the present disclosure. FIG. 12 is a cross-sectional view showing a configuration of a semiconductor substrate in an example of the present disclosure. FIG. 13 is a cross-sectional view showing a configuration of a semiconductor substrate in an example of the present disclosure. Fig. 10 is a cross-sectional view showing the configuration of a semiconductor substrate in Example 6. Fig. 11 is a cross-sectional view showing the configuration of a semiconductor substrate in one configuration example of Example 6. Fig. 12 is a cross-sectional view showing the configuration of a semiconductor substrate in another configuration example of Example 6. Fig. 13 is a cross-sectional view showing the configuration of a template substrate in Example 7. Fig. 14 is a schematic view showing the configuration of a semiconductor substrate manufacturing apparatus in Example 8.

[0007] To facilitate understanding of the semiconductor substrate manufacturing method and the like according to one embodiment of the present disclosure, first, a brief description of the findings of the present disclosure will be given.

[0008] [Summary of Findings of the Present Disclosure] Generally, a technique is known for in-situ observation of film thickness during film formation by irradiating light from a light source onto a wafer during film formation using a film formation apparatus such as an MOCVD (Metal-Organic Chemical Vapor Deposition) apparatus. This type of technique makes it possible to observe the film thickness during film formation in real time, but is basically applied when a film is formed on the entire surface of a wafer.

[0009] The ELO method involves the lateral growth of a semiconductor layer (ELO layer) on a growth substrate. Conventionally, there has been no known method for monitoring the lateral growth of an ELO layer, and empirically determined growth conditions have typically been used for the lateral growth of an ELO layer by the ELO method. However, for example, when forming a gap between two adjacent ELO layers without causing their edges (referred to as ELO edges) to meet, the gap width can vary for each batch of semiconductor substrates fabricated due to various factors. Large variations in the gap widths of multiple semiconductor substrates having ELO layers can reduce the yield when devices are fabricated using the ELO layers of each semiconductor substrate in a downstream device process. Furthermore, even when the ELO edges of two adjacent ELO layers are caused to meet, if the growth conditions are not changed at the appropriate time just before or just after the meeting, the surface flatness of the ELO layer after the meeting can be deteriorated. By appropriately changing the deposition conditions just before or just after the meeting of two adjacent ELO layers, the surface flatness of the ELO layer after the meeting can be improved. It is very significant to calculate the lateral growth rate and know the timing of the meeting by monitoring the ELO edge during the growth of the ELO layer.

[0010] As a result of extensive research, the inventors came up with a new idea that makes it possible to monitor the position of the ELO edge of a laterally growing ELO layer by applying general in-situ observation techniques, and have come up with the present disclosure.

[0011] According to one aspect of the present disclosure, a technology can be provided that can monitor the position of the ELO edge of an ELO layer growing laterally on a substrate capable of selective growth (a substrate having a growth-inhibited region and a growth-enabling region). Specifically, a reflectance-changed region (a third region, described below) with a different optical reflectance from the surrounding area is formed in the growth-inhibited region of the substrate capable of selective growth. The reflectance-changed region can take various forms. Then, light from a light source is irradiated onto the ELO layer during lateral growth, and changes in the reflected light intensity (i.e., optical reflectance) are observed in real time. The trend of the time change in the reflected light intensity until the ELO edge of the ELO layer growing laterally on the growth-inhibited region reaches the reflectance-changed region differs from the trend of the time change in the reflected light intensity after the ELO edge reaches the reflectance-changed region. The inventors discovered that information regarding the position of the ELO edge can be obtained based on such changes in trend.

[0012] The reflectance change region can be formed, for example, around a position where two adjacent ELO layers laterally grow and their ELO ends meet. This allows, for example, when the ELO ends of two adjacent ELO layers are not to meet, to appropriately adjust the growth conditions for the lateral growth of the ELO layer when the ELO ends approach the reflectance change region. As a result, the gap width can be easily controlled. Therefore, the variation in the gap widths of multiple semiconductor substrates can be reduced. This allows for improved yields in the manufacture of semiconductor substrates including semiconductor portions. This yield can be defined as the rate at which semiconductor portions that satisfy the compatibility conditions, such as dislocation density (defect density), aspect ratio, etc., are manufactured. Improving the stability of semiconductor substrate manufacturing is also highly effective in improving the yield of device processes for the ELO layer. Furthermore, even when the ELO ends of two adjacent ELO layers are to meet, for example, by appropriately adjusting the growth conditions for the lateral growth of the ELO layer when the ELO ends approach the reflectance change region, the surface flatness of the ELO layer after the meeting can be easily improved. Also, for example, the lateral growth rate can be calculated based on information on the time when the reflectance change region is reached, and then growth can be stopped or growth conditions can be changed at an appropriate time based on the lateral growth rate.

[0013] [Semiconductor Substrate] FIG. 1 is a cross-sectional view illustrating the configuration of a semiconductor substrate according to an embodiment of the present disclosure. As shown in FIG. 1 , the semiconductor substrate 10 (semiconductor wafer) according to this embodiment includes a template substrate TS and a semiconductor portion 8. The template substrate TS has a growth inhibition region SP and first and second seed regions 4F and 4S adjacent to each other via the growth inhibition region SP. The growth inhibition region SP includes a first region A1 adjacent to the first seed region 4F, a second region A2 adjacent to the second seed region 4S, and a third region A3 located between the first and second regions A1 and A2 and having a different reflectance (optical reflectance) from the first and second regions A1 and A2. The template substrate TS may be used, for example, to grow a nitride semiconductor. The semiconductor portion 8 includes a first semiconductor portion 8F located above the first seed region 4F and the growth inhibition region SP, and a second semiconductor portion 8S located above the second seed region 4S and the growth inhibition region SP. The first region A1, the second region A2, and the third region A3 will be described in detail later together with the description of the method for manufacturing the semiconductor substrate.

[0014] The template substrate TS includes a base substrate BS and has, on the base substrate BS, a mask pattern 6 including a mask portion 5 and a first opening K1 and a second opening K2 adjacent to each other via the mask portion 5. In the template substrate TS, the upper surface of the mask portion 5 is a growth inhibition region SP, and a first seed region 4F overlapping the first opening K1 and a second seed region 4S overlapping the second opening K2 may be located on the upper surface of the base substrate BS. In the semiconductor substrate 10 of this embodiment, the first and second semiconductor portions 8F and 8S are adjacent to each other via a gap GP. Hereinafter, the first and second seed regions 4F and 4S may be collectively referred to as the seed region 4, the first and second openings K1 and K2 may be collectively referred to as the openings K, and the first and second semiconductor portions 8F and 8S may be collectively referred to as the semiconductor portion 8. The semiconductor portion 8 may be a semiconductor layer.

[0015] The template substrate TS may be a growth substrate used to grow a nitride semiconductor, and the base substrate BS may include a nitride semiconductor. The semiconductor portion 8 may be a nitride semiconductor portion containing a nitride semiconductor as a main material. The nitride semiconductor may be, for example, Al ｘ Gaｙ In ｚ N (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors that contain gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0016] The semiconductor portion 8 may be doped (e.g., n-type including donors) or non-doped. In the semiconductor substrate 10, the base substrate BS may include a semiconductor other than a nitride semiconductor (e.g., a silicon-based semiconductor) or a non-semiconductor. The base substrate BS and the mask pattern 6 may collectively be referred to as the template substrate TS. The template substrate TS may be a growth substrate (selective growth substrate) including the third region A3 on which the semiconductor portion 8 can be formed by selective growth, and the specific form of the template substrate TS is not particularly limited. Specific examples of various forms of the template substrate TS will be described later.

[0017] The semiconductor portion 8 can be formed by the ELO method, starting from the seed region 4 (a region exposed from the opening K on the upper surface of the base substrate BS). The seed region 4 may be a region that serves as a starting point for growth of the semiconductor portion 8. The semiconductor portion 8 may be a nitride semiconductor portion, and the thickness direction of the semiconductor portion 8 may be the c-axis direction (<0001> direction) of the nitride semiconductor. The opening K may have an elongated shape, and the width direction thereof may be the a-axis direction (<11-20> direction) of the nitride semiconductor. In the semiconductor substrate 10, the direction from the base substrate BS to the semiconductor portion 8 is defined as "upward." Viewing an object from a line of sight parallel to the normal direction of the semiconductor substrate 10 (including perspective) is sometimes referred to as "planar view."

[0018] [Method of Manufacturing a Semiconductor Substrate] Fig. 2 is a flowchart showing a method of manufacturing a semiconductor substrate according to this embodiment. Fig. 3 is a cross-sectional view showing a method of manufacturing a semiconductor substrate according to this embodiment. The time axis t, points in time TP1 and TP2, and periods PR1, PR2, and PR3 shown in Fig. 3 will be referenced in Fig. 4 and the description using Fig. 4 described below.

[0019] As shown in Figures 2 and 3, the method for manufacturing a semiconductor substrate of this embodiment includes the steps of: preparing a template substrate TS having a growth inhibition region SP and first and second seed regions 4F and 4S adjacent to each other via the growth inhibition region SP, wherein the growth inhibition region SP includes a first region A1 adjacent to the first seed region 4F and a second region A2 adjacent to the second seed region 4S, and a third region A3 located between the first and second regions A1 and A2 and having a reflectance (optical reflectance) different from that of the first and second regions A1 and A2; growing first and second semiconductor portions 8F and 8S above the growth inhibition region SP under predetermined growth conditions; irradiating first light L1 onto at least the third region A3 of the semiconductor substrate 10 including the template substrate TS and the first and second semiconductor portions 8F and 8S; and changing the predetermined growth conditions based on second light L2, which is light reflected from the semiconductor substrate 10.

[0020] A detector including, for example, an optical sensor can be used to receive the second light L2, which is light reflected from the semiconductor substrate 10. In the method for manufacturing a semiconductor substrate of this embodiment, the growth of the first and second semiconductor portions 8F and 8S may be stopped before the first and second semiconductor portions 8F and 8S coalesce by changing predetermined growth conditions based on the second light L2. For example, the growth of the first and second semiconductor portions 8F and 8S can be stopped by stopping the supply of at least a portion of the raw materials. This will be described in detail later.

[0021] The first region A1, the third region A3, and the second region A2 may be aligned in this order in the first direction X1. The third region A3 may be narrower than the first and second regions A1 and A2 in a cross-sectional view including the first direction X1. The first direction X1 may be the a-axis direction (<11-20> direction) of the nitride semiconductor.

[0022] The first light L1 may be irradiated onto the first and second semiconductor portions 8F and 8S and the upper surface (growth suppression region SP) of the mask portion 5. The first light L1 may be irradiated onto the third region A3, the first region A1, and the second region A2. The second light L2 may include light of the first light L1 reflected by the upper surfaces of the first and second semiconductor portions 8F and 8S and light of the first light L1 reflected by the upper surface of the mask portion 5.

[0023] The ratio of the incident light intensity to the reflected light intensity on the upper surface of the semiconductor portion 8 (the reflectance of the semiconductor portion) may be different from the ratio of the incident light intensity to the reflected light intensity on the upper surface of the mask portion 5 (the reflectance of the mask portion). As described above, the reflectance in the third region A3 of the mask portion 5 is different from the reflectance in the first and second regions A1 and A2 of the mask portion 5. In the method for manufacturing a semiconductor substrate according to this embodiment, the reflectance (the reflectance of the semiconductor substrate), which is the ratio of the intensity of the second light L2 to the intensity of the first light L1, or the intensity of the second light L2 (the second light intensity) may be detected in time series.

[0024] In the template substrate TS, the thickness of the third region A3 in the mask portion 5 may be different from the thicknesses of the first region A1 and the second region A2. For example, the thickness of the third region A3 may be greater than the thicknesses of the first region A1 and the second region A2. Alternatively, the thickness of the third region A3 may be smaller than the thicknesses of the first region A1 and the second region A2.

[0025] In the mask portion 5, the constituent material of the third region A3 may be different from the constituent material of the first and second regions A1 and A2. For example, the third region A3 may contain a metal element, while the first and second regions A1 and A2 may not contain the metal element. The metal element may be resistant to the growth temperature during growth of the semiconductor portion 8, and may have a melting point of, for example, 1000°C or higher. Furthermore, in the mask portion 5, the surface material of the third region A3 may be a modified (surface-modified) surface material of the first and second regions A1 and A2.

[0026] 3, the first and second semiconductor portions 8F and 8S do not have to contact the third region A3. Alternatively, the first and second semiconductor portions 8F and 8S may contact the third region. For example, if the thickness of the third region A3 is large or if the third region A3 and the first and second regions A1 and A2 are in a flat positional relationship, the first and second semiconductor portions 8F and 8S may contact the third region A3.

[0027] Fig. 4 is a graph showing a schematic representation of the change over time in the intensity of the second light from the semiconductor substrate. Fig. 4 shows an example in which the wavelength of the first light L1 is 405 nm. Fig. 4 also shows a graph with a schematic shape to explain the main points of the change over time in the intensity of the reflected light. The light receiving unit of the detection device for detecting the intensity of the second light L2 is located above the semiconductor substrate 10 in the normal direction (see Fig. 11).

[0028] 4, first, initial growth of the semiconductor portion 8 is performed on the template substrate TS, starting from the seed region 4. During this initial growth period PR1, periodic fluctuations, so-called fringes (interference fringes), are observed in the temporal change in the intensity of the second light L2, corresponding to an increase in film thickness due to vertical growth from the seed region 4.

[0029] Generally, light with a wavelength of, for example, 405 nm is absorbed by GaN under the conditions of GaN growth temperatures (high temperatures of 1000°C or higher). Therefore, when a GaN layer is grown planarly on a flat substrate that does not include a mask pattern, no fringes are observed in the time change in the intensity of the reflected light. Conventionally, in in-situ observations during GaN film formation, light with a wavelength of 405 nm has been used to obtain information about the magnitude of light scattering, i.e., the surface state, based on the time change in the intensity of the light reflected from the surface after irradiating GaN.

[0030] In contrast, in the example shown in FIG. 4 , fringes are thought to occur due to interference of light reflected by the surface of the semiconductor portion 8 and the surface of the mask portion 5. In this embodiment, light of a wavelength (e.g., 405 nm) that is absorbed by the semiconductor portion 8 at the growth temperature is used, and the interference between the light reflected by the surface of the growing semiconductor portion 8 and the light reflected by the mask portion 5 is measured as fringes (the shape of the temporal change in a physical quantity such as reflectance). This makes it possible to monitor the growth state in the height direction (c-axis direction) regardless of the internal structure of the base substrate BS. The reflectance, which is the ratio of the intensity of the second light L2 to the intensity of the first light L1, may be acquired over time. In this case, the reflectance may fluctuate periodically (fringe occurrence).

[0031] Subsequently, at time TP1 when the semiconductor portion 8 reaches the desired film thickness during the initial growth period PR1, the growth conditions can be changed to initiate lateral growth of the semiconductor portion 8. During period PR2 during which the first and second semiconductor portions 8F and 8S grow laterally on the first region A1 and the second region A2, respectively, the intensity of the second light L2 may tend to decrease over time (expansion of the semiconductor portion 8). This tendency can be caused by factors such as differences in the reflectivity of the semiconductor portion 8 and the mask portion 5 with respect to the first light L1, or an inclined top surface of the semiconductor portion 8 (see FIG. 5 , described below). Furthermore, as the film thickness of the semiconductor portion 8 increases, fringes can be observed in the temporal change in the intensity of the second light L2. Based on these fringes, film thickness information can be obtained, allowing the growth rate of the film thickness to be monitored. As the lateral growth of the semiconductor portion 8 continues, the edge of the semiconductor portion 8 approaches the third region A3.

[0032] As shown in the example of FIG. 4 , the trend of the time change in the intensity of the second light L2 can be captured by calculating, for example, a regression line or a regression curve for the time change in the intensity (or reflectance) of the second light L2 observed in real time. The specific method for calculating the regression line or regression curve is not particularly limited. The trend of the time change in the intensity of the second light L2 refers to the trend of the long-term change in the intensity of the second light L2, which is different from the short-term fluctuation in intensity due to noise, the above-mentioned fringes, and the like. As shown in FIG. 4 , for example, the trend of the time change in the intensity of the second light L2 during the period PR2 can be represented by a regression line RL2.

[0033] In the example shown in FIG. 4 , the time point TP2 can be determined as the time point at which the change in the intensity of the second light L2 over time transitions from the state indicated by the regression line RL2 to the state indicated by the regression line RL3. The time point TP2 may be determined, for example, based on the occurrence of a short-term fluctuation in the intensity of the second light L2 over time that is different from the fringe period during the period PR2. Alternatively, the regression line RL3 may be determined based on the occurrence of a significant deviation (deviation) in the intensity from a virtual line (regression line RL2) obtained by averaging the change in the intensity of the second light L2 over the period PR2, and the time point TP2 may be determined as the intersection of the regression lines RL2 and RL3. Hereinafter, for convenience of explanation, a difference in the trend of the change in the intensity of the second light L2 over time before and after the time point TP2 will be referred to as a "trend change" occurring in the change in the intensity of the second light L2 over time. For example, time TP2 may be the time when the minimum value measured per unit period begins to increase. In this case, it can be said that a positive trend change occurred at time TP2. Alternatively, if a trend change occurs in the opposite direction to the example shown in FIG. 4 , time TP2 may be the time when the maximum value measured per unit period begins to decrease. In this case, it can be said that a negative trend change occurred at time TP2. In other words, if the value obtained by subtracting the slope of the regression line RL2 from the slope of the regression line RL3 before and after time TP2 is negative, it can be said that a negative trend change has occurred. Conversely, if the value obtained by subtracting the slope of the regression line RL2 from the slope of the regression line RL3 is positive, it can be said that a positive trend change has occurred. In the example shown in FIG. 4 , it can be said that a positive trend change has occurred at time TP2.

[0034] As described above, the position of the edge of the semiconductor portion 8 can be monitored by using an instrument for measuring the intensity of the second light L2 (reflected light) and a template substrate TS (growth substrate) having the third region A3. Specifically, a difference (trend change) in the trend of the time change in the intensity of the second light L2 may occur before and after time TP2, when the edge of the semiconductor portion 8 approaches the third region A3. By reading the difference in the trend of the time change in the intensity of the second light L2 before and after this time TP2, information about the position of the edge of the semiconductor portion 8 can be obtained in real time. Information about the growth rate of lateral overgrowth can also be obtained. This allows for more appropriate decisions to be made regarding changing the growth conditions or halting growth. As a result, the yield of manufacturing semiconductor substrates 10 including the semiconductor portion 8 can be improved.

[0035] For example, the growth of the first semiconductor portion 8F and the second semiconductor portion 8S can be stopped before or after the union of both semiconductor portions 8F and 8S by using the change in the intensity of the second light L2. Furthermore, the predetermined growth conditions can be changed depending on the timing at which a trend change in the intensity of the second light L2 appears. For example, the growth conditions can be changed at the beginning of the period PR3 after the time point TP2 so that the growth rate is slower than that during the period PR2.

[0036] In the example shown in FIG. 4 , the intensity of the second light L2 decreases over time during the period PR2. However, this is merely an example, and the intensity of the second light L2 may increase or remain constant over the period PR2. As long as the trends in the changes in the intensity of the second light L2 over time are different before and after the end of the semiconductor portion 8 reaches the third region A3, the specific relationship between the trends in the changes in the intensity of the second light L2 over time during the period PR2 and the trends in the changes in the intensity of the second light L2 over time during the period PR3 is not particularly limited. For example, the third region A3 may have a higher reflectivity than the first and second regions A1 and A2, or conversely, the third region A3 may have a lower reflectivity than the first and second regions A1 and A2. For example, if the reflectivity of the third region A3 is relatively higher than the first and second regions A1 and A2, a negative trend will occur in the changes in the intensity of the second light L2 over time when the end of the semiconductor portion 8 reaches the third region A3. In the example shown in FIG. 4, the reflectance of the third area A3 is relatively lower than that of the first and second areas A1 and A2.

[0037] In an embodiment of the present disclosure, the predetermined growth conditions may be changed based on a time change in the reflectance of the semiconductor substrate 10 (the ratio of the intensity of the second light L2 to the intensity of the first light L1) without being limited to a time change in the intensity of the second light L2. This also applies to the following description, and the case where the reflectance of the semiconductor substrate 10 is used can also be understood by referring to the above description. Hereinafter, a repeated description of the case where the reflectance of the semiconductor substrate 10 is used will be omitted, but in the following description, the term "intensity of the second light L2" can be appropriately replaced with "reflectance (the ratio of the intensity of the second light L2 to the intensity of the first light L1)."

[0038] FIG. 5 is a cross-sectional view showing an example configuration of a semiconductor substrate according to an embodiment of the present disclosure. As shown in FIG. 5 , the semiconductor substrate 10 may include an inclined region SA on the upper surface of the semiconductor portion 8. The inclined region SA can be formed on the upper surface of the semiconductor portion 8 by growing both ends of the semiconductor portion 8 thinner than the center portion. In this case, the reflected light L3 at the inclined region SA is tilted relative to the first light L1, reducing the luminous flux of the second light L2 detected by the detector. As a result, the intensity of the second light L2 decreases as the semiconductor portion 8 grows, as shown in the period PR2 in the graph of FIG. 4 .

[0039] 6 is a graph showing the relationship between the tilt angle of the tilted region SA and the reflectance. As shown in FIG. 6, for a certain wavelength of the first light L1, as the tilt angle of the tilted region SA increases, the (detected) reflectance decreases. This change in reflectance corresponds to a change in the intensity of the second light L2.

[0040] FIG. 7 is a cross-sectional view showing an example of the shape of a semiconductor portion having a sloped region. Regarding the semiconductor portion 8, the thickness of the portion above the opening K (center portion) is s1, the thickness of the edge is s2, the width of the opening K is s3, the distance from the opening K to the edge is s4, the slope angle of the sloped region SA is θ, and tan θ = (s1-s2) / s4. For example, s1 = 1 to 7 μm, s2 = 0.5 to 5 μm, s3 = 5 to 20 μm, s4 = 10 to 50 μm, and θ = 0.5 to 2.0 degrees can be used. The thickness of the mask portion 5 can be, for example, 1 nm to 5 μm or 1 nm to 700 nm. The growth-inhibiting region may be formed by a deposited mask, or a surface-modified surface can also be used as the growth-inhibiting region.

[0041] Furthermore, in the semiconductor substrate 10 according to an embodiment of the present disclosure, the growth inhibition region SP may further include a fourth region located between the first and second regions A1 and A2 and having a different optical reflectivity than the first and second regions A1 and A2. While specific examples of the fourth region will be described later, even when the first and second semiconductor portions 8F and 8S pass through the fourth region, a trend change may occur in the temporal change in the intensity of the second light L2. The growth rate of the lateral growth of the first and second semiconductor portions 8F and 8S can be estimated based on the trend change in the third region A3 and the fourth region. This facilitates calculation of the gap width. In one embodiment, the gap width of the first and second semiconductor portions 8F and 8S may be calculated over time, and the growth of the first and second semiconductor portions 8F and 8S may be stopped when the gap width reaches a predetermined value. The gap width when the growth of the first and second semiconductor portions 8F and 8S is stopped may be smaller than three times the width of each opening K.

[0042] Furthermore, in the semiconductor substrate 10 according to an embodiment of the present disclosure, the growth inhibition region SP may be a modified region on the surface of the base substrate BS. The first and second seed regions 4F and 4S may each be an unmodified region on the surface of the base substrate BS. For example, the third region A3 may contain a metal element having a melting point of 1000°C or higher, while the first and second regions A1 and A2 may not contain the metal element. The first and second regions A1 and A2 may be weakly modified regions on the surface of the base substrate BS, and the third region A3 may be a strongly modified region on the surface of the base substrate BS. The first and second regions A1 and A2 may be strongly modified regions on the surface of the base substrate BS, and the third region A3 may be a weakly modified region on the surface of the base substrate BS. The first and second regions A1 and A2 and the third region A3 may have different reflectivities due to the thicknesses of the modified layers being different from each other.

[0043] 3, the semiconductor substrate 10 may have a flat top surface that is not inclined. As the first and second semiconductor portions 8F and 8S grow on the mask portion 5, the reflectance of the semiconductor portion 8 becomes dominant. Therefore, for example, if the reflectance of the semiconductor portion 8 is greater than the reflectance of the mask portion 5, the reflectance of the semiconductor substrate 10 increases over time.

[0044] In this embodiment, light having a wavelength (e.g., 405 nm) absorbed by the semiconductor portion 8 at the growth temperature is used, and the growth state in the lateral direction (a-axis direction) can be monitored regardless of the internal structure of the base substrate BS by detecting the light reflected from the surface of the growing semiconductor portion 8 and the light reflected from the mask portion 5. The first light L1 may have a wavelength of 395 to 415 nm. The wavelength of light refers to the central wavelength at the spectral peak, and the first light L1 may, of course, have a certain degree of broadening in the spectral peak width. Note that the first light L1 may also be light having a wavelength (e.g., 633 nm or 950 nm) that transmits through nitride semiconductors at the growth temperature. The first light L1 may be spontaneous emission light using an LED (light emitting diode) or laser light.

[0045] The absorption coefficient of the semiconductor portion 8 for the first light L1 at a growth temperature (e.g., 1000° C.) may be 10 times or more greater than the absorption coefficient of the first light L1 at room temperature. The band gap of the semiconductor portion 8 at the growth temperature may be smaller than the band gap (3.4 eV in the case of GaN) of the semiconductor portion 8 at room temperature (e.g., 20° C.). The wavelength of the first light L1 may be set in accordance with the band gap of the semiconductor portion 8 at the growth temperature.

[0046] 8 is a plan view showing an example of a mask pattern. As shown in FIG. 8, the first and second openings K1 and K2 of the mask pattern 6 may function as growth initiation openings that expose the first and second seed regions 4F and 4S and initiate the growth of the first and second semiconductor portions 8F and 8S. The mask portion 5 of the mask pattern 6 may function as a selective growth mask (deposition suppression mask) that causes the semiconductor portion 8 to grow laterally. The openings K are portions of the mask pattern 6 where the mask portions 5 are not formed (non-formation portions), and may not be surrounded by the mask portions 5.

[0047] The mask pattern 6 may be formed above an underlayer (described later). The underlayer may be a seed layer or a buffer layer, or may be a multi-layer structure. In the opening K, the seed layer or the buffer layer may be exposed as a seed region 4 that serves as a growth starting point for the semiconductor portion 8. In addition, in one example of the template substrate TS, an underlayer may be locally formed within the opening K, and in this case, the mask pattern 6 may be formed directly on the surface of the base substrate BS.

[0048] The mask portion 5 may include an inorganic insulating film. The inorganic insulating film may be a silicon oxide film or a silicon nitride film. The material of the mask portion 5 may be silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), diamond-like carbon (DLC), silicon oxide (SiO ２ ), silicon oxynitride (SiON), etc. The mask portion 5 may be a single layer film made of these materials, or may be a multilayer film (laminated film) made of a combination of these materials.

[0049] The thickness of the mask portion 5 may be, for example, 1 nm or more and 2 μm or less. In the template substrate TS of this embodiment, the thickness of the mask portion 5 may be appropriately changed so as to have a third region A3 (reflectance change region) having a reflectance different from that of the first and second regions A1 and A2. The position of the third region A3 in the growth inhibition region SP is not particularly limited. Furthermore, multiple third regions A3 may exist in the growth inhibition region SP. By having multiple third regions A3, the position of the edge of the semiconductor portion 8 can be monitored more accurately and continuously. The above-mentioned fourth region may be one of the multiple third regions A3.

[0050] In the mask pattern 6, the openings K may have an elongated shape, the semiconductor portion 8 may include a nitride semiconductor, and a plurality of openings K may be periodically arranged in the <11-20> direction (a-axis direction) of the nitride semiconductor. The width of the openings K may be approximately 0.2 μm to 20 μm. The smaller the width of the openings K, the fewer the number of threading dislocations propagating from the openings K to the semiconductor portion 8. This also makes it easier to peel off the semiconductor portion 8 in a subsequent process (described below).

[0051] In the mask pattern 6, the semiconductor portion 8 may include a nitride semiconductor, and the first and second openings K1 and K2 may be aligned in the <11-20> direction (a-axis direction) of the nitride semiconductor, and the first and third openings K1 and K3 may be aligned in the <1-100> direction (m-axis direction) of the nitride semiconductor.

[0052] The width of the mask portion 5 may be 20 μm or more, or may be 20 μm or more and 200 μm or less, with the <11-20> direction (a-axis direction) of the nitride semiconductor being the width direction of the mask portion 5 and the opening K. The ratio of the thickness of the mask portion 5 to the width of the opening K may be 3.0 or less.

[0053] FIG. 9 is a cross-sectional view showing an example of the configuration of a base substrate. The base substrate BS is a substrate that serves as a support base (base) for various upper layers. The base substrate BS may have a main substrate 1, and the main substrate 1 may be a heterogeneous substrate having a different lattice constant from that of the semiconductor portion 8. The semiconductor portion 8 may include a GaN-based semiconductor, and the heterogeneous substrate, the main substrate 1, may be a silicon substrate. As the heterogeneous substrate, in addition to a silicon substrate, sapphire (Al２ O ３ ) substrate, silicon carbide (4H-SiC, 6H-SiC) substrate, etc. Examples of the surface orientation of the main substrate 1 are the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, and the 6H-SiC (0001) surface of a SiC substrate. These are merely examples, and any substrate and surface orientation that allows the semiconductor portion 8 to be grown by the ELO method may be used. Furthermore, a nitride semiconductor substrate (such as a GaN or AlN substrate), a ScMgAlO substrate, etc. may also be used as the base substrate BS.

[0054] The base substrate BS may have a main substrate 1 and an underlying portion UB located above the main substrate 1. The semiconductor portion 8 may grow from the upper surface (seed region 4) of the underlying portion UB exposed in the opening K. The underlying portion UB may include a nitride semiconductor. The base substrate BS may be configured as a free-standing single-crystal substrate (e.g., a wafer cut from a bulk crystal) of GaN, SiC, or the like, and a mask pattern 6 may be arranged on the single-crystal substrate.

[0055] 10 is a cross-sectional view showing an example of the configuration of the base portion. The base portion UB may include at least one of a buffer portion 2 and a seed portion 3. The base portion UB may be composed of the seed portion 3, or the base portion UB may be composed of the buffer portion 2 and the seed portion 3. The buffer portion 2 and the seed portion 3 may be formed over the entire surface of the base substrate BS, or may be formed in at least a part of the opening K.

[0056] The buffer section 2 can be made of a GaN-based semiconductor, AlN, SiC, or the like. The inclusion of the buffer section 2 can improve the crystallinity and flatness of the seed section 3. The buffer section 2 can be made of a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, an AlGaInN layer, or the like, which is formed at a low temperature. The thickness of the buffer section 2 is, for example, approximately 10 nm or more and 500 nm or less. In one embodiment of the present disclosure, for example, a portion of the formed buffer section 2 can be modified, and the unmodified region can be used as the seed section 3.

[0057] A nitride semiconductor (e.g., a GaN-based semiconductor) can be used as the seed portion 3. As one example, a GaN layer may be used to form the seed portion 3. The thickness of the seed portion 3 may be, for example, about 100 nm or more and 8 μm or less.

[0058] Furthermore, the template substrate TS may be provided with a buffer section 2 covering the mask pattern 6. For example, the buffer section 2 may be made of a highly reactive AlGaN film. In this case, the upper surface of the buffer section 2 (AlGaN film) includes a growth-inhibiting region SP that overlaps with the mask section 5 in a planar view, a first seed region 4F that overlaps with the first opening K1 in a planar view, and a second seed region 4S that overlaps with the second opening K2 in a planar view. On the upper surface of the buffer section 2 (the AlGaN film surface), the region located above the mask section 5 has low crystallinity and therefore functions as the growth-inhibiting region SP. On the other hand, the regions located above the first and second openings K1 and K2 (above the exposed portions of the base substrate BS) have high crystallinity and therefore function as the first and second seed regions 4F and 4S.

[0059] In the template substrate TS, the base portion UB may contain AlN. The surface of the base portion UB is an AlN layer, and by modifying (surface modifying) a portion of the AlN layer, the growth suppression region SP and the seed region 4 can be formed. Specific examples will be described later.

[0060] The template substrate TS may also have a raised portion (ridge portion) on its upper surface, in which case the seed region 4 may be located on the upper surface of the raised portion. By growing the semiconductor portion 8 starting from the raised portion, the semiconductor substrate 10 may have a gap between the growth suppression region SP and the semiconductor portion 8. This allows the semiconductor portion 8 to grow so that the edge of the semiconductor portion 8 passes above the third region A3 without colliding with the third region A3, even if the third region A3 has a shape that protrudes more than the first and second regions A1 and A2. Specific examples will be described later.

[0061] In this specification, a substrate in a state where a semiconductor portion 8 can be grown by the ELO method may be referred to as a selective growth substrate. The selective growth substrate may be a main substrate 1 on which a buffer portion 2 or a seed portion 3 is formed and further on which a mask pattern 6 is formed, or a single crystal substrate on which a mask pattern 6 is formed. A selective growth substrate on which a semiconductor portion 8 is formed is referred to as a semiconductor substrate 10 (semiconductor wafer, ELO wafer). In the semiconductor substrate 10, the mask pattern 6 (mask portion 5) may be removed after the semiconductor portion 8 is formed. The buffer portion 2 may be a buffer layer, the seed portion 3 may be a seed layer, and the underlayer portion UB may be an underlayer.

[0062] 11 is a schematic diagram illustrating the configuration of a semiconductor substrate manufacturing apparatus according to an embodiment of the present disclosure. As shown in FIG. 11 , the semiconductor substrate manufacturing apparatus 20 includes a stage SG on which a template substrate TS including a base substrate BS and a growth-inhibited region SP and a seed region 4 is mounted, a raw material supply device 22 that supplies raw materials for growing a semiconductor portion 8 on the template substrate TS, an optical device 23 that irradiates a semiconductor substrate 10 including the template substrate TS and the growing semiconductor portion 8 with a first light L1 and receives a second light L2 from the semiconductor substrate 10, and a control device 24 that controls the raw material supply device 22. The control device 24 may be capable of at least one of wired and wireless communication with the optical device 23.

[0063] The control device 24 changes the predetermined growth conditions for the first and second semiconductor portions 8F and 8S based on the information about the second light L2 before or after the first and second semiconductor portions 8F and 8S meet. "Based on the information about the second light L2" means, for example, whether a trend change has occurred in the temporal change in the intensity of the second light L2. Specifically, the control device 24 can control the supply of raw materials from the raw material supply device 22 in accordance with the set growth conditions. When stopping the growth of the first and second semiconductor portions 8F and 8S, the control device 24 may control the raw material supply device 22 to stop the supply of at least some of the raw materials.

[0064] The semiconductor substrate manufacturing apparatus 20 may be provided with a chamber 25 including a stage SG, a flow channel 27 passing through the chamber 25, and a heating device 26 that heats the chamber 25, and the semiconductor substrate 10 may be disposed in the flow channel 27. The control device 24 may determine the timing for stopping high-temperature heating (1000 degrees or higher) by the heating device 26 based on information about the second light L2. The optical device 23 may be located outside the chamber 25. The chamber 25 may be provided with a window 28 through which the first light L1 and the second light L2 pass.

[0065] The stage SG may rotate (with the axis of rotation being the axis normal to the template substrate TS). In Fig. 11, the source gas supply device 22 flows the source gas horizontally (in a direction parallel to the upper surface of the template substrate) into the flow channel 27 and exhausts the gas horizontally, but this is not limiting. The source gas may also flow vertically (in the direction normal to the template substrate TS).

[0066] When detecting a trend change based on the time change in the intensity of the second light L2, the control device 24 may instruct the raw material supply device 22 to stop supplying at least some of the raw materials (e.g., trimethylgallium when the semiconductor portion 8 is a GaN crystal). The control device 24 may also instruct the heating device 26 to stop high-temperature heating. The control device 24 may control the raw material supply device 22 not only based on the time change in the intensity of the second light L2, but also based on the reflectance, which is the ratio of the intensity of the second light L2 to the intensity of the first light L1.

[0067] The control device 24 may be configured to control at least one of the raw material supply device 22 and the heating device 26 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network, and this program and a recording medium on which this program is stored are also included in this embodiment.

[0068] 12 is a cross-sectional view showing a method for manufacturing a semiconductor substrate in Example 1. In Fig. 12, an underlying portion UB including a nitride semiconductor is formed on a main substrate 1, and a mask pattern 6 including a plurality of striped mask portions 5 is provided on the underlying portion UB. A template substrate TS includes a base substrate BS including a nitride semiconductor, and the first and second semiconductor portions 8F and 8S may also include nitride semiconductors.

[0069] In one example, the template substrate TS may include, on a base substrate BS, a mask pattern 6 including a mask portion 5 and two openings K (first and second openings K1 and K2) adjacent to each other via the mask portion 5. The upper surface of the mask portion 5 functions as a growth suppression region SP. Furthermore, portions of the base substrate BS exposed by the first and second openings K1 and K2 function as first and second seed regions 4F and 4S. The first and second openings K1 and K2 may have a tapered shape (a shape that narrows toward the base portion UB).

[0070] In Example 1, a recessed region is formed in part of the mask portion 5 between the first opening K1 and the second opening K2 to vary the thickness of the mask portion 5. The surface of this recessed region can be defined as the third region A3 in the growth suppression region SP. The width of the third region A3 is defined as WA3, and the recessed depth of the mask portion 5 in the third region A3 is defined as dA3. The third region A3 is formed at and around the position where the edges of the first and second semiconductor portions 8F and 8S meet as a result of lateral growth of adjacent first and second semiconductor portions 8F and 8S. The reflectance of the third region A3 differs from the reflectance of the first and second regions A1 and A2, and the difference in reflectance between them can be appropriately adjusted by changing the recessed depth dA3.

[0071] In Example 1, for example, an AlN layer serving as a buffer layer is formed to a thickness of 100 nm on the main substrate 1 using an MOCVD apparatus at a film formation temperature of 1000° C. Then, a GaN layer serving as a seed layer is formed to a thickness of about 3 nm on the buffer layer. This forms a base substrate BS having a nitride semiconductor film serving as an underlayer UB.

[0072] Next, the base substrate BS is removed from the MOCVD apparatus, and a silicon nitride film having a thickness of 200 nm is formed over the entire surface of the base substrate BS using a sputtering apparatus or an EB (Electron Beam Deposition) apparatus. Thereafter, the opening K is formed using a general photolithography technique. For example, the opening K can be formed by patterning a resist on the silicon nitride film and using a technique such as wet etching or dry etching. Alternatively, the silicon nitride film having the opening K may be formed by a lift-off method.

[0073] In Example 1, after forming the openings K, the third regions A3 are formed by separate patterning and etching, thereby forming the mask pattern 6 (stripe pattern). The mask portion 5 has a shape whose longitudinal direction is the m-axis direction of the semiconductor portion 8 containing a nitride semiconductor, and the pitch of the stripes of the growth inhibition regions SP of the mask portion 5 is set to 55 μm.

[0074] The recess depth dA3 of the third region A3 may be smaller than the film thickness of the first and second regions A1 and A2 of the mask portion 5. The recess depth dA3 of the third region A3 may be appropriately set so as to increase the difference in reflectance between the first and second regions A1 and A2 and the reflectance of the third region A3, as long as the underlying portion UB is not exposed. The third region A3 may be formed to extend along the longitudinal direction of the opening K, and may have a shape whose longitudinal direction is, for example, the m-axis direction of the semiconductor portion 8 containing a nitride semiconductor in a plan view. The width WA3 of the third region A3 may be, for example, 3 μm.

[0075] Then, for example, trimethylgallium (TMG) and ammonia (NH ３ The semiconductor portion 8 is grown on the mask pattern 6 by metal organic chemical vapor deposition (MOCVD) using the following (ELO method).

[0076] In Example 1, as shown in Figure 12, an initial growth portion 8p is formed above the base portion UB (seed region) exposed in the first and second openings K1 and K2. The growth conditions at this time are referred to as first conditions. The transition of the growth conditions (from the first conditions to the second conditions) begins immediately before the edge of the initial growth portion 8p rises above the upper surface of the mask portion 5 (the stage where it is in contact with the upper end of the side surface of the mask portion 5) or immediately after it rises above the upper surface of the mask portion 5.

[0077] In Example 1, the first conditions (conditions giving priority to vertical growth) were as follows: growth temperature (set temperature): 1100° C., growth pressure: 10 kPa, ammonia flow rate: 7.5 slm, trimethylgallium flow rate: 3 sccm. The second conditions (conditions giving priority to lateral growth) were as follows: growth temperature (set temperature): 1175° C., growth pressure: 10 kPa, ammonia flow rate: 7.5 slm, trimethylgallium flow rate: 11 sccm.

[0078] The initial growth portion 8p serves as the starting point for lateral growth of the semiconductor portion 8. The initial growth portion 8p can be formed to a thickness of, for example, 30 nm to 1000 nm, 50 nm to 400 nm, or 70 nm to 350 nm. By causing the initial growth portion 8p to grow laterally from a state in which it slightly protrudes from the mask portion 5, growth of the semiconductor portion 8 in the c-axis direction (thickness direction) is suppressed, allowing the semiconductor portion 8 to grow laterally at high speed with high crystallinity, and reducing raw material consumption. This allows a thin, wide, and low-defect semiconductor portion 8 (crystal of a nitride semiconductor such as GaN) to be formed at low cost.

[0079] Then, as described above, the intensity of the second light L2 is detected over time, and information about the positions of the edges of the first and second semiconductor portions 8F and 8S growing laterally on the first and second regions A1 and A2, respectively, is obtained based on the change in the intensity of the second light L2 over time. The point in time when the edges of the laterally growing first and second semiconductor portions 8F and 8S approach the third region A3 is identified, and the transition of the growth conditions (from the second conditions to the third conditions) is initiated at that point or at an appropriate timing thereafter. The third condition may be set as appropriate and may, for example, be a condition that stops the growth of the semiconductor portion 8 or a growth condition that slows the lateral growth of the semiconductor portion 8.

[0080] Of the semiconductor portion 8, the portion located above the initial growth portion 8p becomes a dislocation inheritance portion having many threading dislocations, and the portion above the mask portion 5 (wing portion) becomes a low defect portion YS having a threading dislocation density of 1 / 10 or less compared to the dislocation inheritance portion. A threading dislocation is a dislocation (defect) extending in the c-axis direction (<0001> direction) in the semiconductor portion 8. The threading dislocation density of the low defect portion YS is, for example, 5×10 ６ [pcs / cm ２ As will be described later, when an active section (active layer) including a light emitting section is formed above the semiconductor section 8, the light emitting section can be disposed above the low defect section YS (so as to overlap with the low defect section YS in plan view).

[0081] For the low-defect portion YS, the ratio of the size W1 in the a-axis direction to the thickness d1 (W1 / d1) can be set to, for example, 2.0 or more. Using the technique of Example 1, W1 / d1 can be set to 1.5 or more, 2.0 or more, 4.0 or more, 5.0 or more, 7.0 or more, or 10.0 or more. It has been found that setting W1 / d1 to 1.5 or more facilitates the subsequent division process of the semiconductor portion 8 (e.g., a division process in which the cross section becomes an m-plane). Furthermore, the internal stress of the semiconductor portion 8 is reduced, thereby reducing warpage of the semiconductor substrate 10.

[0082] The aspect ratio of the semiconductor portion 8 (ratio of size in the X1 direction (see FIG. 1 ) to thickness = WL / d1) can be 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more. Furthermore, by using the technique of Example 1, the ratio (WL / WK) of the size WL of the semiconductor portion 8 in the X1 direction to the width WK of the opening K can be 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more, thereby increasing the proportion of low-defect portions. The semiconductor portion 8 (including the initial growth portion 8 p) shown in FIG. 12 can be a nitride semiconductor crystal (e.g., a GaN crystal, an AlGaN crystal, an InGaN crystal, or an InAlGaN crystal).

[0083] Depending on the wavelength of the first light L1, the reflectance of the mask portion 5 (growth-inhibited region) is dominant in the substrate reflectance at the beginning of lateral growth, but as lateral growth progresses, the reflectance of the semiconductor portion 8 becomes dominant. Therefore, when the width of the mask portion 5 is large, the change in substrate reflectance also becomes large, improving the control accuracy of lateral growth. Therefore, the width of the mask portion 5 may be 20 μm or more, and may also be 30 μm or more, 50 μm or more, or 70 μm or more.

[0084] (Configuration example: when adjacent ELO layers are merged) Fig. 13 is a cross-sectional view showing the configuration of a semiconductor substrate in one configuration example of Example 1. The example shown in Fig. 13 shows an example in which, after the ends of the laterally growing first and second semiconductor portions 8F and 8S reach the third region A3, the lateral growth is continued while changing the growth conditions, causing the first and second semiconductor portions 8F and 8S to merge with each other.

[0085] In the example shown in FIG. 13 , the main substrate 1 is made of a material with a higher thermal expansion coefficient than the first and second semiconductor portions 8F and 8S at the deposition temperature of the first and second semiconductor portions 8F and 8S. The main substrate 1 may be, for example, a sapphire substrate. The base portion UB may be deposited on the sapphire substrate using a sputtering device (such as pulse sputter deposition (PSD) or pulse laser deposition (PLD)). For example, an AlN layer with a thickness of approximately 50 nm to 500 nm is formed on the sapphire substrate as a low-temperature buffer, and a GaN layer with a thickness of approximately 0.5 μm to 7 μm is formed on the AlN layer. The surface of this GaN layer is used as a seed region 4 for the growth of the semiconductor portion 8.

[0086] As described above, in one embodiment, a nitride semiconductor formed by sputtering at a low temperature of 600° C. or less can be used as the seed region 4. This makes it possible to reduce warping that occurs in the semiconductor substrate 10 (template substrate TS and semiconductor portion 8) due to stress in the base portion UB when the temperature is lowered from the film formation temperature of the semiconductor portion 8. When a sputtering apparatus is used to form the base portion UB, there are advantages such as low-temperature film formation and large-area film formation being possible, and cost reduction.

[0087] In the underlayer UB, a GaN layer does not have to be formed on the AlN layer, and in this case, the surface of the AlN layer may be used as the seed region 4 to grow the semiconductor portion 8. This allows the base substrate BS to be formed in a relatively short time, thereby reducing costs.

[0088] Next, a mask pattern 6 is formed on the AlN layer or GaN layer to obtain a template substrate TS. A semiconductor portion 8 is grown on the template substrate TS by ELO. In the example shown in FIG. 13 , adjacent first and second semiconductor portions 8F and 8S are joined to form a planar semiconductor portion 8SH with a relatively large surface area, thereby manufacturing a semiconductor substrate 10. By appropriately setting the third condition for lateral growth, it is possible to easily form a planar semiconductor portion 8SH with minimal surface irregularities. The joining occurs approximately at the center of the adjacent first and second openings K1 and K2 (the center of the mask portion 5, above the third region A3). In the planar semiconductor portion 8SH, a groove GV facing the third region A3 may be formed at the joining portion 80 where the first and second semiconductor portions 8F and 8S join together. The groove GV is formed below the joining portion 80 and may be approximately triangular in the cross-sectional view shown in FIG. 13 . Such a groove portion GV is formed by a change in the shape of the side facets when the first and second semiconductor portions 8F and 8S meet.

[0089] The semiconductor portion 8 is formed at a high temperature of approximately 900°C to 1200°C. The thermal expansion coefficient of sapphire is greater than that of GaN. Therefore, when a sapphire substrate is used for the main substrate 1, when the temperature is lowered to room temperature after the formation of the planar semiconductor portion 8SH, the planar semiconductor portion 8SH is subjected to compressive stress from the sapphire substrate in a direction parallel to the longitudinal direction of the opening K. Furthermore, because the planar semiconductor portion 8SH is formed by the mutual meeting of the first and second semiconductor portions 8F and 8S, it is also subjected to compressive stress in a direction perpendicular to the longitudinal direction of the opening K. When compressive stress occurs in the planar semiconductor portion 8SH in this way, cracks are less likely to occur in the planar semiconductor portion 8SH. Furthermore, when a groove GV is formed directly below the meeting portion 80, the groove GV relieves the stress. Therefore, the semiconductor substrate 10 can effectively reduce the possibility of cracks occurring in the planar semiconductor portion 8SH. Furthermore, in Example 1, the surface flatness of the planar semiconductor portion 8SH can be effectively improved by appropriately changing the growth conditions based on the information of the second light L2 at times such as when the ends of the first and second semiconductor portions 8F and 8S approach the third region A3, just before they meet, or just after they meet.

[0090] (Configuration example: when adjacent ELO layers are not merged) Fig. 14 is a cross-sectional view showing the configuration of a semiconductor substrate in one configuration example of Example 1. The example shown in Fig. 14 shows an example in which, after the ends of the laterally growing first and second semiconductor portions 8F and 8S reach the third region A3, the growth conditions are changed to stop the growth of the first and second semiconductor portions 8F and 8S before they merge.

[0091] 14, the main substrate 1 is made of a material with a smaller thermal expansion coefficient than the first and second semiconductor portions 8F and 8S at the deposition temperature of the first and second semiconductor portions 8F and 8S. For example, a Si substrate or a SiC substrate (4H-SiC, 6H-SiC, 3C-SiC, etc.) can be used as the main substrate 1. As in the above example, a base substrate BS having an underlayer portion UB is formed on the main substrate 1. A mask pattern 6 is then formed on the base substrate BS to obtain a template substrate TS. A semiconductor portion 8 is grown on the template substrate TS by the ELO method.

[0092] The thermal expansion coefficient of Si or SiC is smaller than that of GaN. Therefore, when a Si substrate or SiC substrate is used for the main substrate 1, tensile stress is applied to the semiconductor portion 8 when the temperature is lowered to room temperature after the semiconductor portion 8 is formed. The thicker the semiconductor portion 8, the greater the tensile stress that may occur in the semiconductor portion 8. In the example shown in FIG. 14 , growth is stopped before the adjacent first and second semiconductor portions 8F and 8S meet, creating a gap (gap) GP, which significantly reduces the tensile stress that occurs in the semiconductor portion 8. This effectively reduces the possibility of cracks occurring in the semiconductor portion 8.

[0093] In Example 1, the width of the gap GP can be easily adjusted by appropriately changing the growth conditions based on the information from the second light L2, for example, when the ends of the first and second semiconductor portions 8F and 8S approach the third region A3. The width of the gap GP can be, for example, 10 μm or less, 5 μm or less, 3 μm or less, or 2 μm or less. When the ends of the first and second semiconductor portions 8F and 8S approach each other, the side surfaces of the first and second semiconductor portions 8F and 8S may overhang the upper surface of the mask portion 5. This phenomenon can occur due to factors such as the fact that it becomes more difficult for the growth source material to flow into the gap GP when the width of the gap GP is narrowed.

[0094] Here, if the gap GP width differs for each batch of fabricated semiconductor substrates 10, the following problem occurs. That is, a difference in the gap GP width for each batch means that the width (of the upper surface) of the semiconductor portion 8 in the semiconductor substrate 10 differs. In a later process, an InGaN / GaN-MQW layer serving as a light-emitting layer is formed above the semiconductor portion 8, and the width of the semiconductor portion 8 is related to the consumption of raw materials (e.g., trimethylindium) during film formation. As a result, it was found that a difference in the gap GP width for each batch affects the consumption of raw materials during film formation, resulting in unstable emission wavelengths of the light-emitting elements produced. Furthermore, a difference in the gap GP width for each batch may make it difficult to stably proceed with the manufacturing process of LED elements or laser elements.

[0095] In contrast, in Example 1, the width of the gap GP can be more easily controlled accurately. Therefore, the possibility that the width of the gap GP varies from batch to batch can be effectively reduced. As a result, the above-mentioned problems can be made less likely to occur.

[0096] (Configuration Example: Element Manufacturing) Figure 15 is a cross-sectional view showing a method for manufacturing a semiconductor element in Example 1. In Figure 15, after preparing the semiconductor substrate 10 described above, the method includes the steps of forming a compound semiconductor portion 9 and electrodes E1 and E2 on the semiconductor substrate 10, bonding a stacked body EB including the semiconductor portion 8, the compound semiconductor portion 9, and the electrodes E1 and E2 to a support substrate SK via bonding layers H1 and H2, peeling off the base substrate BS, and singulating the support substrate SK into a plurality of support bodies ST to form semiconductor elements SD in which the stacked body EB is held on the support bodies ST. Before peeling off the base substrate BS, the mask portion 5 may be removed by wet etching or the like.

[0097] The semiconductor portion 8 may be an n-type semiconductor crystal. The compound semiconductor portion 9 may include a GaN-based semiconductor. The compound semiconductor portion 9 may include an active portion (e.g., an active layer such as a quantum well structure) and a p-type semiconductor portion, or may include an n-type semiconductor portion (e.g., a regrowth layer, an n-type contact layer) below the active portion. When the active portion of the compound semiconductor portion 9 includes a light-emitting portion, the light-emitting portion can be disposed above the low defect portion YS (so as to overlap with the low defect portion YS in a planar view). This can improve the light-emitting efficiency.

[0098] The electrode E1 located above the low-defect portion YS may be an anode, and the electrode E2 may be a cathode. The support substrate SK may have a conductive pad in contact with the bonding layer H1 and a conductive pad in contact with the bonding layer H2. The bonding layers H1 and H2 may be formed of a solder material. The longitudinally shaped laminate EB may be divided into multiple pieces (by cutting in the short direction) before, during, or after bonding to the support substrate SK. In this case, the dividing step may be performed by cleaving the semiconductor portion 8 and the compound semiconductor portion 9 (e.g., m-plane cleavage in which the cleavage plane is the m-plane). When forming a semiconductor laser element, the m-plane, which is the cleavage plane, may be end-face coated (formed with a reflector film). In FIG. 15 , the laminate EB is transferred from the base substrate BS to the support substrate SK, but this is not limited thereto. It may also be transferred from the base substrate BS to a tape or the like one or more times.

[0099] The semiconductor element SD may function as an LED (light emitting diode) element or a semiconductor laser element. The support ST may be a submount substrate. Example 1 includes electronic devices (e.g., lighting devices, laser devices, display devices, measuring devices, information processing devices, etc.) that have the semiconductor element SD.

[0100] [Example 2] Figure 16 is a cross-sectional view showing a method for manufacturing a semiconductor substrate in Example 2. As shown in Figure 16, the semiconductor substrate 10 in Example 2 may have a third region A3 and a fourth region A4 between the openings K (i.e., between the first and second seed regions 4F and 4S). The fourth region A4 has a different reflectance (light reflectance) from the first and second regions A1 and A2. In the example shown in Figure 16, the growth inhibition region SP of the template substrate TS includes a first region A1 adjacent to the first seed region 4F and a second region A2 adjacent to the second seed region 4S, as well as two third regions A3 and two fourth regions A4 located between the first and second regions A1 and A2. In the example shown in Figure 16, the third region A3 and the fourth region A4 are formed by forming a recessed region in part of the mask portion 5 to change the thickness of the mask portion 5.

[0101] 16, the growth suppression region SP includes an intermediate region AM located between two third regions A3 and two fourth regions A4, and a central region AC located between adjacent third regions A3 and fourth regions A4 and near the center of the first and second openings K1 and K2. The reflectances of the intermediate region AM and central region AC may be the same as the reflectances of the first and second regions A1 and A2. The intermediate region AM and central region AC may be aligned in height with the first and second regions A1 and A2.

[0102] The third region A3 and the fourth region A4 can be formed by forming an opening K in a mask layer on the base substrate BS and then performing separate patterning and etching. The third region A3 and the fourth region A4 may have the same reflectance. Hereinafter, the third region A3 and the fourth region A4 may be collectively referred to as the reflectance change region.

[0103] In the method for manufacturing the semiconductor substrate 10 in Example 2, the first and second semiconductor portions 8F and 8S and the upper surface (growth suppression region SP) of the mask portion 5 are irradiated with the first light L1, the intensity of the second light L2 is detected over time, and predetermined growth conditions can be changed based on the second light L2. Multiple trend changes occur in the change over time in the intensity of the second light L2.

[0104] 16 , when the lateral growth of the first and second semiconductor portions 8F and 8S is initiated, the end of the first semiconductor portion 8F grows laterally over the first region A1, then passes through the first third region A3, then passes through the intermediate region AM and the second third region A3 in that order, and reaches the central region AC. Also, the end of the second semiconductor portion 8S grows laterally over the second region A2, then passes through the first fourth region A4, then passes through the intermediate region AM and the second fourth region A4 in that order, and reaches the central region AC.

[0105] A trend change occurs in the time variation of the intensity of the second light L2 when the ends of the laterally growing first and second semiconductor portions 8F and 8S approach the reflectance change region, and when they pass through the reflectance change region and approach the intermediate region AM or the central region AC. This makes it easy to monitor the positions of the ends of the laterally growing first and second semiconductor portions 8F and 8S from a relatively early stage. Furthermore, the growth rate of the lateral growth can be calculated based on the position of the reflectance change region in the mask unit 5 and the timing at which the above-mentioned trend change occurs multiple times. This makes it possible to appropriately change the growth conditions based on information about the intensity of the second light L2, making it easier to control the gap width.

[0106] The number of third regions A3 and fourth regions A4 in the template substrate TS is not particularly limited. For example, the third region A3 may be located near the center of the first and second openings K1 and K2, and the fourth region A4 may be located between the third region A3 and the first and second openings K1 and K2. The specific configurations of the third region A3 and the fourth region A4 are not particularly limited. When the growth suppression region SP includes multiple third regions A3, various configurations of the third region A3 described in this specification can be combined. The fourth region A4 may have the same configuration as the various configurations of the third region A3 described in this specification. The third region A3 and the fourth region A4 may have different configurations from each other.

[0107] Example 3 FIG. 17 is a cross-sectional view showing the configuration of a semiconductor substrate according to Example 3. As shown in FIG. 17 , in a semiconductor substrate 10 according to Example 3, the mask portion 5 may include a first mask portion 51 and a second mask portion 52. The first mask portion 51 is located between the first opening K1 and the second opening K2 and has a flat surface in a cross-sectional view. The second mask portion 52 is located on the first mask portion 51 at the center thereof. In Example 3, the surface of the second mask portion 52 forms the third region A3 of the growth suppression region SP. The second mask portion 52 protrudes beyond the first mask portion 51, resulting in an overall convex shape in a cross-sectional view. As a result, the thickness of the third region A3 of the mask portion 5 is greater than the thicknesses of the first and second regions A1 and A2.

[0108] In Example 3, in the mask portion 5, the constituent material of the first mask portion 51 and the constituent material of the second mask portion 52 may be the same as or different from each other. The refractive index of the second mask portion 52 may be different from that of the first mask portion 51. After the first mask portion 51 is formed, the second mask portion 52 can be additionally formed on the first mask portion 51. Alternatively, the second mask portion 52 may be formed integrally with the first mask portion 51. In this case, the first mask portion 51 is formed thick, and then etched so that the portions of the first and second regions A1 and A2 are lower than the third region A3, thereby forming the mask portion 5 having a convex shape in cross section.

[0109] When the two adjacent first and second semiconductor portions 8F and 8S grow laterally and reach the third region A3, a trend change occurs in the temporal change in the intensity of the second light L2. By combining materials with different refractive indices for the first mask portion 51 and the second mask portion 52, the difference in reflectance between them can be increased. This makes the trend change clearer, making it easier to identify the point in time when the ends of the first and second semiconductor portions 8F and 8S reach the third region A3.

[0110] (Configuration Example: Material of Second Mask Portion) The second mask portion 52 may be formed of a metal material. In this case, the third region A3 may contain a metal element, while the first and second regions A1 and A2 may not contain the metal element. The second mask portion 52 can be formed so as not to serve as a growth starting point for the semiconductor portion 8 during growth. As this metal material, a type of metal that has a different reflectivity than the first mask portion 51 for the wavelength of the first light L1 at the film formation temperature of the semiconductor portion 8 can be used. The metal element contained in the second mask portion 52 may have a melting point of 1000°C or higher. This can improve the heat resistance (thermal stability) of the second mask portion 52 at the film formation temperature of the semiconductor portion 8.

[0111] Examples of metal elements contained in the second mask portion 52 include titanium, zirconium, hafnium, niobium, tantalum, molybdenum, vanadium, yttrium, osmium, chromium, cobalt, gold, platinum, tungsten, etc. The metal film constituting the second mask portion 52 may be a single layer film of any of these metal elements, or may be a multilayer film of one or more metal elements selected from this group.

[0112] (Configuration Example: Embedded Shape) Fig. 18 is a cross-sectional view showing the configuration of a semiconductor substrate in one configuration example of Example 3. As shown in Fig. 18, in the semiconductor substrate 10 in one configuration example, the mask pattern 6 may have an embedded portion 53 located inside the mask portion 5. The embedded portion 53 is located in the center of the mask portion 5, between the mask portion 5 and the base substrate BS.

[0113] After forming the embedded portion 53 on the base substrate BS, the mask portion 5 can be formed. A portion of the upper surface of the mask portion 5 that overlaps with the embedded portion 53 in a plan view can be defined as a third region A3. The mask portion 5 has a convex shape as a whole in a cross-sectional view, and in the mask portion 5, the height of the third region A3 (the distance from the surface of the base substrate BS) is greater than the heights of the first and second regions A1 and A2.

[0114] The constituent material of the buried portion 53 may be the same as or different from the constituent material of the mask portion 5. The constituent material of the buried portion 53 is not particularly limited, and may be the same type of material as that used for the mask portion 5, or may be a metallic material. Furthermore, the buried portion 53 may be formed using a type of material on which the semiconductor portion 8 can grow. This is because, if the buried portion 53 is covered with the mask portion 5, the buried portion 53 does not act as a growth starting point for the semiconductor portion 8 when the semiconductor portion 8 is formed.

[0115] (Other Examples) In another example, the second mask portion 52 or the embedded portion 53 may be located at a position overlapping the first and second regions A1 and A2 in a plan view, and the surface of the first mask portion 51 may be the third region A3 (not shown). In this case, the position of the third region A3 may be lower than the first and second regions A1 and A2, and the mask portion 5 may have a concave shape as a whole in a cross-sectional view.

[0116] Example 4 Figure 19 is a cross-sectional view showing the configuration of a semiconductor substrate in Example 4. As shown in Figure 19, in a semiconductor substrate 10 in Example 4, the mask portion 5 may include a first mask portion 51 and a modified portion 54. The modified portion 54 can be formed by modifying a portion of the surface of the first mask portion 51, and in the example shown in Figure 19, it is located in the center of the mask portion 5 in a cross-sectional view. In Example 4, the surface of the modified portion 54 forms the third region A3 of the growth suppression region SP. The surface material of the third region A3 may be a modified version of the surface material of the first and second regions A1 and A2.

[0117] In the mask portion 5, the third region A3 may be in a flat positional relationship with the first and second regions A1 and A2, and the thickness of the third region A3 may be approximately the same as the thickness of the first and second regions A1 and A2.

[0118] After the first mask portion 51 is formed, the first mask portion 51 can be partially modified, for example, by ion implantation, oxidation, nitriding, etc. The specific modification may be any process as long as the refractive index of the modified portion 54 is different from that of the first mask portion 51, and there are no particular limitations on the specific process.

[0119] For example, first, a first mask portion 51 having an opening K is formed on the base substrate BS. Next, a resist is patterned on the seed region 4 and the first mask portion 51. Thereafter, by exposing the first mask portion 51 to oxygen plasma, for example, if the material of the first mask portion 51 is SiN, the portion of the first mask portion 51 that is not covered with the resist is oxidized to SiON or SiO ２ In this way, SiN can be converted into SiON or SiO ２The oxidized portion can be used as the modified portion 54, and the modified portion 54 has a refractive index different from that of the non-oxidized portion (SiN). Therefore, the surface of the modified portion 54 can be used as the third region A3.

[0120] When the mask portion 5 is observed with an optical microscope, the modified portion 54 exhibits a different color from the first mask portion 51. In other words, it can be confirmed that the modified portion 54 has a different reflection spectrum from the first mask portion 51. For example, when the wavelength of the first light L1 is set to 405 nm or 630 nm and the first light L1 is irradiated onto the mask portion 5 made of SiN, and the reflection spectrum is measured, it is confirmed that the reflectance is different between the first mask portion 51 and the modified portion 54 (i.e., between the first and second regions A1 and A2 and the third region A3).

[0121] Furthermore, the semiconductor portion 8 was grown on the template substrate TS having the mask portion 5 while irradiating it with the first light L1 and detecting the intensity of the second light L2 over time. It was confirmed that a trend change occurred in the temporal change in the intensity of the second light L2 when the ends of the laterally growing first and second semiconductor portions 8F and 8S approached the third region A3 corresponding to the modified portion 54.

[0122] The mask portion 5 may include a plurality of modified portions 54 formed on the first mask portion 51. The position and number of the plurality of modified portions 54 are not particularly limited. The modified portions 54 may be formed in a portion of the mask portion 5 that protrudes beyond the first mask portion 51 so that the height of the third region A3 is greater than the heights of the first and second regions A1 and A2. In another example, the modified portions 54 may be located at positions that overlap the first and second regions A1 and A2 in a plan view. In this case, the surface of the first mask portion 51 may serve as the third region A3 (not shown).

[0123] (Configuration Example: Depressed Shape) FIG. 20 is a cross-sectional view showing the configuration of a semiconductor substrate in one configuration example of Example 4. As shown in FIG. 20 , in the semiconductor substrate 10 in one configuration example, a recessed region may be formed in a part of the mask portion 5 between the first opening K1 and the second opening K2, and the recessed region may be modified to form a modified portion 54. Furthermore, the mask portion 5 may have the aforementioned second mask portion 52 formed in the recessed region. This makes it easier to increase the reflectance difference between the first and second regions A1 and A2 and the third region A3.

[0124] [Example 5] Figure 21 is a cross-sectional view showing the configuration of a semiconductor substrate in Example 5. As shown in Figure 21, in a semiconductor substrate 10, the seed region 4 is located above the growth inhibition region SP, and the semiconductor portion 8 may have a base portion B located on the seed region 4 and a wing portion F connected to the base portion B and facing the growth inhibition region SP via a gap J. In the semiconductor substrate 10, gaps J may be located between the growth inhibition region SP and each of the first and second semiconductor portions 8F and 8S. The template substrate TS may have a mask portion 5 including a first mask portion 51 and a second mask portion 52, and an opening K that functions as the seed region 4. In Example 5, the surface of the first mask portion 51 may be the first and second regions A1 and A2, and the surface of the second mask portion 52 may be the third region A3.

[0125] 21 , the template substrate TS has a ridge portion R on its upper surface side, and the base portion UB may be included in the ridge portion R. The upper surface of the ridge portion R may be made up of the base portion UB, and the side surface of the ridge portion R may be made up of the first mask portion 51. The main substrate 1 may include a protrusion portion Q on its upper surface side, and the base portion UB may be located on the protrusion portion Q.

[0126] Even when the wing portions F grow so as to face the growth-suppressed region SP across the gap J, the positions of the ends of the first and second semiconductor portions 8F and 8S can be monitored based on information about the intensity of the second light L2. Furthermore, even when the third region A3 is located above the first and second regions A1 and A2, the ends of the laterally growing first and second semiconductor portions 8F and 8S pass above the third region A3, so that the first and second semiconductor portions 8F and 8S do not come into contact with the third region A3. This makes it easier to improve the quality of the wing portions F in the first and second semiconductor portions 8F and 8S.

[0127] (Configuration Example: Protuberance) In one configuration example, in the semiconductor substrate 10, the seed region 4 may be located below the growth inhibition region SP. In this case, for example, after initially growing the semiconductor portion 8 from the seed region 4 to form a protuberance, a growth inhibition film is formed in contact with the protuberance. The semiconductor portion 8 can be further grown laterally, using the corner where the top surface and side surface of the protuberance intersect as the growth starting point. As a result, the wing portion F grows so as to face the growth inhibition region SP across the gap J.

[0128] Sixth Embodiment FIG. 22 is a cross-sectional view showing the configuration of a semiconductor substrate according to a fifth embodiment. As shown in FIG. 22 , in a semiconductor substrate 10 according to the sixth embodiment, an underlying portion UB includes a first underlying portion UB1 and a second underlying portion UB2. The first underlying portion UB1 is located on a main substrate 1, and the second underlying portion UB2 can be formed by modifying a portion of the surface of the first underlying portion UB1. The semiconductor substrate 10 also includes a second mask portion 52 located on the second underlying portion UB2 in a cross-sectional view. In the example shown in FIG. 22 , the upper surfaces of the second underlying portion UB2 and the second mask portion 52 can be used as a growth suppression region SP, and the surface of the second mask portion 52 can be used as a reflectance-changing region. In the semiconductor substrate 10, the surface of the first base portion UB1 can be the seed region 4 (first and second seed regions 4F and 4S), the surface of the second base portion UB2 can be the first and second regions A1 and A2, and the surface of the second mask portion 52 can be the third region A3.

[0129] The modification (surface modification) may involve changing at least one of the contained elements and the crystalline structure of the surface of the first underlayer portion UB1, and at least one of the contained elements and the crystalline structure may be different between the seed region 4 and the first and second regions A1 and A2. The second underlayer portion UB2 may be polycrystalline or amorphous. The first and second regions A1 and A2 may have a higher proportion of polycrystalline or amorphous phase than the seed region 4.

[0130] The first and second regions A1 and A2 may have a higher impurity concentration than the seed region 4, and this impurity concentration may be an oxygen concentration or an argon concentration. At least one element of oxygen (O), silicon (Si), and carbon (C) that is incorporated near the surfaces of the first and second regions A1 and A2 (for example, to a depth of about 0 to 5 nm) in the process of forming the second underlayer portion UB2 may enhance the growth suppression function.

[0131] There are no particular limitations on the specific method for forming the second underlayer portion UB2. For example, a part of the surface of the first underlayer portion UB1 can be modified by performing plasma treatment, annealing treatment, impurity ion implantation treatment, or the like.

[0132] For example, in the plasma treatment, a resist is patterned on the first base portion UB1, and the exposed surface of the first base portion UB1 is irradiated with argon plasma to modify the surface, thereby forming the second base portion UB2. Various types of plasma or mixed plasma can be used for the plasma treatment.

[0133] For example, in the annealing process, a resist is patterned on the first base portion UB1, a coating (e.g., a SiN film) is formed to cover the resist and the first base portion UB1, and the resist is lifted off. After that, a heat treatment is performed at, for example, 1000°C. The coating is then removed. This allows the portion of the first base portion UB1 exposed from the coating to be used as the seed region 4, and allows the second base portion UB2 to be formed in the portion of the first base portion UB1 that was covered by the coating. This is because the heat treatment causes an interdiffusion phenomenon between the coating and the first base portion UB1. If the coating is formed by sputtering, the heat treatment can be omitted.

[0134] For example, in the impurity ion implantation process, a resist is patterned on the first base portion UB1, and impurity ions are embedded in the exposed surface of the first base portion UB1 to modify the surface, thereby forming the second base portion UB2. Examples of impurities include Si, Fe (iron), and Mg (magnesium).

[0135] For example, the first underlying portion UB1 may contain AlN, and the second underlying portion UB2 may contain AlON. Alternatively, the first underlying portion UB1 may contain AlScN (aluminum scandium nitride), and the second underlying portion UB2 may contain AlScON (aluminum scandium oxynitride).

[0136] In Example 6, the growth of the semiconductor portion 8 can be initiated from the seed region 4, which is an exposed portion of the first underlayer portion UB1. The first and second regions A1 and A2, which are the surface of the second underlayer portion UB2, function as selective growth masks (deposition suppression masks), allowing the semiconductor portion 8 to grow laterally.

[0137] (Configuration Example: Strong Modification) FIG. 23 is a cross-sectional view showing the configuration of a semiconductor substrate in a configuration example of Example 6. As shown in FIG. 23 , in the semiconductor substrate 10 in this configuration example, the base portion UB may include a third base portion UB3 in addition to the first base portion UB1 and the second base portion UB2. The third base portion UB3 can be formed by further modifying the second base portion UB2. In the example shown in FIG. 23 , the third base portion UB3 is located in the center between the first seed region 4F and the second seed region 4S, and the surface of the third base portion UB3 can be used as the reflectance modification region. In the semiconductor substrate 10, the surface of the first base portion UB1 can be the seed region 4 (first and second seed regions 4F and 4S), the surface of the second base portion UB2 can be the first and second regions A1 and A2, and the surface of the third base portion UB3 can be the third region A3.

[0138] The surface material of the third region A3 may be a modified (surface-modified) surface material of the first and second regions A1 and A2. That is, the first and second regions A1 and A2 may be weakly modified regions of the surface of the base substrate BS, and the third region A3 may be a strongly modified region of the surface of the base substrate BS. In the foundation portion UB, the second foundation portion UB2 and the third foundation portion UB3 may have different thicknesses, so that the first and second regions A1 and A2 and the third region A3 may have different reflectances.

[0139] There is no particular limitation on the specific method for forming the third underlayer portion UB3. For example, a part of the surface of the second underlayer portion UB2 can be further modified by performing a plasma treatment, an annealing treatment, an implantation treatment of impurity ions, or the like.

[0140] 24 is a cross-sectional view showing the configuration of a semiconductor substrate according to another example of the sixth embodiment. As shown in FIG. 24 , the second base portion UB2 is located in the center between the first seed region 4F and the second seed region 4S, and the surface of the second base portion UB2 may be used as a reflectance-modified region. In the semiconductor substrate 10, the surface of the first base portion UB1 may serve as the seed region 4 (the first and second seed regions 4F and 4S), the surface of the third base portion UB3 may serve as the first and second regions A1 and A2, and the surface of the second base portion UB2 may serve as the third region A3. In this case, the first and second regions A1 and A2 may be strongly modified regions on the surface of the base substrate BS, and the third region A3 may be a weakly modified region on the surface of the base substrate BS.

[0141] The base portion UB may include a plurality of third base portions UB3. The positions and the number of the plurality of third base portions UB3 are not particularly limited.

[0142] [Example 7] Figure 25 is a cross-sectional view showing the configuration of a template substrate in Example 7. As shown in Figure 25, the template substrate TS in Example 7 has a substrate modifying portion 1A partially formed on the surface of the main substrate 1 and a base portion UB partially located on the main substrate 1. The base portion UB may be located on the surface of the main substrate 1 where the substrate modifying portion 1A is not formed. Furthermore, the semiconductor substrate 10 has a second mask portion 52 located on the substrate modifying portion 1A in a cross-sectional view. In the example shown in Figure 25, the surface of the second mask portion 52 can be used as a reflectance changing region. In the semiconductor substrate 10, the surface of the base portion UB can be the seed region 4 (first and second seed regions 4F and 4S), the surface of the substrate modifying portion 1A can be the first and second regions A1 and A2, and the surface of the second mask portion 52 can be the third region A3.

[0143] For example, a base portion UB is formed on a main substrate 1 (silicon substrate, silicon carbide substrate), resist is patterned on the base portion UB, and the portions of the base portion UB not covered by the resist are removed. Then, a substrate modified portion 1A can be formed by performing a thermal oxidation process on the exposed surface of the main substrate 1. The resist is then removed, and a second mask portion 52 is formed to obtain a template substrate TS. The substrate modified portion 1A can also be formed by a nitriding process instead of the thermal oxidation process. Alternatively, the substrate modified portion 1A can be formed by performing a plasma process, an annealing process, an impurity ion implantation process, or the like on the exposed surface of the main substrate 1. Instead of providing the second mask portion 52, the third region A3 can be formed by further modifying the substrate modified portion 1A.

[0144] 26 is a schematic diagram showing the configuration of a semiconductor substrate manufacturing apparatus in Example 8. A semiconductor substrate manufacturing apparatus 20 in Example 8 includes an imaging device 29 that images the surface (top surface) of a semiconductor substrate 10 including a template substrate TS and a semiconductor portion 8 under growth. The imaging device 29 may irradiate the semiconductor substrate 10 with first light L1 (illumination light for imaging) and receive second light L2 (light from the mask portion 5 and light from the semiconductor portion 8) from the semiconductor substrate 10.

[0145] The control device 24 uses the image transmitted from the imaging device 29 as information about the second light L2 to change the predetermined growth conditions for the first and second semiconductor portions 8F and 8S before or after the first and second semiconductor portions 8F and 8S meet. For example, by making the third region A3 a different color from the first and second regions A1 and A2, it is possible to identify the point in time when the ends of the laterally growing first and second semiconductor portions 8F and 8S approach the third region A3, based on the image transmitted from the imaging device 29. The greater the difference in reflectivity between the third region A3 and the first and second semiconductor portions 8F and 8S with respect to the first light L1, the easier it is to identify the positions of the ends of the laterally growing first and second semiconductor portions 8F and 8S.

[0146] [Additional Notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-described embodiments and examples. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments and examples are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure.

[0147] [Summary] A method for manufacturing a semiconductor substrate in aspect 1 of the present disclosure includes the steps of: preparing a template substrate having a growth-inhibition region and first and second seed regions adjacent to each other via the growth-inhibition region, wherein the growth-inhibition region includes a first region adjacent to the first seed region and a second region adjacent to the second seed region, and a third region located between the first and second regions and having a different optical reflectivity from the first and second regions; growing a first semiconductor portion and a second semiconductor portion above the growth-inhibition region under predetermined growth conditions; irradiating first light onto at least the third region of the template substrate and the semiconductor substrate including the first semiconductor portion and the second semiconductor portion; and changing the predetermined growth conditions based on second light, which is reflected light from the semiconductor substrate.

[0148] In the method for manufacturing a semiconductor substrate in aspect 2 of the present disclosure, in the method for manufacturing a semiconductor substrate in aspect 1, the growth of the first semiconductor portion and the second semiconductor portion is stopped before the first semiconductor portion and the second semiconductor portion meet by a step of changing the predetermined growth conditions.

[0149] In a third aspect of the present disclosure, in the method for manufacturing a semiconductor substrate, in the first or second aspect, the first region, the third region, and the second region are positioned side by side in a first direction, and the third region is narrower than the first and second regions in a cross-sectional view including the first direction.

[0150] The method for manufacturing a semiconductor substrate in aspect 4 of the present disclosure is, in any one of aspects 1 to 3, wherein the second light includes reflected light of the first light from the top surfaces of the first and second semiconductor portions and reflected light of the first light from the growth inhibition region.

[0151] A method for manufacturing a semiconductor substrate in aspect 5 of the present disclosure is, in any one of aspects 1 to 4, a fourth region located between the first and second regions and having a different optical reflectivity from the first and second regions in the growth inhibition region.

[0152] A method for manufacturing a semiconductor substrate in aspect 6 of the present disclosure is, in any one of aspects 1 to 5, a method for stopping the growth of both the first semiconductor portion and the second semiconductor portion before or after they combine using a change in the intensity of the second light.

[0153] A method for manufacturing a semiconductor substrate according to a seventh aspect of the present disclosure is any one of the first to sixth aspects, wherein the predetermined growth conditions are changed in accordance with a timing at which a trend change appears in the intensity of the second light.

[0154] A method for manufacturing a semiconductor substrate according to aspect 8 of the present disclosure is, in any one of aspects 1 to 7, wherein the template substrate includes a base substrate including a nitride semiconductor, and the first and second semiconductor portions include nitride semiconductors.

[0155] In a ninth aspect of the present disclosure, the method for manufacturing a semiconductor substrate in the eighth aspect is such that the template substrate has a mask pattern on the base substrate, the mask pattern including a mask portion and two adjacent openings interposed between the mask portion, the mask portion functions as the growth inhibition region, and the portions of the base substrate exposed by the two openings function as the first and second seed regions.

[0156] A tenth aspect of the present disclosure provides the method for manufacturing a semiconductor substrate according to the ninth aspect, wherein the thickness of the third region of the mask portion is different from the thicknesses of the first and second regions.

[0157] In an eleventh aspect of the present disclosure, in the method for manufacturing a semiconductor substrate according to the ninth or tenth aspect, in the mask portion, a constituent material of the third region is different from a constituent material of the first and second regions.

[0158] A method for manufacturing a semiconductor substrate in aspect 12 of the present disclosure is, in any one of aspects 9 to 11, a method in which the third region contains a metal element having a melting point of 1000°C or higher, and the first and second regions do not contain the metal element.

[0159] A thirteenth aspect of the present disclosure provides the method for manufacturing a semiconductor substrate according to the ninth aspect, wherein the surface material of the third region is obtained by modifying the surface materials of the first and second regions.

[0160] A fourteenth aspect of the present disclosure provides a method for manufacturing a semiconductor substrate in any one of the ninth to thirteenth aspects, wherein the first and second semiconductor portions are not in contact with the third region.

[0161] A fifteenth aspect of the present disclosure provides a method for manufacturing a semiconductor substrate in any one of the ninth to thirteenth aspects, wherein the first and second semiconductor portions are in contact with the third region.

[0162] A method for manufacturing a semiconductor substrate in aspect 16 of the present disclosure is, in aspect 8, wherein the growth inhibition region is a modified region of the base substrate surface, and the first and second seed regions are each an unmodified region of the base substrate surface.

[0163] A seventeenth aspect of the present disclosure provides a method for manufacturing a semiconductor substrate according to the sixteenth aspect, wherein the third region contains a metal element having a melting point of 1000° C. or higher, and the first and second regions do not contain the metal element.

[0164] In aspect 18 of the present disclosure, the method for manufacturing a semiconductor substrate is the same as aspect 16, wherein the first and second regions are weakly modified regions of the base substrate surface, and the third region is a strongly modified region of the base substrate surface.

[0165] A method for manufacturing a semiconductor substrate in aspect 19 of the present disclosure is the same as aspect 16, wherein the first and second regions are strongly modified regions of the base substrate surface, and the third region is a weakly modified region of the base substrate surface.

[0166] A twenty-first aspect of the present disclosure provides a method for manufacturing a semiconductor substrate in any one of the eighth to nineteenth aspects, wherein the base substrate has a main substrate and an underlayer located on the main substrate and including the nitride semiconductor.

[0167] A twenty-first aspect of the present disclosure provides a method for manufacturing a semiconductor substrate according to the twenty-first aspect, wherein the underlayer contains AlN.

[0168] A twenty-second aspect of the present disclosure provides a method for manufacturing a semiconductor substrate in any one of the first to twenty-first aspects, wherein the first light has a wavelength of 395 to 415 nm.

[0169] The semiconductor substrate manufacturing apparatus according to aspect 23 of the present disclosure performs each step of the semiconductor substrate manufacturing method according to any one of aspects 1 to 22.

[0170] The template substrate in aspect 24 of the present disclosure is a template substrate for growing a nitride semiconductor, and has a growth-inhibition region and first and second seed regions adjacent to each other via the growth-inhibition region, and the growth-inhibition region includes a first region adjacent to the first seed region, a second region adjacent to the second seed region, and a third region located between the first and second regions and having a different optical reflectivity from the first and second regions.

[0171] A semiconductor substrate in aspect 25 of the present disclosure comprises the template substrate of aspect 24, a first semiconductor portion located above the first seed region and the growth inhibition region, and a second semiconductor portion located above the second seed region and the growth inhibition region.

[0172] A semiconductor substrate according to a twenty-sixth aspect of the present disclosure is the twenty-fifth aspect of the present disclosure, wherein a gap is located between the growth inhibition region and each of the first semiconductor portion and the second semiconductor portion.

[0173] REFERENCE SIGNS LIST 1 Main substrate 2 Buffer portion 3 Seed portion 4 Seed region 4F First seed region 4S Second seed region 5 Mask portion 6 Mask pattern 8 Semiconductor portion 8F First semiconductor portion 8S Second semiconductor portion 9 Compound semiconductor portion 10 Semiconductor substrate 20 Semiconductor substrate manufacturing apparatus 51 First mask portion 52 Second mask portion 53 Buried portion 54 Modified portion A1 First region A2 Second region A3 Third region A4 Fourth region K Opening L1 First light L2 Second light UB Base portion UB1 First base portion UB2 Second base portion UB3 Third base portion

Claims

1. A step of preparing a template substrate having a growth-inhibiting region and first and second seed regions adjacent to each other via the growth-inhibiting region, wherein the growth-inhibiting region includes a first region adjacent to the first seed region and a second region adjacent to the second seed region, and a third region located between the first and second regions and having a different light reflectance from the first and second regions, A step of growing a first semiconductor portion and a second semiconductor portion above the growth suppression region under predetermined growth conditions, A step of irradiating at least the third region of the template substrate and the semiconductor substrate including the first semiconductor portion and the second semiconductor portion with first light, A method for manufacturing a semiconductor substrate, comprising the step of changing predetermined growth conditions based on a second light which is reflected light from the semiconductor substrate.

2. A method for manufacturing a semiconductor substrate according to claim 1, wherein the growth of the first semiconductor portion and the second semiconductor portion is stopped before the first semiconductor portion and the second semiconductor portion come together by the step of changing the predetermined growth conditions.

3. The first region, the third region, and the second region are located side by side in the first direction. The method for manufacturing a semiconductor substrate according to claim 1, wherein the third region is narrower in width than the first and second regions in a cross-sectional view including the first direction.

4. The method for manufacturing a semiconductor substrate according to claim 1, wherein the second light includes the reflected light from the upper surfaces of the first and second semiconductor portions of the first light and the reflected light from the growth-inhibiting region of the first light.

5. The method for manufacturing a semiconductor substrate according to claim 1, wherein the growth-inhibiting region includes a fourth region located between the first and second regions, on the side of the second region that is closer to the third region than the third region, and having a different light reflectance from the first and second regions.

6. A method for manufacturing a semiconductor substrate according to claim 1, wherein the predetermined growth conditions are changed based on the timing at which a trend change appears in the intensity of the second light.

7. The template substrate includes a base substrate containing a nitride semiconductor, The first and second semiconductor parts include a nitride semiconductor, The template substrate comprises a mask pattern located on the base substrate, including a mask portion and two adjacent openings separated by the mask portion. The mask portion functions as the growth-inhibiting region, The method for manufacturing a semiconductor substrate according to claim 1, wherein the portion of the base substrate exposed by the two openings functions as the first and second seed regions.

8. The method for manufacturing a semiconductor substrate according to claim 7, wherein the thickness of the third region in the mask portion is different from the thickness of the first and second regions.

9. The method for manufacturing a semiconductor substrate according to claim 7, wherein the constituent material of the third region in the mask portion is different from the constituent materials of the first and second regions.

10. A method for manufacturing a semiconductor substrate according to claim 7, wherein the third region contains a metal element having a melting point of 1000°C or higher, and the first and second regions do not contain the metal element.

11. The method for manufacturing a semiconductor substrate according to claim 7, wherein the surface material of the third region is obtained by modifying the surface materials of the first and second regions.

12. The method for manufacturing a semiconductor substrate according to claim 7, wherein the base substrate comprises a main substrate and an underlayer located on the main substrate and containing the nitride semiconductor.

13. The method for manufacturing a semiconductor substrate according to claim 12, wherein the underlying layer contains AlN.

14. The method for manufacturing a semiconductor substrate according to claim 1, wherein the first light has a wavelength of 395 to 415 nm.

15. A semiconductor substrate manufacturing apparatus that performs each of the steps described in claim 1.

16. A template substrate for growing nitride semiconductors, It has a growth-inhibiting region and first and second seed regions adjacent to each other via the growth-inhibiting region, The growth-inhibiting region includes a first region adjacent to the first seed region, a second region adjacent to the second seed region, and a third region located between the first and second regions and having a different light reflectivity from the first and second regions, in the template substrate.

17. A semiconductor substrate comprising a template substrate according to claim 16, a first semiconductor portion located above the first seed region and the growth suppression region, and a second semiconductor portion located above the second seed region and the growth suppression region.

18. The semiconductor substrate according to claim 17, wherein a gap is located between the growth-inhibiting region and the first semiconductor portion and the second semiconductor portion, respectively.