Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor comprising a multilayer body, a protective layer, and external electrodes. The multilayer body is formed by stacking a plurality of internal electrodes and a plurality of dielectric layers, and has a substantially rectangular parallelepiped shape having a first surface and a second surface facing each other in the stacking direction. The multilayer body has a first side surface, a second side surface, a third side surface, and a fourth side surface, and has a first ridge portion between the first side surface and the second side surface, a second ridge portion between the second side surface and the third side surface, a third ridge portion between the third side surface and the fourth side surface, and a fourth ridge portion between the fourth side surface and the first side surface. The protective layer covers regions in the first side surface, the second side surface, the third side surface, and the fourth side surface excluding predetermined ridge portions. The external electrodes are connected to the plurality of internal electrodes at the predetermined ridge portions.

Description

Multilayer ceramic capacitors

[0001] The present disclosure relates to a multilayer ceramic capacitor to which a side margin portion is attached, and particularly to a small-sized multilayer ceramic capacitor.

[0002] A conventional multilayer ceramic capacitor is described in, for example, Japanese Patent Application Laid-Open No. 2003-222999.

[0003] Japanese Unexamined Patent Publication No. 62-237714

[0004] The multilayer ceramic capacitor of the present disclosure is a substantially rectangular parallelepiped laminate including a plurality of alternately stacked internal electrodes and a plurality of dielectric layers, and having first and second surfaces opposing each other in a stacking direction, the laminate having a first side surface, a second side surface, a third side surface, and a fourth side surface around an axis along the stacking direction, and further having a first ridge portion located between the first side surface and the second side surface, a second ridge portion located between the second side surface and the third side surface, a third ridge portion located between the third side surface and the fourth side surface, and a fourth ridge portion located between the fourth side surface and the first side surface; a protective layer covering regions of the first side surface, the second side surface, the third side surface, and the fourth side surface excluding predetermined ridge portions among the first ridge portion, the second ridge portion, the third ridge portion, and the fourth ridge portion; and an external electrode connected to the plurality of internal electrodes at the predetermined ridge portions.

[0005] Objects, features, and advantages of the present disclosure will become more apparent from the following detailed description and drawings.

[0023] FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to a first embodiment and a second embodiment.

[0024] FIG. 2 is a perspective view showing a laminate of the multilayer ceramic capacitor according to the first embodiment.

[0025] FIG. 3 is a perspective view showing a protective layer of the multilayer ceramic capacitor according to the first embodiment.

[0026] FIG. 4 is a perspective view showing an element component of the multilayer ceramic capacitor according to the first embodiment.

[0027] FIG. 5 is a plan view showing an element component of the multilayer ceramic capacitor according to the first embodiment.

[0028] FIG. 6 is a perspective view showing a laminate of the multilayer ceramic capacitor according to the second embodiment.

[0029] FIG. 7 is a perspective view showing a protective layer of the multilayer ceramic capacitor according to the second embodiment.

[0030] FIG. 8 is a plan view showing an element component of the multilayer ceramic capacitor according to the second embodiment.

[0031] FIG. 9 is a perspective view showing another example of the multilayer ceramic capacitor according to the third embodiment.

[0032] FIG. 10 is a perspective view showing another example of the laminate of the multilayer ceramic capacitor according to the third embodiment.

[0033] FIG. 11 is a perspective view showing a protective layer of the multilayer ceramic capacitor according to the third embodiment.

[0034] FIG. 12 is a perspective view showing an element component of the multilayer ceramic capacitor according to the third embodiment.

[0035] 15 is a plan view showing a multilayer ceramic capacitor that does not have the features of the multilayer ceramic capacitor according to the third embodiment. FIG. 16 is a plan view showing a ceramic green sheet on which an internal electrode pattern is printed. FIG. 17 is a plan view showing a ceramic green sheet on which an internal electrode pattern is printed. FIG. 18 is a perspective view illustrating an example of a process for producing a base laminate. FIG. 19 is a plan view showing a ceramic green sheet on which a dummy electrode pattern is printed. FIG. 19 is a perspective view illustrating another example of a process for producing a base laminate. FIG. 19 is a perspective view showing an example of a base laminate. FIG. 19 is a perspective view showing a plurality of laminate precursors obtained by cutting the base laminate of FIG. 14. FIG. 20 is a perspective view showing a plurality of laminate precursors aligned on a support sheet. FIG. 21 is a perspective view showing a process for attaching ceramic green sheets for protective layers to the side surfaces of the laminate precursor.1 is a perspective view showing a step of attaching a ceramic green sheet for a protective layer to a side surface of a laminate precursor; FIG. 2 is a perspective view showing a base component precursor and a perspective view showing an base component; and FIG. 3 is a perspective view showing an base component on which a first layer of an external electrode has been formed.

[0006] In recent years, multilayer ceramic capacitors as capacitor elements have been dramatically reduced in size and increased in capacitance, but as electronic devices become more sophisticated, there is a demand for multilayer ceramic capacitors with even greater capacitance.

[0007] A multilayer ceramic capacitor includes a laminate formed by alternately stacking a plurality of ceramic dielectric layers and a plurality of internal electrode layers in a predetermined direction (stacking direction). A multilayer ceramic capacitor can have a large capacitance, for example, by increasing the overlapping area (effective area) between adjacent internal electrode layers in the stacking direction. Patent Document 1 discloses a technique for increasing the effective area by exposing a plurality of internal electrode layers on the side surfaces of an unfired laminate, adding a slurry of a ceramic material constituting the ceramic dielectric layers to the side surfaces to form unfired side margin portions, and co-firing the laminate and the side margin portions.

[0008] Conventional multilayer ceramic capacitors have room for improvement in terms of increasing the effective area while reducing the increase in external dimensions.

[0009] Hereinafter, embodiments of the multilayer ceramic capacitor of the present disclosure will be described with reference to the drawings. The drawings used in the following description are schematic, and the dimensional ratios and the like in the drawings do not necessarily correspond to the actual ones. In the multilayer ceramic capacitor according to the embodiment, any direction may be considered to be up or down. However, in this specification, for convenience, a Cartesian coordinate system XYZ is defined in some drawings. In the following description, the positive side of the Z-axis direction is considered to be up, and terms such as top surface and bottom surface may be used. The X-axis direction is also referred to as the first direction or length direction. The Y-axis direction is also referred to as the second direction or width direction. The Z-axis direction is also referred to as the third direction, height direction, or stacking direction. In this specification, a planar area refers to the area of ​​a component or member of interest when viewed along the stacking direction (Z-axis direction). Furthermore, a planar shape refers to the shape of a component or member of interest when viewed along the stacking direction (Z-axis direction).

[0010] FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to the first embodiment and a second embodiment. FIG. 2A is a perspective view showing a laminate of the multilayer ceramic capacitor according to the first embodiment. FIG. 2B is a perspective view showing a protective layer of the multilayer ceramic capacitor according to the first embodiment. FIG. 2C is a perspective view showing an element component of the multilayer ceramic capacitor according to the first embodiment. FIG. 3 is a plan view showing an element component of the multilayer ceramic capacitor according to the first embodiment. FIG. 4A is a perspective view showing a laminate of the multilayer ceramic capacitor according to the second embodiment. FIG. 4B is a perspective view showing a protective layer of the multilayer ceramic capacitor according to the second embodiment. FIG. 4C is a perspective view showing an element component of the multilayer ceramic capacitor according to the second embodiment. FIG. 5 is a plan view showing an element component of the multilayer ceramic capacitor according to the second embodiment. Note that FIGS. 2A, 2B, 4A, and 4B show the laminate or protective layer before polishing, and FIGS. 2C, 3, 4C, and 5 show the element component after polishing.

[0011] A multilayer ceramic capacitor according to a first embodiment will now be described. As shown in Fig. 1, the multilayer ceramic capacitor 1 of this embodiment includes an element component 2 and external electrodes 3. As shown in Figs. 2A, 2B, and 2C, the element component 2 includes a laminate 4 and a protective layer 5.

[0012] The laminate 4 is formed by alternately stacking a plurality of internal electrodes 6 and a plurality of dielectric layers 7. The plurality of internal electrodes 6 and the plurality of dielectric layers 7 are stacked in the stacking direction (Z-axis direction).

[0013] As shown in FIG. 2A , the laminate 4 has a substantially rectangular parallelepiped shape. The laminate 4 has a first surface 8a and a second surface 8b that face each other in the stacking direction (Z-axis direction). The first surface 8a and the second surface 8b may be perpendicular to the stacking direction. Hereinafter, the first surface 8a and the second surface 8b may be collectively referred to as the main surfaces 8a and 8b. The laminate 4 may have a substantially square shape in a planar view. In other words, the main surfaces 8a and 8b may have a substantially square shape in a planar view.

[0014] The laminate 4 has a first side surface 9a, a second side surface 9b, a third side surface 9c, and a fourth side surface 9d around an axis perpendicular to the principal surfaces 8a and 8b. The first side surface 9a, the second side surface 9b, the third side surface 9c, and the fourth side surface 9d may be parallel to the stacking direction. The laminate 4 also has a first ridge portion 10a located between the first side surface 9a and the second side surface 9b, a second ridge portion 10b located between the second side surface 9b and the third side surface 9c, a third ridge portion 10c located between the third side surface 9c and the fourth side surface 9d, and a fourth ridge portion 10d located between the fourth side surface 9d and the first side surface 9a. In this specification, when the ridge formed by the intersection of the first side surface 9a and the second side surface 9b is defined as the first ridge 11a, the first ridge 10a refers to a region extending from a region of the first side surface 9a closer to the first ridge 11a to a region of the second side surface 9b closer to the first ridge 11a, via the first ridge 11a. The laminate 4 may have a chamfered corner extending from the first side surface 9a to the second side surface 9b. In this case, the edge extending in the third direction in the chamfered region may be defined as the first ridge 11a. The same applies to the second ridge 10b, the third ridge 10c, and the fourth ridge 10d. Hereinafter, the first side surface 9a, the second side surface 9b, the third side surface 9c, and the fourth side surface 9d may be collectively referred to as side surfaces 9a to 9d. The first edge portion 10a, the second edge portion 10b, the third edge portion 10c, and the fourth edge portion 10d may be collectively referred to as edge portions 10a to 10d.

[0015] The internal electrodes 6 are made of a conductive material. The internal electrodes 6 may be made of a metal material whose main component is, for example, a metal such as Ni (nickel), Cu (copper), Sn (tin), Pt (platinum), Pd (palladium), Ag (silver), or Au (gold), or an alloy thereof. In this specification, the term "main component" refers to the component with the highest content in the material or member of interest. The internal electrodes 6 may have a thickness of, for example, 1.5 μm or less. In this case, internal defects caused by internal stress when firing the laminate 4 or when applying a voltage to the internal electrodes 6 can be reduced, thereby improving the reliability of the multilayer ceramic capacitor 1.

[0016] The dielectric layer 7 is made of a dielectric material, for example, BaTiO ３ (barium titanate), CaTiO３ (Calcium titanate), SrTiO ３ (strontium titanate), BaZrO ３ The dielectric layer 7 may be made of a ceramic material having barium zirconate as a main component. The ceramic material constituting the dielectric layer 7 may contain a minor component, such as an Mn (manganese) compound, an Mg (magnesium) compound, an Si (silicon) compound, a Co (cobalt) compound, an Ni compound, or a rare earth compound, in a content lower than that of the major component. The dielectric layer 7 may have a thickness of, for example, 0.1 μm or more and 10 μm or less.

[0017] The multiple internal electrodes 6 include at least one first internal electrode 6 a and at least one second internal electrode 6 b. The first internal electrode 6 a and the second internal electrode 6 b have mutually different polarities, and when the first internal electrode 6 a has a first polarity, the second internal electrode 6 b has a second polarity different from the first polarity. The first internal electrodes 6 a and the second internal electrodes 6 b are alternately arranged in the stacking direction with the dielectric layer 7 interposed therebetween.

[0018] The first internal electrode 6a is exposed in a region of the side surfaces 9a to 9d of the laminate 4 excluding at least one of the ridge portions 10a to 10d. The second internal electrode 6b is exposed in a region of the side surfaces 9a to 9d of the laminate 4 excluding at least one of the ridge portions 10a to 10d. In the multilayer ceramic capacitor 1 of this embodiment, the first internal electrode 6a is exposed in a region of the side surfaces 9a to 9d excluding the second ridge portion 10b, and the second internal electrode 6b is exposed in a region of the side surfaces 9a to 9d excluding the first ridge portion 10a. The ridge portion where the first internal electrode 6a is not exposed (second ridge portion 10b) is different from the ridge portion where the second internal electrode 6b is not exposed (first ridge portion 10a). The number of edge portions where the first internal electrodes 6 a are not exposed may be the same as the number of edge portions where the second internal electrodes 6 b are not exposed, which makes it easier to ensure the characteristics of the multilayer ceramic capacitor.

[0019] For example, as shown in FIG. 3 , the first internal electrode 6a has a notch 12b in a substantially right-angled triangular shape with its apex (right-angled apex) located on the second edge 11b in a plan view. The first internal electrode 6a has the same shape as the laminate 4 in a plan view, except for the notch 12b. The second internal electrode 6b has a notch 12a in a substantially right-angled triangular shape with its apex (right-angled apex) located on the first edge 11a in a plan view. The second internal electrode 6b has the same shape as the laminate 4 in a plan view, except for the notch 12a. In the multilayer ceramic capacitor 1, the effective area contributing to capacitance is reduced by the area of ​​the notches 12a and 12b compared to the plan view area of ​​the laminate 4. Therefore, from the perspective of increasing the capacitance of the multilayer ceramic capacitor 1, the smaller the area of ​​the notches 12a and 12b (the sum of the areas of the notches 12a and 12b) the better.

[0020] The planar shape of the notch 12b of the first internal electrode 6a may be a substantially right-angled isosceles triangle. The planar shape of the notch 12b is not limited to a substantially right-angled triangle. The planar shape of the notch 12b may be a rectangle with one vertex located on the second edge 11b, a sector (quadrants) with its center located on the second edge 11b, or the like. In other words, the notch may be a right-angled triangle with an vertex located on the edge of the edge, or a right-angled triangle with the hypotenuse bulging in an arc shape. If the planar shape of the notch 12b is a substantially right-angled isosceles triangle, printing an internal electrode pattern having a hole that becomes the notch 12b (a square-shaped hole in the internal electrode pattern shown in FIGS. 9A and 9B ) during the manufacturing process of the multilayer ceramic capacitor 1 is facilitated. The same applies to the notch 12a of the second internal electrode 6b.

[0021] The protective layer 5 is located on the side surfaces 9a to 9d of the laminate 4 and forms side margins. The protective layer 5 covers the areas of the side surfaces 9a to 9d except for predetermined edge portions among the edge portions 10a to 10d. The predetermined edge portions not covered by the protective layer 5 are edge portions where one of the first internal electrode 6a and the second internal electrode 6b is exposed and the other is not exposed.

[0022] In the multilayer ceramic capacitor 1 of this embodiment, the protective layer 5 covers the regions of the side surfaces 9a to 9d excluding the first ridge portions 10a and the second ridge portions 10b. In other words, the protective layer 5 covers at least the regions where the first internal electrodes 6a and the second internal electrodes 6b overlap and are exposed when the side surfaces 9a to 9d are viewed in the stacking direction.

[0023] The protective layer 5 is made of a dielectric material, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , BaZrO ３ The ceramic material constituting the protective layer 5 may contain, as a secondary component, a Mn compound, a Mg compound, a Si compound, a Co compound, a Ni compound, a rare earth compound, etc. The protective layer 5 may be made of a ceramic material having the same main component as the ceramic material constituting the dielectric layer 7.

[0024] As shown in FIG. 3 , the protective layer 5 electrically insulates the external electrodes 3 and internal electrodes 6 of opposite polarities from each other. The protective layer 5 electrically insulates the ends of the internal electrodes 6 of different polarities exposed on the side surfaces 9 a to 9 d from each other and physically protects the ends of the internal electrodes 6 exposed on the side surfaces 9 a to 9 d. As shown in FIG. 3 , the distance between the ends of the protective layer 5 is longer than the distance between the two ends of the internal electrodes 6 exposed on the side surfaces. This reduces the possibility of a short circuit due to exposure of the internal electrodes from the protective layer. Even if the effective area of ​​the internal electrodes 6 is increased, thereby increasing the distance between the two ends of the internal electrodes 6 exposed on the side surfaces, increasing the distance between the ends of the protective layer 5 reduces the possibility of exposure of the internal electrodes 6 from the protective layer 5 and thus reduces the possibility of a short circuit with the external electrodes 3. The thinner the protective layer 5, the better, as long as it can fulfill these functions. This increases the ratio of the effective area to the planar area of ​​the element component 2, enabling the multilayer ceramic capacitor 1 to be miniaturized while increasing its capacitance. The effective area refers to the overlapping area in the stacking direction between adjacent internal electrodes 6. The protective layer 5 may have a thickness of, for example, 30 μm or less.

[0025] 2A , when a region on the side surfaces 9a to 9d of the laminate 4 where the internal electrodes 6 (first internal electrodes 6a and second internal electrodes 6b) of different polarities overlap and are exposed in a third direction is defined as a first region R1, and a region where only the internal electrodes 6 of the first polarity or the second polarity (first internal electrode 6a or second internal electrode 6b) are exposed is defined as a second region R2, the protective layer 5 may be located in the first region R1 and the second region R2 within a range that does not reach the edge of a predetermined edge portion. In this case, the external electrodes 3 and internal electrodes 6 of the same polarity can be connected to each other, while the external electrodes 3 and internal electrodes 6 of different polarities can be electrically insulated from each other.

[0026] The external electrodes 3 are made of a conductive material and include a first external electrode 3 a and a second external electrode 3 b. The first external electrode 3 a and the second external electrode 3 b are electrically insulated from each other.

[0027] The first external electrode 3a is located from the first side surface 9a to at least one of the second side surface 9b, the fourth side surface 9d, and the first surface 8a and the second surface 8b. The first external electrode 3a covers the first edge portion 10a and is connected to the first internal electrode 6a exposed at the first edge portion 10a. The first external electrode 3a may be located from the first side surface 9a to at least one of the first surface 8a and the second surface 8b.

[0028] The second external electrode 3b is located from the third side surface 9c to at least one of the second side surface 9b, the fourth side surface 9d, and the first surface 8a and the second surface 8b. The second external electrode 3b covers the second ridge portion 10b and is connected to the second internal electrode 6b exposed at the second ridge portion 10b. The second external electrode 3b may be located from the third side surface 9c to at least one of the first surface 8a and the second surface 8b.

[0029] When the first external electrode 3a is located on the first surface 8a, the second external electrode 3b may also be located on the first surface 8a, and when the first external electrode 3a is located on the second surface 8b, the second external electrode 3b may also be located on the second surface 8b. In this case, when mounting the multilayer ceramic capacitor 1 on a substrate, the first surface 8a or the second surface 8b on which the first external electrode 3a and the second external electrode 3b are located may be mounted facing the mounting surface of the substrate, thereby making it possible to easily mount the multilayer ceramic capacitor 1 on the substrate. When the first external electrode 3a is located on the first surface 8a and the second surface 8b, the second external electrode 3b may also be located on the first surface 8a and the second surface 8b. In this case, when mounting the multilayer ceramic capacitor 1 on a substrate, either the first surface 8a or the second surface 8b may be mounted facing the mounting surface, thereby simplifying the mounting process.

[0030] In the multilayer ceramic capacitor 1, in order to electrically insulate the external electrodes 3 and internal electrodes 6 of different polarities from each other, the shortest distance between the external electrodes 3 of a first polarity and the internal electrodes 6 of a second polarity is set to be equal to or greater than a predetermined insulation distance H. The insulation distance H may be approximately the thickness of the protective layer 5, for example.

[0031] The external electrode 3 may include a first layer in contact with the element component 2 and a second layer covering the first layer. The first layer may be a sintered metal layer. The first layer may be formed by baking a conductive paste containing a metal material such as Cu, Ni, Ag, Pd, an Ag-Pd alloy, or Au onto the surface of the element component 2. The first layer may be formed by baking a conductive paste containing the material by sputtering onto the surface of the element component 2. The first layer may also be a vapor-deposited metal film. For example, a metal film of Cu, Ni, Ag, Pd, an Ag-Pd alloy, or Au may be formed by sputtering. The first layer may also be a conductive resin. For example, it may be an epoxy resin or phenolic resin containing a metal powder such as Ag. The second layer may be a plated layer. The second layer may be formed by a plating method such as electroless plating or electrolytic plating. The second layer may be configured to include, for example, a Ni plating layer and a Sn plating layer covering the Ni plating layer. The second layer may also include, for example, a Sn plating layer, a Cu plating layer, an Au plating layer, etc. The second layer may also be configured by stacking multiple plating layers.

[0032] The external electrodes 3 may be formed only from plating layers. In this case, the thickness of the external electrodes 3 can be reduced, thereby enabling the multilayer ceramic capacitor 1 to be miniaturized. The external electrodes 3 may be formed from a conductive resin paste. In this case, stress generated when the multilayer ceramic capacitor 1 is mounted on a substrate can be alleviated, thereby reducing the risk of cracks occurring in the element component 2. As a result, the reliability of the mounting structure obtained by mounting the multilayer ceramic capacitor 1 on a substrate can be improved. Furthermore, when the multilayer ceramic capacitor 1 is mounted on a substrate and used, noise from the substrate due to electrostriction when voltage is applied can be reduced.

[0033] If, in plan view, the first internal electrode 6a has a rectangular cutout portion with its long side located on the third side surface 9c, and the second internal electrode 6b has a rectangular cutout portion with its long side located on the first side surface 9a, in order to electrically insulate the first internal electrode 6a from the second external electrode 3b and the second internal electrode 6b from the first external electrode 3a, the length of the short side of the rectangular cutout portion needs to be approximately the insulation distance H, which may result in a lower ratio of the effective area to the plan view area of ​​the base component 2.

[0034] 3 , in the multilayer ceramic capacitor 1 of this embodiment, the notches 12 a, 12 b are located only at corners including the first ridge 10 a and the second ridge 10 b of the laminate 4, which allows the areas of the notches 12 a, 12 b to be reduced, thereby increasing the ratio of the effective area to the planar area of ​​the element component 2. Therefore, according to the first embodiment, it is possible to provide a multilayer ceramic capacitor 1 that is small and has a large capacitance. In the disclosed example used in the above description, the notches 12 a, 12 b are located at corners including the first ridge 10 a and the second ridge 10 b of the laminate 4, but similar functions and effects can be achieved even if the notches 12 a, 12 b are located at corners including the first ridge 10 a and the third ridge 10 c.

[0035] Next, a multilayer ceramic capacitor according to a second embodiment will be described. A multilayer ceramic capacitor 1A according to this embodiment is different from the multilayer ceramic capacitor 1 according to the above embodiment in the configurations of the internal electrodes 6 and the protective layer 5, but has the same configuration as the multilayer ceramic capacitor 1 according to the above embodiment. Therefore, the same components as those in the multilayer ceramic capacitor 1 are denoted by the same reference numerals as those in the multilayer ceramic capacitor 1, and detailed description thereof will be omitted.

[0036] As shown in FIG. 1, the multilayer ceramic capacitor 1A includes an element component 2 and external electrodes 3. As shown in FIGS. 4A, 4B, and 4C, the element component 2 includes a laminate 4 and a protective layer 5. The laminate 4 is configured by alternately stacking multiple internal electrodes 6 and multiple dielectric layers 7. The multiple internal electrodes 6 include at least one first internal electrode 6a and at least one second internal electrode 6b. The first internal electrode 6a and the second internal electrode 6b have mutually opposite polarities. The laminate 4 may be approximately square in plan view. In other words, the main surfaces 8a, 8b may be approximately square in plan view.

[0037] The first internal electrode 6a is exposed in a region excluding the second edge portion 10b and the third edge portion 10c on the side surfaces 9a to 9d of the laminate 4. The first internal electrode 6a has, in a plan view, a right-angled triangular cutout portion 12b whose apex (right-angled apex) is located on the second edge 11b, and a right-angled triangular cutout portion 12c whose apex (right-angled apex) is located on the third edge 11c. The first internal electrode 6a has the same shape as the laminate 4 in a plan view, except for the cutout portions 12b and 12c.

[0038] The second internal electrode 6b is exposed in a region excluding the fourth edge 10d and the first edge 10a on the side surfaces 9a to 9d of the laminate 4. The second internal electrode 6b has, in a plan view, a right-angled triangular cutout 12d whose apex (right-angled apex) is located on the fourth edge 11d, and a right-angled triangular cutout 12a whose apex (right-angled apex) is located on the first edge 11a. The second internal electrode 6b has the same shape in a plan view as the laminate 4, except for the cutouts 12d and 12a.

[0039] The protective layer 5 covers the areas of the side surfaces 9a to 9d except for the first edge portion 10a, the second edge portion 10b, the third edge portion 10c, and the fourth edge portion 10d.

[0040] The first external electrode 3a is located from the first side surface 9a to at least one of the second side surface 9b, the fourth side surface 9d, and the first surface 8a and the second surface 8b. The first external electrode 3a covers the fourth edge portion 10d and the first edge portion 10a and is connected to the first internal electrode 6a exposed at the fourth edge portion 10d and the first edge portion 10a. The first external electrode 3a may be located from the first side surface 9a to at least one of the first surface 8a and the second surface 8b.

[0041] The second external electrode 3b is located from the third side surface 9c to at least one of the second side surface 9b, the fourth side surface 9d, and the first surface 8a and the second surface 8b. The second external electrode 3b covers the second ridge portion 10b and the third ridge portion 10c and is connected to the second internal electrode 6b exposed at the second ridge portion 10b and the third ridge portion 10c. The second external electrode 3b may be located from the third side surface 9c to at least one of the first surface 8a and the second surface 8b.

[0042] In the multilayer ceramic capacitor 1A, the first internal electrode 6a has the notches 12d, 12a and the second internal electrode 6b has the notches 12b, 12c, so the ratio of the effective area to the planar area of ​​the element component 2 is slightly lower than in the multilayer ceramic capacitor 1, resulting in a slightly lower capacitance. However, in the multilayer ceramic capacitor 1A, the first external electrode 3a is connected to the first internal electrode 6a at the fourth edge 10d and the first edge 10a, and the second external electrode 3b is connected to the second internal electrode 6b at the second edge 10b and the third edge 10c, so the multilayer ceramic capacitor 1A has a lower equivalent series resistance (ESR) than the multilayer ceramic capacitor 1. The multilayer ceramic capacitor 1 and the multilayer ceramic capacitor 1A may be used appropriately depending on the required characteristics of the electronic circuit in which the multilayer ceramic capacitors 1, 1A are used.

[0043] Next, the multilayer ceramic capacitor according to the third embodiment will be described. FIG. 6A is a perspective view showing an example of the multilayer ceramic capacitor according to the third embodiment, and FIG. 6B is a perspective view showing another example of the multilayer ceramic capacitor according to the third embodiment. FIG. 7A is a perspective view showing an example of a laminate of the multilayer ceramic capacitor according to the third embodiment, FIG. 7B is a perspective view showing a protective layer of the multilayer ceramic capacitor according to the third embodiment, FIG. 7C is a perspective view showing an element component of the multilayer ceramic capacitor according to the third embodiment, and FIG. 7D is a perspective view showing another example of the laminate of the multilayer ceramic capacitor according to the third embodiment. FIG. 8 is a plan view showing an element component of the multilayer ceramic capacitor according to the third embodiment. FIG. 9A is a plan view showing the multilayer ceramic capacitor according to the third embodiment, and FIG. 9B is a plan view showing a multilayer ceramic capacitor that does not have the characteristics of the multilayer ceramic capacitor according to the third embodiment. Note that FIGS. 7A, 7B, and 7D show the laminate or protective layer before polishing, and FIGS. 7C and 8 show the element component after polishing.

[0044] The multilayer ceramic capacitor 1B of this embodiment differs from the multilayer ceramic capacitor 1 of the above embodiment in the configurations of the internal electrodes 6, the protective layer 5, and the external electrodes 3, but has the same configuration as the multilayer ceramic capacitor 1 of the above embodiment. Therefore, the same reference symbols as those in the multilayer ceramic capacitor 1 are used for the similar configurations, and detailed descriptions thereof will be omitted.

[0045] As shown in Figures 6A and 6B, the multilayer ceramic capacitor 1B includes an element component 2 and an external electrode 3. As shown in Figures 7A, 7B, and 7C, the element component 2 includes a laminate 4 and a protective layer 5. The laminate 4 is formed by alternately stacking a plurality of internal electrodes 6 and a plurality of dielectric layers 7. The plurality of internal electrodes 6 includes at least one first internal electrode 6a and at least one second internal electrode 6b. The first internal electrode 6a and the second internal electrode 6b have mutually opposite polarities.

[0046] The laminate 4 may have a substantially square shape in a plan view. In other words, the main surfaces 8a and 8b may have a substantially square shape in a plan view.

[0047] The first internal electrode 6a is exposed in a region of the side surfaces 9a to 9d of the laminate 4 excluding the second edge portion 10b and the fourth edge portion 10d. In a plan view, the first internal electrode 6a has a right-angled triangular cutout portion 12b whose apex (right-angled apex) is located on the second edge 11b, and a right-angled triangular cutout portion 12d whose apex (right-angled apex) is located on the fourth edge 11d. The first internal electrode 6a has the same shape as the laminate 4 in a plan view except for the cutout portions 12b and 12d.

[0048] The second internal electrode 6b is exposed in an area excluding the first edge portion 10a and the third edge portion 10c on the side surfaces 9a to 9d of the laminate 4. The second internal electrode 6b has, in a plan view, a right-angled triangular cutout portion 12a whose apex (right-angled apex) is located on the first edge 11a, and a right-angled triangular cutout portion 12c whose apex (right-angled apex) is located on the third edge 11c. The second internal electrode 6b has the same shape in a plan view as the laminate 4, except for the cutout portions 12a and 12c.

[0049] The protective layer 5 covers the areas of the side surfaces 9a to 9d except for the first edge portion 10a, the second edge portion 10b, the third edge portion 10c, and the fourth edge portion 10d.

[0050] The external electrodes 3 include a first external electrode 3 a, a second external electrode 3 b, a third external electrode 3 c, and a fourth external electrode 3 d. The first external electrode 3 a and the third external electrode 3 c are electrically insulated from the second external electrode 3 b and the fourth external electrode 3 d.

[0051] The first external electrode 3a is located from the first side surface 9a to the second side surface 9b and at least one of the first surface 8a and the second surface 8b. The first external electrode 3a covers the first edge portion 10a and is connected to the first internal electrode 6a exposed at the first edge portion 10a. The first external electrode 3a may be located from the first side surface 9a to at least one of the first surface 8a and the second surface 8b.

[0052] The second external electrode 3b is located from the second side surface 9b to the third side surface 9c and at least one of the first surface 8a and the second surface 8b. The second external electrode 3b covers the second ridge portion 10b and is connected to the second internal electrode 6b exposed at the second ridge portion 10b. The second external electrode 3b may be located from the second side surface 9b to at least one of the first surface 8a and the second surface 8b.

[0053] The third external electrode 3c is located from the third side surface 9c to the fourth side surface 9d and at least one of the first surface 8a and the second surface 8b. The third external electrode 3c covers the third edge portion 10c and is connected to the first internal electrode 6a exposed at the third edge portion 10c. The third external electrode 3c may be located from the third side surface 9c to at least one of the first surface 8a and the second surface 8b.

[0054] The fourth external electrode 3d is located from the fourth side surface 9d to at least one of the first side surface 9a, the first surface 8a, and the second surface 8b. The fourth external electrode 3d covers the fourth edge portion 10d and is connected to the second internal electrode 6b exposed at the fourth edge portion 10d. The fourth external electrode 3d may be located from the fourth side surface 9d to at least one of the first surface 8a and the second surface 8b.

[0055] 6A, the external electrodes 3 may be substantially rectangular when viewed in a direction perpendicular to the side surfaces 9a to 9d. In this case, the contact area between each of the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d and the element component 2 can be increased. As a result, the adhesion between the external electrodes 3 and the element component 2 can be improved, and the reliability of the multilayer ceramic capacitor 1B can be improved.

[0056] In the multilayer ceramic capacitor 1B, the first internal electrode 6a has the notches 12b, 12d and the second internal electrode 6b has the notches 12a, 12c, so the ratio of the effective area to the planar area of ​​the element component 2 is slightly lower than in the multilayer ceramic capacitor 1, resulting in a slightly lower capacitance. However, in the multilayer ceramic capacitor 1B, the external electrodes 3 are connected to the internal electrodes 6 at the four edge portions 10a to 10d, so the multilayer ceramic capacitor 1B has a lower equivalent series resistance (ESR) than the multilayer ceramic capacitor 1. The multilayer ceramic capacitors 1, 1A, and 1B may be used appropriately depending on the required characteristics of the electronic circuit in which the multilayer ceramic capacitors 1, 1A, and 1B are used.

[0057] As shown in FIG. 6B , the external electrodes 3 may be U-shaped when viewed in a direction perpendicular to the side surfaces 9a to 9d. In this case, when the multilayer ceramic capacitor 1B is mounted on a substrate, creeping of the solder paste can be reduced, improving reliability against substrate deflection and temperature cycles. Furthermore, the occurrence of short circuits between the first external electrodes 3a and the third external electrodes 3c and the second external electrodes 3b and the fourth external electrodes 3d due to migration can be reduced. As a result, the reliability of a mounting structure in which the multilayer ceramic capacitor 1B is mounted on a substrate can be improved.

[0058] The multilayer ceramic capacitor 1B may be configured such that all of the first external electrodes 3a, the second external electrodes 3b, the third external electrodes 3c, and the fourth external electrodes 3d are located on at least one of the first surface 8a and the second surface 8b. In this case, when mounting the multilayer ceramic capacitor 1 on a substrate, the first surface 8a or the second surface 8b on which all of the first external electrodes 3a, the second external electrodes 3b, the third external electrodes 3c, and the fourth external electrodes 3d are located is mounted so as to face the mounting surface of the substrate, thereby making it possible to easily mount the multilayer ceramic capacitor 1B on the substrate.

[0059] The multilayer ceramic capacitor 1B may be configured such that the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d are all located on both the first surface 8a and the second surface 8b. In this case, when the multilayer ceramic capacitor 1B is mounted on a substrate, either the first surface 8a or the second surface 8b may face the mounting surface, which simplifies the mounting process.

[0060] The multilayer ceramic capacitor 1B is configured such that its electrical characteristics do not change even when it is rotated by 90° around an axis along the lamination direction (Z-axis direction) when mounted on a substrate, thereby simplifying the mounting process.

[0061] 7D , the laminate 4 includes a capacitance-forming portion 40 and a first cover layer 41 and a second cover layer 42 located at both ends of the capacitance-forming portion in the stacking direction (Z-axis direction). The capacitance-forming portion 40 is configured by alternately stacking a plurality of internal electrodes 6 and a plurality of dielectric layers 7, and forms a capacitance. The first cover layer 41 and the second cover layer 42 protect the capacitance-forming portion 40.

[0062] The first cover layer 41 includes a dielectric 41a and a plurality of first dummy electrodes 41b. The plurality of first dummy electrodes 41b are exposed on the first surface 8a and the side surfaces 9a to 9d and are connected to the external electrodes 3. The plurality of first dummy electrodes 41b do not connect the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d to one another.

[0063] The second cover layer 42 includes a dielectric 42a and a plurality of second dummy electrodes 42b. The plurality of second dummy electrodes 42b are exposed on the second surface 8b and the side surfaces 9a to 9d and are connected to the external electrodes 3. The plurality of second dummy electrodes 42b do not connect the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d to one another.

[0064] The dielectrics 41 a, 42 a are made of a dielectric material. The dielectrics 41 a, 42 a may be made of a ceramic material having the same main component as the ceramic material that constitutes the dielectric layer 7. The first dummy electrode 41 b and the second dummy electrode 42 b are made of a conductive material. The first dummy electrode 41 b and the second dummy electrode 42 b may be made of a metal material having the same main component as the metal material that constitutes the internal electrode 6.

[0065] 7D , the contact area between each of the first external electrode 3 a, the second external electrode 3 b, the third external electrode 3 c, and the fourth external electrode 3 d and the element component 2 can be increased. As a result, the adhesion between the external electrodes 3 and the element component 2 can be further improved, and the reliability of the multilayer ceramic capacitor 1B can be further improved. Note that the multiple first dummy electrodes 41 b may be spaced apart from each other in the stacking direction (Z-axis direction) with the dielectric 41 a therebetween, or may be integrated. The same applies to the multiple second dummy electrodes 42 b.

[0066] Next, the effects of the multilayer ceramic capacitor 1B of this embodiment will be quantitatively described with reference to FIGS. 9A and 9B . FIG. 9A shows the multilayer ceramic capacitor 1B of this embodiment, and FIG. 9B shows a multilayer ceramic capacitor (hereinafter also referred to as multilayer ceramic capacitor C) that does not have the characteristics of the multilayer ceramic capacitor 1B. The multilayer ceramic capacitor C is a multilayer ceramic capacitor manufactured using a manufacturing method that does not add side margins. The multilayer ceramic capacitor C has a similar appearance to the multilayer ceramic capacitor 1B, but differs from the multilayer ceramic capacitor 1B in the configuration of the laminate 4, particularly the side margins and internal electrodes 6. In the multilayer ceramic capacitor C, the thickness of the side margins must be set relatively large to reduce exposure of the internal electrodes on the side surfaces of the laminate during fabrication. In FIGS. 9A and 9B , the area surrounded by dashed lines indicates the area that contributes to the formation of capacitance in the internal electrodes 6.

[0067] As shown in FIG. 9A and Table 1, for multilayer ceramic capacitor 1B, the length L and width W were set to 0.6 mm, the thickness SM of protective layer 5 was set to 0.032 mm, and the length b along the side surface of each edge portion was set to 0.08 mm. Furthermore, the length L1 and width L1 of element component 2 were set to 0.57 mm. As shown in FIG. 9B and Table 1, for multilayer ceramic capacitor C, the length L and width W were set to 0.6 mm, and the thickness SM of the side margin portion was set to 0.57 mm. Furthermore, the length L1 and width L1 of element component 2 of multilayer ceramic capacitor C were set to 0.57 mm. In Table 1, multilayer ceramic capacitor 1B is referred to as capacitor 1B, and multilayer ceramic capacitor C is referred to as capacitor C.

[0068] The capacitance contribution area in Table 1 indicates the effective area of ​​the multilayer ceramic capacitor 1B and the multilayer ceramic capacitor C. The area ratio in Table 1 indicates the ratio of the capacitance contribution area of ​​the multilayer ceramic capacitor 1B to the capacitance contribution area of ​​the multilayer ceramic capacitor C. The multilayer ceramic capacitor 1B has an area ratio of 1.1, which means that the effective area is increased by 10% compared to the multilayer ceramic capacitor C. Since the capacitance of a multilayer ceramic capacitor is proportional to the effective area, it can be said that the capacitance of the multilayer ceramic capacitor 1B is increased by 10% compared to the multilayer ceramic capacitor C.

[0069]

[0070] Next, a method for manufacturing the multilayer ceramic capacitor of the present disclosure will be described. Hereinafter, a method for manufacturing the multilayer ceramic capacitor 1B, particularly the multilayer ceramic capacitor 1B shown in Fig. 6B, will be described, but the multilayer ceramic capacitors 1, 1A and the multilayer ceramic capacitor 1B shown in Fig. 6A can also be manufactured in the same manner.

[0071]

[0033] Figures 10A and 10B are plan views showing ceramic green sheets on which internal electrode patterns are printed, Figure 11 is a perspective view illustrating an example of a process for producing a base laminate, Figure 12 is a plan view showing a ceramic green sheet on which a dummy electrode pattern is printed, Figure 13 is a perspective view illustrating another example of a process for producing a base laminate, and Figure 14 is a perspective view showing an example of a base laminate. Figure 15 is a perspective view showing multiple laminate precursors obtained by cutting the base laminate of Figure 14, Figure 16 is a perspective view showing multiple laminate precursors aligned on a support sheet, and Figures 17A, 17B, and 17C are perspective views showing a process for forming protective layer precursors on the side surfaces of the laminate precursors. Figure 18A is a perspective view showing an element component precursor, Figure 18B is a perspective view showing an element component, and Figure 18C is a perspective view showing an element component on which first layers of external electrodes have been formed. 10A, 10B, 11 to 16, 17A, 17B, 17C, 18A, and 18B, the internal electrode patterns, dummy electrode patterns, and external electrode inks are shown with hatching for ease of illustration. Note that the internal electrode patterns are shown with grid-like cutting lines that do not actually exist, in order to make it easier to understand the regions that will be incorporated into individual laminates.

[0072] First, BaTiO ３ A raw material powder containing the above as a main component is prepared. Next, an organic vehicle is mixed with the prepared raw material powder to prepare a ceramic slurry. The organic vehicle used to prepare the ceramic slurry may be, for example, a resin such as a butyral resin dissolved in a solvent mixture of ethyl alcohol and toluene. Next, using the prepared ceramic slurry, a ceramic green sheet 13 that will become the dielectric layer 7 is formed on a carrier film by a sheet forming method such as a die coater method, a doctor blade method, or a gravure coater method. The thickness of the ceramic green sheet 13 may be, for example, approximately 0.5 to 5 μm. The thinner the ceramic green sheet 13, the greater the capacitance of the multilayer ceramic capacitor.

[0073] Next, a conductive paste is prepared by mixing an organic vehicle with a powder containing, as a main component, a metal such as Ni, Cu, Sn, Pt, Pd, Ag, or Au, or an alloy thereof. The organic vehicle used to prepare the conductive paste may be, for example, a resin such as ethyl cellulose dissolved in a solvent mixture of a dihydroterpineol-based solvent and butyl cellosolve. The dispersant may be, for example, oleic acid, polyethylene glycol, or the like. Next, the prepared conductive paste is used to produce ceramic green sheets 13 having internal electrode patterns that become the internal electrodes 6 printed on their main surfaces by a printing method such as screen printing or gravure printing.

[0074] 10A shows a ceramic green sheet 13 on which an internal electrode pattern for the first internal electrode 6a is printed, and FIG. 10B shows a ceramic green sheet 13 on which an internal electrode pattern for the second internal electrode 6b is printed. While FIGS. 10A and 10B show an example in which multiple internal electrode patterns are printed in a continuous line, the multiple internal electrode patterns may be printed spaced apart from one another. Hereinafter, the ceramic green sheet 13 on which the internal electrode pattern for the first internal electrode 6a is printed may be referred to as a first pattern sheet 14. Furthermore, the ceramic green sheet 13 on which the internal electrode pattern for the second internal electrode 6b is printed may be referred to as a second pattern sheet 15. Furthermore, the first pattern sheet 14 and the second pattern sheet 15 may be collectively referred to as pattern sheets 14 and 15. The first pattern sheet 14 and the second pattern sheet 15 may have margins (i.e., blank areas where no internal electrode patterns are printed) at their outer peripheries.

[0075] 10A and 10B show an example in which the first pattern sheet 14 and the second pattern sheet 15 are produced separately, but the present invention is not limited to this. For example, a plurality of first pattern sheets 14 may be produced, and when producing a temporary laminate (see FIG. 11 ), the plurality of first pattern sheets 14 may be stacked while being offset by a predetermined distance.

[0076] Next, after drying the internal electrode patterns, as shown in FIG. 11 , a predetermined number of pattern sheets 14 and 15 are laminated on a predetermined number of laminated ceramic green sheets (also referred to as cover sheets) 13, and a predetermined number of cover sheets 13 are laminated on top of the pattern sheets 14 and 15 to produce a temporary laminate. The pattern sheets 14 and 15 may be laminated alternately, with the first pattern sheet 14 and the second pattern sheet 15, or the first pattern sheet 14 may be laminated with a predetermined offset distance. Although not shown in FIG. 11 , the temporary laminate is produced on a support sheet 16. The support sheet 16 may be a weak adhesive sheet or a foam release sheet, or an adhesive-release sheet that can be adhered and released. The support sheet 16 may be fixed to a base (also referred to as a first base) 17.

[0077] When preparing the temporary laminate, ceramic green sheets 13 on which dummy electrode patterns are printed may be used as cover sheets 13. These dummy electrodes (first dummy electrode 41b and second dummy electrode 42b) do not contribute to the capacitance of the multilayer ceramic capacitor 1B (see FIG. 12 ). Hereinafter, ceramic green sheets 13 on which dummy electrode patterns are printed may be referred to as dummy sheets 18. The dummy sheets 18 may have margins (i.e., blank areas where no dummy electrode patterns are printed) around their peripheries. FIG. 13 shows an example of preparing a temporary laminate by stacking a predetermined number of pattern sheets 14 and 15 on top of a predetermined number of stacked dummy sheets 18, and then stacking a predetermined number of dummy sheets 18 on top of those. The inclusion of dummy electrodes in the laminate 4 facilitates the formation of external electrodes 3 using a plating method. As shown in FIG. 13 , at least one ceramic green sheet 13 may be disposed between the dummy sheets 18 and the pattern sheets 14 and 15. Furthermore, the uppermost and lowermost layers of the temporary laminate may be ceramic green sheets 13. In this case, when the laminate precursor 21 obtained by cutting the base laminate 19 is peeled from the support sheet 16, it is possible to reduce the possibility of part of the dummy electrode pattern remaining on the support sheet 16 (electrode erosion). As a result, it is possible to reduce the occurrence of defective formation of the dummy electrodes due to electrode erosion, and ultimately to improve the reliability of the multilayer ceramic capacitor 1B.

[0078] Next, the temporary laminate is pressed in the lamination direction to obtain a mother laminate 19 as shown in Fig. 14. The temporary laminate can be pressed using, for example, a hydrostatic press.

[0079] 14 shows a base laminate 19 obtained by pressing the temporary laminate shown in FIG. 13 in the stacking direction, with external electrode ink 22 printed on the top surface thereof to serve as a base for the external electrodes 3. Forming a base can improve adhesion between the external electrodes 3 and the element component 2. Bases may be formed on the top and bottom surfaces of the base laminate 19, in which case adhesion between the external electrodes 3 and the element component 2 can be further improved.

[0080] The external electrode ink 22 may be a paste obtained by kneading powder of a metal material such as Cu, Ni, Ag, Pd, an Ag-Pd alloy, or Au with a sintering aid such as glass powder, a binder resin, and a plasticizer together with a solvent. The external electrode ink 22 is fired together with the element component precursor 25 (see FIG. 18A ) to form the base of the external electrode 3. A resin paste may also be used as the external electrode ink 22.

[0081] The external electrode ink 22 does not have to be printed on the base laminate 19. The external electrode ink 22 may be printed on the ceramic green sheet 13, and when a temporary laminate is produced, the ceramic green sheet 13 on which the external electrode ink 22 is printed may be used as the uppermost layer of the temporary laminate.

[0082] 15 , the base laminate 19 is cut along the planned cutting lines 20 to produce a plurality of laminate precursors 21. The base laminate 19 may be cut while placed on the support sheet 16. The base laminate 19 may be cut using, for example, a press cutter, a dicing saw, or the like.

[0083] 16 , each laminate precursor 21 is rotated by 90° on the support sheet 16 so that the side on which the internal electrode pattern is exposed faces the open surface (upper surface). In this step, a plurality of laminate precursors 21 may be aligned in a matrix on the support sheet 16. In this case, it is possible to efficiently attach the ceramic green sheet that will become the protective layer 5 to the side surface of the laminate precursor 21.

[0084] Next, a ceramic green sheet (also referred to as a protective layer ceramic green sheet) that will become the protective layer 5 is attached to the side surface of the laminate precursor to prepare an element component precursor. Hereinafter, the ceramic green sheet that will become the protective layer 5 may be referred to as a protective layer ceramic green sheet 23. Figures 17A, 17B, and 17C show the process of attaching the protective layer ceramic green sheet 23 to the side surface of the laminate precursor 21.

[0085] First, as shown in FIG. 17A , a strip-shaped ceramic green sheet 23 for a protective layer is prepared, and the ceramic green sheet 23 for a protective layer is placed on the upper surface of a pedestal (also referred to as a second pedestal) 24. Next, a plurality of laminate precursors 21 shown in FIG. 16 are placed so that the open surface of each laminate precursor 21 faces the upper surface of the second pedestal 24. The plurality of laminate precursors 21 are held by a support sheet 16 fixed to a first pedestal 17. The thickness of the ceramic green sheet 23 for a protective layer may be 30 μm or less, or may be 25 μm to 10 μm. The width of the ceramic green sheet 23 for a protective layer (the width in the left-right direction in FIG. 17A ) may be any dimension that completely covers the exposed area of ​​the side surface of the laminate precursor 21 where the internal electrode pattern that will become the first internal electrode 6a and the internal electrode pattern that will become the second internal electrode 6b overlap in the stacking direction, but does not cover the areas that will become the edge portions 10a to 10d.

[0086] 17B , the first pedestal 17 is moved toward the second pedestal 24, and the open surface of each laminate precursor 21 is pressed against the protective layer ceramic green sheet 23, thereby pressure-bonding the protective layer ceramic green sheet 23 to the open surface of each laminate precursor 21. The pressing force may be set appropriately. Alternatively, the protective layer ceramic green sheet 23 may be pressure-bonded to the open surface of each laminate precursor 21 while at least one of the open surface of each laminate precursor 21 and the protective layer ceramic green sheet 23 is heated. In this case, the protective layer ceramic green sheet 23 can be pressure-bonded well to the open surface of each laminate precursor 21.

[0087] 17C , by moving the first pedestal 17 in a direction away from the second pedestal 24, a laminate precursor 21 can be produced in which the protective layer ceramic green sheets 23 are pressure-bonded to the open surface. By repeating the process of bonding the protective layer ceramic green sheets 23 to the open surface of the laminate precursor 21 while rotating a plurality of laminate precursors 21 on the support sheet 16 (while changing the open surface of the laminate precursor 21), a laminate precursor 21 in which the protective layer ceramic green sheets 23 are pressure-bonded to four side surfaces, i.e., a base component precursor 25, can be produced (see FIG. 18A ).

[0088] 17A, 17B, and 17C show an example in which protective layer ceramic green sheets 23 are pressure-bonded to the side surfaces of laminate precursor 21 to produce element component precursor 25, but the present invention is not limited to this. Alternatively, element component precursor 25 may be produced by applying protective layer ceramic slurry to the side surfaces of laminate precursor 21 and drying the applied slurry.

[0089] Next, the element component precursor 25 shown in FIG. 18A is fired. The firing temperature can be set appropriately depending on the metal material contained in the conductive paste that will form the internal electrodes 6, the ceramic material contained in the ceramic green sheets that will form the dielectric layers 7, and other factors. The firing temperature may be, for example, approximately 1100 to 1250°C. The element component precursor 25 may be subjected to a degreasing process before firing. The degreasing process may be performed in an air atmosphere, an inert gas atmosphere, or a reducing atmosphere. The degreasing process may be performed under atmospheric pressure or under reduced pressure. Furthermore, the element component 2 after firing may be subjected to a re-oxidation process in an oxidizing atmosphere.

[0090] Next, the fired element component 2 is placed in a rotary pot containing an abrasive and barrel-polished to remove burrs from the surface of the element component 2, round the edges 11a-11d and corners, and fully expose the internal electrodes 6, first dummy electrodes 41b, and second dummy electrodes 42b at the edges 10a-10d. Figure 18B shows the element component 2 after polishing. By fully exposing the internal electrodes 6 at the edges 10a-10d, it is possible to bond the internal electrodes 6 and the external electrodes 3 well. Furthermore, by fully exposing the first dummy electrodes 41b and second dummy electrodes 42b at the edges 10a-10d, it is possible to enhance the bonding strength between the element component 2 and the external electrodes 3. This improves the reliability of the multilayer ceramic capacitor 1B.

[0091] FIG. 18C shows an element component on which a first layer 31 of the external electrode 3 is formed. The first layer 31 of the external electrode 3 can be formed by repeatedly immersing the edge portions 10a to 10d on which the first layer 31 is to be formed in external electrode paste, then lifting them out of the external electrode paste, and baking the external electrode paste attached to the edge portions 10a to 10d. The external electrode paste may be applied to the edge portions 10a to 10d on which the first layer is to be formed by a printing method such as screen printing or gravure printing. Alternatively, a metal film of Ni or Cu may be formed by a sputtering method or the like. Next, a second layer is formed by a plating method such as electroless plating or electrolytic plating to cover the first layer 31, thereby producing the multilayer ceramic capacitor 1B of FIG. 6B.

[0092] According to the present disclosure, a small-sized, large-capacitance multilayer ceramic capacitor can be provided.

[0093] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above-described embodiments, and various modifications, improvements, etc. are possible within the scope that does not deviate from the gist of the present disclosure.

[0094] The present disclosure can be implemented in the following configurations (1) to (9).

[0095] (1) A multilayer ceramic capacitor comprising: a laminate having a substantially rectangular parallelepiped shape, the laminate including a plurality of alternately stacked internal electrodes and a plurality of dielectric layers, and having first and second surfaces opposing each other in a stacking direction; the laminate having a first side surface, a second side surface, a third side surface, and a fourth side surface around an axis along the stacking direction, and further having a first ridge portion located between the first side surface and the second side surface, a second ridge portion located between the second side surface and the third side surface, a third ridge portion located between the third side surface and the fourth side surface, and a fourth ridge portion located between the fourth side surface and the first side surface; a protective layer covering regions of the first side surface, the second side surface, the third side surface, and the fourth side surface excluding predetermined ridge portions among the first ridge portion, the second ridge portion, the third ridge portion, and the fourth ridge portion; and an external electrode connected to the plurality of internal electrodes at the predetermined ridge portions.

[0096] (2) The multilayer ceramic capacitor according to the above configuration (1), wherein the external electrodes include: a first external electrode located at least from the first side surface to the first surface and / or the second surface and connected at the first ridge to an internal electrode of a first polarity among the plurality of internal electrodes; and a second external electrode located at least from the third side surface to the first surface and / or the second surface and connected at the second ridge to an internal electrode of a second polarity among the plurality of internal electrodes.

[0097] (3) The multilayer ceramic capacitor according to the above configuration (1), wherein the external electrodes include: a first external electrode located at least from the first side surface to the first surface and / or the second surface, and connected to an internal electrode of a first polarity among the plurality of internal electrodes at the first ridge portion and the fourth ridge portion; and a second external electrode located at least from the third side surface to the first surface and / or the second surface, and connected to an internal electrode of a second polarity among the plurality of internal electrodes at the second ridge portion and the third ridge portion.

[0098] (4) The multilayer ceramic capacitor according to the above configuration (1), wherein the external electrodes include: a first external electrode located at least from the first side surface to the first surface and / or the second surface and connected at the first ridge to an internal electrode of a first polarity among the plurality of internal electrodes; a second external electrode located at least from the second side surface to the first surface and / or the second surface and connected at the second ridge to an internal electrode of a second polarity among the plurality of internal electrodes; a third external electrode located at least from the third side surface to the first surface and / or the second surface and connected at the third ridge to an internal electrode of a first polarity among the plurality of internal electrodes; and a fourth external electrode located at least from the fourth side surface to the first surface and / or the second surface and connected at the fourth ridge to an internal electrode of a second polarity among the plurality of internal electrodes.

[0099] (5) A multilayer ceramic capacitor according to any one of the above structures (1) to (4), wherein each of the plurality of internal electrodes has a notch portion that, when viewed in the stacking direction, is in the shape of a right triangle whose apex is located on the edge of the predetermined edge portion, or in the shape of a right triangle whose hypotenuse bulges in an arc shape.

[0100] (6) A multilayer ceramic capacitor according to any one of the above structures (1) to (5), wherein a region where internal electrodes of different polarities are exposed in the stacking direction is defined as a first region, and a region where only internal electrodes of the first polarity or the second polarity are exposed is defined as a second region, and the protective layer is located in the first region and the second region within a range that does not reach the edge of the predetermined edge portion.

[0101] (7) The multilayer ceramic capacitor according to any one of the above structures (1) to (6), wherein the protective layer is made of a material having the same main component as the dielectric layer.

[0102] (8) The multilayer ceramic capacitor according to any one of the above configurations (1) to (7), wherein the protective layer has a thickness of 30 μm or less.

[0103] (9) A multilayer ceramic capacitor according to any one of the above structures (1) to (8), wherein the laminate includes a first cover layer including the first surface and a second cover layer including the second surface, the first cover layer includes a plurality of first dummy electrodes to which the external electrodes are connected, and the second cover layer includes a plurality of second dummy electrodes to which the external electrodes are connected.

[0104] REFERENCE SIGNS LIST 1, 1A, 1B Multilayer ceramic capacitor 2 Element component 3 External electrode 31 First layer 3a First external electrode 3b Second external electrode 3c Third external electrode 3d Fourth external electrode 4 Laminate 40 Capacitance forming portion 41 First cover layer 41a Dielectric 41b First dummy electrode 42 Second cover layer 42a Dielectric 42b Second dummy electrode 5 Protective layer 6 Internal electrode 6a First internal electrode 6b Second internal electrode 7 Dielectric layer 8a Main surface 8a First surface 8b Second surface 9a First side surface 9b Second side surface 9c Third side surface 9d Fourth side surface 10a First ridge portion 10b Second ridge portion 10c Third ridge portion 10d Fourth ridge portion 11a First ridge portion 11b Second ridge portion 11c Third ridge portion 11d Fourth edge 12a, 12b, 12c, 12d Notch portion 13 Ceramic green sheet (cover sheet) 14 First pattern sheet 15 Second pattern sheet 16 Support sheet 17 Base (first base) 18 Dummy sheet 19 Base laminate 20 Planned cutting line 21 Laminate precursor 22 External electrode ink 23 Ceramic green sheet for protective layer 24 Base (second base) 25 Base part precursor

Claims

1. A substantially rectangular parallelepiped laminate comprising a plurality of alternately stacked internal electrodes and a plurality of dielectric layers, having a first surface and a second surface facing each other in the stacking direction, A laminate having a first side surface, a second side surface, a third side surface, and a fourth side surface around an axis along the stacking direction, and further having a first edge portion located between the first side surface and the second side surface, a second edge portion located between the second side surface and the third side surface, a third edge portion located between the third side surface and the fourth side surface, and a fourth edge portion located between the fourth side surface and the first side surface, A protective layer covering the area of ​​the first side, second side, third side, and fourth side, excluding predetermined edges from the first edge portion, second edge portion, third edge portion, and fourth edge portion, A multilayer ceramic capacitor comprising multiple internal electrodes and external electrodes connected at predetermined ridge portions.

2. The aforementioned external electrode is A first external electrode is located at least from the first side to the first and / or second surface and is connected at the first edge to an internal electrode of the first polarity among the plurality of internal electrodes, A multilayer ceramic capacitor according to claim 1, comprising: a second external electrode located at least from the third side surface to the first surface and / or the second surface, and connected at the second edge portion to an internal electrode of the second polarity among the plurality of internal electrodes.

3. The aforementioned external electrode is A first external electrode is located at least from the first side to the first and / or second surface and is connected at the first and fourth edges to an internal electrode of the first polarity among the plurality of internal electrodes, A multilayer ceramic capacitor according to claim 1, comprising: a second external electrode located at least from the third side surface to the first surface and / or the second surface, and connected at the second edge portion and the third edge portion to an internal electrode of the second polarity among the plurality of internal electrodes.

4. The aforementioned external electrode is A first external electrode is located at least from the first side to the first and / or second surface and is connected at the first edge to an internal electrode of the first polarity among the plurality of internal electrodes, A second external electrode is located at least from the second side to the first and / or second surface and is connected at the second edge to an internal electrode of the second polarity among the plurality of internal electrodes, A third external electrode is located at least from the third side to the first and / or second surface and is connected at the third edge to an internal electrode of the first polarity among the plurality of internal electrodes, A multilayer ceramic capacitor according to claim 1, comprising: a fourth external electrode located at least from the fourth side to the first and / or second surface, and connected at the fourth edge to an internal electrode of the second polarity among the plurality of internal electrodes.

5. The multilayer ceramic capacitor according to claim 1, wherein each of the plurality of internal electrodes has a notch that, when viewed in the stacking direction, is a right triangle with its vertex located on the edge of the predetermined edge portion, or a right triangle with a hypotenuse that bulges out in an arc shape.

6. When the region in which internal electrodes with different polarities are exposed in the stacking direction is defined as the first region, and the region in which only internal electrodes of the first polarity are exposed is defined as the second region, The multilayer ceramic capacitor according to claim 1, wherein the protective layer is located in the first region and the second region in a range that does not reach the predetermined edge portion.

7. The multilayer ceramic capacitor according to claim 1, wherein the protective layer is made of a material having the same main components as the dielectric layer.

8. The multilayer ceramic capacitor according to claim 1, wherein the protective layer has a thickness of 30 μm or less.

9. The laminate includes a first cover layer including the first surface and a second cover layer including the second surface. The first cover layer includes a plurality of first dummy electrodes to which the external electrodes are connected, The multilayer ceramic capacitor according to claim 1, wherein the second cover layer includes a plurality of second dummy electrodes to which the external electrodes are connected.