Overcurrent protection circuit, semiconductor device, electronic equipment, and vehicle

Abstract

An overcurrent protection circuit 34 comprises: a sense signal generation circuit 50 that generates a sense signal Vsns 1 in accordance with a monitored current IOUT; a count maximum value setting circuit 60 that sets a count maximum value Cmax in accordance with the results of comparing a second sense signal Vsns 2 corresponding to the sense signal Vsns 1 with thresholds Vth(0) to Vth(n); and a counter 70 that counts up a count value CNT when the monitored current IOUT is larger than a count start threshold Ith(0) (when Vsns 2 < Vth1(0) in this drawing), and forcibly stops the monitored current IOUT when the count value CNT reaches the count maximum value Cmax.

Description

Overcurrent protection circuit, semiconductor device, electronic device, vehicle

[0001] The present disclosure relates to an overcurrent protection circuit, a semiconductor device, an electronic device, and a vehicle.

[0002] The applicant of the present application has proposed many new technologies relating to semiconductor devices called IPDs (intelligent power devices) and SPSs (smart power switches) (see, for example, Patent Document 1).

[0003] International Publication No. 2017 / 187785

[0004] [Summary] However, with an overcurrent protection circuit incorporated in a conventional semiconductor device, it is difficult to ensure the necessary current while protecting the wire (harness) through which the current flows.

[0005] For example, an overcurrent protection circuit according to the present disclosure includes a sense signal generating circuit configured to generate a sense signal in accordance with a current to be monitored; a count expiration value setting circuit configured to set a count expiration value in accordance with a comparison result between the sense signal or a signal corresponding thereto and a plurality of threshold values; and a counter configured to count up a count value when the current to be monitored is greater than a count start threshold value, and to forcibly stop the current to be monitored when the count value reaches the count expiration value.

[0006] FIG. 1 is a diagram showing an example of the configuration of an electronic device including a semiconductor device. FIG. 2 is a block circuit diagram showing the electrical structure of the semiconductor device. FIG. 3 is a diagram showing an example of an electronic device including a mechanical fuse. FIG. 4 is a diagram showing an example of a semiconductor device that replaces a mechanical fuse. FIG. 5 is a diagram showing a cross section of a wire. FIG. 6 is a diagram showing an equivalent model of an insulator. FIG. 7 is a diagram showing general current-time characteristics. FIG. 8 is a diagram showing an embodiment of an overcurrent protection circuit. FIG. 9 is a diagram showing an example of the configuration of a counter. FIG. 10 is a diagram showing an example of overcurrent protection operation. FIG. 11 is a diagram showing the relationship between a count value and an output current. FIG. 12 is a diagram showing current-time characteristics in this embodiment. FIG. 13 is a diagram showing current-time characteristics in a modified example. FIG. 14 is a diagram showing a first example of the configuration of a sense signal generation circuit. FIG. 15 is a diagram showing a second example of the configuration of a sense signal generation circuit. FIG. 16 is a diagram showing a modified example of a count expiration value setting circuit. FIG. 17 is a diagram showing the exterior of a vehicle. FIG. 18 is a diagram showing a signal system of a vehicle.

[0007] 1 is a diagram showing an example of the configuration of an electronic device including a semiconductor device. Electronic device A of this configuration example includes a semiconductor device 1, a DC power supply 2, and a load 3.

[0008] The semiconductor device 1 is a high-side switch IC (a type of IPD) that connects / disconnects a DC power supply 2 and a load 3, and is configured by integrating a power MISFET (metal insulator semiconductor field effect transistor) 9 and a controller 10.

[0009] The semiconductor device 1 also includes a plurality of external electrodes as means for establishing electrical connection with the outside of the device. Referring to the figure, the semiconductor device 1 includes a drain electrode 11 (corresponding to the power supply electrode VBB), a source electrode 12 (corresponding to the output electrode OUT), an input electrode 13 (corresponding to the input electrode IN), and a reference voltage electrode 14 (corresponding to the ground electrode GND).

[0010] The power MISFET 9 is an example of an insulated gate power transistor (=output switch), and functions as a high-side switch element that connects / disconnects the drain electrode 11 and the source electrode 12 .

[0011] The controller 10 includes a plurality of types of functional circuits that realize various functions, including, for example, a circuit that generates a gate control signal VG that drives and controls the power MISFET 9 based on an external electrical signal.

[0012] The drain electrode 11 transmits a power supply voltage VB to the drain of the power MISFET 9 and various circuits of the controller 10. The source electrode 12 is connected to the source of the power MISFET 9 and transmits an output voltage VOUT and an output current IOUT to the load 3. Note that a wire (harness) laid between the source electrode 12 and the load 3 generally has an inductance component L (and a resistance component). The input electrode 13 transmits an input voltage (=input signal IN) for driving the controller 10. The reference voltage electrode 14 transmits a reference voltage (e.g., ground voltage) to the controller 10. Note that a resistance component R generally accompanies the reference voltage electrode 14 and the ground terminal.

[0013] <Semiconductor Device> Fig. 2 is a block circuit diagram showing the electrical structure of the semiconductor device 1 shown in Fig. 1. The following description will be made taking as an example a case where the semiconductor device 1 is mounted on a vehicle X. When mounted on the vehicle X, the semiconductor device 1 can be used as a high-side switch for controlling the supply of electricity to a light source such as a bulb lamp or an LED (light emitting diode) lamp, or to other types of electronic control devices.

[0014] The semiconductor device 1 includes a drain electrode 11 , a source electrode 12 , an input electrode 13 , a reference voltage electrode 14 , an enable electrode 15 , a sense electrode 16 , a gate control wiring 17 , a power MISFET 9 , and a controller 10 .

[0015] The drain electrode 11 (=power supply electrode VBB) is connected to a DC power supply 2. The drain electrode 11 provides a power supply voltage VB to the power MISFET 9 and the controller 10. The power supply voltage VB may be 10 V or more and 20 V or less. On the other hand, the source electrode 12 (=output electrode OUT) is connected to a load 3.

[0016] The input electrode 13 (=input electrode IN) may be connected to an MCU (micro controller unit), a DC / DC converter, an LDO (low drop out) regulator, or the like. The input electrode 13 provides an input voltage to the controller 10. The input voltage may be 1 V or more and 10 V or less. The reference voltage electrode 14 is connected to a reference voltage wiring (ground terminal). The reference voltage electrode 14 provides a reference voltage to the power MISFET 9 and the controller 10.

[0017] The enable electrode 15 may be connected to the MCU. An electrical signal for enabling or disabling some or all of the functions of the controller 10 is input to the enable electrode 15. The sense electrode 16 transmits an electrical signal for detecting an abnormality in the controller 10 to an external device. The sense electrode 16 may be pulled up or down by a resistor.

[0018] The gate of the power MISFET 9 is connected to the controller 10 (particularly, a gate control circuit 25 described later) via a gate control wiring 17. The drain of the power MISFET 9 is connected to a drain electrode 11. The source of the power MISFET 9 is connected to the controller 10 (particularly, a current detection circuit 27 described later) and a source electrode 12.

[0019] The controller 10 includes a sensor MISFET 21 , an input circuit 22 , a current / voltage control circuit 23 , a protection circuit 24 , a gate control circuit 25 , an active clamp circuit 26 , a current detection circuit 27 , a power supply reverse connection protection circuit 28 , and an abnormality detection circuit 29 .

[0020] The gate of the sensor MISFET 21 is connected to the gate control circuit 25. The drain of the sensor MISFET 21 is connected to the drain electrode 11. The source of the sensor MISFET 21 is connected to the current detection circuit 27.

[0021] The input circuit 22 is connected to the input electrode 13 and the current / voltage control circuit 23. The input circuit 22 may include a Schmitt trigger circuit. The input circuit 22 shapes the waveform of the electrical signal applied to the input electrode 13. The signal generated by the input circuit 22 is input to the current / voltage control circuit 23.

[0022] The current / voltage control circuit 23 is connected to a protection circuit 24, a gate control circuit 25, a power supply reverse connection protection circuit 28, and an abnormality detection circuit 29. The current / voltage control circuit 23 may include a logic circuit.

[0023] The current / voltage control circuit 23 generates various voltages in response to the electrical signals from the input circuit 22 and the protection circuit 24. In this embodiment, the current / voltage control circuit 23 includes a drive voltage generation circuit 30, a first constant voltage generation circuit 31, a second constant voltage generation circuit 32, and a reference voltage / reference current generation circuit 33.

[0024] The drive voltage generation circuit 30 generates a drive voltage for driving the gate control circuit 25. The drive voltage may be set to a value obtained by subtracting a predetermined value from the power supply voltage VB. The drive voltage generation circuit 30 may generate a drive voltage between 5 V and 15 V, which is obtained by subtracting 5 V from the power supply voltage VB. The drive voltage is input to the gate control circuit 25.

[0025] The first constant voltage generating circuit 31 generates a first constant voltage for driving the protection circuit 24. The first constant voltage generating circuit 31 may include a Zener diode or a regulator circuit (here, a Zener diode). The first constant voltage may be equal to or greater than 1 V and equal to or less than 5 V. The first constant voltage is input to the protection circuit 24 (more specifically, to the open load detection circuit 35, etc., which will be described later).

[0026] The second constant voltage generating circuit 32 generates a second constant voltage for driving the protection circuit 24. The second constant voltage generating circuit 32 may include a Zener diode or a regulator circuit (here, a regulator circuit). The second constant voltage may be equal to or greater than 1 V and equal to or less than 5 V. The second constant voltage is input to the protection circuit 24 (more specifically, an overheat protection circuit 36 ​​and an undervoltage lockout circuit 37, which will be described later).

[0027] The reference voltage / reference current generating circuit 33 generates a reference voltage and a reference current for the various circuits. The reference voltage may be 1 V or more and 5 V or less. The reference current may be 1 mA or more and 1 A or less. The reference voltage and the reference current are input to the various circuits. If the various circuits include a comparator, the reference voltage and the reference current may be input to the comparator.

[0028] The protection circuit 24 is connected to the current / voltage control circuit 23, the gate control circuit 25, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The protection circuit 24 includes an overcurrent protection circuit 34, an open load detection circuit 35, an overheat protection circuit 36, and an undervoltage lockout circuit 37.

[0029] The overcurrent protection circuit 34 protects the power MISFET 9 from an overcurrent. The overcurrent protection circuit 34 is connected to the gate control circuit 25 and the source of the sensor MISFET 21. The overcurrent protection circuit 34 may include a current monitor circuit. A signal generated by the overcurrent protection circuit 34 is input to the gate control circuit 25 (more specifically, to a drive signal output circuit 40, which will be described later).

[0030] The open load detection circuit 35 detects a short state and an open state of the power MISFET 9. The open load detection circuit 35 is connected to the current / voltage control circuit 23 and the source of the power MISFET 9. A signal generated by the open load detection circuit 35 is input to the current / voltage control circuit 23.

[0031] The overheat protection circuit 36 ​​monitors the temperature of the power MISFET 9 and protects the power MISFET 9 from an excessive temperature rise. The overheat protection circuit 36 ​​is connected to the current / voltage control circuit 23. The overheat protection circuit 36 ​​may include a temperature-sensing device such as a temperature-sensing diode or a thermistor. A signal generated by the overheat protection circuit 36 ​​is input to the current / voltage control circuit 23.

[0032] The undervoltage lockout circuit 37 prevents the power MISFET 9 from malfunctioning when the power supply voltage VB is less than a predetermined value. The undervoltage lockout circuit 37 is connected to the current / voltage control circuit 23. A signal generated by the undervoltage lockout circuit 37 is input to the current / voltage control circuit 23.

[0033] The gate control circuit 25 controls the on and off states of the power MISFET 9 and the sensor MISFET 21. The gate control circuit 25 is connected to the current / voltage control circuit 23, the protection circuit 24, the gate of the power MISFET 9, and the gate of the sensor MISFET 21.

[0034] The gate control circuit 25 outputs a gate control signal VG to the gate control wiring 17 in response to an electric signal from the current / voltage control circuit 23 and an electric signal from the protection circuit 24. The gate control signal VG is input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17. Specifically, the gate control circuit 25 controls the gate control signal VG in response to an electric signal (input signal) applied to the input electrode 13, thereby turning the power MISFET 9 on / off.

[0035] More specifically, the gate control circuit 25 includes an oscillation circuit 38, a charge pump circuit 39, and a drive signal output circuit 40. The oscillation circuit 38 oscillates in response to an electrical signal from the current / voltage control circuit 23 to generate a predetermined electrical signal. The electrical signal generated by the oscillation circuit 38 is input to the charge pump circuit 39. The charge pump circuit 39 generates a boosted voltage VCP based on the electrical signal from the oscillation circuit 38. The boosted voltage VCP generated by the charge pump circuit 39 is input to the drive signal output circuit 40.

[0036] The drive signal output circuit 40 operates by receiving the boosted voltage VCP output from the charge pump circuit 39, and generates a gate control signal VG in response to an electrical signal from the protection circuit 24 (more specifically, the overcurrent protection circuit 34). The gate control signal VG is input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17. The sensor MISFET 21 and the power MISFET 9 are simultaneously controlled by a gate control circuit 25.

[0037] The active clamp circuit 26 protects the power MISFET 9 from back electromotive force. The active clamp circuit 26 is connected to the drain electrode 11, the gate of the power MISFET 9, and the gate of the sensor MISFET 21. The active clamp circuit 26 may include a plurality of diodes.

[0038] The active clamp circuit 26 may include a plurality of diodes connected to each other in a forward bias state. The active clamp circuit 26 may include a plurality of diodes connected to each other in a reverse bias state. The active clamp circuit 26 may include a plurality of diodes connected to each other in a forward bias state and a plurality of diodes connected to each other in a reverse bias state.

[0039] The multiple diodes may include pn junction diodes, Zener diodes, or a combination of pn junction diodes and Zener diodes. The active clamp circuit 26 may include multiple Zener diodes connected to each other in a biased manner. The active clamp circuit 26 may include a Zener diode and a pn junction diode connected to each other in a reverse biased manner.

[0040] The current detection circuit 27 detects the currents flowing through the power MISFET 9 and the sensor MISFET 21. The current detection circuit 27 is connected to the protection circuit 24, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The current detection circuit 27 generates a current detection signal in response to the electrical signal (=output current IOUT) generated by the power MISFET 9 and the electrical signal (=current signal exhibiting the same behavior as the output current IOUT) generated by the sensor MISFET 21. The current detection signal is input to the abnormality detection circuit 29.

[0041] The power supply reverse connection protection circuit 28 protects the current / voltage control circuit 23, the power MISFET 9, etc. from reverse voltage when the DC power supply 2 is reverse connected. The power supply reverse connection protection circuit 28 is connected to the reference voltage electrode 14 and the current / voltage control circuit 23.

[0042] Abnormality detection circuit 29 monitors the voltage of protection circuit 24. Abnormality detection circuit 29 is connected to current / voltage control circuit 23, protection circuit 24, and current detection circuit 27. If an abnormality (such as a voltage fluctuation) occurs in any of overcurrent protection circuit 34, open load detection circuit 35, overheat protection circuit 36, and undervoltage malfunction suppression circuit 37, abnormality detection circuit 29 generates an abnormality detection signal corresponding to the voltage of protection circuit 24 and outputs it to the outside.

[0043] More specifically, the abnormality detection circuit 29 includes a first multiplexer circuit 41 and a second multiplexer circuit 42. The first multiplexer circuit 41 includes two inputs, one output, and one selection control input. The protection circuit 24 and the current detection circuit 27 are connected to the inputs of the first multiplexer circuit 41. The second multiplexer circuit 42 is connected to the output of the first multiplexer circuit 41. The current / voltage control circuit 23 is connected to the selection control input of the first multiplexer circuit 41.

[0044] The first multiplexer circuit 41 generates an abnormality detection signal in response to the electrical signal from the current / voltage control circuit 23, the voltage detection signal from the protection circuit 24, and the current detection signal from the current detection circuit 27. The abnormality detection signal generated by the first multiplexer circuit 41 is input to the second multiplexer circuit 42.

[0045] The second multiplexer circuit 42 has two inputs and one output. The inputs of the second multiplexer circuit 42 are connected to the output of the second multiplexer circuit 42 and the enable electrode 15. The output of the second multiplexer circuit 42 is connected to the sense electrode 16.

[0046] When an MCU is connected to enable electrode 15 and a pull-up or pull-down resistor is connected to sense electrode 16, an ON signal is input from the MCU to enable electrode 15, and an abnormality detection signal is extracted from sense electrode 16. The abnormality detection signal is converted into an electrical signal by the resistor connected to sense electrode 16. An abnormal state of semiconductor device 1 is detected based on this electrical signal.

[0047] 3 is a diagram showing an example of an electronic device equipped with a mechanical fuse. The electronic device B of this configuration example includes a control unit B10, a battery B20, a load B30, and a fuse box B40.

[0048] The control unit B10 drives a load B30 by receiving a power supply voltage VB from a battery B20 via a fuse box B40. Referring to the figure, the control unit B10 includes a DC / DC converter B11, a microcomputer B12, an upper switch B13, a power supply electrode B14, an output electrode B15, and a reference voltage electrode B16. The control unit B10 may be, for example, an ECU (electronic control unit).

[0049] The DC / DC converter B11 generates a desired internal power supply voltage from the power supply voltage VB and outputs it to each part (such as the microcomputer B12) of the control unit B10.

[0050] The microcomputer B12 receives the internal power supply voltage from the DC / DC converter B11 and controls the on / off of the upper switch B13.

[0051] The upper switch B13 is connected between the power supply electrode B14 and the output electrode B15, and is controlled to be turned on / off in response to an instruction from the microcomputer B12.

[0052] The power supply electrode B14 is supplied with a power supply voltage VB from a battery B20 via a fuse box B40. The output electrode B15 is connected to a load B30 via a wire W3, for example. The reference voltage electrode B16 is connected to a ground terminal, for example.

[0053] The fuse box B40 includes n fuses B41(1) to B41(n), an input electrode B42, and output electrodes B43(1) to B43(n).

[0054] The fuse B41(i) (where i = 1, 2, ..., n) is connected between the input electrode B42 and the output electrode B43(i). The fuse B41(i) is a so-called mechanical fuse, and when a current exceeding the rated current flows through it, it melts down due to Joule heat, thereby protecting the circuit.

[0055] The input electrode B42 is connected to the positive terminal of the battery B20 (=the terminal to which the power supply voltage VB is applied) via, for example, a wire W1. The output electrode B43(1) is connected to the power supply electrode B14 of the control unit B10 via, for example, a wire W2.

[0056] Electronic device B using fuse box B40 has two problems. First, the reaction time of fuse B41(i) (i.e., the time required for it to blow) is unknown and inaccurate. As a result, damage to the control unit B10 it protects can often be a problem. Second, blown fuse B41(i) must be replaced. In many cases, a complete system replacement (i.e., a replacement of fuse box B40) is required.

[0057] In order to solve the above problem, it is conceivable to use an electronic fuse (so-called e-fuse) using an IPD instead of a mechanical fuse.

[0058] 4 is a diagram showing an example of a semiconductor device that replaces a mechanical fuse. In the electronic device B of this configuration example, the fuse box B40 is replaced with a semiconductor device 1, based on the electronic device B shown in FIG.

[0059] The electronic device B may be mounted on the vehicle X. The battery B20 corresponds to a DC power supply that supplies power to the electronic device B. A wire W11 may be laid between the battery B20 and the electronic device B, serving as a current path from the battery B20 to the electronic device B. A wire W12 may be laid between the electronic device B and the control unit B10, serving as a current path from the electronic device B to the control unit B10. A wire W13 may be laid between the control unit B10 and earth (ground end), serving as a current path from the control unit B10 to earth.

[0060] The control unit B10, which is externally attached to the source electrode 12 (=output electrode OUT) of the semiconductor device 1, functions as a capacitive load with a large capacitance value when viewed from the semiconductor device 1. Therefore, the control unit B10 is depicted equivalently as a parallel circuit of a capacitor C1 and a resistor R1. Also shown in this figure is a resistor R2 for pulling down the sense electrode 16 to the ground terminal.

[0061] The semiconductor device 1 has basically the same configuration as that shown in Fig. 2. Therefore, the components already mentioned are given the same reference numerals as in Fig. 2 to avoid redundant explanation, and the main components and components related thereto will be mainly described.

[0062] The power MISFET 9 is an output switch that connects / disconnects the drain electrode 11 and the source electrode 12 in response to a gate control signal VG.

[0063] The overcurrent protection circuit 34 detects a current to be monitored and controls the gate control signal VG to apply overcurrent protection. The current to be monitored may be the output current IOUT flowing through the power MISFET 9. For example, the overcurrent protection circuit 34 may limit the output current IOUT to an overcurrent protection threshold Iocp or less (so-called current limiting operation). Alternatively, the overcurrent protection circuit 34 may repeatedly forcibly turn off and restart the power MISFET 9 every time the output current IOUT increases up to the overcurrent protection threshold Iocp (so-called hiccup control).

[0064] The overheat protection circuit 36 ​​detects the temperature to be monitored and controls the gate control signal VG to apply overheat protection. For example, the overheat protection circuit 36 ​​may repeatedly forcibly turn off and restart the power MISFET 9 every time the temperature to be monitored rises to the overheat protection threshold Ttsd.

[0065] The temperature to be monitored may be a first temperature Temp1 detected in the power element formation region including the power MISFET 9. The first temperature Temp1 may be, for example, a pn junction temperature Tj1 in the power element formation region.

[0066] The temperature to be monitored may be a temperature difference ΔTemp (=Temp1-Temp2) between a first temperature Temp1 and a second temperature Temp2 detected in an area other than the power element forming area. The second temperature Temp2 may be, for example, a pn junction temperature Tj2 in the analog circuit forming area or the logic circuit forming area, or may be a case temperature Tc of the semiconductor device 1 or an ambient temperature Ta.

[0067] As described above, in the electronic device B of this configuration example, the aforementioned fuse box B40 is replaced with the semiconductor device 1. That is, when the output current IOUT becomes excessive (for example, several tens to 100 A), the power MISFET 9 is forcibly turned off, thereby limiting or cutting off the output current IOUT quickly and accurately. Therefore, both the semiconductor device 1 and the control unit B10 can be safely protected. Furthermore, unlike a configuration using a mechanical fuse, there is no need to replace a blown fuse B41(i) even if a failure occurs.

[0068] <Considerations on Wire Protection Function> The semiconductor device 1 is an electronic circuit that controls large amounts of power. Therefore, the semiconductor device 1 has sufficient capability and robustness to protect not only its own internal circuitry, but also the load (control unit B10) and the surrounding environment. The semiconductor device 1 is a modern form of electronic relay. An intelligent protection function is implemented inside the semiconductor device 1. In an automotive environment, it is desirable to use the semiconductor device 1 to control various loads 3 (e.g., light sources such as bulb lamps or LED (light emitting diode) lamps, or other types of electronic control devices).

[0069] However, the load (control unit B10) that is the driving target of the semiconductor device 1 is connected to the battery B20 and earth via wires W11 to W13. Therefore, it is desirable that the semiconductor device 1 that functions as an electronic fuse not only has the function of protecting its own internal circuitry, the load (control unit B10), and the surrounding environment, but also has the function of protecting the wires W11 to W13.

[0070] Modern electrical / electronic devices or systems (such as vehicles, industrial equipment, and household appliances) place increasingly stringent demands on power distribution and energy management architectures. The more complex the architectures, the more electronic circuits and loads they control and drive, respectively, while requiring higher robustness, i.e., higher safety levels.

[0071] Even state-of-the-art mechanical fuses are no longer able to meet these requirements. Alternatives to mechanical fuses are needed to increase system resilience and add short-circuit or overload protection. Furthermore, other requirements arising from increasingly complex power distribution architectures, such as self-resetting capabilities, make the use of mechanical fuses alone inappropriate. Furthermore, vehicles with highly automated driving requirements require the replacement or supplementation of standard mechanical fuses or fuse boxes.

[0072] In today's applications, it is essential to maintain an acceptable thermal budget on the harness insulation material to protect the harness, connectors, and PCB (printed circuit board) traces, thus requiring new electronic circuit breakers or electronic fuses (e-fuses).

[0073] An IPD that can continuously monitor the current flowing through the harness and estimate / emulate the wire temperature can interrupt the flow of energy through the harness to the load at any time. Such an IPD can also resume current flow after an appropriate cooling period, thus acting as a self-resetting fuse, thus protecting the harness and improving the fault tolerance of the system.

[0074] Furthermore, IPDs with analog or digital interfaces can be pre-programmed with harness protection parameters (such as wire area and insulation material wire temperature limits), so using such IPDs as electronic fuses can help reduce the overall cost of the device or system.

[0075] Furthermore, by using multiple IPDs in series or in combination with conventional wire blow fuses, flexibility at the architecture level is improved. In this way, by using the electronic fuses according to the present disclosure, it is possible to increase the architecture flexibility at the system level without any constraints.

[0076] FIG. 5 is a diagram showing a cross section of a wire W. The wire W can be understood as the wires W11 to W13 mentioned above. Typically, the wire W includes a conductor Wa and an insulator Wb that covers the conductor Wa. The conductor Wa may be an annealed copper wire. The insulator Wb may be a polymer such as XLPE (cross-linked polyethylene). The maximum heat generation amount of the insulator Wb is limited. Therefore, the wire W needs to be protected. The thermal resistance of the insulator Wb is Rth. The heat capacity of the insulator Wb is Cth.

[0077] FIG. 6 is a diagram showing an equivalent model of the insulator Wb. As shown in this figure, the insulator Wb can be modeled as a time constant τ (=Rth×Cth) with thermal resistance Rth and thermal capacity Cth. The heat source is the product of the electrical resistance Rel of the conductor Wa and the square of the current I(t) flowing through the wire W (=Rel×I ２ (t)), where the thermal resistance Rth, the heat capacity Cth, and the electrical resistance Rel are each values ​​per unit length of the wire W.

[0078] A simple frequency domain approach using an equivalent model of the insulator Wb yields the following equation (1) for the temperature T(s) of the wire W: where Tamb denotes the ambient temperature of the wire W.

[0079]

[0080] Furthermore, when the above equation (1) is transformed back into the time domain using an inverse Laplace transform, the following equation (2) is obtained.

[0081]

[0082] The heat capacity Cth (and hence the time constant τ) is very large. Therefore, even if an excessive current flows in short pulses, it does not pose much of a problem. However, if an overload state (overcurrent state) continues for a long period of time, the insulator Wb will overheat and exceed its upper limit of allowable temperature. Therefore, overcurrent protection is necessary. Furthermore, the insulator Wb also cools slowly after heating. Therefore, not only the peak value of the current I flowing through the wire W but also its actual RMS (root mean square) value is important.

[0083] Considering the cooling of the insulator Wb after heating, the above formula (2) can be rewritten as the following formula (3): T init in formula (3) represents the wire temperature before the application of the current pulse.

[0084]

[0085] From the above equation (3), it can be seen that heating is due to the Joule effect caused by the electrical resistance Rel (and hence loss) of the conductor Wa, and that cooling is due to the thermal impedance of the insulator Wb.

[0086] 5 and 6, it can be seen that in a thermal equilibrium state, i.e., when the heat capacity Cth is ignored, cooling is due to the heat flow (per unit length) from the conductor Wa to the surroundings. Therefore, the power flow is given by {T(t)-Tamb} / Rth (=dT / Rth). Also, the power input or power loss inside the wire W is given by I ２ (t) × Rel. These two terms must be equal. Therefore, the following equation (4) is obtained.

[0087]

[0088] The above equation (4) can be defined as the allowable current of the wire W.

[0089] 7 is a diagram showing a typical current-time characteristic. The horizontal axis (logarithmic axis) represents the magnitude of the current flowing through the harness. The vertical axis (logarithmic axis) represents the time the current is supplied.

[0090] Curve L1 shows the relationship between the magnitude of the current (= load current) required to flow through the harness to drive the load and the current supply time. Curve L2 shows the relationship between the magnitude of the current (= harness fusing current) that will cause the harness to melt and the current supply time. Curve L3 shows the relationship between the magnitude of the upper limit current (= harness protection current) set to protect the harness and the current supply time. Curves L4 and L5 both show the relationship between the magnitude of the current (= protection current) that will activate the conventional overcurrent protection operation or overheat protection operation and the current supply time. Curve L4 shows the protection current of an IPD with an output switch on-resistance value of 4 mΩ (= 4 mΩ IPD). Curve L5 shows the protection current of an IPD with an output switch on-resistance value of 8 mΩ (= 8 mΩ IPD).

[0091] As can be seen from the comparison between curves L1 and L4, a protection current of 4 mΩ IPD can satisfy the load current. However, as can be seen from the comparison between curves L3 and L4 (see dashed box α in particular), a protection current of 4 mΩ IPD cannot satisfy the harness protection current. On the other hand, as can be seen from the comparison between curves L3 and L5, a protection current of 8 mΩ IPD can satisfy the harness protection current. However, as can be seen from the comparison between curves L1 and L5 (see dashed box β and γ in particular), a protection current of 8 mΩ IPD cannot satisfy the load current.

[0092] As described above, with conventional overcurrent protection or overheat protection, it is difficult to ensure the current necessary to drive the load while protecting the wire (harness) through which the current flows.

[0093] If the harness protection current of curve L3 can be implemented in an IPD by emulating the above-mentioned equation (2), it would be possible to both protect the harness and ensure the current necessary to drive the load. However, in order to emulate the temperature T(t) of the wire W, the square of the current I flowing through the wire W must be integrated. Therefore, it is necessary to measure the RMS value of the current I flowing through the wire W.

[0094] Furthermore, calculating the temperature rise of the wire W based on the above equation (1) requires expensive silicon solutions (such as analog-to-digital converters (ADCs), squaring, filtering, multiplication, integration, and digital memories) and / or microcontrollers capable of digitizing information and performing complex data processing.

[0095] In view of the above considerations, the following proposes an embodiment that can achieve both protection of the harness and ensuring the current necessary to drive the load by emulating the thermal behavior of the wire W (= the aforementioned equation (2)) with a lower-cost circuit configuration.

[0096] 8 is a diagram showing an embodiment of the overcurrent protection circuit 34. The overcurrent protection circuit 34 of this embodiment includes, for example, a sense signal generation circuit 50, a count expiration value setting circuit 60, and a counter 70.

[0097] The sense signal generation circuit 50 monitors an output current IOUT flowing through the power MISFET 9 (corresponding to an output switch) and generates a first sense voltage Vsns1 (corresponding to a sense signal) in accordance with the output current IOUT.

[0098] Referring to the figure, the sense signal generating circuit 50 includes a sensor MISFET 51 (for example, an N-channel MISFET), a bias circuit 52 , and a resistor 53 .

[0099] The gate of the sensor MISFET 51 is connected to the gate of the power MISFET 9 (= the application terminal of the gate control signal VG). The drain of the sensor MISFET 51 is connected to the drain of the power MISFET 9 (= the drain electrode 11). The source of the sensor MISFET 51 is connected to a bias circuit 52 (details of which will be described later). The sensor MISFET 51 connected in this manner functions as a sensor switch that is controlled in synchronization with the power MISFET 9 and generates a first sense current Isns1 corresponding to the output current IOUT. Note that the power MISFET 9 may be an element having an on-resistance value of, for example, 4 mΩ. In other words, the semiconductor device 1 may be equivalent to a 4 mΩ IPD.

[0100] The bias circuit 52 makes the source voltage Vs (51) of the sensor MISFET 51 equal to the source voltage (=output voltage VOUT) of the power MISFET 9. Referring to the figure, the bias circuit 52 includes an amplifier 521 and a transistor 522 (for example, a P-channel MISFET).

[0101] The amplifier 521 controls the gate of the transistor 522 so that the source voltage Vs (51) input to the non-inverting input terminal (+) matches the output voltage VOUT input to the inverting input terminal (-).

[0102] The source of the transistor 522 is connected to the application terminal of the source voltage Vs (51). The drain of the transistor 522 is connected to the application terminal of the first sense voltage Vsns1. The gate of the transistor 522 is connected to the output terminal of the amplifier 521.

[0103] The resistor 53 (resistance value: Ra) functions as a current / voltage conversion element that converts the first sense current Isns1 flowing through the sensor MISFET 51 into a first sense voltage Vsns1 (=Isns1×Ra). The sense signal generation circuit 50 outputs the first sense voltage Vsns1 as a sense signal.

[0104] The count completion value setting circuit 60 sets the count completion value Cmax in accordance with the result of comparing the first sense voltage Vsns1 (in this figure, the corresponding second sense voltage Vsns2) with a plurality of threshold voltages Vth1(0) to Vth1(n). Referring to this figure, the count completion value setting circuit 60 includes a signal adjustment circuit 61, a threshold voltage generation circuit 62, and a comparison circuit 63.

[0105] The signal adjustment circuit 61 adjusts the gain and level of the first sense voltage Vsns1 to generate a second sense voltage Vsns2 based on the power supply voltage VB. Referring to the figure, the signal adjustment circuit 61 includes an amplifier 611, a transistor 612 (e.g., an N-channel MISFET), a resistor 613, an external electrode 614, and a resistor 615.

[0106] The amplifier 611 controls the gate of the transistor 612 so that the first sense voltage Vsns1 input to the non-inverting input terminal (+) and the node voltage Va input to the inverting input terminal (-) match.

[0107] The source of the transistor 612 is connected to the application terminal of the node voltage Va. The drain of the transistor 612 is connected to the application terminal of the second sense voltage Vsns2. The gate of the transistor 612 is connected to the output terminal of the amplifier 611.

[0108] The resistor 613 (resistance value: Rb) is a voltage / current conversion element that converts the node voltage Va into a second sense current Isns2 (=Va / Rb).

[0109] The external electrode 614 is connected to a terminal to which a second sense voltage Vsns2 is applied.

[0110] The resistor 615 (resistance value: Rc) is externally connected between the drain electrode 11 (=application terminal of the power supply voltage VB) and the external electrode 614. The resistor 615 is a current / voltage conversion element that converts the second sense current Isns2 into a second sense voltage Vsns2 (=VB-Isns2×Rc).

[0111] For example, the larger the output current IOUT, the larger the first sense current Isns1. Therefore, the node voltage Va becomes higher and the second sense current Isns2 becomes larger. As a result, the second sense voltage Vsns2 becomes lower. Conversely, the smaller the output current IOUT, the smaller the first sense current Isns1. Therefore, the node voltage Va becomes lower and the second sense current Isns2 becomes smaller. As a result, the second sense voltage Vsns2 becomes higher.

[0112] The threshold voltage generation circuit 62 generates threshold voltages Vth1(0) to Vth1(n) based on the power supply voltage VB. Referring to the figure, the threshold voltage generation circuit 62 includes resistors 621(0) to 621(n+1) connected in series between the drain electrode 11 (the application terminal of the power supply voltage VB) and the application terminal of the reference voltage Vref. The reference voltage Vref may be, for example, a floating voltage (=VB-5V) that is 5V lower than the power supply voltage VB.

[0113] The threshold voltage Vth1(i) (where i=0, 1, ..., n) is drawn from the connection node between resistors 621(i) and 621(i+1), where Vth1(0)>Vth1(1)>...>Vth1(n) holds.

[0114] The comparison circuit 63 compares the second sense voltage Vsns2 with a plurality of threshold voltages Vth1(0) to Vth1(n) to generate a plurality of comparison signals D0 to Dn. Referring to the figure, the comparison circuit 63 includes a plurality of comparators 631(0) to 631(n).

[0115] The comparator 631(i) (where i = 0, 1, ..., n) compares the second sense voltage Vsns2 input to the inverting input terminal (-) with the threshold voltage Vth1(i) input to the non-inverting input terminal (+) to generate a comparison signal Di. The comparison signal Di goes low when the second sense voltage Vsns2 is higher than the threshold voltage Vth1(i). The comparison signal Di goes high when the second sense voltage Vsns2 is lower than the threshold voltage Vth1(i).

[0116] The count completion value Cmax is set as a digital signal Dn...D1D0, for example, with the comparison signals D0 to Dn as bits for each digit. In other words, the count completion value setting circuit 60 can be understood as a simple analog-to-digital conversion circuit.

[0117] The counter 70 receives a count expiration value Cmax (=comparison signals D0 to Dn), an input signal IN, a power-on reset signal POR, and a clock signal CLK, and generates a counter output signal CO. The counter output signal CO is output to the drive signal output circuit 40 as a forced stop signal (=overcurrent protection signal) for the output current IOUT.

[0118] For example, the counter 70 counts up the count value CNT when the comparison signal D0 is at a high level, and when the count value CNT reaches a count completion value Cmax, the counter 70 raises the counter output signal CO from a low level to a high level, forcibly stopping the output current IOUT.

[0119] 9 is a diagram showing an example of the configuration of the counter 70. The counter 70 of this example configuration includes latch circuits 71(0) to 71(n), an AND gate 72, inverters 73 and 74, and an up / down counter 75.

[0120] Latch circuit 71(i) (where i = 0, 1, ..., n) latches comparison signal Di to generate latch signal Zi. Referring to the figure, latch circuit 71(i) may be a D flip-flop that takes in a high-level signal (e.g., internal power supply voltage VDD) input to a data input terminal (D) at the timing when comparison signal Di input to a clock input terminal (>) rises to high level, and outputs the latch signal Zi from an output terminal (Q).

[0121] The latch circuit 71(i) may be reset by a power-on reset signal POR, and the latch circuit 71(0) may be reset when the counter output signal CO rises to a high level.

[0122] The AND gate 72 generates a logical product signal AO of the latch signal Z0 and the input signal IN. The logical product signal AO is at low level when at least one of the latch signal Z0 and the input signal IN is at low level. The logical product signal AO is at high level when both the latch signal Z0 and the input signal IN are at high level.

[0123] The inverter 73 inverts the logic level of the logical product signal AO to generate the countdown signal DN. The countdown signal DN is low when the logical product signal AO is high, and is high when the logical product signal AO is low.

[0124] The inverter 74 inverts the logic level of the count-down signal DN to generate the count-up signal UP. The count-up signal UP is at a low level when the count-down signal DN is at a high level, and is at a high level when the count-down signal DN is at a low level.

[0125] The up / down counter 75 counts up or down a count value CNT in synchronization with the clock signal CLK, and when the count value CNT reaches a count end value Cmax, the up / down counter 75 raises the counter output signal CO from low level to high level.

[0126] The up / down counter 75 counts up the count value CNT when the count-up signal UP is at a high level. On the other hand, the up / down counter 75 counts down the count value CNT when the count-down signal DN is at a high level. That is, the up / down counter 75 switches between counting up and counting down the count value CNT in accordance with the latch signal Z0, which corresponds to the least significant bit (=comparison signal D0) of the digital signal Dn...D1D0, among the latch signals Z0 to Zn.

[0127] In addition, the up / down counter 75 has a count end value Cmax set in accordance with the remaining latch signals Z1 to Zn.

[0128] Although not explicitly shown in the figure, the counter 70 may also have an analog or digital interface that accepts an external counter adjustment signal. This configuration allows the user to arbitrarily adjust the relationship between the magnitude of the output current IOUT and the current supply time (e.g., the oscillation frequency of the clock signal CLK or the number of series-connected flip-flops that form the up / down counter 75). This allows the user to predefine the maximum temperature rise dT of wires, PCB traces, or other insulators that form the electrical interface (see FIG. 5 ). This increases the flexibility of application design. This configuration also facilitates adapting the operation of electronic fuses to that of mechanical fuses.

[0129] Fig. 10 is a diagram showing an example of the overcurrent protection operation by the overcurrent protection circuit 34 of Fig. 8. In this diagram, from top to bottom, the input signal IN, the output current IOUT, the count value CNT and the count completion value Cmax, and the counter output signal CO are depicted.

[0130] At time t1, when the input signal IN rises to a high level, the power MISFET 9 is turned on. As a result, the output current IOUT flows. Note that the output current IOUT under normal conditions is smaller than the count start threshold Ith(0). The count start threshold Ith(0) can be understood as a current value corresponding to the aforementioned threshold voltage Vth1(0). Therefore, the comparison signal D0 (and hence the latch signal Z0) goes low, and the count value CNT does not start counting up. Furthermore, since the comparison signals D1 to Dn also go low, the count completion value Cmax is set to the highest set value Cmax(0). Furthermore, since the count value CNT has not yet reached the count completion value Cmax, the counter output signal CO remains low.

[0131] At time t2, when the output current IOUT becomes greater than the count start threshold Ith(0), the comparison signal D0 (and therefore the latch signal Z0) goes high. As a result, the count-up signal UP goes high, and the count value CNT starts to count up. Note that when the output current IOUT is lower than the threshold Ith(1), the comparison signals D1 to Dn remain low. Therefore, the count completion value Cmax is maintained at the previously mentioned set value Cmax(0). The threshold Ith(1) can be understood as the current value corresponding to the previously mentioned threshold voltage Vth1(1). Furthermore, because the count value CNT has not yet reached the count completion value Cmax, the counter output signal CO is maintained at a low level.

[0132] At time t3, when the output current IOUT exceeds the threshold value Ith(1), the comparison signal D1 (and therefore the latch signal Z1) goes high. As a result, the count end value Cmax is lowered to a set value Cmax(1), which is one step lower than the set value Cmax(0). The threshold value Ith(2) can be understood as a current value corresponding to the aforementioned threshold voltage Vth1(2). Furthermore, because the count value CNT has not yet reached the count end value Cmax, the counter output signal CO remains low.

[0133] At time t4, when the output current IOUT becomes greater than the threshold value Ith(2), the comparison signal D2 (and hence the latch signal Z2) goes high. As a result, the count end value Cmax is reduced to a set value Cmax(2), which is one step smaller than the set value Cmax(1). Furthermore, because the count value CNT has not yet reached the count end value Cmax, the counter output signal CO remains low.

[0134] At time t5, when the count value CNT reaches the count completion value Cmax, the counter output signal CO rises to a high level. As a result, the output current IOUT is forcibly stopped (shut down). When the latch signal Z0 is reset to a low level at the rising edge of the counter output signal CO, the countdown signal DN rises to a high level. Therefore, the countdown of the count value CNT begins.

[0135] In this way, it is preferable that the count completion value Cmax be reduced as the output current IOUT increases. That is, when the output current IOUT is greater than the count start threshold Ith(0), the output current IOUT is latched off in a shorter time as the output current IOUT increases. Conversely, the supply of the output current IOUT is permitted for a longer time as the output current IOUT decreases.

[0136] 11 is a diagram showing the relationship between the count value CNT and the output current IOUT. The horizontal axis represents the count value CNT of the counter 70. The vertical axis represents the output current IOUT normalized to the RMS allowable current of the wire W.

[0137] The count value CNT on the horizontal axis may be understood as the count completion value Cmax, and therefore as the current supply time of the output current IOUT. As shown in this figure, it can be seen that the count value CNT (count completion value Cmax) is reduced as the output current IOUT increases.

[0138] 12 is a diagram showing current-time characteristics in this embodiment. The horizontal axis (logarithmic axis) represents the magnitude of the current flowing through the harness. The vertical axis (logarithmic axis) represents the time the current is supplied.

[0139] Curves L1 to L5 represent the load current, the harness melting current, the 4 mΩ IPD protection current, and the 8 mΩ IPD protection current, as in Fig. 7. Curve L6 represents the relationship between the magnitude of the current (=protection current) at which the overcurrent protection operation of this embodiment is activated and the current supply time.

[0140] As can be seen from a comparison between the curves L1 and L6, the protection current of this embodiment can satisfy the load current requirement. Also, as can be seen from a comparison between the curves L3 and L6, the protection current of this embodiment can also satisfy the harness protection current requirement.

[0141] In this way, the overcurrent protection circuit 34 of this embodiment can emulate the thermal behavior of the wire W (= the above-mentioned equation (2)) with a lower-cost circuit configuration without requiring expensive silicon solutions and / or microcontrollers, thereby making it possible to both protect the harness and ensure the current required to drive the load.

[0142] Furthermore, by implementing a harness protection function in the semiconductor device 1, it is possible to reduce the load on the MCU.

[0143] 13 is a diagram showing the current-time characteristics of a modified example of this embodiment. As shown by curve L7 in this figure, multiple protection functions may be combined so that the smaller of the protection currents (curve L4) from the conventional overcurrent protection and overheat protection and the protection current (curve L6) from this embodiment takes priority. For example, the output current IOUT may be forcibly stopped in response to a logical OR signal between the first abnormality protection signal generated by the conventional overcurrent protection and overheat protection and the second abnormality protection signal (= counter output signal CO) generated by the overcurrent protection circuit 34 of this embodiment.

[0144] 14 is a diagram showing a first configuration example of the sense signal generation circuit 50. The sense signal generation circuit 50 of this configuration example is based on the previously mentioned FIG. 8, with some modifications added.

[0145] As a first change, the sense signal generating circuit 50 shares the amplifier (corresponding to the amplifier 521 described above) that forms the bias circuit 52 with the current detecting circuit 27. Referring to this figure, the current detecting circuit 27 includes a bias circuit 271.

[0146] The bias circuit 271 matches the source voltage Vs(21) of the sensor MISFET 21, which generates a current signal Ics corresponding to the output current IOUT, with the source voltage (=output voltage VOUT) of the power MISFET 9. Referring to the figure, the bias circuit 271 includes an amplifier 271a and a transistor 271b (e.g., a P-channel MISFET).

[0147] The amplifier 271a controls the gate of the transistor 271b so that the source voltage Vs(21) input to the non-inverting input terminal (+) matches the output voltage VOUT input to the inverting input terminal (-).

[0148] The source of the transistor 271b is connected to the application terminal of the source voltage Vs(21), the drain of the transistor 271b is connected to the sense electrode 16 (=the application terminal of the current detection signal Vcs), and the gate of the transistor 271b is connected to the output terminal of the amplifier 271a.

[0149] In the sense signal generation circuit 50 of this configuration example, the gate of the transistor 522 is also connected to the output terminal of the amplifier 271a. That is, the bias circuit 52 shares the amplifier 271a of the bias circuit 271. With this configuration, the amplifier 521 described above is omitted, and the circuit scale of the sense signal generation circuit 50 is reduced.

[0150] As a second change, the sense signal generation circuit 50 of this configuration example includes an external electrode 54 connected to the drain of the transistor 522 (=the application terminal of the first sense voltage Vsns1). The resistor 53 mentioned above is externally attached between the external electrode 54 and the ground terminal. With this configuration, the detection gain of the output current IOUT can be arbitrarily adjusted according to the resistance value of the resistor 53.

[0151] 15 is a diagram showing a second configuration example of the sense signal generation circuit 50. Unlike the first configuration example ( FIG. 14 ) described above, the sense signal generation circuit 50 of this configuration example includes individual amplifiers 521 and 271 a for the bias circuits 52 and 271, respectively. With this configuration, the first sense current Isns1 (and therefore the first sense voltage Vsns1) can be generated with higher accuracy.

[0152] 16 is a diagram showing a modified example of the count completion value setting circuit 60. The count completion value setting circuit 60 of this modified example is based on the count completion value setting circuit 60 shown in FIG. 8, but does not include the level adjustment function. That is, in the count completion value setting circuit 60 of this modified example, the reference potential is changed from the power supply voltage VB to the ground voltage GND.

[0153] The signal adjustment circuit 61 adjusts the gain of the first sense voltage Vsns1 to generate a second sense voltage Vsns2 based on the ground voltage GND. Referring to the figure, the signal adjustment circuit 61 includes an amplifier 616 and resistors 617 and 618.

[0154] The amplifier 616 generates a second sense voltage Vsns2 so that the first sense voltage Vsns1 input to the non-inverting input terminal (+) and the node voltage Vb input to the inverting input terminal (-) match.

[0155] The resistors 617 and 618 are connected between the application terminal of the second sense voltage Vsns2 and the ground terminal (= application terminal of the ground voltage GND). The resistors 617 and 618 function as a resistive voltage divider circuit that outputs a node voltage Vb (= divided voltage of the second sense voltage Vsns2) from a connection node between them.

[0156] The threshold voltage generation circuit 62 generates threshold voltages Vth2(0) to Vth2(n) based on the ground voltage GND. Referring to the figure, the threshold voltage generation circuit 62 includes resistors 622(0) to 622(n+1) connected in series between the ground terminal (the terminal to which the ground voltage GND is applied) and the terminal to which the reference voltage Vref is applied.

[0157] The threshold voltage Vth2(i) (where i=0, 1, ..., n) is drawn from the connection node between resistors 622(i) and 622(i+1), where Vth2(0)<Vth2(1)< ...<Vth2(n) holds.

[0158] The comparison circuit 63 compares the second sense voltage Vsns2 with a plurality of threshold voltages Vth2(0) to Vth2(n) to generate a plurality of comparison signals D0 to Dn. Referring to the figure, the comparison circuit 63 includes a plurality of comparators 632(0) to 632(n).

[0159] The comparator 632(i) (where i = 0, 1, ..., n) compares the second sense voltage Vsns2 input to the non-inverting input terminal (+) with the threshold voltage Vth2(i) input to the inverting input terminal (-) to generate a comparison signal Di. The comparison signal Di goes low when the second sense voltage Vsns2 is lower than the threshold voltage Vth2(i). The comparison signal Di goes high when the second sense voltage Vsns2 is higher than the threshold voltage Vth2(i).

[0160] In this way, the count end value setting circuit 60 does not necessarily have to have a level adjustment function.

[0161] <Application to Vehicles> Fig. 17 is a diagram showing the appearance of a vehicle X. The vehicle X of this configuration example is equipped with various electronic devices (none of which are shown) that operate by receiving power supply from a battery.

[0162] Vehicle X includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0163] The semiconductor device 1 described above can be incorporated into any of the electronic devices mounted on the vehicle X.

[0164] 18 is a diagram showing a signal system of a vehicle X. As shown in this diagram, the vehicle X includes a central ECU 80 and a plurality of zone ECUs 81 to 86. The zone ECUs 81 to 86 are provided in various parts of the vehicle X and communicate with the central ECU 80.

[0165] For example, the zone ECU 81 is provided on the front right side of the vehicle X and controls the right headlamp and turn signal lamps. The zone ECU 82 is provided on the front left side of the vehicle and controls the left headlamp and turn signal lamps. The zone ECU 83 is provided on the right side of the vehicle X and controls the right electric side mirror. The zone ECU 84 is provided on the left side of the vehicle X and controls the left electric side mirror. The zone ECU 85 is provided on the rear right side of the vehicle X and controls the right tail lamp and turn signal lamps. The zone ECU 86 is provided on the rear left side of the vehicle X and controls the left tail lamp and turn signal lamps.

[0166] The aforementioned semiconductor device 1 may be provided as an electronic fuse in multiple locations, with each of the zone ECUs 81 to 86 acting as a load. This configuration allows the length and diameter of the harness to be optimized. Furthermore, cooperation between the central ECU 80 and the zone ECUs 81 to 86 allows for optimal power supply.

[0167] <Additional Notes> The following additional notes are provided regarding the above disclosure.

[0168] For example, the overcurrent protection circuit according to the present disclosure has a configuration (first configuration) including a sense signal generating circuit configured to generate a sense signal in accordance with the current to be monitored, a count completion value setting circuit configured to set a count completion value in accordance with the result of comparing the sense signal or a signal corresponding thereto with a plurality of threshold values, and a counter configured to count up a count value when the current to be monitored is greater than a count start threshold, and to forcibly stop the current to be monitored when the count value reaches the count completion value.

[0169] In the overcurrent protection circuit according to the first configuration, the count completion value may be reduced as the monitored current increases (second configuration).

[0170] Furthermore, in the overcurrent protection circuit of the first or second configuration, the count expiration value setting circuit may include a signal adjustment circuit configured to generate a second sense signal by performing at least one of gain adjustment and level adjustment of the sense signal, and a comparison circuit configured to compare the second sense signal with the plurality of threshold values ​​to generate a plurality of comparison signals, respectively, and the count expiration value may be configured (third configuration) to be set as a digital signal in which the plurality of comparison signals are bits for each digit.

[0171] Furthermore, in the overcurrent protection circuit of the third configuration, the counter may include a plurality of latch circuits configured to latch the plurality of comparison signals to generate a plurality of latch signals, respectively, and an up / down counter configured to count up or count down the count value in synchronization with a clock signal, and the up / down counter may be configured such that the count up or count down of the count value is switched in accordance with a latch signal among the plurality of latch signals that corresponds to the least significant bit of the digital signal, and the count expiration value is set in accordance with the remaining latch signals (fourth configuration).

[0172] Furthermore, for example, a semiconductor device according to the present disclosure includes an output switch and an overcurrent protection circuit having any one of the first to fourth configurations described above, and the overcurrent protection circuit is configured to detect the output current flowing through the output switch as the monitored current (fifth configuration).

[0173] In the semiconductor device according to the fifth configuration, the sense signal generation circuit may include a sensor switch configured to be synchronously controlled with the output switch to generate a sense current corresponding to the output current, a bias circuit configured to match a node voltage of the sensor switch with a node voltage of the output switch, and a current / voltage conversion circuit configured to convert the sense current into a sense voltage, and may be configured to output the sense voltage as the sense signal (sixth configuration).

[0174] The semiconductor device according to the sixth configuration may further include a current detection circuit configured to generate a current detection signal corresponding to the output current, and the sense signal generation circuit may be configured to share an amplifier that forms the bias circuit with the current detection circuit (seventh configuration).

[0175] Furthermore, for example, the electronic device according to the present disclosure is configured (eighth configuration) to include a semiconductor device having any one of the fifth to seventh configurations described above, and a load configured to operate by receiving the output current from the semiconductor device.

[0176] Furthermore, for example, a vehicle according to the present disclosure is configured (ninth configuration) to include an electronic device according to the eighth configuration described above, a battery configured to supply power to the electronic device, and a wire configured to be a current path from the battery to the electronic device.

[0177] In addition, the vehicle according to the ninth configuration may be configured to include a central ECU (electronic control unit) and a plurality of zone ECUs provided in various parts of the vehicle and configured to communicate with the central ECU, and the semiconductor device may be configured to be provided in multiple units so that each of the plurality of zone ECUs serves as the load (tenth configuration).

[0178] According to the present disclosure, it is possible to ensure the necessary current while protecting the wires (harness) through which the current flows.

[0179] <Others> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0180] 1 Semiconductor device (high-side switch IC) 2 DC power supply 3 Load 9 Power MISFET (output switch) 10 Controller 11 Drain electrode (power supply electrode) 12 Source electrode (output electrode) 13 Input electrode 14 Reference voltage electrode 15 Enable electrode 16 Sense electrode 17 Gate control wiring 21 Sensor MISFET 22 Input circuit 23 Current / voltage control circuit 24 Protection circuit 25 Gate control circuit 26 Active clamp circuit 27 Current detection circuit 271 Bias circuit 271a Amplifier 271b Transistor (P-channel MISFET) 28 Power supply reverse connection protection circuit 29 Abnormality detection circuit 30 Drive voltage generation circuit 31 First constant voltage generation circuit 32 Second constant voltage generation circuit 33 Reference voltage / reference current generation circuit 34 Overcurrent protection circuit 35 Open load detection circuit 36 ​​Overheat protection circuit 37 DESCRIPTION OF SYMBOLS 38 Under voltage malfunction suppression circuit 38 Oscillator circuit 39 Charge pump circuit 40 Drive signal output circuit 41 First multiplexer circuit 42 Second multiplexer circuit 50 Sense signal generation circuit 51 Sensor MISFET 52 Bias circuit 521 Amplifier 522 Transistor (P-channel MISFET) 53 Resistor 54 External electrode 60 Count completion value setting circuit 61 Signal adjustment circuit 611 Amplifier 612 Transistor (N-channel MISFET) 613 Resistor 614 External electrode 615 Resistor 616 Amplifier 617, 618 Resistor 62 Threshold voltage generation circuit 621(0) to 621(n+1) Resistors 622(0) to 622(n+1) Resistors 63 Comparison circuit 631(0) to 631(n) Comparator 632(0) to 632(n) Comparator 70 Counter71(0) to 71(n) Latch circuit 72 AND gate 73, 74 Inverter 75 Up / down counter 80 Central ECU 81 to 86 Zone ECU A Electronic device B Electronic device B10 Control unit (ECU) B11 DC / DC converter B12 Microcomputer B13 Upper switch B14 Power electrode B15 Output electrode B16 Reference voltage electrode B20 Battery B30 Load B40 Fuse box B41(1) to B41(n) Fuse B42 Input electrode B43(1) to B43(n) Output electrode C1 Capacitor L Inductance component R Resistance component R1 Resistor W, W1 to W3, W11 to W13 Wire Wa Conductor Wb Insulator X Vehicle

Claims

1. A sense signal generation circuit configured to generate a sense signal according to the monitored current, A count completion value setting circuit configured to set a count completion value according to the comparison result between the sense signal or a corresponding signal and a plurality of thresholds, A counter configured to increment a count value when the monitored current is greater than a count start threshold, and to forcibly stop the monitored current when the count value reaches the count completion value, An overcurrent protection circuit equipped with this.

2. The overcurrent protection circuit according to claim 1, wherein the count expiration value is lowered as the monitored current increases.

3. The aforementioned count expiration value setting circuit is: A signal adjustment circuit configured to generate a second sense signal by performing at least one of gain adjustment and level adjustment of the aforementioned sense signal, A comparison circuit configured to generate multiple comparison signals by comparing the second sense signal with the multiple thresholds, Includes, The overcurrent protection circuit according to claim 1, wherein the count completion value is set as a digital signal with the plurality of comparison signals as bits for each digit.

4. The aforementioned counter is Multiple latch circuits configured to latch the multiple comparison signals and generate multiple latch signals, An up / down counter configured to count up or count down the count value in synchronization with a clock signal, Includes, The overcurrent protection circuit according to claim 3, wherein the up / down counter switches between counting up and counting down the count value in accordance with the latch signal corresponding to the least significant bit of the digital signal among the plurality of latch signals, and sets the count completion value in accordance with the remaining latch signals.

5. Output switch, An overcurrent protection circuit according to any one of claims 1 to 4, Equipped with, The overcurrent protection circuit is a semiconductor device that detects the output current flowing through the output switch as the current to be monitored.

6. The aforementioned sense signal generation circuit is A sensor switch configured to generate a sense current corresponding to the output current in synchronization with the output switch, A bias circuit configured to match the node voltage of the sensor switch with the node voltage of the output switch, A current / voltage conversion circuit configured to convert the aforementioned sense current into a sense voltage, Includes, The semiconductor device according to claim 5, which outputs the sense voltage as the sense signal.

7. The system further includes a current detection circuit configured to generate a current detection signal corresponding to the output current, The semiconductor device according to claim 6, wherein the sense signal generation circuit shares the amplifier forming the bias circuit with the current detection circuit.

8. The semiconductor device according to claim 5, A load configured to operate by receiving the output current supplied from the semiconductor device, An electronic device equipped with the following features.

9. The electronic device according to claim 8, A battery configured to supply power to the aforementioned electronic device, A wire configured to form a current path from the battery to the electronic device, A vehicle equipped with the following features.

10. Central ECU [electronic control unit], A plurality of zone ECUs are provided in various parts of the vehicle and configured to communicate with the central ECU, Equipped with, The vehicle according to claim 9, wherein a plurality of semiconductor devices are provided so that each of the plurality of zone ECUs becomes the load.