Plasma processing device

Abstract

The present invention provides a technique for stabilizing plasma. Provided is a plasma processing device comprising: a chamber; a substrate supporting part that is disposed within the chamber and includes at least one lower electrode; an upper electrode that is disposed above the substrate supporting part; an RF signal generator that is electrically connected to any of the at least one lower electrode or the upper electrode and is configured to generate an RF signal in order to generate plasma within the chamber; a first voltage signal generator that is electrically connected to any of the at least one lower electrode and is configured to generate a first voltage signal comprising a sequence of first voltage pulses; a second voltage signal generator that is electrically connected to the upper electrode and is configured to generate a second voltage signal; a capacitor; and a rectifying element that includes a first electrode and a second electrode, wherein the first electrode is electrically connected to a node between the upper electrode and the second voltage signal generator, and the second electrode is electrically connected to a ground potential via the capacitor.

Description

Plasma processing equipment

[0001] SUMMARY OF THE INVENTION An exemplary embodiment of the present disclosure relates to a plasma processing apparatus.

[0002] Patent Document 1 discloses a DC power supply for applying a negative DC voltage to an upper electrode, and Patent Document 2 discloses a voltage pulse generator for applying a negative voltage pulse to a bias electrode of a substrate support.

[0003] JP 2015-5755 A U.S. Patent Application Publication No. 2022 / 37119

[0004] The present disclosure provides techniques for stabilizing a plasma.

[0005] In one exemplary embodiment of the present disclosure, there is provided a plasma processing apparatus including: a chamber; a substrate support disposed within the chamber and including at least one lower electrode; an upper electrode disposed above the substrate support; an RF signal generator electrically connected to either the at least one lower electrode or the upper electrode and configured to generate an RF signal to generate a plasma in the chamber; a first voltage signal generator electrically connected to either the at least one lower electrode and configured to generate a first voltage signal, the first voltage signal having a sequence of first voltage pulses; a second voltage signal generator electrically connected to the upper electrode and configured to generate a second voltage signal; and a rectifying element including a capacitor and a first electrode and a second electrode, wherein the first electrode is electrically connected to a node between the upper electrode and the second voltage signal generator, and the second electrode is electrically connected to ground potential via the capacitor.

[0006] According to one exemplary embodiment of the present disclosure, a technique for stabilizing a plasma can be provided.

[0007] 1 is a diagram for explaining an example of the configuration of a plasma processing system. FIG. 1 is a diagram for explaining an example of the configuration of a capacitively coupled plasma processing apparatus. FIG. 2 is a diagram showing an example of coupling between a power supply 30 and a chamber 10. FIG. 3 is a timing chart showing an example of voltage waveforms of a first DC signal and a second DC signal. FIG. 4 is a timing chart showing an example of voltage waveforms of a first DC signal and a second DC signal. FIG. 5 is a timing chart showing an example of voltage waveforms of a first DC signal and a second DC signal. FIG. 6 is a timing chart showing an example of voltage waveforms of a first DC signal and a second DC signal. FIG. 7 is a diagram showing an example of the configuration of a plasma stabilization circuit according to the first embodiment. FIG. 8 is a diagram showing an example of a first filter. FIG. 9 is a diagram showing an example of a second filter. FIG. 10 is a diagram showing another example of the arrangement of a node N1. FIG. 11 is a diagram for explaining the operation of a plasma stabilization circuit 70. FIG. 12 is a diagram for explaining the operation of a plasma stabilization circuit 70. FIG. 13 is a diagram for explaining the rectification action of a first rectifying element D1. FIG. 14 is a diagram for explaining the rectification action of a first rectifying element D1. FIG. 15 is a diagram showing an example of a plasma stabilization circuit according to the second embodiment. FIG. 16 is a diagram showing an example of a second rectifying element. FIG. 1 is a diagram showing another example of coupling between the power supply 30 and the chamber 10. FIG. 2 is a diagram showing an example of the configuration of a plasma stabilization circuit according to the third embodiment. FIG. 3 is a diagram showing a modified example of the first embodiment. FIG. 4 is a diagram showing a modified example of the second embodiment. FIG. 5 is a diagram showing an example of a polarity switching circuit. FIG. 6 is a diagram showing another example of coupling between the power supply 30 and the chamber 10. FIG. 7 is a diagram showing another example of coupling between the power supply 30 and the chamber 10. FIG. 8 is a diagram showing another example of coupling between the power supply 30 and the chamber 10.

[0008] Hereinafter, each embodiment of the present disclosure will be described.

[0009] In one exemplary embodiment, a plasma processing apparatus is provided, comprising: a chamber; a substrate support disposed within the chamber and including at least one lower electrode; an upper electrode disposed above the substrate support; an RF signal generator electrically connected to either the at least one lower electrode or the upper electrode and configured to generate an RF signal to generate a plasma in the chamber; a first voltage signal generator electrically connected to either the at least one lower electrode and configured to generate a first voltage signal, the first voltage signal having a sequence of first voltage pulses; a second voltage signal generator electrically connected to the upper electrode and configured to generate a second voltage signal; and a rectifying element including a capacitor and a first electrode and a second electrode, wherein the first electrode is electrically connected to a node between the upper electrode and the second voltage signal generator, and the second electrode is electrically connected to ground potential via the capacitor.

[0010] In one exemplary embodiment, the second voltage signal comprises a sequence of second voltage pulses.

[0011] In one exemplary embodiment, the second voltage signal has a constant voltage level.

[0012] In one exemplary embodiment, the second voltage signal has a negative polarity, the first electrode is a cathode electrode, and the second electrode is an anode electrode.

[0013] In one exemplary embodiment, the sequence of first voltage pulses has a first pulse frequency in the range of 0.1 MHz to 2 MHz.

[0014] In one exemplary embodiment, the second sequence of voltage pulses has a second pulse frequency in the range of 0.1 kHz to 50 kHz.

[0015] In one exemplary embodiment, the device further comprises a filter circuit provided in a transmission line between the upper electrode and the second voltage signal generator.

[0016] In one exemplary embodiment, the device further comprises a filter circuit provided in the transmission line between the upper electrode and the node.

[0017] In one exemplary embodiment, the device further comprises a filter circuit disposed in the transmission line between the node and the second voltage signal generator.

[0018] In one exemplary embodiment, the device further comprises a first filter provided in a transmission line between the upper electrode and the node, the first filter configured to filter signals in a band of RF frequencies of the RF signal, and a second filter provided in a transmission line between the node and the second voltage signal generator, the second filter configured to filter signals in a band of pulse frequencies of the sequence of first voltage pulses.

[0019] In one exemplary embodiment, a plasma processing apparatus is provided, comprising: a chamber; a substrate support disposed within the chamber and including at least one lower electrode; an upper electrode disposed above the substrate support; an RF signal generator electrically connected to either the at least one lower electrode or the upper electrode and configured to generate an RF signal to generate a plasma in the chamber; a voltage signal generator electrically connected to either the at least one lower electrode and configured to generate a voltage signal, the voltage signal having a sequence of voltage pulses; an impedance fixing circuit electrically connected to the upper electrode; and a rectifying element including a capacitor and a first electrode and a second electrode, wherein the first electrode is electrically connected to a node between the upper electrode and the impedance fixing circuit, and the second electrode is electrically connected to ground potential via the capacitor.

[0020] In one exemplary embodiment, the voltage pulse has a negative polarity, the first electrode is a cathode electrode, and the second electrode is an anode electrode.

[0021] In one exemplary embodiment, the sequence of voltage pulses has a first pulse frequency in the range of 0.1 MHz to 2 MHz.

[0022] In one exemplary embodiment, the impedance fixing circuit includes at least one of a capacitor and an inductor.

[0023] In one exemplary embodiment, a plasma processing apparatus is provided that includes: a chamber; a substrate support disposed within the chamber and including an electrode; a first voltage signal generator electrically connected to the electrode and configured to generate a first voltage signal, the first voltage signal having a sequence of first voltage pulses; and a conductive member that forms part of the chamber or is disposed within the chamber, the rectifying element including a capacitor and a first electrode and a second electrode, the first electrode being electrically connected to the conductive member and the second electrode being electrically connected to ground potential via the capacitor.

[0024] In one exemplary embodiment, the device further comprises a second voltage signal generator electrically connected to a node between the conductive member and the first electrode of the rectifying element and configured to generate a second voltage signal.

[0025] In one exemplary embodiment, the device further comprises an impedance fixing circuit electrically connected to a node between the conductive member and the first electrode of the rectifying element.

[0026] In one exemplary embodiment, the impedance fixing circuit includes at least one of a capacitor and an inductor.

[0027] In one exemplary embodiment, the conductive member is any one of (a) an upper electrode disposed above the substrate support, (b) a ring assembly disposed on the substrate support so as to surround the substrate on the substrate support, (c) a liner disposed along the inner wall of the chamber, and (d) a baffle plate disposed so as to surround the substrate support.

[0028] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. In each drawing, the same or similar elements are designated by the same reference numerals, and redundant explanations will be omitted. Unless otherwise specified, the positional relationships, such as up, down, left, and right, will be described based on the positional relationships shown in the drawings. The dimensional ratios in the drawings do not represent actual ratios, and the actual ratios are not limited to the ratios shown in the drawings.

[0029] <Configuration Example of Plasma Processing System> FIG. 1 is a diagram illustrating a configuration example of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20 (described later), and the gas exhaust port is connected to an exhaust system 40 (described later). The substrate support 11 is disposed in the plasma processing space and has a substrate support surface for supporting a substrate.

[0030] The plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma generated in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR plasma), helicon wave plasma (HWP), surface wave plasma (SWP), or the like. Various types of plasma generators may be used, including alternating current (AC) plasma generators and direct current (DC) plasma generators. In one embodiment, the AC signal (AC power) used in the AC plasma generator has a frequency in the range of 100 kHz to 10 GHz. Thus, AC signals include radio frequency (RF) signals and microwave signals. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0031] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 may be implemented by, for example, a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. This program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 for execution. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a random access memory (RAM), a read-only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0032] The following describes a configuration example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1. Fig. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0033] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply 20, a power supply 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the plasma processing chamber 10. The gas inlet includes a showerhead 13. The substrate support 11 is disposed within the plasma processing chamber 10. The showerhead 13 is disposed above the substrate support 11. In one embodiment, the showerhead 13 forms at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the showerhead 13, a sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 is grounded. The showerhead 13 and the substrate support 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0034] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112.

[0035] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that the annular region 111b may also be provided by another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Furthermore, at least one RF / DC electrode coupled to an RF power supply 31 and / or a DC power supply 32, which will be described later, may be disposed within the ceramic member 1111a. In this case, the at least one RF / DC electrode functions as a lower electrode. When a bias RF signal and / or a DC signal, which will be described later, is supplied to the at least one RF / DC electrode, the RF / DC electrode is also called a bias electrode. Note that the conductive member of the base 1110 and the at least one RF / DC electrode may function as multiple lower electrodes. Furthermore, the electrostatic electrode 1111b may function as a lower electrode. Therefore, the substrate support 11 includes at least one lower electrode.

[0036] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0037] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the backside of the substrate W and the central region 111a.

[0038] The showerhead 13 is configured to introduce at least one process gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c. The process gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the multiple gas inlets 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas inlet may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 10a.

[0039] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one process gas.

[0040] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates a plasma from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a part of the plasma generation unit 12. Furthermore, by supplying a bias RF signal to the at least one lower electrode, a bias potential is generated on the substrate W, thereby attracting ion components in the formed plasma to the substrate W.

[0041] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0042] The second RF generator 31b is coupled to at least one lower electrode via at least one impedance matching circuit and is configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0043] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generator 32a and a second DC generator 32b. In one embodiment, the first DC generator 32a is connected to the at least one lower electrode and configured to generate a first DC signal. The generated first DC signal is applied to the at least one lower electrode. In one embodiment, the second DC generator 32b is connected to the at least one upper electrode and configured to generate a second DC signal. The generated second DC signal is applied to the at least one upper electrode.

[0044] In various embodiments, the first and second DC signals may be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or combination thereof pulse waveform. In one embodiment, a waveform generator for generating the sequence of voltage pulses from the DC signal is connected between the first DC generator 32a and at least one lower electrode. Thus, the first DC generator 32a and the waveform generator constitute a voltage pulse generator. When the second DC generator 32b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulses may have either positive or negative polarity. Furthermore, the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses within one period. The first and second DC generating units 32a and 32b may be provided in addition to the RF power supply 31, or the first DC generating unit 32a may be provided instead of the second RF generating unit 31b.

[0045] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is regulated by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0046] <Example of Coupling Between Power Supply 30 and Plasma Processing Chamber 10> FIG. 3 is a diagram showing an example of coupling between power supply 30 and plasma processing chamber 10 (hereinafter also referred to as "chamber 10") of plasma processing apparatus 1. As shown in FIG.

[0047] In one embodiment, the first RF generator 31a is electrically connected to the lower electrode of the substrate support 11 via a transmission line L2. The substrate support 11 may be provided with one or more lower electrodes. If multiple lower electrodes are provided, the first RF generator 31a may be electrically connected to any one of the multiple lower electrodes. At least one impedance matching circuit is provided on the transmission line L2. The first RF generator 31a is configured to generate a source RF signal for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generator 31a may be configured to generate multiple source RF signals having different frequencies. In one embodiment, the first RF generator 31a may be electrically connected to the upper electrode via at least one impedance matching circuit. In this case, only one lower electrode may be provided on the substrate support (i.e., multiple lower electrodes do not need to be provided on the substrate support).

[0048] In one embodiment, the first DC generating unit 32a is electrically connected to the lower electrode of the substrate support 11 via a transmission line L3. When a plurality of lower electrodes are provided, the first DC generating unit 32a may be electrically connected to the same lower electrode as the first RF generating unit 31a, or may be electrically connected to a lower electrode different from that of the first RF generating unit 31a. The first DC generating unit 32a is configured to generate a first DC signal.

[0049] In one embodiment, the first DC signal may be pulsed. For example, a first waveform generating unit may be provided on the output side (lower electrode side) of the first DC generating unit 32a. The first waveform generating unit may generate a sequence of first voltage pulses from the first DC signal. As a result, a first voltage signal having the sequence of first voltage pulses may be applied to the lower electrode. The first voltage pulses may have a pulse waveform that is rectangular, trapezoidal, triangular, or a combination thereof. Note that the first waveform generating unit may be provided integrally within the first DC generating unit 32a.

[0050] In one embodiment, the first DC signal may not be pulsed, for example, the first DC signal may have a constant voltage level and the first DC signal having the constant voltage level may be applied to the lower electrode.

[0051] In one embodiment, the second DC generator 32b is electrically connected to the upper electrode of the shower head 13 via a transmission line L1. The second DC generator 32b is configured to generate a second DC signal. A rectifying element that restricts the direction of current is provided on the transmission line L1 between the second DC generator 32b and the upper electrode. Each component of the transmission line L1, including the rectifying element, will be described later.

[0052] In one embodiment, the second DC signal may be pulsed. For example, a second waveform generating unit may be provided on the transmission line L1 on the output side (upper electrode side) of the second DC generating unit 32b. The second waveform generating unit generates a sequence of second voltage pulses from the second DC signal. As a result, the second DC signal having the sequence of second voltage pulses may be applied to the upper electrode. The second voltage pulses may have a pulse waveform that is rectangular, trapezoidal, triangular, or a combination thereof. Note that the second waveform generating unit may be provided integrally within the second DC generating unit 32b.

[0053] In one embodiment, the second DC signal may not be pulsed, for example, the second DC signal may have a constant voltage level and the second DC signal having the constant voltage level may be applied to the upper electrode.

[0054] <Example of First DC Signal and Second DC Signal> Figures 4A to 4D are timing charts showing example voltage waveforms of the first DC signal and the second DC signal. In one embodiment, the voltage waveforms of the first DC signal and the second DC signal may be repeated multiple times with a repetition period T (see Figures 4A to 4D). In one example, the first DC signal may have a repetition frequency (1 / T) of 0.1 kHz to 50 kHz. In one example, the second DC signal may have a repetition frequency (1 / T) of 0.1 kHz to 50 kHz. The repetition frequency of the first DC signal and the second DC signal may be the same or different. The first DC signal and the second DC signal may be synchronized (see Figures 4A to 4C), or may not be synchronized. For example, the first DC signal and the second DC signal may be out of phase with each other by a given value (180 degrees, for example).

[0055] FIG. 4A illustrates an example in which both the first DC signal (DC1) and the second DC signal (DC2) are pulsed. The first DC signal and the second DC signal may be generated by a first waveform generating unit and a second waveform generating unit, respectively. In one embodiment, the first DC signal has a sequence of first voltage pulses having a first voltage level V11 during a first period T1 within the repetition period T. In one example, the sequence of first voltage pulses may have a pulse frequency of 0.1 MHz to 2 MHz (hereinafter, voltage pulses with such a pulse frequency will also be referred to as "high-speed pulses"). The first DC signal has a reference voltage level V10 during a second period T2 within the repetition period T. The absolute value of the reference voltage level V10 is smaller than the absolute value of the first voltage level V11. In one embodiment, the first voltage level V11 has negative polarity. In one embodiment, the reference voltage level V10 has a zero voltage level.

[0056] The second DC signal (DC2) has a second sequence of voltage pulses having a second voltage level V21 during a first time period T1. In one example, the second sequence of voltage pulses may have a pulse frequency of 0.1 MHz to 2 MHz. The pulse frequency of the second sequence of voltage pulses may be the same as or different from the pulse frequency of the first sequence of voltage pulses. The second DC signal also has a reference voltage level V20 during a second time period T2. The reference voltage level V20 is less than the absolute value of the second voltage level V21. In one embodiment, the second voltage level V21 has negative polarity. In one embodiment, the reference voltage level V20 has a zero voltage level.

[0057] FIG. 4B shows a variation of the voltage waveform shown in FIG. 4A . The first DC signal (DC1) and the second DC signal (DC2) may be generated by a first waveform generator and a second waveform generator, respectively. Both the first DC signal and the second DC signal are pulsed. In this example, the first DC signal has a third sequence of voltage pulses having a third voltage level V12 during a second period T2 within the repetition period T. The absolute value of the third voltage level V12 is greater than the absolute value of the reference voltage level V10 and less than the absolute value of the first voltage level V11. The third sequence of voltage pulses may have a pulse frequency between 0.1 MHz and 2 MHz. The second DC signal also has a fourth sequence of voltage pulses having a fourth voltage level V22 during a second period T2 within the repetition period T. The absolute value of the fourth voltage level V22 is greater than the absolute value of the reference voltage level V20 and less than the absolute value of the second voltage level V21. The fourth sequence of voltage pulses may have a pulse frequency of 0.1 MHz to 2 MHz. Other aspects are similar to those of the example shown in FIG. 4A. In the example shown in FIG. 4B, the repeating period T may further include a third period T3. The first DC signal may have a reference voltage level V10 during the third period T3 within the repeating period T. The second DC signal may have a reference voltage level V20 during the third period T3 within the repeating period T.

[0058] FIG. 4C shows a modified example of the voltage waveform shown in FIG. 4A . Both the first DC signal (DC1) and the second DC signal (DC2) are pulsed. The first DC signal may be generated by a first waveform generating unit. The second DC signal may be generated by a second waveform generating unit (including a case where the second DC signal is integrally configured with the second DC generating unit 32b) or may be generated by the second DC generating unit 32b. In this example, the second DC signal has a sequence of second voltage pulses in a repetition period T. That is, the sequence of second voltage pulses in this example has a second voltage level V21 during the first period T1 and a reference voltage level V20 during the second period T2. The pulse frequency of the sequence of second voltage pulses may be the same as the repetition frequency (1 / T) of the first DC signal, for example, 0.1 kHz to 50 kHz (hereinafter, voltage pulses with such pulse frequencies will also be referred to as "slow pulses"). Other points may be the same as those in the example shown in FIG. 4A.

[0059] Fig. 4D is a modified example of the voltage waveform shown in Fig. 4A. In this example, only the first DC signal (DC1) is pulsed, and the second DC signal has a constant voltage level (second voltage level V21) during the first period T1 and the second period T2 within the repeating period T. The second DC signal may be generated by the second DC generating unit 32b. Other aspects may be similar to those of the example shown in Fig. 4A.

[0060] First Embodiment Immediately after a first DC signal is supplied to the lower electrode (e.g., after about one to three cycles of a high-speed pulse), a sudden current (hereinafter, this current may also be referred to as a "transient current") may instantaneously flow through the upper electrode. The magnitude of the transient current tends to increase as the voltage level of the first DC signal (bias signal) increases. The transient current is considered to be a current necessary for stabilizing the plasma in the chamber. If the transient current is limited by the circuit configuration of the power supply 30, for example, the plasma may become unstable. If the plasma becomes unstable, an abnormal discharge or the like may occur, for example, at the upper electrode (e.g., the gas inlet 13c of the shower head 13). In the first embodiment, the plasma stabilization circuit described below is provided to suppress such plasma destabilization.

[0061] FIG. 5 is a diagram illustrating a configuration example of a plasma stabilization circuit according to the first embodiment. The first embodiment is a configuration example in which a negative first DC signal is supplied to the lower electrode. As shown in FIG. 5, a node N1 is provided on a transmission line L1 between the chamber 10 (upper electrode) and the second DC generator 32b. A first rectifying element D1 and a plasma stabilization circuit 70 are provided on a transmission line L12 between the node N1 and ground potential. A first filter F1 and a second filter F2 are also provided on the transmission line L1 from the chamber 10 (upper electrode) toward the second DC generator 32b. In the example illustrated in FIG. 5, the node N1 is located on the transmission line L1 between the first filter F1 and the second filter F2. In the example illustrated in FIG. 5, the first rectifying element D1 is provided on the transmission line L12 between the node N1 and the plasma stabilization circuit 70. In one embodiment, the first rectifying element D1 may be provided on the transmission line L12 between the plasma stabilization circuit 70 and the ground potential.

[0062] In one embodiment, the second DC generating unit 32b generates a second DC signal of negative polarity. The second DC signal generated by the second DC generating unit 32b may have a slow pulse as shown in FIG. 4C . Alternatively, the second DC signal generated by the second DC generating unit 32b may have a constant voltage level as shown in FIG. 4D . The second waveform generating unit may not be provided. In one embodiment, the second DC generating unit 32b may generate a second DC signal of positive polarity.

[0063] The plasma stabilization circuit 70 includes a capacitor C1. The capacitance of the capacitor C1 is large enough to instantly supply a sufficient charge to the upper electrode. In one example, the capacitance of the capacitor C1 is 10 nF to 100 nF. The capacitor C1 may be composed of one or more capacitors.

[0064] In one embodiment, the plasma stabilization circuit 70 may be configured to include a resistor R as a neutralization circuit. The resistor R is connected in parallel with the capacitor C1. The resistor R may be configured to neutralize the charge on the capacitor C1 in approximately 1 to 10 seconds. Note that an inductor may be used as the neutralization circuit instead of or in addition to the resistor R. Furthermore, when the first rectifying element D1 is provided on the transmission line L12 between the plasma stabilization circuit 70 and the ground potential, the resistor R may be connected to a node on the transmission line L12 between the capacitor C1 and the first rectifying element D1.

[0065] The plasma stabilization circuit 70 instantaneously supplies a necessary amount of charge to the upper electrode, for example, immediately after the first DC signal (bias signal) is supplied to the lower electrode. In other words, the plasma stabilization circuit 70 allows a sufficient transient current to flow through the upper electrode, thereby preventing the plasma from becoming unstable.

[0066] The first rectifying element D1 is disposed so that the chamber 10 (upper electrode) side is the forward direction of the current when viewed from the plasma stabilization circuit 70.

[0067] In one embodiment, the first rectifying element D1 may be a diode. In this case, a cathode electrode of the first rectifying element D1 (diode) may be electrically connected to node N1. Furthermore, an anode electrode of the first rectifying element D1 (diode) may be electrically connected to the plasma stabilization circuit 70. That is, the anode electrode of the first rectifying element D1 may be electrically connected to ground potential via a capacitor C1 of the plasma stabilization circuit 70. In one example, the diode may be a mesa-type or planar-type PN junction diode. The first rectifying element D1 may be composed of multiple diodes, and in this case, the diodes may be connected in series or in parallel with each other.

[0068] The rectifying action of the first rectifying element D1 prevents the second DC signal from the second DC generating unit 32b from flowing to the plasma stabilization circuit 70. This prevents the large-capacity capacitor C1 of the plasma stabilization circuit 70 from distorting the voltage waveform of the second DC signal.

[0069] The first filter F1 is configured to filter signals (hereinafter referred to as "radio frequency signals") in the frequency band of the source RF signal generated by the first RF generator 31a. That is, the first filter F1 blocks or attenuates the radio frequency signal flowing from the chamber 10 (upper electrode) toward the first rectifying element D1. This prevents all or part of the radio frequency signal from passing through the first rectifying element D1 and heating the first rectifying element D1, which in turn reduces the rectifying effect of the first rectifying element D1. The first filter F1 also prevents the radio frequency signal from entering the second DC generator 32b. Note that if the first rectifying element D1 is located on the input side (chamber 10 side) of the first filter F1, the attenuation performance of the first filter F1 may be affected if the impedance of the first rectifying element D1 changes. In this regard, in the example shown in FIG. 5, the first rectifying element D1 is located on the output side (second DC generator 32b side) of the first filter F1. Therefore, the attenuation performance of the first filter F1 can be prevented from being affected by changes in the impedance of the first rectifying element D1.

[0070] 6A is a diagram showing an example of the first filter F1. As shown in (a) to (d) of FIG. 6A, the first filter F1 may be configured to include one or more inductors (ID) and capacitors (C). The capacitance of the capacitor of the first filter F1 is sufficiently smaller than that of the capacitor C1 of the plasma stabilization circuit 70, and in one example, is 0.01 nF to 1 nF.

[0071] The second filter F2 is configured to filter a signal (hereinafter referred to as a "bias pulse signal") in the pulse frequency band of the first DC signal (bias signal) generated by the first DC generating unit 32a. That is, the second filter F2 blocks or attenuates the bias pulse signal flowing from the first rectifying element D1 to the second DC generating unit 32b. This can prevent the bias pulse signal from entering the second DC generating unit 32b. Note that if the second filter F2 causes interference with the second DC signal, the second filter F2 may not be provided. For example, if the second DC signal has a frequency close to the pulse frequency of the first DC signal (e.g., within ±10% of the frequency), the second filter F2 may not be provided.

[0072] FIG. 6B illustrates an example of the second filter F2. As shown in (a) to (e) of FIG. 6B, the second filter F2 may include one or more inductors (ID) and capacitors (C). In one embodiment, the capacitance of the capacitor of the second filter F2 is sufficiently smaller than that of the capacitor C1 of the plasma stabilization circuit 70, for example, 0.01 nF to 1 nF. Note that in one embodiment, the capacitance of the capacitor of the second filter F2 may be approximately the same as that of the capacitor C1 of the plasma stabilization circuit 70 (for example, 10 nF to 100 nF). In this case, a rectifying element may be provided in the second filter F2. The rectifying element may prevent the second DC signal from the second DC generator 32b from flowing to the capacitor of the second filter F2, thereby preventing the waveform of the second DC signal from being distorted.

[0073] 7A and 7B are diagrams showing other arrangement examples of the node N1. As shown in FIG. 7A, the node N1 may be located on the transmission line L1 between the second filter F2 and the second DC generating unit 32b. As shown in FIG. 7B, the node N1 may be located on the transmission line L1 between the chamber 10 (upper electrode) and the first filter F1. In the examples shown in FIGS. 7A and 7B, the first filter F1 and the second filter F2 may be integrated into a single filter circuit.

[0074] In one embodiment, the position of node N1 on transmission line L1 may be appropriately set so as not to impede the current flowing from the plasma stabilization circuit 70 to the upper electrode. For example, if the first filter F1 has a relatively high inductance (e.g., approximately 100 μH to 10,000 μH), node N1 may be located between the chamber 10 (upper electrode) and the first filter F1 (see FIG. 7B). This prevents the current flowing from the plasma stabilization circuit 70 to the upper electrode from being impeded by the first filter F1. For example, if the first filter F1 has a relatively low inductance (e.g., approximately 0.1 μH to 10 μH), node N1 may be located between the first filter F1 and the second filter F2 (see FIG. 5). In this case, node N1 may also be located between the second filter F2 and the second DC generator 32b (see FIG. 7A). This is because the presence of the first filter F1 and the second filter F2 does not impede the current flowing from the plasma stabilization circuit 70 to the upper electrode.

[0075] 8A and 8B are diagrams for explaining the operation of the plasma stabilization circuit 70. Fig. 8A shows an example of a case where the plasma stabilization circuit 70 is not provided for the upper electrode. Fig. 8B shows an example of a case where the plasma stabilization circuit 70 is provided for the upper electrode. In Figs. 8A and 8B, "DC1" shows an example of the voltage waveform of the first DC signal supplied to the lower electrode, and "I" shows an example of the current waveform of the transient current flowing through the upper electrode at this time.

[0076] As shown in FIG. 8A , when the plasma stabilization circuit 70 is not provided, the peak (Ia) of the current waveform of the transient current at the upper electrode is suppressed. That is, a sufficient transient current does not flow to the upper electrode. This is because a sufficient charge is not supplied to the upper electrode. In this case, the plasma in the chamber 10 becomes unstable, and abnormal discharge, etc., may occur. In contrast, as shown in FIG. 8B , when the plasma stabilization circuit is provided, the peak (Ib > Ia) of the transient current at the upper electrode is not suppressed. That is, a sufficient transient current flows to the upper electrode. This is because a charge is instantaneously supplied from the capacitor C1 of the plasma stabilization circuit 70 to the upper electrode immediately after the first DC signal (bias signal) is supplied to the lower electrode. This can suppress destabilization of the plasma in the chamber 10.

[0077] 9A and 9B are diagrams for explaining the rectifying action of the first rectifying element D1. FIG. 9A shows an example in which the first rectifying element D1 is not provided on the transmission line L12. FIG. 9B shows an example in which the first rectifying element D1 is provided on the transmission line L12. In FIGS. 9A and 9B, the upper part shows an example of a voltage waveform of the second DC signal output from the second DC generating unit 32b. In FIGS. 9A and 9B, the lower part shows an example of a voltage waveform of the second DC signal input to the upper electrode.

[0078] 9A, when the first rectifying element D1 is not provided, the voltage waveform of the second DC signal input to the upper electrode may be significantly distorted due to the influence of the large-capacitance capacitor C1. In contrast, when the first rectifying element D1 is provided, as shown in FIG. 9B, the influence of the large-capacitance capacitor C1 is limited, and distortion of the voltage waveform of the second DC signal input to the upper electrode may be suppressed.

[0079] Second Embodiment Fig. 10 is a diagram showing a configuration example of a plasma stabilization circuit according to a second embodiment. The second embodiment is a configuration example in which a negative first DC signal is supplied to the lower electrode. The following description will focus on the configuration different from the first embodiment.

[0080] In the example shown in FIG. 10 , a second waveform generating unit 50 is provided on the transmission line L1 between the node N1 and the second DC generating unit 32b. In one embodiment, the second DC signal generated by the second DC generating unit 32b has negative polarity. The second waveform generating unit 50 is configured to pulse the second DC signal generated by the second DC generating unit 32b. The second DC signal output from the second waveform generating unit 50 may have a fast pulse as shown in FIG. 4A or 4B . Alternatively, the second DC signal output from the second waveform generating unit 50 may have a slow pulse as shown in FIG. 4C . In one embodiment, the second DC generating unit 32b may generate a positive polarity second DC signal.

[0081] In the example shown in Fig. 10, the second filter F2 shown in Fig. 5 is not provided. The second filter F2 may be provided if the second filter F2 does not interfere with the second DC signal. For example, the second filter F2 may be provided if the first DC signal has fast pulses and the second DC signal has slow pulses. In this case, the second filter F2 may be provided on the transmission line L1 between the first filter F1 and the second waveform generating section 50.

[0082] In the second embodiment, the plasma stabilization circuit 70 also instantaneously supplies the required amount of charge to the upper electrode, for example, immediately after the first DC signal (bias signal) is supplied to the lower electrode. This allows a sufficient transient current to flow through the upper electrode, thereby preventing the plasma from becoming unstable. Furthermore, due to the rectification action of the first rectifying element D1, the second DC signal output from the second waveform generating unit 50 does not flow through the plasma stabilization circuit 70. This prevents the voltage waveform of the second DC signal from being distorted by the large-capacity capacitor C1 of the plasma stabilization circuit 70.

[0083] <Second Rectifying Element> Plasma control by the second DC signal may become unstable due to a voltage (hereinafter also referred to as "VDC voltage") generated at the upper electrode by supplying a first DC signal (bias signal) to the lower electrode. For example, when the voltage level of the VDC voltage at the upper electrode becomes greater than the voltage level of the second DC signal, a period may occur in which a current of opposite polarity to that of the second DC signal flows through the upper electrode (i.e., the current flows backward). During the current backward flow, the plasma cannot be controlled by the second DC signal, and the plasma in the chamber 10 may become unstable. To suppress this phenomenon, in one embodiment, a second rectifying element may be provided in the transmission line L1.

[0084] 11 and 12 are diagrams showing examples of the second rectifying element D2. Fig. 11 shows an example in which the second rectifying element D2 is provided in the configuration according to the first embodiment shown in Fig. 5. Fig. 12 shows an example in which the second rectifying element D2 is provided in the configuration according to the second embodiment shown in Fig. 10. The second rectifying element D2 may be provided on the transmission line L1 between the node N1 and the second filter F2 (see Fig. 11), or between the node N1 and the second waveform generating section 50 (see Fig. 12).

[0085] The second rectifying element D2 is configured to block or suppress a current having a polarity opposite to that of the second DC signal generated by the second DC generating unit 32 b. For example, in the examples shown in Figures 11 and 12 and 6, when the second DC signal has negative polarity, the second rectifying element D2 may be configured to block or suppress a current flowing through the transmission line L1 from the second DC generating unit 32 b or the second waveform generating unit 50 toward the node N1.

[0086] In one embodiment, the second rectifying element D2 may be a diode. In this case, an anode electrode of the second rectifying element D2 (diode) may be electrically connected to the chamber 10 (upper electrode). Furthermore, a cathode electrode of the second rectifying element D2 (diode) may be electrically connected to the second DC generating unit 32b or the second waveform generating unit 50. In one example, the diode may be a mesa-type or planar-type PN junction diode. The second rectifying element D2 may be composed of multiple diodes, and in this case, the diodes may be connected in series or in parallel with each other.

[0087] The second rectifying element D2 can block or suppress current flowing backward through the transmission line L1 from the second DC generating unit 32b toward the node N1. This prevents the plasma control by the second DC signal from becoming unstable. This prevents the plasma in the chamber 10 from becoming unstable and causing abnormal discharge or the like.

[0088] 13 is a diagram showing another example of coupling between the power supply 30 and the chamber 10 of the plasma processing apparatus 1. In the example shown in Fig. 13, an impedance fixing circuit 60 is connected to the upper electrode via a transmission line L4, instead of the second DC generating unit 32b.

[0089] The impedance fixing circuit 60 is a circuit used to define the impedance of the upper electrode. The impedance fixing circuit may be configured by connecting inductors and / or capacitors in series or parallel to obtain a desired impedance for a desired frequency. In one embodiment, the impedance fixing circuit 60 may be configured similarly to the first filter or the second filter shown in FIG. 6A or 6B.

[0090] 14 is a diagram showing a configuration example of a plasma stabilization circuit according to a third embodiment. The third embodiment is a configuration example in which a negative first DC signal is supplied to the lower electrode. As shown in FIG. 14, a node N2 is provided between the chamber 10 (upper electrode) and the impedance fixing circuit 60. A first rectifying element D1 and a plasma stabilization circuit 70 are provided on a transmission line L42 between the node N2 and ground potential, as described in the first and second embodiments.

[0091] In the third embodiment, the plasma stabilization circuit 70 also instantaneously supplies a necessary amount of charge to the upper electrode immediately after the first DC signal (bias signal) is supplied to the lower electrode, etc. In other words, the plasma stabilization circuit 70 allows a sufficient transient current to flow through the upper electrode, thereby preventing the plasma from becoming unstable.

[0092] The capacitor C1 of the plasma stabilization circuit 70 has a low impedance. Therefore, without the first rectifying element D1, the capacitor C1 may have a strong effect on the impedance of the impedance fixing circuit 60 as viewed from the chamber 10 (upper electrode) side. In the third embodiment, the first rectifying element D1 is provided on the transmission line L42 between the node N2 and the plasma stabilization circuit 70. The first rectifying element D1 functions as a high-impedance element. Therefore, the effect of the capacitor C1 on the impedance of the impedance fixing circuit 60 as viewed from the chamber 10 (upper electrode) side can be suppressed.

[0093] <Modifications> Fig. 15A is a diagram showing a modification of the first embodiment (Fig. 5). Fig. 15B is a diagram showing a modification of the second embodiment (Fig. 10). These examples are configuration examples in which the first DC signal generated by the first DC generating unit 32a has positive polarity. Note that the second DC signal generated by the second DC generating unit 32b may have either positive polarity or negative polarity.

[0094] 15A and 15B, a third rectifying element D3 is provided on the transmission line L12. The third rectifying element D3 is arranged so that the rectifying direction is opposite to that of the first rectifying element D1, i.e., the current flows in the opposite direction on the chamber 10 (upper electrode) side as viewed from the plasma stabilization circuit 70. Except for the opposite rectifying direction, the third rectifying element D3 may be configured similarly to the first rectifying element D1.

[0095] FIG. 16 is a diagram illustrating an example of a polarity switching circuit. As shown in FIG. 16, the polarity switching circuit 80 may be provided on the transmission line L12. The polarity switching circuit 80 is configured to switch between the first rectifying element D1 and the third rectifying element D3 at a given timing. For example, the polarity switching circuit 80 may switch between the first rectifying element D1 and the third rectifying element D3 when the polarity of the first DC signal is reversed during the process. Specifically, when the first DC signal generated by the first DC generating unit 32a is negative, the polarity switching circuit 80 may turn on the switching element S-1 and turn off the switching element S-2 to enable the first rectifying element D1. In one example, when the first DC signal generated by the first DC generating unit 32a is positive, the polarity switching circuit 80 may turn off the switching element S-1 and turn on the switching element S-2 to enable the third rectifying element D3.

[0096] FIG. 17 is a diagram showing another example of the coupling between the power supply 30 and the chamber 10. In the example shown in FIG. 17, the second RF generator 31b is electrically connected to the lower electrode via a transmission line L5. That is, a bias RF signal may be supplied to the lower electrode as a bias signal. Other points may be the same as those in the example shown in FIG. 3. As in the first and second embodiments, a plasma stabilization circuit 70 and the like may be electrically connected to the upper electrode via a node N1 of the transmission line L1.

[0097] 18 is a diagram showing another example of the coupling between the power supply 30 and the chamber 10. In the example shown in FIG. 18, the second DC generating unit 32b is electrically connected to the ring assembly 112 via a transmission line L6. That is, a second DC signal may be supplied to the ring assembly 112. Other points may be the same as those in the example shown in FIG. 3. As in the first and second embodiments, the plasma stabilization circuit 70 and the like may be electrically connected to the ring assembly 112 via a node of the transmission line L6.

[0098] 18 , in one embodiment, the second DC generator 32b may be electrically connected to a conductive member other than the upper electrode. The conductive member may be disposed within the chamber 10 or may constitute a part of the chamber 10, provided that the conductive member is not the ground electrode (including the conductive path to the ground electrode). For example, the conductive member may be the ring assembly 112 described above, or a ring-shaped electrode disposed radially inside or outside the ring assembly 112 at a distance. Furthermore, for example, the conductive member may be the inner wall of the chamber 10, a liner disposed along the inner wall, or a baffle plate disposed to surround the substrate support 11. As in the first and second embodiments, a plasma stabilization circuit 70 or the like may be electrically connected to a node between the second DC generator 32b and the conductive member.

[0099] Fig. 19 is a diagram showing another example of coupling between the power supply 30 and the chamber 10. Fig. 19 is a modified example of the configuration shown in Fig. 18. In this example, instead of the second DC generating unit 32b, an impedance fixing circuit 60 is electrically connected to the ring assembly 112. As in the third embodiment, the plasma stabilization circuit 70 and the like may be electrically connected to the ring assembly 112 via a node of the transmission line L7.

[0100] 19 , in one embodiment, the impedance fixing circuit 60 may be electrically connected to a conductive member other than the upper electrode. The conductive member may be disposed within the chamber 10 or may constitute a part of the chamber 10, provided that the conductive member is an ungrounded electrode. The conductive member may be the ring assembly 112 described above, or a ring-shaped electrode disposed radially inside or outside the ring assembly 112 at a distance. For example, the conductive member may be the inner wall of the chamber 10, a liner disposed along the inner wall 10, or a baffle plate disposed to surround the substrate support 11. As in the third embodiment, a plasma stabilization circuit 70 or the like may be electrically connected to a node between the impedance fixing circuit 60 and the conductive member.

[0101] Embodiments of the present disclosure further include the following aspects.

[0102] (Supplementary Note 1) A plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber and including at least one lower electrode; an upper electrode disposed above the substrate support; an RF signal generator electrically connected to either the at least one lower electrode or the upper electrode and configured to generate an RF signal to generate plasma in the chamber; a first voltage signal generator electrically connected to either the at least one lower electrode and configured to generate a first voltage signal, the first voltage signal having a sequence of first voltage pulses; a second voltage signal generator electrically connected to the upper electrode and configured to generate a second voltage signal; a capacitor; and a rectifying element including a first electrode and a second electrode, the first electrode electrically connected to a node between the upper electrode and the second voltage signal generator, and the second electrode electrically connected to a ground potential via the capacitor.

[0103] (Supplementary Note 2) The plasma processing apparatus of Supplementary Note 1, wherein the second voltage signal has a sequence of second voltage pulses.

[0104] (Supplementary Note 3) The plasma processing apparatus according to Supplementary Note 1, wherein the second voltage signal has a constant voltage level.

[0105] (Supplementary Note 4) The plasma processing apparatus according to Supplementary Note 2, wherein the second voltage signal has a negative polarity, the first electrode is a cathode electrode, and the second electrode is an anode electrode.

[0106] (Supplementary Note 5) The plasma processing apparatus of Supplementary Note 4, wherein the sequence of first voltage pulses has a first pulse frequency in a range of 0.1 MHz to 2 MHz.

[0107] (Supplementary Note 6) The plasma processing apparatus according to Supplementary Note 4 or Supplementary Note 5, wherein the second sequence of voltage pulses has a second pulse frequency in the range of 0.1 kHz to 50 kHz.

[0108] (Supplementary Note 7) The plasma processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 6, further comprising a filter circuit provided in a transmission line between the upper electrode and the second voltage signal generator.

[0109] (Supplementary Note 8) The plasma processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 7, further comprising a filter circuit provided in a transmission line between the upper electrode and the node.

[0110] (Supplementary Note 9) The plasma processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 8, further comprising a filter circuit provided in a transmission line between the node and the second voltage signal generator.

[0111] (Supplementary Note 10) The plasma processing apparatus according to any one of Supplementary Note 1 to Supplementary Note 9, further comprising: a first filter provided in a transmission line between the upper electrode and the node and configured to filter signals in an RF frequency band of the RF signal; and a second filter provided in a transmission line between the node and the second voltage signal generator and configured to filter signals in a pulse frequency band of the sequence of first voltage pulses.

[0112] (Supplementary Note 11) A plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber and including at least one lower electrode; an upper electrode disposed above the substrate support; an RF signal generator electrically connected to either the at least one lower electrode or the upper electrode and configured to generate an RF signal to generate plasma in the chamber; a voltage signal generator electrically connected to either the at least one lower electrode and configured to generate a voltage signal, the voltage signal having a sequence of voltage pulses; an impedance fixing circuit electrically connected to the upper electrode; a capacitor; and a rectifying element including a first electrode and a second electrode, the first electrode electrically connected to a node between the upper electrode and the impedance fixing circuit, and the second electrode electrically connected to ground potential via the capacitor.

[0113] (Supplementary Note 12) The plasma processing apparatus according to Supplementary Note 11, wherein the voltage pulse has a negative polarity, the first electrode is a cathode electrode, and the second electrode is an anode electrode.

[0114] (Supplementary Note 13) The plasma processing apparatus of Supplementary Note 11 or Supplementary Note 12, wherein the sequence of voltage pulses has a first pulse frequency in a range of 0.1 MHz to 2 MHz.

[0115] (Supplementary Note 14) The plasma processing apparatus according to any one of Supplementary Note 11 to Supplementary Note 13, wherein the impedance fixing circuit includes at least one of a capacitor and an inductor.

[0116] (Supplementary Note 15) A plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber and including an electrode; a first voltage signal generator electrically connected to the electrode and configured to generate a first voltage signal, the first voltage signal having a sequence of first voltage pulses; a conductive member forming part of the chamber or disposed within the chamber; a capacitor; and a rectifying element including a first electrode and a second electrode, the first electrode being electrically connected to the conductive member and the second electrode being electrically connected to a ground potential via the capacitor.

[0117] (Supplementary Note 16) The plasma processing apparatus of Supplementary Note 15, further comprising a second voltage signal generator electrically connected to a node between the conductive member and the first electrode of the rectifying element and configured to generate a second voltage signal.

[0118] (Supplementary Note 17) The plasma processing apparatus according to Supplementary Note 15, further comprising an impedance fixing circuit electrically connected to a node between the conductive member and the first electrode of the rectifying element.

[0119] (Supplementary Note 18) The plasma processing apparatus according to Supplementary Note 17, wherein the impedance fixing circuit includes at least one of a capacitor and an inductor.

[0120] (Supplementary Note 19) A plasma processing apparatus according to any one of Supplementary Note 15 to Supplementary Note 18, wherein the conductive member is any one of: (a) an upper electrode disposed above the substrate support; (b) a ring assembly disposed on the substrate support so as to surround the substrate on the substrate support; (c) a liner disposed along the inner wall of the chamber; and (d) a baffle plate disposed so as to surround the substrate support.

[0121] The above embodiments are described for the purpose of explanation and are not intended to limit the scope of the present disclosure. Various modifications can be made to the above embodiments without departing from the scope and spirit of the present disclosure. For example, some components in one embodiment can be added to other embodiments. Also, some components in one embodiment can be replaced with corresponding components in other embodiments.

[0122] REFERENCE SIGNS LIST 1: Plasma processing apparatus, 2: Control unit, 10: Plasma processing chamber, 13: Shower head, 31a: First RF generating unit, 31b: Second RF generating unit, 32a: First DC generating unit, 32b: Second DC generating unit, 50: Second waveform generating unit, 60: Impedance fixing circuit, 70: Plasma stabilization circuit, 80: Polarity switching circuit, D1: First rectifying element, D2: Second rectifying element, F1: First filter, F2: Second filter, L1: Transmission line

Claims

1. A plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber and including at least one lower electrode; an upper electrode disposed above the substrate support; an RF signal generator electrically connected to either the at least one lower electrode or the upper electrode and configured to generate an RF signal to generate a plasma in the chamber; a first voltage signal generator electrically connected to either the at least one lower electrode and configured to generate a first voltage signal, the first voltage signal having a sequence of first voltage pulses; a second voltage signal generator electrically connected to the upper electrode and configured to generate a second voltage signal; a capacitor; and a rectifying element including a first electrode and a second electrode, the first electrode being electrically connected to a node between the upper electrode and the second voltage signal generator, and the second electrode being electrically connected to a ground potential via the capacitor.

2. The plasma processing apparatus of claim 1, wherein the second voltage signal comprises a sequence of second voltage pulses.

3. The plasma processing apparatus of claim 1, wherein the second voltage signal has a constant voltage level.

4. The plasma processing apparatus of claim 2, wherein said second voltage signal has a negative polarity, said first electrode is a cathode electrode, and said second electrode is an anode electrode.

5. The plasma processing apparatus of claim 4, wherein the first sequence of voltage pulses has a first pulse frequency in the range of 0.1 MHz to 2 MHz.

6. The plasma processing apparatus of claim 5, wherein the second sequence of voltage pulses has a second pulse frequency in the range of 0.1 kHz to 50 kHz.

7. The plasma processing apparatus of claim 1, further comprising a filter circuit provided in a transmission line between said upper electrode and said second voltage signal generator.

8. The plasma processing apparatus of claim 1, further comprising a filter circuit provided in a transmission line between said upper electrode and said node.

9. The plasma processing apparatus of claim 1, further comprising a filter circuit provided in a transmission line between said node and said second voltage signal generator.

10. The plasma processing apparatus of claim 1, further comprising: a first filter provided in a transmission line between the upper electrode and the node, the first filter configured to filter signals in a band of an RF frequency of the RF signal; and a second filter provided in a transmission line between the node and the second voltage signal generator, the second filter configured to filter signals in a band of a pulse frequency of the sequence of first voltage pulses.

11. A plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber and including at least one lower electrode; an upper electrode disposed above the substrate support; an RF signal generator electrically connected to either the at least one lower electrode or the upper electrode and configured to generate an RF signal to generate a plasma in the chamber; a voltage signal generator electrically connected to either the at least one lower electrode and configured to generate a voltage signal, the voltage signal having a sequence of voltage pulses; an impedance fixing circuit electrically connected to the upper electrode; a capacitor; and a rectifying element including a first electrode and a second electrode, the first electrode being electrically connected to a node between the upper electrode and the impedance fixing circuit, and the second electrode being electrically connected to a ground potential via the capacitor.

12. The plasma processing apparatus of claim 11, wherein the voltage pulse has a negative polarity, the first electrode is a cathode electrode, and the second electrode is an anode electrode.

13. The plasma processing apparatus of claim 12, wherein the sequence of voltage pulses has a first pulse frequency in the range of 0.1 MHz to 2 MHz.

14. The plasma processing apparatus according to claim 13, wherein the impedance fixing circuit includes at least one of a capacitor and an inductor.

15. A plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber and including an electrode; a first voltage signal generator electrically connected to the electrode and configured to generate a first voltage signal, the first voltage signal having a sequence of first voltage pulses; a conductive member forming part of the chamber or disposed within the chamber; a capacitor; and a rectifying element including a first electrode and a second electrode, the first electrode being electrically connected to the conductive member and the second electrode being electrically connected to a ground potential via the capacitor.

16. The plasma processing apparatus of claim 15, further comprising a second voltage signal generator electrically connected to a node between the conductive member and the first electrode of the rectifying element and configured to generate a second voltage signal.

17. The plasma processing apparatus according to claim 15, further comprising an impedance fixing circuit electrically connected to a node between the conductive member and the first electrode of the rectifying element.

18. The plasma processing apparatus according to claim 17, wherein the impedance fixing circuit includes at least one of a capacitor and an inductor.

19. The plasma processing apparatus of any one of claims 15 to 18, wherein the conductive member is any one of: (a) an upper electrode disposed above the substrate support; (b) a ring assembly disposed on the substrate support so as to surround the substrate on the substrate support; (c) a liner disposed along an inner wall of the chamber; and (d) a baffle plate disposed so as to surround the substrate support.