Semiconductor device

Abstract

This semiconductor device has: first, second, and third power supply lines that are formed on a substrate; first and second semiconductor layers that are formed above the substrate; and third and fourth semiconductor layers that are formed on the first and second semiconductor layers, respectively. The semiconductor device further has: a first gate that is formed between the first and second semiconductor layers and between the third and fourth semiconductor layers; and a switch transistor that has the first and second semiconductor layers and the first gate and is formed between the first and second power supply lines, or a switch transistor that has the third and fourth semiconductor layers and the first gate and is formed between the first and second power supply lines.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] A known technology is a complementary field effect transistor (CFET) technology that forms transistors by stacking them. A known technology is a buried power rail (BPR) technology that supplies a power supply potential or a ground potential to a transistor using buried wiring in which a conductor is formed in a trench formed on the surface of a semiconductor substrate. A known technology is a power switch circuit that controls the on / off supply of the power supply potential in a standard cell or the like.

[0003] US Patent Application Publication No. 2023 / 0178435 US Patent Application Publication No. 2023 / 0067311 US Patent Application Publication No. 2022 / 0123023 US Patent Application Publication No. 2022 / 0181258 International Publication No. 2020 / 065916 International Publication No. 2020 / 066797 International Publication No. 2020 / 217396 International Publication No. 2020 / 217400 US Patent Application Publication No. 2021 / 0366902 US Patent Application Publication No. 2022 / 0102479 US Patent Application Publication No. 2021 / 0210600

[0004] When a power switch circuit is formed by connecting the source or drain of a CFET to the wiring of a BPR, no detailed consideration has been given to how the power switch circuit should be laid out.

[0005] The present invention has been made in view of the above points, and has as its object to provide an appropriate layout for a power switch circuit formed using a CFET whose source and drain are connected to the wiring of a BPR.

[0006] In one aspect of the present invention, a semiconductor device includes a substrate, a first power supply line, a second power supply line, and a third power supply line formed on the substrate, a first semiconductor layer and a second semiconductor layer formed above the substrate, a third semiconductor layer formed on the first semiconductor layer, a fourth semiconductor layer formed on the second semiconductor layer, a first gate formed between the first semiconductor layer and the second semiconductor layer and between the third semiconductor layer and the fourth semiconductor layer, and a switch transistor formed between the first power supply line and the second power supply line, the switch transistor having the first semiconductor layer, the second semiconductor layer, and the first gate, or the switch transistor having the third semiconductor layer, the fourth semiconductor layer, and the first gate.

[0007] According to the disclosed technique, it is possible to appropriately layout a power switch circuit formed using a CFET whose source and drain are connected to the wiring of a BPR.

[0008] 1. A plan view showing an example of the layout of a semiconductor device in a first embodiment. 2. A cross-sectional view showing an example of the cross-sectional structure of the semiconductor device in FIG. 1. 3. A circuit diagram showing an example of a circuit arranged in the standard cell block in FIG. 1. 4. A circuit diagram showing an example of a power switch circuit in FIG. 3. 5. A perspective view showing an example of a layout of the power switch circuit and standard cell in FIG. 3. 6. A perspective view showing an example of a method of connecting a top wiring to a wiring of a BPR layer formed on a substrate. 7. A plan view showing an example of a plan view of the power switch circuit and standard cell in FIG. 5, as viewed from the top wiring side toward the substrate SUB. 8. A cross-sectional view showing an example of a cross section along the X1-X1' line in FIGS. 7 and 8. 9. A cross-sectional view showing an example of a cross section along the X2-X2' line in FIGS. 7 and 8. 10. A cross-sectional view showing an example of a cross section along the Y1-Y1' line in FIGS. 7 and 8. 11. A perspective view showing an example of a layout of the power switch circuit and standard cell in a second embodiment. 12. A circuit diagram showing an example of a power switch circuit and standard cell in a third embodiment. 13. A perspective view showing an example of a layout of the power switch circuit and standard cell in FIG. 13. 15 is a plan view showing an example of a plan view of the power switch circuit and standard cell of FIG. 14 when a substrate SUB is viewed from a top wiring side. FIG. 16 is a plan view showing an example of a plan view of the power switch circuit and standard cell of FIG. 14 when a substrate side is viewed from a bottom wiring side. FIG. 17 is a circuit diagram showing an example of a power switch circuit and standard cell in a fourth embodiment. FIG. 18 is a perspective view showing an example of a layout of the power switch circuit and standard cell of FIG. 17. FIG. 19 is a circuit diagram showing an example of a layout of the power switch circuit and standard cell of FIG. 18.

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal line or a signal terminal. A symbol indicating a power supply potential is also used to indicate a power supply line or a power supply terminal to which the power supply potential is supplied.

[0010] 1 shows an example of the layout of a semiconductor device according to the first embodiment. For example, the semiconductor device 100 shown in FIG. 1 may be a SoC (System on Chip), a standalone FPGA (Field-Programmable Gate Array), or the like.

[0011] The semiconductor device 100 has a plurality of I / O cells IOC and IOCP and an internal circuit region INTR. The I / O cell IOC is an interface circuit for a signal SGNL such as an input signal, an output signal, or an input / output signal. The I / O cell IOCP is an interface circuit for a power supply potential or a ground potential.

[0012] Each I / O cell IOC, IOCP is connected to an internal circuit region INTR. For example, the internal circuit region INTR has one or more standard cell blocks SCB in which standard cells are provided. Note that the internal circuit region INTR may also be equipped with logic circuits other than standard cells, or may also be equipped with a memory. The memory may be equipped within the standard cell block SCB.

[0013] 2 shows an example of a cross-sectional structure of the semiconductor device 100 of FIG. 1. The semiconductor device 100 has a substrate SUB and a wiring layer WL1 formed on the surface FS side of the substrate SUB. On the surface FS of the substrate SUB, source / drain S / D, which is part of a CFET, is formed on both the bottom side, which is closer to the substrate SUB, and the top side, which is farther from the substrate SUB. The source / drain S / D of the CFET may be connected to a wiring W1 formed in the wiring layer WL1. A trench is formed on the surface FS of the substrate SUB, and a conductive buried wiring BPR is formed in the trench.

[0014] 3 shows an example of a circuit arranged in the standard cell block SCB of FIG. 1. The standard cell block SCB has a power switch circuit PSW and standard cells SC. The standard cells SC are connected to a virtual power line VVDD and a ground line VSS, and operate by receiving a virtual power potential VVDD from the virtual power line VVDD. The standard cells SC have various logic circuits.

[0015] The power switch circuit PSW is connected to a power line TVDD and a ground line VSS and operates. The power switch circuit PSW includes a control circuit CNTL and a switch transistor SWT. For example, the control circuit CNTL generates a control signal COUT that controls the switch transistor SWT in response to an input signal (not shown). The power line TVDD is an example of a first power line, the virtual power line VVDD is an example of a second power line, and the ground line VSS is an example of a third power line.

[0016] The switch transistor SWT has a PMOS transistor whose source is connected to the power supply line TVDD and whose drain is connected to the virtual power supply line VVDD, and operates by receiving the voltage of a control signal COUT from the control circuit CNTL as a gate potential. While the switch transistor SWT is on, the power supply line TVDD and the virtual power supply line VVDD are electrically connected, and the power supply potential TVDD is supplied to the standard cell SC via the virtual power supply line VVDD. While the switch transistor SWT is off, the electrical connection between the power supply line TVDD and the virtual power supply line VVDD is cut off, and the virtual power supply line VVDD is set to a floating state.

[0017] 4 shows an example of the power switch circuit PSW of FIG. 3. The power switch circuit PSW has a switch transistor SWT including a PMOS transistor PM and an NMOS transistor NM. The source of the PMOS transistor PM is connected to the power supply line TVDD, and the drain is connected to the virtual power supply line VVDD. Both the source and drain of the NMOS transistor NM are floating. The gates of the PMOS transistor PM and the NMOS transistor NM receive a control signal COUT output from the control circuit CNTL of FIG. 3. The source and drain of the NMOS transistor NM of the power switch circuit PSW may be set to floating while connected to each other by wiring.

[0018] 4 shows an example in which the standard cell SC has an inverter arranged between the virtual power line VVDD and the ground line VSS. For example, the transistors of the power switch circuit PSW and the standard cell SC are CFETs.

[0019] FIG. 5 shows an example of the layout of the power switch circuit PSW and standard cell SC of FIG. 3 . In FIG. 5 , the interlayer insulating film is omitted, and the substrate SUB is simply indicated by a thick dashed line. In the layout shown in FIG. 5 , the source / drain S / D of the PMOS transistor PM of the CFET is formed in a bottom semiconductor layer disposed on the substrate SUB, and the source / drain S / D of the NMOS transistor NM of the CFET is formed in a top semiconductor layer disposed on the bottom semiconductor layer. In a CFET, the two bottom semiconductor layers are connected to each other by a nanosheet NS, and the two top semiconductor layers are connected to each other by a top nanosheet NS. In a CFET, the gate of the PMOS transistor and the gate of the NMOS transistor are common. The source / drain S / D of the NMOS transistor NM has N-type conductivity, and the source / drain S / D of the PMOS transistor PM has P-type conductivity. In the present invention, semiconductor layers may be referred to as source / drain S / D, even when they do not function as transistors. Furthermore, even if a part of the CFET structure does not function as a transistor, it may be referred to as an NMOS transistor NM or a PMOS transistor PM depending on the conductivity type of its semiconductor layer.

[0020] The symbols S and D attached to the source / drain S / D of the NMOS transistor NM and the PMOS transistor PM respectively indicate the source and drain of the transistor. The source / drain S / D of the NMOS transistor NM without the symbol S or D indicates, for example, an open state and does not function as a transistor.

[0021] 5, in the power switch circuit PSW, the PMOS transistor group and the NMOS transistor group are arranged in the order of drain, gate, source, gate, and drain along the Y direction. The Y direction is an example of the first direction. As shown in FIG. 4, the source and drain of the NMOS transistor of the switch transistor SWT are in an open state.

[0022] The PMOS transistor group and NMOS transistor group of the power switch circuit PSW are arranged on the substrate SUB at a position corresponding to the position between the power supply line TVDD and the virtual power supply line VVDD of the BPR layer in a plan view. That is, the PMOS transistor group and NMOS transistor group of the power switch circuit PSW are arranged at a position shifted in the X direction in a plan view from the power supply line TVDD and the virtual power supply line VVDD of the BPR layer. The X direction is an example of the second direction.

[0023] In the power switch circuit PSW, the source of the PMOS transistor of the switch transistor SWT is connected to the power line TVDD of the BPR layer via a bottom wiring BTM and a via VIA extending in the X direction. The drain of the PMOS transistor of the switch transistor SWT is connected to the virtual power line VVDD of the BPR layer via a bottom wiring BTM and a via VIA extending in the X direction. The bottom wiring BTM and the transistor on the substrate SUB side (bottom side) of the CFET have portions that are positioned at the same position in the Z direction.

[0024] In the standard cell SC, the source of the NMOS transistor is connected to the ground line VSS of the BPR layer via a top wiring TOP extending in the X direction and a via VIA. In the standard cell SC, the drain of the NMOS transistor is connected to an upper layer wiring (not shown) via a top wiring TOP extending in the X direction and a via VIA. In the standard cell SC, the drain of the NMOS transistor is also connected to a bottom wiring BTM via a via VIA. The top wiring TOP and the transistor on the opposite side (top side) of the CFET from the substrate SUB have portions that are located at the same position in the Z direction.

[0025] In the standard cell SC, the source of the PMOS transistor is connected to the virtual power line VVDD of the BPR layer via a bottom wiring BTM and a via VIA that are common to the drain D of the PMOS transistor PM of the power switch circuit PSW and extend in the X direction. In the standard cell SC, the drain of the PMOS transistor is connected to the top wiring TOP via a bottom wiring BTM and a via VIA that also extend in the X direction. Note that, in the PMOS and NMOS transistors of the standard cell SC, the gates and sources on the far side in the Y direction in FIG. 5 are set to an open state and are not used.

[0026] In the switch transistor SWT and the standard cell SC, the gate GT of each transistor is connected to an upper wiring (not shown) through a via VIA formed on the gate GT. The gate GT of the switch transistor SWT is an example of a first gate.

[0027] 5, the virtual power supply line VVDD of the BPR layer at the boundary between the power supply switch circuit PSW and the standard cell SC is connected in common to the power supply switch circuit PSW and the standard cell SC, but separate virtual power supply lines VVDD may be provided for each. Also, in the power supply switch circuit PSW, the positions of the power supply line TVDD and the virtual power supply line VVDD of the BPR layer may be interchanged.

[0028] 6A and 6B show examples of methods for connecting the top wiring TOP and the wiring of the BPR layer formed on the substrate SUB. As shown in FIG. 6A, the top wiring TOP and the wiring of the BPR layer may be directly connected by a via VIA without going through the bottom wiring BTM, similar to the wiring of the standard cell SC in FIG. 5. As shown in FIG. 6B, the top wiring TOP and the wiring of the BPR layer may be connected through the bottom wiring BTM. Note that the wiring method of FIG. 6B may be applied to other embodiments.

[0029] 7 shows an example of a plan view of the power switch circuit PSW and the standard cell SC as viewed from the top wiring TOP side to the substrate SUB side in FIG. 7. In FIG. 7, the source and drain of the NMOS transistor NM not marked with either the symbol S or D are in an open state and do not function as a transistor.

[0030] The wiring indicated by thick solid lines extending in the Y direction indicates the wiring of the wiring layer FSM1 (FSM stands for Frontside Metal) arranged above the switch transistor SWT and the standard cell SC (the side from the substrate SUB toward the position where the CFET is arranged in the Z direction). The wiring of the line layer FSM1 is located above the top wiring TOP, and is formed using one of the wiring layers on the top wiring TOP.

[0031] The power switch circuit PSW and the NMOS transistor NM of the standard cell SC are disposed at positions offset in the X direction in plan view from the power supply line TVDD, virtual power supply line VVDD, and ground line VSS of the BPR layer. The source and drain of the NMOS transistor NM are disposed at positions corresponding to the formation region of the top wiring TOP in the Z direction. The source and drain of the NMOS transistor NM are disposed on both sides of the gate GT in the Y direction.

[0032] In the NMOS transistor NM of the power switch circuit PSW, one of the source and the drain is an example of one of the third semiconductor layer and the fourth semiconductor layer, and the other of the source and the drain is an example of the other of the third semiconductor layer and the fourth semiconductor layer.

[0033] When an inverter is formed in a standard cell SC, the drain D of the NMOS transistor NM of the inverter is connected to the output signal line OUT of the wiring layer FSM1 via the top wiring TOP and an upper via VIA, and to the bottom wiring BTM via the top wiring TOP and a lower via VIA. Hereinafter, the wiring layer FSM1 will also be referred to as the FSM1 layer. The source S of the NMOS transistor NM of the inverter is connected to the ground line VSS of the BPR layer via the top wiring TOP and a via VIA on the bottom wiring BTM side. The gate of the inverter is connected to the input signal line IN of the FSM1 layer via a via VIA.

[0034] Fig. 8 shows an example of a plan view of the power switch circuit PSW and the standard cell SC as viewed from the bottom wiring BTM side to the substrate SUB side in Fig. 5. In Fig. 8, the source and drain of the PMOS transistor PM not marked with either the symbol S or D are in an open state and do not function as a transistor.

[0035] The power switch circuit PSW and the PMOS transistor PM of the standard cell SC are disposed at positions offset in the X direction in plan view from the power supply line TVDD, virtual power supply line VVDD, and ground line VSS of the BPR layer. The source and drain of the PMOS transistor PM are disposed at positions corresponding to the formation region of the bottom wiring BTM in the Z direction. The source and drain of the PMOS transistor PM are disposed on both sides of the gate GT in the Y direction.

[0036] In the PMOS transistor PM of the power switch circuit PSW, one of the source and the drain is an example of one of the first semiconductor layer and the second semiconductor layer, and the other of the source and the drain is an example of the other of the first semiconductor layer and the second semiconductor layer.

[0037] In the power switch circuit PSW, the source S of the PMOS transistor PM is connected to the power supply line TVDD of the BPR layer through the bottom wiring BTM and the via VIA, and the drain D of the PMOS transistor PM is connected to the virtual power supply line VVDD of the BPR layer through the bottom wiring BTM and the via VIA.

[0038] 8 , when the switch transistor SWT has multiple PMOS transistors PM, the sources S of the multiple PMOS transistors PM may be connected to the power supply line TVDD of the BPR layer via a common bottom wiring BTM. Furthermore, when the virtual power supply line VVDD of the BPR layer is disposed between rows of PMOS transistors PM spaced apart in the X direction in plan view, the drains D of the rows of multiple PMOS transistors PM may be connected to the virtual power supply line VVDD of the BPR layer via a common bottom wiring BTM. This allows the number of bottom wirings BTM connected to the drains D of the PMOS transistors PM to be reduced.

[0039] When an inverter is formed in the standard cell SC, the drain D of the PMOS transistor PM is connected to the drain D of the NMOS transistor NM and the output signal line OUT in Fig. 7 through the bottom wiring BTM and the via VIA. The source S of the PMOS transistor PM of the inverter is connected to the virtual power line VVDD of the BPR layer through the bottom wiring BTM and the via VIA.

[0040] 8, the bottom wiring BTM that connects the source S of the PMOS transistor PM of the inverter to the virtual power line VVDD of the BPR layer is also connected to the drain D of the PMOS transistor PM of the switch transistor SWT. The common bottom wiring BTM that interconnects the source S of the PMOS transistor PM of the inverter of the standard cell SC and the drain D of the PMOS transistor PM of the switch transistor SWT is an example of a fourth wiring.

[0041] 9 shows an example of a cross section taken along line X1-X1' in FIGS. 7 and 8. The gate GT of each transistor is connected to the wiring of the FSM1 layer through a via VIA. The gate GT of each transistor is disposed on the substrate SUB via an insulating film, and is disposed between the wiring of the BPR layer that is spaced apart in the X direction. The nanosheet NS is provided to penetrate the gate GT.

[0042] Fig. 10 shows an example of a cross section taken along line X2-X2' in Fig. 7 and Fig. 8. In the power switch circuit PSW, the source / drain S / D of the NMOS transistor NM is set to an open state, and the drain D of the PMOS transistor PM is connected to the virtual power line VVDD of the BPR layer through the bottom wiring BTM and the via VIA.

[0043] In the standard cell SC, the source S of the NMOS transistor NM is connected to the ground line VSS of the BPR layer through a top wiring TOP and a via VIA, and the source S of the PMOS transistor PM is connected to the virtual power line VVDD of the BPR layer through a bottom wiring BTM shared with the drain D of the PMOS transistor PM of the power switch circuit PSW and a via VIA.

[0044] 11 shows an example of a cross section taken along line Y1-Y1' in FIGS. 7 and 8. The source and drain S / D of the NMOS transistor NM are in an open state and do not function as a transistor. The gate GT of each transistor is connected to the wiring of the FSM1 layer via a via VIA. Nanosheets NS are formed between the source and drain S / D of the NMOS transistor NM and between the source and drain S / D of the PMOS transistor PM.

[0045] As described above, in the first embodiment, the power switch circuit PSW using a CFET can be appropriately laid out by connecting the source and drain of the CFET to the power line TVDD and the virtual power line VVDD formed in the BPR layer on the surface of the substrate SUB. As a result, the power switch circuit PSW with a reduced circuit size can be mounted on the semiconductor device 100.

[0046] Second Embodiment FIG. 12 shows an example of a layout of a power switch circuit and standard cells in a second embodiment. Elements similar to those in FIG. 5 are assigned the same reference numerals, and detailed description thereof will be omitted. For example, the power switch circuit PSW and standard cells SC shown in FIG. 12 are mounted in a standard cell block SCB of a semiconductor device 100, similar to FIG. 1. The cross-sectional structure of the semiconductor device 100 in which the power switch circuit PSW and standard cells SC of FIG. 12 are mounted is similar to FIG. 2. The circuitry arranged in the standard cell block SCB is similar to FIG. 3. An example of the circuitry of the power switch circuit PSW and standard cells SC shown in FIG. 12 is similar to FIG. 4.

[0047] 12 differs from the layout of FIG. 5 in that the Z-direction positions of the PMOS transistor PM and the NMOS transistor NM in each CFET are reversed compared to those in FIG. 5. That is, in FIG. 12, the source / drain S / D of the PMOS transistor PM is arranged on the top side, and the source / drain S / D of the NMOS transistor NM is arranged on the bottom side.

[0048] The drain D of the PMOS transistor PM of the power switch circuit PSW is connected to the virtual power line VVDD of the BPR layer through the top wiring TOP and the via VIA. Similarly, the source S of the PMOS transistor PM of the power switch circuit PSW is connected to the power line TVDD of the BPR layer through the top wiring TOP and the via VIA.

[0049] In the standard cell SC, the source S of the PMOS transistor PM is connected to the virtual power line VVDD of the BPR layer via a top wiring TOP and a via VIA that are common to the drain D of the PMOS transistor PM of the power switch circuit PSW. In the standard cell SC, the source of the NMOS transistor NM is connected to the ground line VSS of the BPR layer via a bottom wiring BTM and a via VIA.

[0050] 12, the virtual power supply line VVDD of the BPR layer at the boundary between the power supply switch circuit PSW and the standard cell SC is commonly connected to the power supply switch circuit PSW and the standard cell SC, but separate virtual power supply lines VVDD may be provided for each. Also, in the power supply switch circuit PSW, the positions of the power supply line TVDD and the virtual power supply line VVDD of the BPR layer may be interchanged.

[0051] As described above, in the second embodiment, as in the first embodiment, the power switch circuit PSW using a CFET can be appropriately laid out by connecting the source and drain of the CFET to the power line TVDD and the virtual power line VVDD formed in the BPR layer on the surface of the substrate SUB. As a result, the power switch circuit PSW with a reduced circuit size can be mounted on the semiconductor device 100.

[0052] Third Embodiment FIG. 13 shows an example of a power switch circuit and a standard cell according to a third embodiment. Elements similar to those in FIG. 4 are assigned the same reference numerals, and detailed description thereof will be omitted. For example, the power switch circuit PSW and standard cell SC shown in FIG. 13 are mounted in a standard cell block SCB of a semiconductor device 100, similar to FIG. 1. The cross-sectional structure of the semiconductor device 100 in which the power switch circuit PSW and standard cell SC of FIG. 13 are mounted is similar to that of FIG. 2. The circuit arranged in the standard cell block SCB is similar to that of FIG. 3. FIG. 13 has the same circuit configuration as that of FIG. 4, except that the source and drain of the NMOS transistor NM are connected to the virtual power line VVDD.

[0053] 14 shows an example of the layout of the power switch circuit PSW and standard cell SC of FIG. 13. Elements similar to those in FIG. 5 are assigned the same reference numerals, and detailed description thereof will be omitted. In FIG. 14, the source / drain S / D of the NMOS transistor NM of the power switch circuit PSW is connected to the virtual power line VVDD of the FSM1 layer via the top wiring TOP and via VIA. Furthermore, the drain D of the PMOS transistor PM of the power switch circuit PSW is connected to the virtual power line VVDD of the FSM1 layer not only via the virtual power line VVDD of the BPR layer, but also via the bottom wiring BTM, via VIA, top wiring TOP, and via VIA. The layout of the standard cell SC is the same as that of FIG. 5.

[0054] In the switch transistor SWT, the source / drain S / D of the NMOS transistor NM is connected to the virtual power line VVDD without being left open, thereby stabilizing the potential of the source / drain S / D of the NMOS transistor NM. This makes it possible to suppress fluctuations in the characteristics of the power switch circuit PSW. It also makes it possible to suppress charge / discharge currents (leak currents) in the source and drain regions.

[0055] 14, the positions of the PMOS transistor PM and the NMOS transistor NM in the Z direction may be reversed. That is, the source / drain S / D of the PMOS transistor PM may be arranged on the top side, and the source / drain S / D of the NMOS transistor NM may be arranged on the bottom side.

[0056] 15 shows an example of a plan view of the power switch circuit PSW and the standard cell SC in FIG. 14, as viewed from the top wiring TOP side toward the substrate SUB. Elements similar to those in FIG. 7 are given the same reference numerals, and detailed description thereof will be omitted.

[0057] The source / drain S / D of the NMOS transistor NM of the switch transistor SWT is connected to the virtual power line VVDD of the FSM1 layer through the top wiring TOP and the via VIA. The layout of the standard cell SC is the same as that of FIG.

[0058] The top wiring TOP, which connects the sources and drains S / D of the NMOS transistors NM adjacent in the X direction, is an example of the first wiring or the second wiring. The virtual power supply line VVDD of the FSM1 layer, which is connected to the sources and drains S / D of the NMOS transistors NM through the top wiring TOP and the vias VIA, is an example of the third wiring.

[0059] 16 shows an example of a plan view of the power switch circuit PSW and the standard cell SC in FIG. 14 as viewed from the bottom wiring side toward the substrate side. Elements similar to those in FIG. 8 are given the same reference numerals, and detailed description thereof will be omitted.

[0060] The drain D of the PMOS transistor PM of the switch transistor SWT is connected to the virtual power line VVDD of the BPR layer through the bottom wiring BTM and the lower via VIA, and is further connected to the virtual power line VVDD of the FSM1 layer in Fig. 15 through the bottom wiring BTM and the upper via VIA. The layout of the standard cell SC is the same as that in Fig. 8.

[0061] As described above, in the third embodiment, as in the first and second embodiments, the power switch circuit PSW using a CFET can be appropriately laid out by connecting the source and drain of the CFET to the power line TVDD and the virtual power line VVDD formed in the BPR layer on the surface of the substrate SUB. As a result, the power switch circuit PSW with a reduced circuit size can be mounted on the semiconductor device 100.

[0062] Furthermore, in the third embodiment, the source and drain of the NMOS transistor NM in the switch transistor SWT are connected to the virtual power line VVDD without being open, thereby stabilizing the potentials of the source and drain of the NMOS transistor NM. This makes it possible to suppress fluctuations in the characteristics of the switch transistor SWT. It also makes it possible to suppress charge / discharge currents (leak currents) in the source and drain regions.

[0063] (Fourth Embodiment) FIG. 17 shows an example of a power switch circuit and a standard cell according to a fourth embodiment. Elements similar to those in FIG. 4 are assigned the same reference numerals, and detailed description thereof will be omitted. For example, the power switch circuit PSW and standard cell SC shown in FIG. 17 are mounted in a standard cell block SCB of a semiconductor device 100, similar to FIG. 1. The cross-sectional structure of the semiconductor device 100 in which the power switch circuit PSW and standard cell SC of FIG. 17 are mounted is similar to that of FIG. 2. The circuit arranged in the standard cell block SCB is similar to that of FIG. 3. FIG. 17 has the same circuit configuration as that of FIG. 4, except that the switch transistor SWT of the power switch circuit PSW does not include an NMOS transistor NM, but includes only a PMOS transistor PM.

[0064] 18 shows an example of the layout of the power switch circuit PSW and standard cell SC in FIG. 17. The same elements as those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 18, the source / drain S / D of the PMOS transistor PM is formed on both the bottom side and the top side in the layout region of the power switch circuit PSW.

[0065] The wiring etc. connected to the source / drain S / D of the bottom-side PMOS transistor PM are the same as those in Fig. 5. The source S of the top-side PMOS transistor PM is connected to the power supply line TVDD of the BPR layer via a top wiring TOP and a via VIA, and a bottom wiring BTM and a via VIA that are common to the source S of the bottom-side PMOS transistor PM.

[0066] The drain D of the top-side PMOS transistor PM is connected to the virtual power line VVDD of the BPR layer via a top wiring TOP and a via VIA, and a bottom wiring BTM and a via VIA that are common to the drain D of the bottom-side PMOS transistor PM. The layout of the other elements of the power switch circuit PSW is the same as that in FIG. 5. The layout of the standard cell SC is the same as that in FIG. 8.

[0067] As described above, in the fourth embodiment, similarly to the first to third embodiments, the power switch circuit PSW using a CFET can be appropriately laid out by connecting the source and drain of the CFET to the power line TVDD and the virtual power line VVDD formed in the BPR layer on the surface of the substrate SUB. As a result, the power switch circuit PSW with a reduced circuit size can be mounted on the semiconductor device 100.

[0068] Furthermore, in the fourth embodiment, the source / drain S / D of the PMOS transistor PM is formed on both the top side and the bottom side of the power switch circuit PSW, so that the supply capability of the virtual power supply potential VVDD by the power switch circuit PSW can be improved compared to FIG. 5 and the like.

[0069] Fifth Embodiment Fig. 19 shows an example of a power switch circuit and a standard cell according to a fifth embodiment. Elements similar to those in Fig. 4 are given the same reference numerals, and detailed description thereof will be omitted. For example, the power switch circuit PSW and standard cell SC shown in Fig. 19 are mounted in a standard cell block SCB of a semiconductor device 100, similar to Fig. 1. The cross-sectional structure of the semiconductor device 100 on which the power switch circuit PSW and standard cell SC of Fig. 19 are mounted is similar to that of Fig. 2.

[0070] 19, the switch transistor SWT of the power switch circuit PSW is formed of an NMOS transistor NM, and each circuit of the standard cell SC is connected to a power supply line VDD and a virtual ground line VVSS to operate. For example, when an inverter is formed in the standard cell SC, the source of the PMOS transistor of the inverter is connected to the power supply line VDD, and the source of the NMOS transistor of the inverter is connected to the virtual ground line VVSS.

[0071] The switch transistor SWT has an NMOS transistor NM whose source is connected to a ground line TVSS and whose drain is connected to a virtual ground line VVSS. For example, the gate of the NMOS transistor NM of the switch transistor SWT receives a control signal / COUT, which is the inverted logic of the control signal COUT output from the control circuit CNTL of Fig. 3. The ground line TVSS is an example of a first power supply line, the virtual ground line VVSS is an example of a second power supply line, and the power supply line VDD is an example of a third power supply line.

[0072] 20 shows an example of the layout of the power switch circuit PSW and standard cell SC in FIG. 19. Elements similar to those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted. In FIG. 20, the layout region of the power switch circuit PSW has the source / drain S / D of the NMOS transistor NM formed on both the bottom and top sides. Furthermore, in the BPR layer, virtual ground lines VVSS, TVSS, VVSS, and power supply lines VDD extending in the Y direction are formed at intervals in the X direction.

[0073] The drain D of the bottom-side NMOS transistor NM is connected to the virtual ground line VVSS of the BPR layer via the bottom wiring BTM and the via VIA, and the source S of the bottom-side NMOS transistor NM is connected to the ground line TVSS of the BPR layer via the bottom wiring BTM and the via VIA.

[0074] The drain D of the top-side NMOS transistor NM is connected to the virtual ground line VVSS of the BPR layer via the top wiring TOP and via VIA, and the bottom wiring BTM and via VIA that are common to the drain D of the bottom-side NMOS transistor NM. The source S of the top-side NMOS transistor NM is connected to the ground line TVSS of the BPR layer via the top wiring TOP and via VIA, and the bottom wiring BTM and via VIA that are common to the source S of the bottom-side NMOS transistor NM.

[0075] In the standard cell SC, the source of the NMOS transistor is connected to the virtual ground line VVSS of the BPR layer via the top wiring TOP, via VIA, bottom wiring BTM, and via VIA, which are common to the drain D of the NMOS transistor NM of the switch transistor SWT. In the standard cell SC, the drain of the NMOS transistor is connected to an upper wiring (not shown) via the top wiring TOP and the upper via VIA, and is further connected to the bottom wiring BTM via the lower VIA.

[0076] In the standard cell SC, the source of the PMOS transistor is connected to the power supply line VDD of the BPR layer via the bottom wiring BTM and the via VIA. In the standard cell SC, the drain of the PMOS transistor is connected to the top wiring TOP via the bottom wiring BTM and the via VIA. In the PMOS and NMOS transistors of the standard cell SC, the gates and sources on the far side in the Y direction in FIG. 20 are set to an open state and are not used.

[0077] As described above, in the fifth embodiment, the source and drain of the CFET provided in the power switch circuit PSW are connected to the ground line TVSS and the virtual ground line VVSS formed in the BPR layer on the surface of the substrate SUB, and the source and drain of the CFET provided in the standard cell SC are connected to the power line VDD and the virtual ground line VVSS formed in the BPR layer on the surface of the substrate SUB.

[0078] This allows the power switch circuit PSW using a CFET to be appropriately laid out even when the standard cell SC has a switch transistor SWT whose source is connected to the ground line TVSS and whose drain is connected to the virtual ground line VVSS, and each circuit of the standard cell SC is connected to the power line VDD and the virtual ground line VVSS for operation. As a result, the power switch circuit PSW with a reduced circuit size can be mounted on the semiconductor device 100.

[0079] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0080] 100 semiconductor device BPR buried wiring BTM bottom wiring CNTL control circuit COUT, / COUT control signal D drain FSM1 wiring layer GT gate IN input signal line INTR internal circuit area IOC, IOCP I / O cell NM NMOS transistor NS nanosheet OUT output signal line PAD pad PM PMOS transistor PSW power switch circuit S source SC standard cell SCB standard cell block SGNL signal SUB substrate SWT switch transistor TOP top wiring TVDD power line TVSS ground line VDD power line VIA via VSS ground line VVDD virtual power line VVSS virtual ground line W1, W2, W3 wiring WL1, WL2 wiring layer

Claims

1. A semiconductor device comprising: a substrate; a first power supply line, a second power supply line, and a third power supply line formed on the substrate; a first semiconductor layer and a second semiconductor layer formed above the substrate; a third semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on the second semiconductor layer; a first gate formed between the first semiconductor layer and the second semiconductor layer and between the third semiconductor layer and the fourth semiconductor layer; and a switch transistor formed between the first power supply line and the second power supply line, and having the first semiconductor layer, the second semiconductor layer, and the first gate, or having the third semiconductor layer, the fourth semiconductor layer, and the first gate.

2. The semiconductor device according to claim 1, wherein the switch transistor has the first semiconductor layer, the second semiconductor layer and the first gate, and the third semiconductor layer and the fourth semiconductor layer are electrically connected.

3. The semiconductor device according to claim 1, wherein the first and second semiconductor layers, and the third and fourth semiconductor layers, have different conductivity types.

4. The semiconductor device according to claim 3, comprising a plurality of said switch transistors, wherein said third semiconductor layer and said fourth semiconductor layer of said plurality of said switch transistors are electrically connected to each other.

5. The semiconductor device according to claim 4, comprising: a first wiring that interconnects a plurality of the third semiconductor layers that are adjacent in a second direction different from a first direction in which the first power supply line, the second power supply line, and the third power supply line extend; a second wiring that interconnects a plurality of the fourth semiconductor layers that are adjacent in the second direction; and a third wiring that extends in the first direction above the first wiring and the second wiring and interconnects the first wiring and the second wiring.

6. The semiconductor device according to claim 1, wherein the third semiconductor layer and the fourth semiconductor layer are electrically connected to the second power supply line.

7. The semiconductor device according to claim 1, further comprising: a fourth wiring connected to either the first semiconductor layer or the second semiconductor layer of the switch transistor; and a standard cell having a PMOS transistor formed between the second power supply line and the third power supply line, the fourth wiring being connected to a source of the PMOS transistor.

8. The semiconductor device according to claim 1, wherein the first and second semiconductor layers, and the third and fourth semiconductor layers, have the same conductivity type.