Multilayered substrate

Abstract

This multilayered substrate comprises a substrate body and a high-frequency IC. The substrate body comprises a mounting surface pad layer, a conductor layer, a first ground layer, a high-frequency layer, and a second ground layer, in the stated order. The mounting surface pad layer, the conductor layer, the first ground layer, the high-frequency layer, and the second ground layer are laminated with a respective dielectric layer therebetween. Bumps include a mounting surface bump electrically connected to the mounting surface pad layer, a conductor bump electrically connected to the conductor layer, a first ground bump electrically connected to the first ground layer, a high-frequency bump electrically connected to the high-frequency layer, and a second ground bump electrically connected to the second ground layer. The thickness of the thinner dielectric layers among those on the first ground layer side and the second ground layer side of the high-frequency layer is greater than the thickness of the dielectric layer between the conductor layer and the mounting surface pad layer that is the closest to the mounting surface.

Description

multilayer board

[0001] This application claims priority from Japanese Patent Application No. 2023-192833, filed on November 13, 2023, the contents of which are incorporated herein by reference.

[0002] Non-Patent Document 1 discloses a multi-layer substrate including a substrate with a multi-layer structure and a beamformer mounted on this substrate.

[0003] A. Nafe, M. Sayginer, K. Kibaroglu and GM Rebeiz, "2 × 64-Element Dual-Polarized Dual-Beam Single-Aperture 28-GHz Phased Array With 2 × 30 Gb / s Links for 5G Polarization MIMO," in IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 9, pp. 3872-3884, Sept. 2020

[0004] Radio frequency integrated circuits (RFICs) are mounted on multilayer substrates via multiple bumps. For example, in multilayer substrates that perform high-frequency communication using the millimeter wave band, miniaturization of RFICs is required. Narrowing the bump pitch is an effective way to miniaturize RFICs. Considering factors such as the accuracy of conductive layer formation, it is desirable to thin the layers that make up the multilayer substrate in order to narrow the bump pitch. However, thin layers result in a lower characteristic impedance, making it difficult to achieve impedance matching with the radio frequency IC, which can result in reduced output and signal quality degradation. Therefore, it is not easy to ensure impedance matching while narrowing the bump pitch.

[0005] An object of one aspect of the present invention is to provide a multilayer substrate that ensures impedance matching and allows the bump pitch to be narrowed.

[0006] A multilayer substrate according to a first aspect of the present invention comprises a substrate body having one surface serving as a mounting surface, and a radio frequency IC mounted via bumps on each of a plurality of mounting surface pad layers formed on the mounting surface, wherein the substrate body comprises, from the mounting surface side, the mounting surface pad layer, a conductor layer including at least one of a power supply layer and a digital wiring layer, a first ground layer, a radio frequency layer, and a second ground layer, in this order, and the mounting surface pad layer, the conductor layer, the first ground layer, the radio frequency layer, and the second ground layer are each laminated via a dielectric layer, and The bumps include a mounting surface bump electrically connected to the mounting surface pad layer, a conductor bump electrically connected to the conductor layer, a first ground bump electrically connected to the first ground layer, a high-frequency bump electrically connected to the high-frequency layer, and a second ground bump electrically connected to the second ground layer, and the thickness of the thinner of the dielectric layers on the first ground layer side and the second ground layer side of the high-frequency layer is greater than the thickness of the dielectric layer between the conductor layer closest to the mounting surface and the mounting surface pad layer.

[0007] With this configuration, the dielectric layer closest to the mounting surface (the dielectric layer between the conductor layer closest to the mounting surface and the mounting surface pad layer) is relatively thin, allowing the via diameter to be small. This allows the pitch of multiple bumps to be narrowed. This makes it easier to miniaturize the high-frequency IC. With this configuration, the dielectric layer in contact with the high-frequency layer formed away from the mounting surface (the thinner of the dielectric layers on the first ground layer side and the second ground layer side of the high-frequency layer) is relatively thick, improving the characteristic impedance of the high-frequency layer. This ensures impedance matching with the high-frequency IC. This suppresses output reduction, signal quality degradation, and the like.

[0008] A second aspect of the present invention is a multilayer board according to the first aspect, wherein the conductor layer includes, from the mounting surface side, the power supply layer, a third ground layer, and the digital wiring layer, in this order, and the power supply layer, the third ground layer, and the digital wiring layer may each be stacked with the dielectric layer interposed therebetween.

[0009] A third aspect of the present invention is a multilayer substrate according to the first or second aspect, wherein the thinner of the dielectric layer on the first ground layer side of the high-frequency layer and the dielectric layer on the second ground layer side has a thickness of 0.09 mm or more, and the thickness of the dielectric layer between the conductor layer closest to the mounting surface and the mounting surface pad layer may be 0.07 mm or less.

[0010] A fourth aspect of the present invention is a multilayer substrate according to any one of the first to third aspects, wherein a first pitch, which is the pitch between the high-frequency bump and the bump adjacent to the high-frequency bump, is compared with a second pitch, which is the pitch between the conductor bump and the bump adjacent to the conductor bump, and the second pitch may be smaller than the first pitch.

[0011] A fifth aspect of the present invention may be the fourth multilayer substrate, wherein the first pitch is not less than 0.45 mm and not more than 0.55 mm.

[0012] A sixth aspect of the present invention is that, in the multilayer substrate of the fourth or fifth aspect, the thickness of the dielectric layer between the conductor layer closest to the mounting surface and the mounting surface pad layer may be less than one-third of the second pitch.

[0013] A seventh aspect of the present invention is a multilayer substrate according to any one of the first to sixth aspects, wherein the high-frequency layer may be electrically connected to the high-frequency bump through a plurality of stack vias that penetrate the dielectric layer.

[0014] An eighth aspect of the present invention is a multilayer board according to any one of the first to seventh aspects, wherein the board body comprises a core layer, a first buildup layer laminated on a first surface of the core layer, and a second buildup layer laminated on a second surface of the core layer opposite the first surface, the mounting surface being the outer surface of the second buildup layer, the second ground layer being formed on the second surface of the core layer, an antenna being formed on the first buildup layer side of the second ground layer, and the antenna being connected at least electrically and electromagnetically to the high-frequency IC via the high-frequency layer.

[0015] A ninth aspect of the present invention is the multilayer substrate of the eighth aspect, wherein the high frequency IC is capable of controlling the phase and intensity of a high frequency signal, has a plurality of input / output terminals for the high frequency signal, and has a plurality of antennas, each of which is connected to the plurality of input / output terminals and functions as a phased array antenna.

[0016] A tenth aspect of the present invention is the multilayer substrate according to the eighth or ninth aspect, wherein the antenna may be capable of transmitting and receiving a plurality of different polarized waves.

[0017] According to one aspect of the present invention, a multilayer substrate is provided that ensures impedance matching and allows for a narrow bump pitch.

[0018] 1A and 1B are cross-sectional views of a multilayer substrate according to a first embodiment and a multilayer substrate according to a second embodiment.

[0019] The multilayer substrate according to the first embodiment will be described in detail with reference to the drawings.

[0020] [Multilayer Substrate] (First Embodiment) Fig. 1 is a cross-sectional view of a multilayer substrate 100 according to a first embodiment. As shown in Fig. 1, the multilayer substrate 100 includes a substrate body 1 and a high-frequency IC 50.

[0021] Below, the vertical positional relationship of the multilayer substrate 100 will be provisionally defined in accordance with Figure 1. The side of the first buildup layer 20 relative to the core layer 10 is defined as the upper side. The side of the second buildup layer 30 relative to the core layer 10 is defined as the lower side. The positional relationship defined here does not limit the orientation of the multilayer substrate 100 during use. The vertical direction is the thickness direction of the layers that make up the substrate body 1. The vertical direction is the direction perpendicular to the mounting surface. Viewing from the vertical direction is called a planar view.

[0022] The substrate body 1 includes a core layer 10, a first buildup layer 20, and a second buildup layer 30. The core layer 10 is provided with a plurality of conductive layers 11. A dielectric layer 12 (insulating layer) is provided between the plurality of conductive layers 11. The core layer 10 is provided with two conductive layers 11a and 11b as the conductive layers 11. The number of conductive layers 11 is not particularly limited.

[0023] The conductive layer 11a is formed on the upper surface 10a (one surface) of the core layer 10. The conductive layer 11b is formed on the lower surface 10b (the other surface) of the core layer 10. The upper surface 10a is an example of a "first surface." The lower surface 10b is an example of a "second surface." The lower surface 10b is the surface opposite to the upper surface 10a. An electrically grounded second ground layer 11B is formed on the conductive layer 11b.

[0024] The first buildup layer 20 is provided on the upper surface 10a of the core layer 10. The first buildup layer 20 has a plurality of conductive layers 21. Dielectric layers 22 (insulating layers) are provided between the plurality of conductive layers 21. The first buildup layer 20 is formed by alternately stacking the conductive layers 21 and the dielectric layers 22.

[0025] The first buildup layer 20 has six conductive layers 21a to 21f arranged in order from the top surface 20a (one surface) to the bottom surface 20b (the other surface) of the first buildup layer 20 as the conductive layer 21. The number of conductive layers 21 is not particularly limited. The conductive layer 21a is formed on the top surface 20a of the first buildup layer 20. The dielectric layer 22 is also provided between the conductive layer 21f and the conductive layer 11a of the core layer 10.

[0026] The antenna 2 is formed above the second ground layer 11B (conductive layer 11b) (on the first buildup layer 20 side, (first buildup layer side)). The antenna 2 is located, for example, below the conductive layer 21b. The antenna 2 is electrically or electromagnetically connected to the high-frequency layer 31A (described later). The antenna 2 is connected at least electrically and / or electromagnetically to the high-frequency IC 50 via the high-frequency layer 31A. The antenna 2 transmits and receives high-frequency wireless signals, for example. The antenna 2 may be configured to only transmit or only receive high-frequency wireless signals.

[0027] There may be multiple antennas. The multiple antennas may be connected to multiple input / output terminals of the high frequency IC 50, respectively. A multilayer substrate equipped with multiple antennas can function as a phased array antenna. The use of a phased array antenna enables beamforming. The antenna may be capable of transmitting and receiving multiple different polarized waves. The antenna may be, for example, a dual-polarized antenna capable of transmitting and receiving two polarized waves (vertically polarized wave and horizontally polarized wave).

[0028] The second buildup layer 30 is provided on the lower surface 10b of the core layer 10. The second buildup layer 30 has a plurality of conductive layers 31. Dielectric layers 32 (insulating layers) are provided between the plurality of conductive layers 31. The second buildup layer 30 is formed by alternately stacking the conductive layers 31 and the dielectric layers 32. The lower surface 30b of the second buildup layer 30 (one surface of the substrate body 1) is the outer surface of the second buildup layer 30. The lower surface 30b is an example of a mounting surface.

[0029] The second buildup layer 30 has six conductive layers 31a to 31f provided in order from the top surface 30a (one surface) to the bottom surface 30b (the other surface) of the second buildup layer 30 as the conductive layer 31. The number of conductive layers 31 is not particularly limited. A dielectric layer 32 is also provided between the conductive layer 31a and the conductive layer 11b of the core layer 10.

[0030] The conductive layer 31a is provided with a high-frequency layer 31A through which high-frequency signals pass. The conductive layer 31b is provided with a first ground layer 31B that is electrically grounded. The conductive layer 31c is provided with a digital wiring layer 31C through which digital signals that control the operation of the high-frequency IC 50 pass. The conductive layer 31d is provided with a third ground layer 31D that is electrically grounded. The conductive layer 31e is provided with a power supply layer 31E that supplies power to the high-frequency IC 50. The conductive layer 31f is provided on the lower surface 30b (mounting surface) of the second buildup layer 30. The conductive layer 31f is provided with a plurality of mounting surface pad layers 31F.

[0031] As described above, the board body 1 includes, in this order from the mounting surface side, the mounting surface pad layer 31F, the power supply layer 31E (conductor layer), the third ground layer 31D (conductor layer), the digital wiring layer 31C (conductor layer), the first ground layer 31B, the high-frequency layer 31A, and the second ground layer 11B. The mounting surface pad layer 31F, the power supply layer 31E, the third ground layer 31D, the digital wiring layer 31C, the first ground layer 31B, the high-frequency layer 31A, and the second ground layer 11B are each stacked with a dielectric layer 32 interposed therebetween. The conductor layers include, in this order from the mounting surface side, the power supply layer 31E, the third ground layer 31D, and the digital wiring layer 31C.

[0032] In this embodiment, the power supply layer 31E, the third ground layer 31D, and the digital wiring layer 31C are all conductor layers. The multilayer substrate includes at least one of a power supply layer and a digital wiring layer as a conductor layer. The multilayer substrate may include only a power supply layer as a conductor layer, or may include only a digital wiring layer as a conductor layer. The multilayer substrate may include both a power supply layer and a digital wiring layer as conductor layers.

[0033] The multiple mounting surface pad layers 31F include a first mounting surface pad layer 31F1, a second mounting surface pad layer 31F2, a third mounting surface pad layer 31F3, a fourth mounting surface pad layer 31F4, a fifth mounting surface pad layer 31F5, a sixth mounting surface pad layer 31F6, and a seventh mounting surface pad layer 31F7.

[0034] The substrate body 1 is provided with a first via 13A, a second via 13B, a third via 13C, a fourth via 13D, a fifth via 13E, a sixth via 13F, a seventh via 13G, and an eighth via 13H.

[0035] The first via 13A penetrates the dielectric layer 32 between the power supply layer 31E and the second mounting surface pad layer 31F2 in the thickness direction. The first via 13A electrically connects the power supply layer 31E and the second mounting surface pad layer 31F2. The second via 13B penetrates the dielectric layer 32 between the third ground layer 31D and the third mounting surface pad layer 31F3 in the thickness direction. The second via 13B electrically connects the third ground layer 31D and the third mounting surface pad layer 31F3.

[0036] The third via 13C penetrates the dielectric layer 32 between the digital wiring layer 31C and the fourth mounting surface pad layer 31F4 in the thickness direction. The third via 13C electrically connects the digital wiring layer 31C and the fourth mounting surface pad layer 31F4. The fourth via 13D penetrates the dielectric layer 32 between the first ground layer 31B and the fifth mounting surface pad layer 31F5 in the thickness direction. The fourth via 13D electrically connects the first ground layer 31B and the fifth mounting surface pad layer 31F5.

[0037] The fifth via 13E penetrates the dielectric layer 32 between the high-frequency layer 31A and the sixth mounting surface pad layer 31F6 in the thickness direction. The fifth via 13E electrically connects the high-frequency layer 31A and the sixth mounting surface pad layer 31F6. At least a portion of the fifth via 13E is composed of a plurality of stacked vias 33 formed in each of the plurality of dielectric layers 32. The stacked vias 33 penetrate the dielectric layer 32 from one surface to the other. The plurality of stacked vias 33 at least partially overlap each other in a plan view. The stacked vias 33 are arranged coaxially in the stacking direction.

[0038] The sixth via 13F penetrates the first buildup layer 20, the core layer 10, and the second buildup layer 30 in the thickness direction. The sixth via 13F is formed from the conductive layer 21a to the seventh mounting surface pad layer 31F7, penetrating the dielectric layer in the thickness direction. The seventh via 13G is formed from the conductive layer 21a to the first ground layer 31B, penetrating the dielectric layer in the thickness direction. The eighth via 13H is formed from the conductive layer 21b to the high-frequency layer 31A, penetrating the dielectric layer in the thickness direction.

[0039] A high-frequency IC 50 is mounted on the lower surface 30b (mounting surface) of the second buildup layer 30 via a plurality of mounting surface pad layers 31F and a plurality of bumps 40. The high-frequency IC 50 is mounted via the bumps 40 on each of the plurality of mounting surface pad layers 31F formed on the lower surface 30b.

[0040] The plurality of bumps 40 include mounting surface bumps 41, power bumps 42, third ground bumps 43, digital bumps 44, first ground bumps 45, high-frequency bumps 46, and second ground bumps 47. The power bumps 42, the third ground bumps 43, and the digital bumps 44 are examples of "conductor bumps."

[0041] The first mounting surface pad layer 31F1 is electrically connected to the high frequency IC 50 via mounting surface bumps 41. The second mounting surface pad layer 31F2 is electrically connected to the high frequency IC 50 via power supply bumps 42. The third mounting surface pad layer 31F3 is electrically connected to the high frequency IC 50 via third ground bumps 43. The fourth mounting surface pad layer 31F4 is electrically connected to the high frequency IC 50 via digital bumps 44. The fifth mounting surface pad layer 31F5 is electrically connected to the high frequency IC 50 via first ground bumps 45. The sixth mounting surface pad layer 31F6 is electrically connected to the high frequency IC 50 via high frequency bumps 46. The seventh mounting surface pad layer 31F7 is electrically connected to the high frequency IC 50 via second ground bumps 47.

[0042] Of the dielectric layer 32 (32A) adjacent to the lower side (first ground layer 31B side, (first ground layer side)) of the high-frequency layer 31A and the dielectric layer 32 (32B) adjacent to the upper side (second ground layer 11B side) of the high-frequency layer 31A, the thickness of the thinner dielectric layer 32 is defined as "T1". In this embodiment, the dielectric layer 32 (32A) below the high-frequency layer 31A is thinner than the dielectric layer 32 (32B) above the high-frequency layer 31A, and therefore the thickness of the dielectric layer 32 (32A) below the high-frequency layer 31A is defined as T1.

[0043] The thickness of the dielectric layer 32 below the high-frequency layer 31A is equal to the distance between the high-frequency layer 31A and the first ground layer 31B. The thickness of the dielectric layer 32 above the high-frequency layer 31A is equal to the distance between the high-frequency layer 31A and the second ground layer 31B. The thickness of the dielectric layer 32 below the high-frequency layer 31A and the thickness of the dielectric layer 32 above the high-frequency layer 31A may be the same. In this case, both the upper and lower dielectric layers 32 of the high-frequency layer 31A correspond to the "thinner dielectric layer 32."

[0044] In this embodiment, the power supply layer 31E, the third ground layer 31D, and the digital wiring layer 31C are all conductor layers. Of these, the conductor layer closest to the bottom surface 30b (mounting surface) is the power supply layer 31E. The thickness of the dielectric layer 32 (32C) between the power supply layer 31E and the mounting surface pad layer 31F is defined as "T2." The dielectric layer 32 (32C) between the power supply layer 31E and the mounting surface pad layer 31F is the "dielectric layer between the conductor layer closest to the mounting surface and the mounting surface pad layer."

[0045] The thickness of the dielectric layer 32 (32C) between the power supply layer 31E and the mounting surface pad layer 31F is equal to the distance between the power supply layer 31E and the mounting surface pad layer 31F.

[0046] The thickness of the dielectric layer 32 (32A) below the high-frequency layer 31A is greater than the thickness of the dielectric layer 32 (32C) between the power supply layer 31E and the mounting surface pad layer 31F. That is, the thickness T1 of the dielectric layer 32 (32A) is greater than the thickness T2 of the dielectric layer 32 (32C).

[0047] When the thickness T1 is greater than the thickness T2, the dielectric layer 32 (32C) closest to the mounting surface is relatively thin, allowing the diameter of the vias (e.g., the first vias 13A) to be smaller. This allows the pitch of the multiple bumps 40 to be narrower. Furthermore, the dielectric layer 32 (32A) in contact with the high-frequency layer 31A is relatively thick, resulting in a good characteristic impedance in the high-frequency layer 31A. This ensures impedance matching with the high-frequency IC 50. This makes it possible to suppress output reduction, signal quality degradation, and the like.

[0048] The thickness T1 of the dielectric layer 32 (32A) below the high-frequency layer 31A may be 0.09 mm or more. When the thickness T1 is in this range, the characteristic impedance of the high-frequency layer 31A is good. The thickness T1 can be, for example, 0.5 mm or less.

[0049] The thickness T2 of the dielectric layer 32 (32C) between the power supply layer 31E and the mounting surface pad layer 31F may be 0.07 mm or less. When the thickness T2 is in this range, the diameter of the via (e.g., the first via 13A) can be reduced, thereby narrowing the pitch of the bumps 40. The thickness T2 can be, for example, 0.01 mm or more.

[0050] The pitch (first pitch) between the high-frequency bump 46 and the first ground bump 45 (the bump 40 adjacent to the high-frequency bump 46) is defined as P1. The first pitch P1 is preferably 0.45 mm or more and 0.55 mm or less. When the first pitch P1 is in this range, the diameter of the via (e.g., the fifth via 13E) can be increased, making it easier to ensure electrical connection from the high-frequency layer 31A to the mounting surface pad layer 31F. The first pitch P1 may also be the pitch between the high-frequency bump 46 and the second ground bump 47 (the bump 40 adjacent to the high-frequency bump 46). This first pitch P1 is also preferably 0.45 mm or more and 0.55 mm or less.

[0051] The pitch (second pitch) between the power bump 42 (conductor bump) and the mounting surface bump 41 (bump 40 adjacent to the power bump 42) is defined as P2. Comparing the first pitch P1 and the second pitch P2, it is desirable that the second pitch P2 be smaller than the first pitch P1. By reducing the second pitch P2, it becomes easier to miniaturize the high-frequency IC 50. When there are multiple power bumps 42, it is desirable that the pitch between the power bumps 42 be smaller than the first pitch P1. It is desirable that the pitch between the power bumps 42 and the third ground bump 43 be smaller than the first pitch P1.

[0052] The thickness T2 of the dielectric layer 32 (32C) between the power supply layer 31E and the mounting surface pad layer 31F is preferably less than one-third of the second pitch P2. When the thickness T2 is in this range, the diameter of the vias (e.g., the first vias 13A) can be made smaller, and therefore the pitch between the multiple bumps 40 can be narrowed.

[0053] In the multilayer substrate 100, it is preferable that not only the dielectric layer 32 (32C) but all the dielectric layers 32 from the mounting surface to the digital wiring layer 31C are thinner than the dielectric layer 32 (32A). This allows the pitch of the plurality of bumps 40 to be narrower.

[0054] The thickness of the thinner of the dielectric layer 32 adjacent to the upper side of the digital wiring layer 31C and the dielectric layer 32 adjacent to the lower side of the digital wiring layer 31C may be greater than the thickness of the dielectric layer 32 (32C) between the power supply layer 31E and the mounting surface pad layer 31F. This improves the characteristic impedance of the digital wiring layer 31C, thereby ensuring impedance matching with the high-frequency IC 50.

[0055] The bumps 40 may include a plurality of high-frequency bumps and a plurality of ground bumps. By arranging the high-frequency bumps and the ground bumps alternately at equal intervals, crosstalk can be suppressed. Therefore, the high-frequency bumps can be arranged at a high density.

[0056] The high-frequency bumps 46 may be disposed on the outside of the high-frequency IC 50 compared to the power supply bumps 42. This increases the redundancy of the bumps located on the inside of the high-frequency IC 50 in a planar view. The "outside of the high-frequency IC 50" refers to a direction away from the center of the high-frequency IC 50 in a planar view. The "inside of the high-frequency IC 50" refers to a direction toward the center of the high-frequency IC 50 in a planar view.

[0057] The high frequency IC 50 can control the phase and intensity of the high frequency signal. The high frequency IC 50 has, for example, a plurality of input / output terminals for the high frequency signal.

[0058] [Effects of the Multilayer Substrate of the First Embodiment] In the multilayer substrate 100 of this embodiment, the dielectric layer 32 (32A) below the high-frequency layer 31A is thicker than the dielectric layer 32 (32C) between the power supply layer 31E and the mounting surface pad layer 31F. Because the dielectric layer 32 (32C) closest to the mounting surface is relatively thin, the diameter of the via (e.g., the first via 13A) can be made smaller. This allows the pitch between the multiple bumps 40 to be narrower. This makes it easier to miniaturize the high-frequency IC 50.

[0059] In the multilayer substrate 100, the dielectric layer 32 (32A) in contact with the high-frequency layer 31A formed at a position away from the mounting surface is relatively thick, so that the characteristic impedance of the high-frequency layer 31A is good. This ensures impedance matching with the high-frequency IC 50. This makes it possible to suppress output reduction, signal quality degradation, and the like.

[0060] The multilayer substrate 100 includes a digital wiring layer 31C, a third ground layer 31D, and a power supply layer 31E. The multilayer substrate 100 includes the digital wiring layer 31C through which digital signals that control the operation of the high frequency IC 50 pass, and therefore the performance of the high frequency IC 50 can be improved.

[0061] The multilayer substrate 100 includes a core layer 10, a first buildup layer 20, and a second buildup layer 30. The first buildup layer 20 is provided on the upper surface 10a of the core layer 10. The second buildup layer 30 is provided on the lower surface 10b of the core layer 10. Because a buildup layer is provided on each side of the core layer 10, warping of the multilayer substrate 100 can be suppressed.

[0062] The second ground layer 11B is formed on the lower surface 10b of the core layer 10. The antenna 2 is formed closer to the first buildup layer 20 than the second ground layer 11B. Since the second ground layer 11B has a sufficient thickness on the first buildup layer 20 side, the operating frequency band of the antenna 2 can be widened.

[0063] [Multilayer Substrate] (Second Embodiment) Fig. 2 is a cross-sectional view of a multilayer substrate 200 according to a second embodiment. As shown in Fig. 2, the multilayer substrate 200 includes a substrate body 201 and a high-frequency IC 50. Components common to the multilayer substrate 100 of the first embodiment (see Fig. 1) are designated by the same reference numerals and will not be described again.

[0064] The substrate body 201 includes a core layer 210, a first buildup layer 220, and a second buildup layer 230. The core layer 210 is provided with a plurality of conductive layers 111. A dielectric layer 12 is provided between the plurality of conductive layers 111. The core layer 210 is provided with two conductive layers 111a and 111b as the conductive layers 111. The number of conductive layers 111 is not particularly limited.

[0065] The conductive layer 111a is formed on the upper surface 10a of the core layer 210. The conductive layer 111b is formed on the lower surface 10b of the core layer 210. An electrically grounded first ground layer 111A is formed on the conductive layer 111a. An electrically grounded fourth ground layer 111B is formed on the conductive layer 111b.

[0066] The first buildup layer 220 is provided on the upper surface 10a of the core layer 210. A plurality of conductive layers 121 are provided in the first buildup layer 220. A dielectric layer 22 is provided between the plurality of conductive layers 121. The first buildup layer 220 is formed by alternately stacking the conductive layers 121 and the dielectric layers 22.

[0067] The first buildup layer 220 has four conductive layers 121a to 121d provided in this order as the conductive layer 121 from the top surface 20a to the bottom surface 20b of the first buildup layer 220. The number of conductive layers 121 is not particularly limited. The conductive layer 121a is formed on the top surface 20a of the first buildup layer 220. The dielectric layer 22 is also provided between the conductive layer 121d and the conductive layer 111a of the core layer 210.

[0068] An electrically grounded second ground layer 121C is formed on the conductive layer 121c, and a high frequency layer 121D is formed on the conductive layer 121d.

[0069] An antenna 202 is formed above the second ground layer 121C (conductive layer 121c) and is electrically or electromagnetically connected to the high frequency layer 121D.

[0070] The second buildup layer 230 is provided on the lower surface 10b of the core layer 210. The second buildup layer 230 has a plurality of conductive layers 131 provided therein. A dielectric layer 32 is provided between the plurality of conductive layers 131. The second buildup layer 230 is formed by alternately stacking the conductive layers 131 and the dielectric layers 32. The lower surface 30b of the second buildup layer 230 is the outer surface of the second buildup layer 230. The lower surface 30b is an example of a mounting surface.

[0071] The second buildup layer 230 has four conductive layers 131a to 131d provided as the conductive layer 131 in this order from the upper surface 30a to the lower surface 30b of the second buildup layer 230. The number of conductive layers 131 is not particularly limited. A dielectric layer 32 is also provided between the conductive layer 131a and the conductive layer 111b of the core layer 210.

[0072] The conductive layer 131a is formed with a digital wiring layer 131A through which digital signals that control the operation of the high frequency IC 50 pass. The conductive layer 131b is formed with a third ground layer 131B that is electrically grounded. The conductive layer 131c is formed with a power supply layer 131C that supplies power to the high frequency IC 50. The conductive layer 131d is provided on the lower surface 30b (mounting surface) of the second buildup layer 230. The conductive layer 131d is formed with a plurality of mounting surface pad layers 131D.

[0073] As described above, the board body 201 includes, in this order from the mounting surface side, the mounting surface pad layer 131D, the power supply layer 131C (conductor layer), the third ground layer 131B (conductor layer), the digital wiring layer 131A (conductor layer), the fourth ground layer 111B, the first ground layer 111A, the high-frequency layer 121D, and the second ground layer 121C. The mounting surface pad layer 131D, the power supply layer 131C, the third ground layer 131B, the digital wiring layer 131A, the fourth ground layer 111B, the first ground layer 111A, the high-frequency layer 121D, and the second ground layer 121C are laminated with the dielectric layer 32 interposed therebetween.

[0074] The conductor layers 131A to 131C include, from the mounting surface side, a power supply layer 131C, a third ground layer 131B, and a digital wiring layer 131A in this order.

[0075] The multiple mounting surface pad layers 131D include a first mounting surface pad layer 131D1, a second mounting surface pad layer 131D2, a third mounting surface pad layer 131D3, a fourth mounting surface pad layer 131D4, a fifth mounting surface pad layer 131D5, a sixth mounting surface pad layer 131D6, and a seventh mounting surface pad layer 131D7.

[0076] The substrate body 201 is provided with a first via 113A, a second via 113B, a third via 113C, a fourth via 113D, a fifth via 113E, a sixth via 113F, a seventh via 113G, and an eighth via 113H.

[0077] The first via 113A penetrates the dielectric layer 32 between the power supply layer 131C and the second mounting surface pad layer 131D2 in the thickness direction. The first via 113A electrically connects the power supply layer 131C and the second mounting surface pad layer 131D2. The second via 113B penetrates the dielectric layer 32 between the third ground layer 131B and the third mounting surface pad layer 131D3 in the thickness direction. The second via 113B electrically connects the third ground layer 131B and the third mounting surface pad layer 131D3.

[0078] The third via 113C penetrates the dielectric layer 32 between the digital wiring layer 131A and the fourth mounting surface pad layer 131D4 in the thickness direction. The third via 113C electrically connects the digital wiring layer 131A and the fourth mounting surface pad layer 131D4. The fourth via 113D penetrates the dielectric layer between the first ground layer 111A and the fifth mounting surface pad layer 131D5 in the thickness direction. The fourth via 113D electrically connects the first ground layer 111A and the fourth ground layer 111B to the fifth mounting surface pad layer 131D5.

[0079] The fifth via 113E penetrates the dielectric layer between the high-frequency layer 121D and the sixth mounting surface pad layer 131D6 in the thickness direction. The fifth via 113E electrically connects the high-frequency layer 121D and the sixth mounting surface pad layer 131D6. The fifth via 113E is composed of a plurality of stacked vias 33 formed in each of the plurality of dielectric layers. The stacked vias 33 penetrate the dielectric layer from one surface to the other. The plurality of stacked vias 33 at least partially overlap each other in a plan view.

[0080] The sixth via 113F penetrates the second buildup layer 230, the core layer 210, and the first buildup layer 220 in the thickness direction. The sixth via 113F is formed from the conductive layer 121a to the seventh mounting surface pad layer 131D7, penetrating the dielectric layer in the thickness direction. The seventh via 113G is formed from the conductive layer 121a to the fourth ground layer 111B, penetrating the dielectric layer in the thickness direction. The eighth via 113H is formed from the conductive layer 121a to the high-frequency layer 121D, penetrating the dielectric layer in the thickness direction.

[0081] A high frequency IC 50 is mounted via a plurality of mounting surface pad layers 131D and a plurality of bumps 40 (41 to 47) on the lower surface 30b (mounting surface) of the second buildup layer 230. The high frequency IC 50 is mounted via the bumps 40 on each of the plurality of mounting surface pad layers 131D formed on the lower surface 30b.

[0082] The first mounting surface pad layer 131D1 is electrically connected to the high frequency IC 50 via the mounting surface bumps 41. The second mounting surface pad layer 131D2 is electrically connected to the high frequency IC 50 via the power supply bumps 42. The third mounting surface pad layer 131D3 is electrically connected to the high frequency IC 50 via the third ground bumps 43. The fourth mounting surface pad layer 131D4 is electrically connected to the high frequency IC 50 via the digital bumps 44. The fifth mounting surface pad layer 131D5 is electrically connected to the high frequency IC 50 via the first ground bumps 45. The sixth mounting surface pad layer 131D6 is electrically connected to the high frequency IC 50 via the high frequency bumps 46. The seventh mounting surface pad layer 131D7 is electrically connected to the high frequency IC 50 via the second ground bumps 47.

[0083] Of the dielectric layer 22 (22A) on the lower side (the first ground layer 111A side) of the high-frequency layer 121D and the dielectric layer 22 (22B) on the upper side (the second ground layer 121C side) of the high-frequency layer 121D, the thinner dielectric layer 22 has a thickness T3. In this embodiment, the thickness of the dielectric layer 22 (22A) on the lower side of the high-frequency layer 121D is T3.

[0084] The thickness of the dielectric layer 22 below the high-frequency layer 121D is equal to the distance between the high-frequency layer 121D and the first ground layer 111A. The thickness of the dielectric layer 22 above the high-frequency layer 121D is equal to the distance between the high-frequency layer 121D and the second ground layer 121C. The thickness of the dielectric layer 22 below the high-frequency layer 121D may be the same as the thickness of the dielectric layer 22 above the high-frequency layer 121D. In this case, the dielectric layer 22 in contact with the high-frequency layer 121D on the upper side and the dielectric layer 22 in contact with the high-frequency layer 121D on the lower side both correspond to the "thinner dielectric layer 22."

[0085] In this embodiment, the power supply layer 131C, the third ground layer 131B, and the digital wiring layer 131A are all conductor layers. Of these, the conductor layer closest to the bottom surface 30b (mounting surface) is the power supply layer 131C. The thickness of the dielectric layer 32 (32C) between the power supply layer 131C and the mounting surface pad layer 131D is "T4." The dielectric layer 32 (32C) between the power supply layer 131C and the mounting surface pad layer 131D is the "dielectric layer between the conductor layer closest to the mounting surface and the mounting surface pad layer."

[0086] The thickness of the dielectric layer 32 (32C) between the power supply layer 131C and the mounting surface pad layer 131D is equal to the distance between the power supply layer 131C and the mounting surface pad layer 131D.

[0087] The thickness of the dielectric layer 22 (22A) below the high-frequency layer 121D is greater than the thickness of the dielectric layer 32 (32C) between the power supply layer 131C and the mounting surface pad layer 131D. That is, the thickness T3 of the dielectric layer 22 (22A) is greater than the thickness T4 of the dielectric layer 32 (32C).

[0088] When the thickness T3 is greater than the thickness T4, the dielectric layer 32 (32C) closest to the mounting surface is relatively thin, allowing the diameter of the via (e.g., the first via 113A) to be small. This allows the pitch of the bumps 40 to be narrowed. Furthermore, the dielectric layer 22 (22A) in contact with the high-frequency layer 121D formed away from the mounting surface is relatively thick, improving the characteristic impedance of the high-frequency layer 121D. This ensures impedance matching with the high-frequency IC 50, suppressing output degradation and signal quality degradation.

[0089] The thickness of the thinner of the dielectric layer 32 adjacent to the upper side of the digital wiring layer 131A and the dielectric layer 32 adjacent to the lower side of the digital wiring layer 131A may be greater than the thickness of the dielectric layer 32 (32C) between the power supply layer 131C and the mounting surface pad layer 131D. This improves the characteristic impedance of the digital wiring layer 131A, thereby ensuring impedance matching with the high-frequency IC 50.

[0090] [Effects of the Multilayer Substrate of the Second Embodiment] In the multilayer substrate 200 of this embodiment, the thickness of the dielectric layer 22 (22A) below the high-frequency layer 121D is greater than the thickness of the dielectric layer 32 (32C) between the power supply layer 131C and the mounting surface pad layer 131D. Because the dielectric layer 32 (32C) closest to the mounting surface is relatively thin, the diameter of the via (e.g., the first via 113A) can be made smaller. This allows the pitch between the multiple bumps 40 to be narrower. This makes it easier to miniaturize the high-frequency IC 50.

[0091] In the multilayer substrate 200, the dielectric layer 22 (22A) in contact with the high-frequency layer 121D formed at a position away from the mounting surface is relatively thick, so that the characteristic impedance of the high-frequency layer 121D is favorable, thereby ensuring impedance matching with the high-frequency IC 50 and suppressing output reduction, degradation of signal quality, and the like.

[0092] While preferred embodiments of the present invention have been described and illustrated above, it should be understood that these are illustrative of the present invention and should not be considered limiting. Additions, omissions, substitutions, and other modifications may be made without departing from the scope of the present invention. While the multilayer substrate shown in FIG. 1 includes one high-frequency IC, the multilayer substrate may include multiple high-frequency ICs. A multilayer substrate including multiple high-frequency ICs may form, for example, a phased array antenna. This allows for a large number of antennas and high gain while reducing the wiring density on the substrate body. Furthermore, the components in the above-described embodiments may be replaced with known components as appropriate, and the above-described embodiments and variations may be combined as appropriate, without departing from the spirit of the present invention.

[0093] According to one aspect of the present invention, a multilayer substrate is provided that ensures impedance matching and allows for a narrow bump pitch.

[0094] 1,201...board body, 2,202...antenna, 10,210...core layer, 10a...upper surface (first surface), 10b...lower surface (second surface), 11B, 121C...second ground layer, 12, 22, 32...dielectric layer, 20, 220...first buildup layer, 30, 230...second buildup layer, 31A, 121D...high frequency layer, 31B, 111A...first ground layer, 31C, 131A...digital wiring layer (conductor layer), 31D, 131B...third ground layer (conductor layer), 31E, 131C...power supply layer (conductor layer), 31F, 131D...mounting surface pad layer, 22A, 32A... Dielectric layer (thinner of the dielectric layers on the first ground layer side and second ground layer side of the high-frequency layer), 32C...dielectric layer (dielectric layer between the conductor layer closest to the mounting surface and the mounting surface pad layer), 33...stacked via, 40...bump, 41...mounting surface bump, 42...power supply bump (conductor bump), 43...third ground bump (conductor bump), 44...digital bump (conductor bump), 45...first ground bump, 46...high-frequency bump, 47...second ground bump, 50...high-frequency IC, 100, 200...multilayer substrate, P1...first pitch, P2...second pitch

Claims

1. A circuit board body with one side designated as the mounting surface, The system comprises a high-frequency IC mounted on each of a plurality of mounting surface pad layers formed on the aforementioned mounting surface via bumps, The substrate body comprises, from the mounting surface side, the mounting surface pad layer, a conductor layer including at least one of a power supply layer and a digital wiring layer, a first ground layer, a high-frequency layer, and a second ground layer, in this order. The mounting surface pad layer, the conductor layer, the first ground layer, the high-frequency layer, and the second ground layer are each laminated with a dielectric layer in between. The bump includes a mounting surface bump electrically connected to the mounting surface pad layer, a conductor bump electrically connected to the conductor layer, a first ground bump electrically connected to the first ground layer, a high-frequency bump electrically connected to the high-frequency layer, and a second ground bump electrically connected to the second ground layer. The thickness of the thinner dielectric layer of the first ground layer side and the second ground layer side of the high-frequency layer is greater than the thickness of the dielectric layer between the conductor layer closest to the mounting surface and the mounting surface pad layer. Multilayer board.

2. The conductor layer comprises, from the mounting surface side, the power supply layer, the third ground layer, and the digital wiring layer in this order. The power supply layer, the third ground layer, and the digital wiring layer are each stacked with the dielectric layer in between. The multilayer substrate according to claim 1.

3. The thickness of the thinner dielectric layer of the high-frequency layer, between the dielectric layer on the first ground layer side and the dielectric layer on the second ground layer side, is 0.09 mm or more. The thickness of the dielectric layer between the conductor layer closest to the mounting surface and the mounting surface pad layer is 0.07 mm or less. A multilayer substrate according to claim 1 or claim 2.

4. The high-frequency bump and the first pitch which is the pitch between the high-frequency bump and the bump adjacent to the high-frequency bump, Comparing the aforementioned conductor bump with the second pitch, which is the pitch between the conductor bump and the adjacent bump, The second pitch is smaller than the first pitch. A multilayer substrate according to claim 1 or claim 2.

5. The first pitch is 0.45 mm or more and 0.55 mm or less. The multilayer substrate according to claim 4.

6. The thickness of the dielectric layer between the conductor layer closest to the mounting surface and the mounting surface pad layer is less than one-third of the second pitch. The multilayer substrate according to claim 4.

7. The high-frequency layer is electrically connected to the high-frequency bump via a plurality of stacked vias that penetrate the dielectric layer. A multilayer substrate according to claim 1 or claim 2.

8. The substrate body comprises a core layer, a first build-up layer laminated on the first surface of the core layer, and a second build-up layer laminated on the second surface of the core layer opposite to the first surface. The aforementioned mounting surface is the outer surface of the second build-up layer, The second ground layer is formed on the second surface of the core layer, An antenna is formed on the side of the first build-up layer from the second ground layer. The antenna is connected to the high-frequency IC via the high-frequency layer, at least electrically and electromagnetically. A multilayer substrate according to claim 1 or claim 2.

9. The aforementioned high-frequency IC is capable of controlling the phase and intensity of the high-frequency signal and has a plurality of input and output terminals for the high-frequency signal. There are multiple antennas, Multiple antennas are connected to the multiple input / output terminals, respectively, and function as a phased array antenna. The multilayer substrate according to claim 8.

10. The aforementioned antenna is capable of transmitting and receiving multiple different polarizations. The multilayer substrate according to claim 8.