Transmission line structure

Abstract

This transmission line structure includes a first ground plane 108a, a second ground plane (108b), and a third ground plane (108c) which are embedded in a dielectric layer (103) between a substrate (101) and a first strip line (106) and a second strip line (107). A thickness-direction interval h1 between a first section (106a) and the first ground plane 108a is larger than a thickness-direction interval h3 between a third section (106c) and the third ground plane (108c). A thickness-direction interval h2 between a second section (106b) and the second ground plane (108b) becomes gradually smaller from a first region (121) to a third region (123).

Description

Transmission Line Structure

[0001] The present invention relates to transmission line structures.

[0002] As modules have become increasingly high-frequency in recent years, the configuration of the transmission lines on high-frequency transmission line boards has become extremely important in order to transmit signals at high speeds without causing operational errors. For example, when multiple ICs are integrated on a transmission line board, it is sometimes desirable for all the wiring that transmits high-frequency signals to be connected by wiring with the same characteristic impedance.

[0003] Typical transmission line structures used to propagate high-speed signals on high-frequency transmission line substrates include microstrip lines, coplanar lines, and grounded coplanar lines. For example, a microstrip line is constructed with a ground plane of a planar conductive layer formed on one side of a dielectric substrate and a strip-shaped line formed on the other side. The characteristic impedance of these lines is determined by the width and thickness of the signal line, the dielectric constant and thickness of the dielectric substrate, and the geometric dimensions of the gap between the signal line and the ground pattern.

[0004] 2, a first stripline 206 and a second stripline 207 are used to connect an output signal of a first integrated circuit 204 arranged on a substrate 203 to an input signal of a second integrated circuit 205. The first stripline 206 is composed of an output line 206a connected to an output section 204a of the first integrated circuit 204, an input line 206c connected to an input section 205a of the second integrated circuit 205, and an intermediate line 206b connecting these. Similarly, the second stripline 207 is composed of an output line 207a connected to an output section 204b of the first integrated circuit 204, an input line 207c connected to an input section 205b of the second integrated circuit 205, and an intermediate line 207b connecting these.

[0005] Due to issues with the layout and PAD shape of the first integrated circuit 204 and the second integrated circuit 205, the spacing between the input lines 206c and 207c of the second integrated circuit 205 may be wider than the spacing between the output lines 206a and 207a of the first integrated circuit 204. In this case, the characteristic impedance of the strip line changes as the spacing between the lines changes, which causes a problem in that high-frequency signals cannot be transmitted efficiently.

[0006] P. Pramanick, et al., "Tapered Microstrip Transmission Lines" IEEE MTT-S Int. Microw. Symp. Dig., vol. 1983, pp. 242-244, 1983.

[0007] Various studies have been conducted to solve the problems caused by the transmission lines described above. For example, as shown in FIG. 3, a configuration using a first strip line 206' and a second strip line 207', each of which is made up of an input line 206c' and an input line 207c' with a line width wider than that of the output line 206a and the output line 207a, is shown (Non-Patent Document 1). In this case, intermediate lines 206b' and 207b' are used, which have a narrow line width on the input line side and gradually widen toward the output line side. The intermediate lines 206b' and 207b' also widen in line width as the line width widens from the input line side to the output line side. This adjusts the characteristic impedance by the line width so that it is equivalent to the increase or decrease in characteristic impedance due to the line spacing.

[0008] However, when adjusting the characteristic impedance by the line width, there are restrictions such as the allowable current amount of the transmission signal, and the range of adjustment is limited, making it impractical. Also, in a configuration with different line widths, there is a problem that the variation in characteristic impedance due to manufacturing errors becomes large in the parts with smaller line widths (large tolerance), making it difficult to improve the signal transmission characteristics between integrated circuits.

[0009] The present invention has been made to solve the above problems, and has as its object to improve the signal transmission characteristics between integrated circuits via transmission lines.

[0010] A transmission line structure according to the present invention comprises a first integrated circuit and a second integrated circuit arranged on a substrate made of a dielectric, a ground layer formed on the back surface of the substrate, a dielectric layer formed on the substrate between the first integrated circuit and the second integrated circuit, a first stripline arranged on the surface of the dielectric layer and connecting the first integrated circuit and the second integrated circuit, a second stripline arranged on the same plane as the first stripline on the surface of the dielectric layer and connecting the first integrated circuit and the second integrated circuit, and a first ground plane, a second ground plane and a third ground plane embedded in the dielectric layer between the substrate and the first and second striplines, and the first stripline has, from the first integrated circuit to the second integrated circuit, a first portion arranged in a first region, a second portion arranged in a second region and a third portion arranged in a third region, The line extends from the first integrated circuit to the second integrated circuit and includes a fourth portion arranged parallel to the first portion in a first region, a fifth portion arranged in the second region, and a sixth portion arranged parallel to the third portion in a third region, the first ground plane is arranged in the first region, the second ground plane is arranged in the second region, and the third ground plane is arranged in the third region, the distance between the third portion and the sixth portion is larger than the distance between the first portion and the fourth portion, the distance between the second portion and the fifth portion is gradually increased from the first region to the third region, the distance in the thickness direction between the first portion and the fourth portion and the first ground plane is larger than the distance in the thickness direction between the third portion and the sixth portion and the third ground plane, and the distance in the thickness direction between the second portion and the fifth portion and the second ground plane is gradually decreased from the first region to the third region.

[0011] As described above, according to the present invention, a ground plane is provided between a dielectric substrate and each strip line, and the distance in the thickness direction between the ground plane and each strip line is changed to match the distance between the first strip line and the second strip line, thereby improving the signal transmission characteristics between integrated circuits via transmission lines.

[0012] FIG. 1A is a plan view showing a configuration of a transmission line structure according to an embodiment of the present invention. FIG. 1B is a cross-sectional view showing a configuration of a transmission line structure according to an embodiment of the present invention. FIG. 1C is a cross-sectional view showing a partial configuration of a transmission line structure according to an embodiment of the present invention. FIG. 1D is a cross-sectional view showing a partial configuration of a transmission line structure according to an embodiment of the present invention. FIG. 1E is a cross-sectional view showing a partial configuration of a transmission line structure according to an embodiment of the present invention. FIG. 2 is a plan view showing a configuration of a conventional transmission line structure. FIG. 3 is a plan view showing a configuration of a conventional transmission line structure.

[0013] A transmission line structure according to an embodiment of the present invention will be described below with reference to Figures 1A, 1B, 1C, 1D, and 1E. Figure 1C shows a cross section taken along line aa' in Figure 1A. Figure 1D shows a cross section taken along line bb' in Figure 1A. Figure 1E shows a cross section taken along line cc' in Figure 1A.

[0014] This transmission line structure comprises a first integrated circuit 104 and a second integrated circuit 105 arranged on a substrate 101 made of a dielectric, a ground layer 102 formed on the back surface of the substrate 101, and a dielectric layer 103 formed on the substrate 101 between the first integrated circuit 104 and the second integrated circuit 105.

[0015] The substrate 101 can be made of, for example, an inorganic base material such as a compound semiconductor or ceramic, or a mixture of an inorganic base material and an organic base material such as glass epoxy. Although not shown, in addition to the first integrated circuit 104 and the second integrated circuit 105, circuit elements can also be mounted on the substrate 101 as appropriate.

[0016] For example, a dielectric layer 103 can be formed on the substrate 101 so as to bury the sides of the first integrated circuit 104 and the second integrated circuit 105. The dielectric layer 103 can be made of a dielectric insulating material with a low dielectric constant and low Tan δ, i.e., excellent high-frequency characteristics, and can be formed to a predetermined thickness. Specific examples of the dielectric layer 103 include resin materials such as benzocyclobutene (BCB), polyphenylene ether resin (PPE), bismaleimide triazine (BT-resin), polyimide resin, epoxy resin, cyanide resin, and phenolic resin.

[0017] This transmission line structure also includes a first stripline 106 disposed on the surface of the dielectric layer 103 and connecting the first integrated circuit 104 and the second integrated circuit 105, and a second stripline 107 disposed on the same plane as the first stripline 106 on the surface of the dielectric layer 103 and connecting the first integrated circuit 104 and the second integrated circuit 105. The first stripline 106 and the second stripline 107 can have the same line width throughout.

[0018] This transmission line structure also includes a first ground plane 108a, a second ground plane 108b, and a third ground plane 108c embedded in the dielectric layer 103 between the substrate 101 and the first stripline 106 and the second stripline 107. The first ground plane 108a, the second ground plane 108b, and the third ground plane 108c are at the same potential. For example, the first ground plane 108a, the second ground plane 108b, and the third ground plane 108c are formed continuously.

[0019] Here, the first stripline 106 includes a first portion 106a arranged in a first region 121, a second portion 106b arranged in a second region 122, and a third portion 106c arranged in a third region 123, extending from the first integrated circuit 104 to the second integrated circuit 105. The first portion 106a is an output line connected to the first output section 104a of the first integrated circuit 104, and the third portion 106c is an input line connected to the first input section 105a of the second integrated circuit 105. The first portion 106a, the second portion 106b, and the third portion 106c are formed continuously.

[0020] On the other hand, the second stripline 107 includes a fourth portion 107a arranged in a first region 121 from the first integrated circuit 104 to the second integrated circuit 105, a fifth portion 107b arranged in a second region 122, and a sixth portion 107c arranged in a third region 123. The fourth portion 107a and the first portion 106a are parallel to each other. The sixth portion 107c and the third portion 106c are parallel to each other. The fourth portion 107a is an output line connected to the second output portion 104b of the first integrated circuit 104, and the sixth portion 107c is an input line connected to the second input portion 105b of the second integrated circuit 105. The fourth portion 107a, the fifth portion 107b, and the sixth portion 107c are continuously formed.

[0021] The first ground plane 108 a is disposed in the first region 121 , the second ground plane 108 b is disposed in the second region 122 , and the third ground plane 108 c is disposed in the third region 123 .

[0022] The distance G3 between the third portion 106c and the sixth portion 107c is larger than the distance G1 between the first portion 106a and the fourth portion 107a. The distance G2 between the second portion 106b and the fifth portion 107b gradually increases from the first region 121 to the third region 123.

[0023] The distance h1 between the first portion 106a and the fourth portion 107a and the first ground plane 108a in the thickness direction (normal to the plane of the substrate 101) is larger than the distance h3 between the third portion 106c and the sixth portion 107c and the third ground plane 108c in the thickness direction. The distance h2 between the second portion 106b and the fifth portion 107b and the second ground plane 108b in the thickness direction (normal to the plane of the substrate 101) is gradually reduced from the first region 121 to the third region 123.

[0024] For example, the first ground plane 108a and the third ground plane 108c and the plane of the substrate 101 may be parallel to each other.

[0025] Each of the first portion 106a, the second portion 106b, the third portion 106c, the fourth portion 107a, the fifth portion 107b, and the sixth portion 107c may be formed, for example, in a linear shape, and each of the first ground plane 108a, the second ground plane 108b, and the third ground plane 108c may be formed, for example, in a flat plate shape.

[0026] The first ground plane 108a can be individually formed in a region corresponding to the region where the first portion 106a and the fourth portion 107a are formed in a plan view, the second ground plane 108b can be individually formed in a region corresponding to the region where the second portion 106b and the fifth portion 107b are formed in a plan view, and the third ground plane 108c can be individually formed in a region corresponding to the region where the third portion 106c and the sixth portion 107c are formed in a plan view.

[0027] As described above, the distance h2 in the thickness direction between the second portion 106b and the fifth portion 107b and the second ground plane 108b is gradually reduced from the first region 121 to the third region 123, thereby canceling out the effect of the characteristic impedance value of each strip line increasing as the distance (G1<G2<G3) between the first strip line 106 and the second strip line 107 increases. By adjusting the amount of change in the distance h2, the characteristic impedance value of each strip line can be made constant.

[0028] In the above description, the transmission line (strip line) between the first integrated circuit and the second integrated circuit is used as an example, and two strip lines and one dielectric layer are used as an example, but it goes without saying that the present invention is not limited to this.

[0029] As described above, according to the present invention, a ground plane is provided between a dielectric substrate and each strip line, and the distance in the thickness direction between the ground plane and each strip line is changed to match the distance between the first strip line and the second strip line, thereby improving the signal transmission characteristics between integrated circuits via transmission lines.

[0030] Some or all of the above-described embodiments may also be described as, but are not limited to, the following supplementary notes.

[0031] [Supplementary Note 1] A semiconductor device comprising: a first integrated circuit and a second integrated circuit disposed on a substrate made of a dielectric; a ground layer formed on the back surface of the substrate; a dielectric layer formed on the substrate between the first integrated circuit and the second integrated circuit; a first stripline disposed on a surface of the dielectric layer and connecting the first integrated circuit and the second integrated circuit; a second stripline disposed on the same plane as the first stripline on the surface of the dielectric layer and connecting the first integrated circuit and the second integrated circuit; and a first ground plane, a second ground plane, and a third ground plane embedded in the dielectric layer between the substrate and the first and second striplines, wherein the first stripline has, from the first integrated circuit to the second integrated circuit, a first portion disposed in a first region, a second portion disposed in a second region, and a third portion disposed in a third region. a fourth portion disposed in parallel to the first portion in the first region, a fifth portion disposed in the second region, and a sixth portion disposed in parallel to the third portion in the third region, the first ground plane being disposed in the first region, the second ground plane being disposed in the second region, and the third ground plane being disposed in the third region; a distance between the third portion and the sixth portion is larger than a distance between the first portion and the fourth portion, a distance between the second portion and the fifth portion is gradually increased from the first region to the third region, a distance between the first portion and the fourth portion and the first ground plane in a thickness direction is larger than a distance between the third portion and the sixth portion and the third ground plane, and a distance between the second portion and the fifth portion and the second ground plane in the thickness direction is gradually decreased from the first region to the third region.

[0032] [Supplementary Note 2] The transmission line structure according to Supplementary Note 1, wherein the first ground plane, the third ground plane, and the plane of the substrate are parallel to each other.

[0033] [Supplementary Note 3] In the transmission line structure according to Supplementary Note 1 or 2, each of the first portion, the second portion, the third portion, the fourth portion, the fifth portion, and the sixth portion is formed in a linear shape, and each of the first ground plane, the second ground plane, and the third ground plane is formed in a flat plate shape.

[0034] [Supplementary Note 4] In the transmission line structure described in any one of Supplementary Notes 1 to 3, the first ground plane is formed in a region that corresponds to a region where the first portion and the fourth portion are formed in a planar view, the second ground plane is formed in a region that corresponds to a region where the second portion and the fifth portion are formed in a planar view, and the third ground plane is formed in a region that corresponds to a region where the third portion and the sixth portion are formed in a planar view.

[0035] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0036] 101...substrate, 102...ground layer, 103...dielectric layer, 104...first integrated circuit, 104a...first output section, 104b...second output section, 105...second integrated circuit, 105a...first input section, 105b...second input section, 106...first strip line, 106a...first portion, 106b...second portion, 106c...third portion, 107...second strip line, 107a...fourth portion, 107b...fifth portion, 107c...sixth portion, 108a...first ground plane, 108b...second ground plane, 108c...third ground plane, 121...first region, 122...second region, 123...third region.

Claims

1. A first integrated circuit and a second integrated circuit disposed on a substrate made of a dielectric, a ground layer formed on the back surface of the substrate, a dielectric layer formed on the substrate between the first integrated circuit and the second integrated circuit, a first strip line disposed on the surface of the dielectric layer to connect the first integrated circuit and the second integrated circuit, a second strip line disposed on the same plane as the first strip line on the surface of the dielectric layer to connect the first integrated circuit and the second integrated circuit, and a first ground plane, a second ground plane, and a third ground plane embedded in the dielectric layer between the substrate and the first strip line and the second strip line. The first strip line includes a first portion disposed in a first region, a second portion disposed in a second region, and a third portion disposed in a third region from the first integrated circuit to the second integrated circuit. The second strip line includes a fourth portion disposed in the first region parallel to the first portion, a fifth portion disposed in the second region, and a sixth portion disposed in the third region parallel to the third portion from the first integrated circuit to the second integrated circuit. The first ground plane is disposed in the first region, the second ground plane is disposed in the second region, and the third ground plane is disposed in the third region. The distance between the third portion and the sixth portion is made larger than the distance between the first portion and the fourth portion. The distance between the second portion and the fifth portion is gradually increased from the first region to the third region. The distance in the thickness direction between the first portion and the fourth portion and the first ground plane is made larger than the distance in the thickness direction between the third portion and the sixth portion and the third ground plane. The distance in the thickness direction between the second portion and the fifth portion and the second ground plane is gradually decreased from the first region to the third region. A transmission line structure.

2. The transmission line structure according to claim 1, wherein the first ground plane and the third ground plane are parallel to the plane of the substrate.

3. In the transmission line structure according to claim 1, each of the first part, the second part, the third part, the fourth part, the fifth part, and the sixth part is formed in a straight line, and each of the first ground plane, the second ground plane, and the third ground plane is formed in a flat plate shape.

4. In the transmission line structure according to any one of claims 1 to 3, the first ground plane is formed in a region corresponding to the region where the first part and the fourth part are formed in a plan view, the second ground plane is formed in a region corresponding to the region where the second part and the fifth part are formed in a plan view, and the third ground plane is formed in a region corresponding to the region where the third part and the sixth part are formed in a plan view.