Semiconductor package

Abstract

A semiconductor package (10) comprising a passive component and an active component is provided with a first component layer having a first principal surface (10A) and a second principal surface (10B) on the opposite side from the first principal surface (10A). The semiconductor package (10) is provided with a first wiring layer adjacent to the first component layer in a direction orthogonal to the first principal surface (10A). The first component layer has a first sealing part (11) containing an inorganic material, and an active component (12A) positioned inside the first sealing part (11). The first component layer has a plurality of first via wires (14) extending in a direction intersecting the first principal surface (10A) inside the first sealing part (11), and having an end exposed from the first sealing part (11) on the first principal surface (10A). The first wiring layer has a first insulating resin part (21) and a first wiring part (22) extending inside the first insulating resin part (21). A connection terminal (13) of the active component (12A) is exposed from the first sealing part (11) on the second principal surface (10B) side of the first sealing part (11).

Description

Semiconductor Package

[0001] The present disclosure relates to semiconductor packages.

[0002] The electronic component described in Patent Document 1 has a core substrate. The core substrate has an opening penetrating the core substrate. The inside of the opening is filled with a magnetic resin. The magnetic resin further has a through hole. A through-hole conductor is located inside the through hole. The electronic component also has an insulating layer and a conductor layer. The insulating layer is located on a main surface of the core substrate. The conductor layer is located on the surface of the insulating layer. The conductor layer, together with the through-hole conductor, forms an inductor.

[0003] Japanese Patent Application Laid-Open No. 2020-178007

[0004] In the electronic component described in Patent Document 1, the inductor is composed of a conductor layer and a through-hole conductor. It is difficult to determine whether such an inductor operates normally until the entire electronic component is manufactured and a current is passed through the electronic component. Therefore, with the electronic component described in Patent Document 1, a test to determine whether the inductor operates normally must be conducted after the entire electronic component is manufactured. Note that although an inductor is used as an example here, even if the electronic component includes passive or active components other than an inductor, a similar problem arises in that it is difficult to determine whether the electronic component operates normally until the entire electronic component is manufactured.

[0005] In order to solve the above-described problems, one aspect of the present disclosure is a semiconductor package having passive components and active components, the semiconductor package comprising: a first component layer having a first main surface and a second main surface opposite to the first main surface; and a first wiring layer adjacent to the first component layer in a direction perpendicular to the first main surface, the first component layer having a first sealing portion containing an inorganic material, at least one of the active components located inside the first sealing portion, and a plurality of first via wirings extending inside the first sealing portion in a direction intersecting the first main surface and having ends exposed from the first sealing portion at the first main surface, the first wiring layer having a first insulating resin portion and a first wiring portion extending inside the first insulating resin portion, and a connection terminal of the active component exposed from the first sealing portion on the second main surface side of the first sealing portion.

[0006] According to the above configuration, passive components that have been judged to be acceptable can be mounted, improving reliability.

[0007] FIG. 1 is a schematic diagram of a semiconductor package according to a first embodiment. FIG. 2 is an explanatory diagram of a manufacturing method for a semiconductor package according to the first embodiment. FIG. 3 is an explanatory diagram of a manufacturing method for a semiconductor package according to the first embodiment. FIG. 4 is an explanatory diagram of a manufacturing method for a semiconductor package according to the first embodiment. FIG. 5 is an explanatory diagram of a manufacturing method for a semiconductor package according to the first embodiment. FIG. 6 is an explanatory diagram of a manufacturing method for a semiconductor package according to the first embodiment. FIG. 7 is an explanatory diagram of a manufacturing method for a semiconductor package according to the first embodiment. FIG. 8 is an explanatory diagram of a manufacturing method for a semiconductor package according to the first embodiment. FIG. 9 is an explanatory diagram of a manufacturing method for a semiconductor package according to the first embodiment. FIG. 10 is an explanatory diagram of a manufacturing method for a semiconductor package according to the first embodiment. FIG. 11 is an explanatory diagram of a manufacturing method for a semiconductor package according to the first embodiment. FIG. 12 is a schematic diagram of a semiconductor package according to a second embodiment. FIG. 13 is a schematic diagram of a semiconductor package according to a modified example. FIG. 14 is a schematic diagram of a semiconductor package according to a modified example. FIG. 15 is a schematic diagram of a semiconductor package according to a modified example.

[0008] An embodiment of a semiconductor package will be described below with reference to the drawings. The drawings may show components enlarged for ease of understanding. The dimensional ratios of the components may differ from those in the actual components or from those in other drawings. In the following description, some components are designated as first, second, etc. These are for convenience only and do not indicate the priority of the components. Furthermore, the first and second numbers may be interpreted interchangeably.

[0009] First Embodiment <Overall Configuration> As shown in FIG. 1 , the semiconductor package 10 includes a first layer L1. The outer shape of the first layer L1 is generally rectangular. The first layer L1 has a first main surface 10A and a second main surface 10B. The first main surface 10A is one of the outer surfaces of the first layer L1 with the largest area. When viewed in a direction perpendicular to the first main surface 10A, the first main surface 10A is rectangular. The second main surface 10B is the outer surface of the first layer L1 on the opposite side to the first main surface 10A. The second main surface 10B is parallel to the first main surface 10A. When viewed in a direction perpendicular to the second main surface 10B, the shape of the second main surface 10B is the same as the shape of the first main surface 10A.

[0010] In the following description, an axis perpendicular to the first main surface 10A is referred to as a first axis X. A specific direction along the first axis X is referred to as a first positive direction X1, and a direction opposite to the first positive direction X1 is referred to as a first negative direction X2. In the first embodiment, the first positive direction X1 coincides with the direction in which the first main surface 10A faces. The first negative direction X2 coincides with the direction in which the second main surface 10B faces.

[0011] The semiconductor package 10 includes a first layer L1 and a second layer L2, a third layer L3, a fourth layer L4, and a fifth layer L5 stacked thereon. When viewed in a direction along the first axis X, the first layer L1 to the fifth layer L5 all have a rectangular outer shape. The layers of the semiconductor package 10 are arranged in the following order from the first negative direction X2 toward the first positive direction X1: the second layer L2, the first layer L1, the third layer L3, the fourth layer L4, and the fifth layer L5.

[0012] The first layer L1 has a first sealing portion 11, a plurality of first electronic components 12, a plurality of first via wirings 14, and a plurality of first component external terminals 15. The first layer L1 is a first component layer including the first electronic components 12.

[0013] The first sealing portion 11 has a substantially rectangular parallelepiped outer shape. The plane of the outer surface of the first sealing portion 11 facing the first positive direction X1 is the first main surface 10A. The plane of the outer surface of the first sealing portion 11 facing the first negative direction X2 is the second main surface 10B. The first sealing portion 11 is made of TEOS (Tetra EthOxy Silane). That is, the first sealing portion 11 contains an inorganic material. Examples of materials containing an inorganic material that can be used for the first sealing portion 11 include SiO ２ Alternatively, TiN, TiO, SiCOH, etc. may be used.

[0014] The first electronic component 12 is a passive component or an active component. A passive component is either an inductor, a resistor, or a capacitor. An active component is an electronic component that performs an active task such as amplifying, rectifying, or converting current. For example, active components include diodes, transistors, and integrated circuits that include these. Note that even if the integrated circuit includes an inductor, a resistor, and a capacitor, it is treated as an active component as long as it has at least one active component. In the following explanation, "electronic component" refers to either a passive component or an active component.

[0015] 1 , the first layer L1 has three first electronic components 12. The three first electronic components 12 are two active components 12A and one passive component 12B. That is, at least one of the first electronic components 12 is the active component 12A. Also, one of the first electronic components 12 is the passive component 12B.

[0016] The passive component 12B includes an inorganic material. For example, if the passive component 12B is an inductor, the passive component 12B includes inorganic materials such as Fe, FeSi, and chromium-zirconium-tantalum alloys. These materials are contained in the core of the inductor. Furthermore, if the passive component 12B is an inductor, the passive component 12B includes inorganic materials such as Cu and Ag. These materials are contained in the wiring of the inductor.

[0017] Furthermore, when the passive component 12B is a capacitor, the passive component 12B is made of an inorganic material such as SiO ２ , SiN, barium titanate, etc. These materials are contained in the core of the capacitor. Furthermore, when the passive component 12B is a capacitor, the passive component 12B contains materials such as Al and Ni. These materials are contained in the electrodes. In addition, in both the case of an inductor and a capacitor, the passive component 12B contains organic materials such as epoxy-based and polyimide-based resins.

[0018] In the first embodiment, the volume fraction of the inorganic material in the passive component 12B is 80 vol % or more, that is, the volume fraction of the inorganic material in the passive component 12B is 50 vol % or more.

[0019] Each of the first electronic components 12 is located inside the first sealing portion 11. Specifically, the three first electronic components 12 are lined up in a direction parallel to the first main surface 10A. Each of the first electronic components 12 is located inside the first layer L1, closer to the second main surface 10B. Specifically, one main surface of each of the first electronic components 12 is generally flush with the second main surface 10B of the first layer L1.

[0020] Of the first electronic components 12, the two active components 12A have the same maximum dimension in the direction perpendicular to the first main surface 10A. The remaining first electronic component 12, the passive component 12B, has a maximum dimension in the direction perpendicular to the first main surface 10A that is larger than the maximum dimension of each active component 12A in the direction perpendicular to the first main surface 10A.

[0021] Each active component 12A includes a component body 12M, a connection terminal 13, and an internal terminal 13A. The connection terminal 13 functions as an external terminal for connecting the first electronic component 12 to external wiring or the like of the first electronic component 12. In the example shown in FIG. 1 , each active component 12A has two connection terminals 13 and two internal terminals 13A. The two connection terminals 13 are exposed toward the first negative direction X2. Specifically, each connection terminal 13 protrudes from the component body 12M. Furthermore, each connection terminal 13 is exposed from the first sealing portion 11 on the second main surface 10B side of the first sealing portion 11. Note that each connection terminal 13 protrudes from the first sealing portion 11.

[0022] The volume fraction of Cu is 50 vol % or more on the outer surface of the connection terminal 13 of each first electronic component 12. In the first embodiment, the volume fraction of Cu is 90 vol % or more throughout each connection terminal 13. Each connection terminal 13 contains traces of S, Ni, and O in addition to the Cu component.

[0023] The two internal terminals 13A are exposed from the component body 12M toward the first positive direction X1. That is, each internal terminal 13A is exposed from the component body 12M on the side opposite the connection terminal 13 in the direction perpendicular to the first main surface 10A. In the example shown in FIG. 1 , the internal terminals 13A do not protrude from the component body 12M. In other words, the end face of the internal terminal 13A on the first positive direction X1 side is flush with the component body 12M. That is, the protrusion amount of the connection terminal 13 is greater than the protrusion amount of the internal terminal 13A. The material of each internal terminal 13A is the same as the material of the connection terminal 13.

[0024] In the example shown in FIG. 1 , the passive component 12B of the first electronic component 12 has two connection terminals 13. The material of the two connection terminals 13 is the same as the material of the connection terminals 13 of the active component 12A. The two connection terminals 13 are exposed toward the first negative direction X2. Furthermore, each connection terminal 13 on the first negative direction X2 side is exposed from the first sealing portion 11 on the second main surface 10B side of the first sealing portion 11. Note that each connection terminal 13 on the first negative direction X2 side protrudes from the first sealing portion 11. In this way, the connection terminals 13 of each first electronic component 12 are exposed from the first sealing portion 11 only on the second main surface 10B of the first sealing portion 11.

[0025] In the example shown in FIG. 1 , the first layer L1 has four first via wirings 14. Each first via wiring 14 is substantially cylindrical. Each first via wiring 14 extends inside the first sealing portion 11 in a direction intersecting the first main surface 10A. In the first embodiment, each first via wiring 14 extends in a direction perpendicular to the first main surface 10A. A first end of each first via wiring 14 is connected to an internal terminal 13A of the active component 12A. A second end of each first via wiring 14 is exposed from the first sealing portion 11. That is, the end of the first via wiring 14 is exposed from the first sealing portion 11 on the first main surface 10A.

[0026] The first via wiring 14 contains a Cu component. The volume fraction of Cu in the first via wiring 14 is 50 vol % or more. In the first embodiment, the volume fraction of Cu in the first wiring portion 22 is 90 vol % or more.

[0027] The first component external terminals 15 protrude from the first sealing portion 11. Specifically, the first component external terminals 15 are exposed from the first positive direction X1 side of the first sealing portion 11. Each first component external terminal 15 is connected to a second end of a first via wiring 14. The material of each first component external terminal 15 is the same as the material of the first via wiring 14.

[0028] The second layer L2 is stacked on the first negative direction X2 side with respect to the first layer L1. In other words, the second layer L2 is stacked directly on the second main surface 10B of the first layer L1. Therefore, the second layer L2 is adjacent to the first component layer in a direction perpendicular to the first main surface 10A.

[0029] The second layer L2 has a first insulating resin portion 21, a first wiring portion 22, and a plurality of first wiring external terminals 23. Therefore, the second layer L2 is a first wiring layer including the first wiring portion 22.

[0030] The first insulating resin portion 21 has a substantially rectangular parallelepiped outer shape. The outer shape of the first insulating resin portion 21 substantially matches the outer shape of the second layer L2. The first insulating resin portion 21 is made of a synthetic resin containing an inorganic filler. Examples of the synthetic resin include epoxy and polyimide resins. The first insulating resin portion 21 covers the peripheral surfaces of the connection terminals 13 of the first electronic component 12 that protrude from the first sealing portion 11.

[0031] The first wiring portion 22 has a plurality of first columnar wirings 22B extending in a direction intersecting the first main surface 10A and a plurality of first wirings 22A extending in a direction parallel to the first main surface 10A. The first columnar wirings 22B are connected to the first wirings 22A. The plurality of first columnar wirings 22B and the plurality of first wirings 22A are connected to each other. Note that in FIG. 1 , only some of the first columnar wirings 22B and some of the first wirings 22A are denoted by reference numerals.

[0032] The first wiring portion 22 is connected to the connection terminal 13 of the first electronic component 12. The first wiring portion 22 extends in an arbitrary pattern inside the first insulating resin portion 21. The material of the first wiring portion 22 is the same as the material of the first via wiring 14. That is, the volume fraction of Cu in the first wiring portion 22 is 50 vol % or more.

[0033] The first wiring external terminals 23 protrude from the first insulating resin portion 21. Specifically, the first wiring external terminals 23 are exposed from the first negative direction X2 side of the first insulating resin portion 21. The material of each first wiring external terminal 23 has a three-layer structure consisting of, from the first positive direction X1 side, a layer mainly composed of Cu, a layer mainly composed of Ni, and a layer mainly composed of Au. The first wiring external terminals 23 function as external terminals when mounting the semiconductor package 10 on a substrate or the like. Note that only some of the first wiring external terminals 23 are labeled with reference numerals in FIG. 1 .

[0034] The third layer L3 is stacked on the first positive direction X1 side with respect to the first layer L1. In other words, the third layer L3 is stacked on the first main surface 10A of the first layer L1. That is, the third layer L3 is adjacent to the first component layer in a direction perpendicular to the first main surface 10A.

[0035] The third layer L3 has a second insulating resin portion 31, a second wiring portion 32, and a plurality of second wiring external terminals 33. The third layer L3 is a second wiring layer including the second wiring portion 32. The outer shape of the second insulating resin portion 31 is a substantially rectangular parallelepiped. The outer shape of the second insulating resin portion 31 substantially matches the outer shape of the third layer L3. The second insulating resin portion 31 is made of a synthetic resin containing an inorganic filler. The second insulating resin portion 31 covers the peripheral surfaces of the first component external terminals 15.

[0036] The second wiring portion 32 has a plurality of second wirings 32A extending in a direction parallel to the first main surface 10A and a plurality of second columnar wirings 32B extending in a direction intersecting the first main surface 10A. The second columnar wirings 32B are connected to the second wirings 32A. The plurality of second columnar wirings 32B and the plurality of second wirings 32A are connected to each other. Note that in FIG. 1 , only some of the second columnar wirings 32B and some of the second wirings 32A are denoted by reference numerals.

[0037] The second wiring portion 32 is connected to the first component external terminal 15. That is, the second wiring portion 32 is connected to the first via wiring 14 in the first layer L1 via the first component external terminal 15. In other words, the second end of the first via wiring 14 is connected to the second wiring portion 32 in the second wiring layer.

[0038] The second wiring portion 32 extends in an arbitrary pattern inside the second insulating resin portion 31. The material of the second wiring portion 32 is the same as the material of the first wiring portion 22. That is, the volume fraction of Cu in the second wiring portion 32 is 50 vol % or more.

[0039] The second wiring external terminals 33 protrude from the second insulating resin portion 31. Specifically, the second wiring external terminals 33 are exposed from the first positive direction X1 side of the second insulating resin portion 31. The material of each second wiring external terminal 33 is the same as the material of the first component external terminals 15.

[0040] The fourth layer L4 is stacked on the first positive direction X1 side of the third layer L3. The fourth layer L4 has a second sealing portion 41, a plurality of second electronic components 42, second via wirings 44, a plurality of second component external terminals 45, a plurality of connection portions 47, and an underfill 46. The fourth layer L4 is a second component layer including the second electronic components 42.

[0041] The second sealing portion 41 has a substantially rectangular parallelepiped outer shape. The outer shape of the second sealing portion 41 substantially matches the outer shape of the fourth layer L4. The material of the second sealing portion 41 is a synthetic resin containing an inorganic filler. In the example shown in FIG. 1 , the fourth layer L4 includes three second electronic components 42. The second electronic components 42 are two active components 42A and one passive component 42B. That is, at least one of the second electronic components 42 is the active component 42A. Also, one of the second electronic components 42 is the passive component 42B. The volume fraction of the inorganic material in the passive component 42B is 80 vol % or more.

[0042] Each second electronic component 42 is located inside the second sealing portion 41. Specifically, the three second electronic components 42 are lined up in a direction parallel to the first main surface 10A. Each second electronic component 42 has a connection terminal 43. The connection terminal 43 functions as an external terminal for connecting the second electronic component 42 to external wiring or the like.

[0043] 1 , each second electronic component 42 has two connection terminals 43. Each connection terminal 43 is exposed toward the first negative direction X2. These connection terminals 43 are not covered by the second insulating resin portion 31. The material of the connection terminals 43 of each second electronic component 42 is the same as the material of the connection terminals 43 of the first electronic component 12.

[0044] The second via wiring 44 has a substantially cylindrical shape. The second via wiring 44 extends inside the second sealing portion 41 in a direction intersecting the first main surface 10A. In the first embodiment, the second via wiring 44 extends in a direction perpendicular to the first main surface 10A. A first end of the second via wiring 44 is connected to one of the second wiring external terminals 33. A second end of the second via wiring 44 is exposed from the second sealing portion 41. That is, the end of the second via wiring 44 is exposed from the second sealing portion 41 on the surface on the first positive direction X1 side. The material of the second via wiring 44 is the same as the material of the first via wiring 14.

[0045] The second component external terminals 45 protrude from the second sealing portion 41. Specifically, the second component external terminals 45 are exposed from the first positive direction X1 side of the second sealing portion 41. One of the second component external terminals 45 is connected to the second end of the second via wiring 44. The material of each second component external terminal 45 is the same as the material of the first component external terminals 15.

[0046] The second wiring external terminals 33 that are not connected to the second via wirings 44 are connected to the connection terminals 43 of the second electronic component 42 through connection portions 47. The connection portions 47 are made of a conductive material such as solder. There are as many connection portions 47 as there are second wiring external terminals 33. Each connection portion 47 is applied to the corresponding second wiring external terminal 33. In other words, the connection portions 47 cover the surfaces of the second wiring external terminals 33 facing the first positive direction X1.

[0047] The underfill 46 is located inside the second sealing portion 41. The underfill 46 is located in a region from the first positive direction X1 side of the second insulating resin portion 31 to the end of the connection terminal 43 on the first positive direction X1 side. That is, the underfill 46 covers the peripheral surfaces of the second wiring external terminal 33, the connection portion 47, and the connection terminal 43. The material of the underfill 46 is, for example, an epoxy resin. Note that the material of the underfill 46 is not limited to epoxy-based resin, but may also be polyimide-based resin, liquid crystal polymer-based resin, acrylic-based resin, phenol-based resin, or a combination thereof. The underfill 46 may also contain silica filler as an inorganic filler.

[0048] The fifth layer L5 is stacked on the first positive direction X1 side of the fourth layer L4. The fifth layer L5 has a third insulating resin portion 51 and a third wiring portion 52. The fifth layer L5 is a third wiring layer including the third wiring portion 52.

[0049] The third insulating resin portion 51 has a substantially rectangular parallelepiped shape. The shape of the third insulating resin portion 51 substantially matches the shape of the fifth layer L5. The material of the third insulating resin portion 51 is the same as the material of the first insulating resin portion 21. The second component external terminal 45 is embedded in the third insulating resin portion 51 on the side of the third insulating resin portion 51 in the first negative direction X2.

[0050] The third wiring portion 52 has a plurality of third columnar wirings 52B extending in a direction intersecting the first main surface 10A and a plurality of third wirings 52A extending in a direction parallel to the first main surface 10A. The third columnar wirings 52B are connected to the third wirings 52A. Note that in FIG. 1, only some of the third columnar wirings 52B and some of the third wirings 52A are denoted by reference numerals.

[0051] The third wiring portion 52 is connected to the second component external terminal 45. The third wiring portion 52 extends in an arbitrary pattern inside the third insulating resin portion 51. The material of the third wiring portion 52 is the same as the material of the first wiring portion 22. That is, the volume fraction of Cu in the third wiring portion 52 is 50 vol % or more.

[0052] <Method of Manufacturing Semiconductor Package> A method of manufacturing the semiconductor package 10 will be described. Note that in some cases, reference numerals are assigned to only some of the components in FIGS.

[0053] As shown in FIG. 2 , first, a plate-shaped base substrate BL is prepared. The base substrate BL is made of silicon. In the following description, it is assumed that the main surface of the base substrate BL is perpendicular to the first axis X. When viewed in the first negative direction X2, the base substrate BL has, for example, a rectangular shape. The dimensions of each side of the base substrate BL are such that multiple semiconductor packages 10 can be accommodated. Next, a first release layer RL1 is applied to the first positive direction X1 side of the base substrate BL, i.e., the entire upper surface. The first release layer RL1 is a sheet-shaped member having adhesive properties, such as an infrared-curable resin tape, an acrylic resin adhesive, or a polyimide adhesive.

[0054] 3, the first electronic component 12 is placed on the first release layer RL1. Specifically, the first electronic component 12 is placed so that the connection terminals 13 of the first electronic component 12 face the first release layer RL1.

[0055] Next, as shown in FIG. 4 , the first sealing portion 11 is formed. Specifically, first, an insulator is formed from the first positive direction X1 side of each first electronic component 12 and the first release layer RL1 using a known technique such as CVD. The insulator is made of TEOS. Next, a first through hole PO1 is formed in the insulator using a known technique such as the Bosch method. The first through hole PO1 is formed at a position overlapping the internal terminal 13A of the first electronic component 12 when viewed in the first negative direction X2.

[0056] 5, a first via wiring 14 is formed in the first through hole PO1. The first via wiring 14 is formed by a known technique such as a via-fill method. Although not shown in the drawings, a seed layer made of Cu is formed in the process of forming the first via wiring 14.

[0057] 6 , the second insulating resin portion 31, the second wiring portion 32, and the second wiring external terminals 33 are formed on the first positive direction X1 side of the first sealing portion 11. The second insulating resin portion 31 is formed by photolithography. The second wiring portion 32 and the second wiring external terminals 33 are formed by a known technique such as a semi-additive method. In this process, the second wiring external terminals 33 may be surface-treated by a known method such as electroless plating or electrolytic plating.

[0058] Next, as shown in Fig. 7, the second electronic component 42 is mounted. Specifically, the terminals of the second electronic component 42 are connected onto the second wiring external terminals 33 with solder. The solder after connection forms a connection portion 47. Furthermore, epoxy resin is filled between the second insulating resin portion 31 and the second electronic component 42. This forms an underfill 46.

[0059] Next, the second sealing portion 41 is formed. Specifically, an insulator is laminated from the first positive direction X1 side of the second electronic component 42 and the second insulating resin portion 31. The material of the insulator is an organic resin containing an inorganic filler. Next, a laser is irradiated onto the insulator from the first positive direction X1 side. Specifically, the laser is irradiated onto the insulator in a portion on the first positive direction X1 side of the second wiring external terminal 33 that is not connected to the second electronic component 42 and where the second via wiring 44 will be formed. This processes the insulator, and a second through hole PO2 is formed.

[0060] 8, a second via wiring 44 is formed in the second through hole PO2. The second via wiring 44 is formed by a known technique such as a via-fill method. Although not shown, a seed layer made of Cu is formed in the process of forming the second via wiring 44. Then, a portion of the second sealing portion 41 and the second via wiring 44 on the first positive direction X1 side is polished to a desired size.

[0061] Next, as shown in FIG. 9 , the third insulating resin portion 51, the third wiring portion 52, and the second component external terminals 45 are formed. The third insulating resin portion 51 is formed by photolithography. The third wiring portion 52 and the second component external terminals 45 are formed by a known technique such as a semi-additive method. Next, the first release layer RL1 is removed by cutting. Furthermore, a second release layer RL2 is formed on the first positive direction X1 side of the third insulating resin portion 51. The second release layer RL2 is formed so as to cover the entire third insulating resin portion 51. The material of the second release layer RL2 is the same as the material of the first release layer RL1.

[0062] 10 , a first insulating resin portion 21, a first wiring portion 22, and a first wiring external terminal 23 are formed on the first negative direction X2 side of the first sealing portion 11. The first insulating resin portion 21 is formed by photolithography. The first wiring portion 22 and a portion of the first wiring external terminal 23 are formed by a known technique such as a semi-additive method. Furthermore, a layer mainly composed of Ni and a layer mainly composed of Au are formed on a portion of the formed first wiring external terminal 23 by a known method such as electroless plating or electrolytic plating. This forms the first wiring external terminal 23.

[0063] 11, the semiconductor package 10 is diced along the break lines DL to separate the semiconductor package 10 into individual pieces of a desired size. Then, the second release layer RL2 is removed by cutting.

[0064] <Effects of the First Embodiment> (1-1) According to the first embodiment, the semiconductor package 10 includes active components 12A and passive components 12B. These active components 12A and passive components 12B are mounted during the process of forming the semiconductor package 10. In other words, according to the above configuration, only active components 12A and passive components 12B that have been determined to be non-defective in advance can be used. Therefore, after the entire semiconductor package 10 is formed, it is not necessarily necessary to test these active components 12A and passive components 12B to determine whether they operate normally. This configuration can increase the yield rate of the semiconductor package 10.

[0065] (1-2) In the first embodiment, the second layer L2, which is the first wiring layer, is stacked on the second main surface 10B of the first layer L1, which is the first component layer. By stacking the second layer L2 on the first layer L1, the second main surface 10B of the first layer L1 is covered by the second layer L2. With this configuration, the second layer L2 can absorb external impacts acting on the active components 12A and passive components 12B included in the first layer L1.

[0066] In the first embodiment, the third layer L3, which is the second wiring layer, is stacked on the first main surface 10A of the first layer L1, which is the first component layer. This configuration further reduces the impact on the active components 12A and the passive components 12B.

[0067] (1-3) In the first embodiment described above, the first end of the first via wiring 14 is connected to the first electronic component 12. The second end of the first via wiring 14 is connected to the first wiring portion 22 in the first wiring layer. That is, the first via wiring 14 connects the first electronic component 12 and the first wiring portion 22. With this configuration, the first via wiring 14 allows a current to flow directly through the first electronic component 12 in a direction perpendicular to the first main surface 10A. In other words, the first electronic component 12 and the first wiring portion 22 can be connected within the first layer L1 without requiring a configuration such as wiring extending parallel to the first main surface 10A and vias extending in a direction intersecting the first main surface 10A.

[0068] (1-4) In the first embodiment, the volume fraction of Cu on the outer surface of the connection terminal 13 of the first electronic component 12 is 50 vol% or more. The volume fraction of Cu in the first wiring portion 22 is also 50 vol% or more. In the first embodiment, the material of the first via wiring 14 connecting the first wiring portion 22 and the connection terminal 13 is the same as the material of the first wiring portion 22 and contains 50 vol% or more of Cu. That is, since the interface between the connection terminal 13 and the first via wiring 14 is made of the same material, the connection terminal 13 and the first via wiring 14 are easily integrated. This improves the connection strength between the connection terminal 13 and the first via wiring 14. Similarly, since the interface between the first wiring portion 22 and the first via wiring 14 is made of the same material, the connection strength between the first wiring portion 22 and the first via wiring 14 is easily improved. This improves the electrical connection between the first electronic component 12 and the first wiring portion 22.

[0069] (1-5) In the first embodiment, the passive component 12B contains an inorganic material. The volume fraction of the inorganic material in the passive component 12B is 50 vol% or more. The first sealing portion 11 covering the peripheral surface of the passive component 12B also contains an inorganic material. That is, with this configuration, the difference between the thermal expansion coefficients of the passive component 12B and the first sealing portion 11 is not extremely large. With such a relationship in thermal expansion coefficients, the amount of deformation of these components due to temperature changes does not differ significantly, thereby suppressing warpage in the first layer L1 due to thermal deformation.

[0070] (1-6) In the first embodiment, the maximum dimension of the passive component 12B in the direction perpendicular to the first main surface 10A is larger than the maximum dimension of the active component 12A in the direction perpendicular to the first main surface 10A. That is, the thickness of the passive component 12B is accordingly large. Therefore, for example, if the passive component 12B is an inductor, it is easy to design it to obtain a desired inductance. Also, if the passive component 12B is a capacitor, it is easy to design it to obtain a desired capacitance.

[0071] (1-7) In the first embodiment, the protrusion amount of the connection terminals 13 of the active component 12A of the first electronic component 12 is greater than the protrusion amount of the internal terminals 13A. Because the connection terminals 13 protrude a greater amount, the connection terminals 13 can be used for positioning when arranging the active component 12A in the manufacturing process of the semiconductor package 10. Furthermore, the connection terminals 13 increase the surface area of ​​the surface of the first layer L1 facing the first negative direction X2, thereby improving adhesion with the second layer L2. Furthermore, because the protrusion amount of the internal terminals 13A is relatively small, it is possible to prevent the dimension of the active component 12A itself from increasing in a direction perpendicular to the first main surface 10A.

[0072] Second Embodiment <Overall Configuration> A second embodiment of the semiconductor package will now be described.

[0073] 12, the semiconductor package 10 of the second embodiment includes a first layer L1 and a second layer L2. The first layer L1 has a first main surface 10A and a second main surface 10B. The first main surface 10A and the second main surface 10B are the same as those in the first embodiment. The first axis X, the first positive direction X1, and the first negative direction X2 are also treated in the same manner as those in the first embodiment.

[0074] The first layer L1 includes a first component layer PT1 and two first wiring layers LN1. In the second embodiment, each of the first wiring layers LN1, which is a layer separate from the first component layer PT1, is embedded inside the first component layer PT1.

[0075] The first component layer PT1 has a first sealing portion 21, a plurality of first electronic components 22, a plurality of first via wirings 24, and a plurality of first component external terminals 25. The first sealing portion 21 has an outer shape of a substantially rectangular parallelepiped. The two first wiring layers LN1 described above are located inside the first sealing portion 21. That is, the first wiring layer LN1 is adjacent to the first sealing portion 21 or the first electronic components 22, which are part of the first component layer PT1, in a direction perpendicular to the first main surface 10A. The material of the first sealing portion 21 is the same as that in the first embodiment. That is, the first sealing portion 21 contains an inorganic material.

[0076] 12 , the first layer L1 has three first electronic components 22. All three first electronic components 22 are active components, that is, at least one of the first electronic components 22 is an active component.

[0077] Each of the first electronic components 22 is located inside the first sealing portion 21. Specifically, the three first electronic components 22 are lined up in a direction parallel to the first main surface 10A. Each of the first electronic components 22 is located inside the first layer L1, closer to the second main surface 10B. Specifically, one main surface of each of the first electronic components 22 is generally flush with the second main surface 10B of the first layer L1.

[0078] Two of the three first electronic components 22 are adjacent to different first wiring layers LN1. Specifically, a first wiring layer LN1 is stacked on each of the surfaces of the two first electronic components 22 facing the first positive direction X1. The first wiring layers LN1 are not electrically connected to each other within the first layer L1.

[0079] Each first electronic component 22 includes a connection terminal 26. The connection terminal 26 functions as an external terminal for connecting the first electronic component 22 to external wiring or the like. In the example shown in FIG. 12 , each first electronic component 22 has a plurality of connection terminals 26. Each connection terminal 26 is exposed toward the first negative direction X2. Each connection terminal 26 is exposed from the first sealing portion 21 on the second main surface 10B side of the first sealing portion 21. Each connection terminal 26 protrudes from the first sealing portion 21. The volume fraction of Cu in the outer surface of each connection terminal 26 is 50 vol % or more. The material of the connection terminals 26 in the second embodiment is the same as that in the first embodiment.

[0080] Each first wiring layer LN1 has a first wiring portion 12 and a first insulating resin portion 11. Note that FIG. 12 omits the illustration of the first wiring portion 12 and the first insulating resin portion 11 inside the first wiring layer LN1. The first wiring portion 12 and the first insulating resin portion 11 have the same configuration as in the first embodiment. That is, the outer shape of each first insulating resin portion 11 is approximately rectangular parallelepiped. However, the dimension of each first insulating resin portion 11 in a direction parallel to the first main surface 10A is smaller than the dimension of the first layer L1 in a direction parallel to the first main surface 10A. Furthermore, the dimension of each first insulating resin portion 11 in a direction perpendicular to the first main surface 10A is smaller than the dimension of the first layer L1 in a direction perpendicular to the first main surface 10A. Each first insulating resin portion 11 is made of a synthetic resin containing an inorganic filler.

[0081] Each first wiring portion 12 extends in an arbitrary pattern inside each first insulating resin portion 11. The material of each first wiring portion 12 is the same as the material of the first wiring portion 12 in the first embodiment. That is, the volume fraction of Cu in each first wiring portion 12 is 50 vol % or more.

[0082] Two first electronic components 22 adjacent to the first wiring layer LN1 are provided with through-hole wires 23. That is, one or more selected from the active components are provided with through-hole wires 23. Each of the active components is provided with two through-hole wires 23. Each through-hole wire 23 is substantially cylindrical. Each through-hole wire 23 penetrates the active component in a direction perpendicular to the first main surface 10A. The end of each through-hole wire 23 on the first positive direction X1 side is connected to the first wiring portion 12 of the first wiring layer LN1. Furthermore, the end of each through-hole wire 23 on the first negative direction X2 side is connected to the connection terminal 26.

[0083] 12 , the first component layer PT1 has four first via wirings 24. Each first via wiring 24 is substantially cylindrical. The diameter of each first via wiring 24 is larger than the diameter of each through wiring 23. In other words, the maximum dimension of the through wiring 23 in a direction parallel to the first main surface 10A is smaller than the maximum dimension of the first via wiring 24 in a direction parallel to the first main surface 10A. Each first via wiring 24 extends in a direction intersecting the first main surface 10A inside the first sealing portion 21. In the second embodiment, each first via wiring 24 extends in a direction perpendicular to the first main surface 10A.

[0084] Two of the four first via wirings 24 extend from the first wiring layer LN1. That is, first ends of the first via wirings 24 on the first negative direction X2 side are connected to the first wiring portion 12 of the first wiring layer LN1. Second ends of the first via wirings 24 on the first positive direction X1 side are exposed from the first sealing portion 21 on the first main surface 10A side.

[0085] Furthermore, first ends of the remaining two first via wirings 24 on the first negative direction X2 side are exposed from the first sealing portion 21 on the second main surface 10B side. Second ends of the two first via wirings 24 on the first positive direction X1 side are exposed from the first sealing portion 21 on the first main surface 10A side. That is, the ends of the four first via wirings 24 in the second embodiment are exposed from the first sealing portion 21 on the first main surface 10A side.

[0086] The first via wiring 24 contains a Cu component. The volume fraction of Cu in the first via wiring 24 is 50 vol % or more. In the second embodiment, similarly to the first embodiment, the volume fraction of Cu in the first via wiring 24 is 90 vol % or more.

[0087] 12, the first layer L1 has ten first component external terminals 25. Note that the first layer L1 may have other first component external terminals 25 that are not shown in the cross section of FIG. 12. Two of these first component external terminals 25 protrude from the first negative direction X2 side of the first sealing portion 21. The first component external terminals 25 are each connected to a first end of a first via wiring 24 exposed from the first sealing portion 21 on the second main surface 10B side. The material of these ten first component external terminals 25 is the same as the material of the connection terminals 26.

[0088] The remaining eight first component external terminals 25 of the first component external terminals 25 on the cross section shown in FIG. 12 are exposed on the first positive direction X1 side of the first sealing portion 21. The peripheral surfaces of the eight first component external terminals 25 are covered by the first sealing portion 21. Four of these first component external terminals 25 are connected to the ends of the first via wirings 24 on the first positive direction X1 side. The remaining four first component external terminals 25 are stacked directly on the first positive direction X1 side of the first wiring layer LN1. The first component external terminals 25 are electrically connected to the first wiring portion 12 in the first wiring layer LN1. The material of these eight first component external terminals 25 is the same as the material of the first wiring portion 12. Note that in FIG. 12, only some of the first component external terminals 25 are labeled with reference numerals.

[0089] The second layer L2 is stacked directly on the first layer L1 on the first positive direction X1 side. The second layer L2 includes a second component layer PT2 and four second wiring layers LN2. As with the first layer L1 described above, the second layer L2 also includes a second wiring layer LN2, which is a separate layer from the second component layer PT2, embedded within the second component layer PT2.

[0090] The second component layer PT2 has a second sealing portion 41, a plurality of second electronic components 42, and a plurality of second component external terminals 43. The outer shape of the second sealing portion 41 is a substantially rectangular parallelepiped. The four second wiring layers LN2 described above are located inside the second sealing portion 41. That is, the second wiring layer LN2 is adjacent to the second sealing portion 41 or the second electronic components 42, which are part of the second component layer PT2, in a direction perpendicular to the first main surface 10A. The material of the second sealing portion 41 is the same as the material of the first sealing portion 21. That is, the second sealing portion 41 contains an inorganic material.

[0091] 12 , the second layer L2 has five second electronic components 42. Four of the five second electronic components 42 are active components 42A. The remaining second electronic component 42 is a passive component 42B. That is, at least one of the second electronic components 42 is an active component 42A. At least one of the second electronic components 42 is a passive component 42B.

[0092] Two of the four active components 42A are aligned in a direction parallel to the first main surface 10A. A second wiring layer LN2 is stacked on each of the surfaces of these two active components 42A facing the first negative direction X2. Furthermore, a second wiring layer LN2 and another active component 42A are stacked on each of the surfaces of the two active components 42A facing the first positive direction X1. Therefore, these elements form a stack of four elements stacked in the order of the second wiring layer LN2, active component 42A, second wiring layer LN2, and active component 42A toward the first positive direction X1. Two sets of such stacks are aligned in a direction parallel to the first main surface 10A. Adjacent second wiring layers LN2 and active components 42A are electrically connected to each other. Note that the second wiring layers LN2 are not electrically connected to each other within the second layer L2.

[0093] Here, the two active components 42A in one set of laminates stacked in a direction along the first axis X are referred to as the first active component 42A1 and the second active component 42A2, respectively. The first active component 42A1 is located on the first negative direction X2 side relative to the second active component 42A2. The first active component 42A1 and the second active component 42A2 are stacked on the first component layer PT1 in a direction perpendicular to the first main surface 10A. Furthermore, no electronic components are present between the first active component 42A1 and the first component layer PT1. That is, the first active component 42A1 and the second active component 42A2 are stacked on the first component layer PT1 in a direction perpendicular to the first main surface 10A without any other electronic components interposed therebetween. The maximum dimension of the first active component 42A1 in the direction perpendicular to the first main surface 10A is the same as the maximum dimension of the second active component 42A2 in the direction perpendicular to the first main surface 10A. The active components 42A have the same thickness dimension.

[0094] The passive component 42B of the second electronic component 42 is positioned next to the two stacked layers of the active component 42A and the second wiring layer LN2 in a direction parallel to the first main surface 10A. The passive component 42B contains an inorganic material. The volume fraction of the inorganic material in the passive component 42B is 80 vol % or more.

[0095] The maximum dimension of the passive component 42B in a direction perpendicular to the first main surface 10A is greater than the sum of the maximum dimension of the first active component 42A1 in a direction perpendicular to the first main surface 10A and the maximum dimension of the second active component 42A2 in a direction perpendicular to the first main surface 10A.

[0096] Each of the second wiring layers LN2 described above includes a second wiring portion 32 and a second insulating resin portion 31. Note that FIG. 12 does not illustrate the second wiring portion 32 and the second insulating resin portion 31 inside the second wiring layer LN2. The second wiring portion 32 and the second insulating resin portion 31 have the same configuration as the first wiring layer LN1. That is, the outer shape of each second insulating resin portion 31 is a substantially rectangular parallelepiped. However, because the second wiring layer LN2 is embedded in the second component layer PT2, the dimension of each second insulating resin portion 31 in a direction parallel to the first main surface 10A is smaller than the dimension of the second layer L2 in a direction parallel to the first main surface 10A. Furthermore, the dimension of each second insulating resin portion 31 in a direction perpendicular to the first main surface 10A is smaller than the dimension of the second layer L2 in a direction perpendicular to the first main surface 10A. The material of each second insulating resin portion 31 is a synthetic resin containing an inorganic filler.

[0097] Each second wiring portion 32 extends in an arbitrary pattern inside each second insulating resin portion 31. The material of each second wiring portion 32 is the same as the material of the second wiring portion 32. That is, the volume fraction of Cu in the second wiring portion 32 is 50 vol % or more.

[0098] In the cross section shown in FIG. 12 , the second layer L2 has eight second component external terminals 43. Note that the second layer L2 may have other second component external terminals 43 not shown in the cross section of FIG. 12 . Seven of the second component external terminals 43 in the cross section shown in FIG. 12 are stacked directly on the first negative direction X2 side of the second wiring layer LN2. These seven second component external terminals 43 are electrically connected to the second wiring layer LN2. Furthermore, the remaining second component external terminal 43 of the second component external terminals 43 in the cross section shown in FIG. 12 is stacked directly on the first negative direction X2 side of the passive component 42B of the second electronic component 42.

[0099] 12, the peripheral surfaces of the eight second component external terminals 43 are covered by the second sealing portion 41. The eight second component external terminals 43 are exposed on the first negative direction X2 side of the second sealing portion 41. That is, each second component external terminal 43 is exposed from the surface of the second sealing portion 41 facing the first component layer PT1.

[0100] 12 , eight of the first component external terminals 25 are exposed on the first positive direction X1 side of the first sealing portion 21. That is, the first component external terminals 25 are exposed from the surface of the first sealing portion 21 facing the second component layer PT2. The first component external terminals 25 are connected to the second component external terminals 43 without any intervening member. Similarly, the first sealing portion 21 facing in the first positive direction X1 is in contact with the second sealing portion 41 facing in the first negative direction X2 without any intervening member.

[0101] Each of the components of the first layer L1 and the second layer L2 contains an inorganic material. In the second embodiment, the inorganic material accounts for most of the entire semiconductor package 10. Specifically, the volume fraction of the inorganic material in the entire semiconductor package 10 is 90 vol % or more.

[0102] Advantages of the Second Embodiment (2-1) According to the second embodiment, the first component layer PT1 includes the first electronic components 22. The first electronic components 22 are mounted during the process of forming the semiconductor package 10. That is, according to the above configuration, only first electronic components 22 that have been determined to be non-defective in advance can be used. Therefore, after the entire semiconductor package 10 is formed, it is not necessarily necessary to test these first electronic components 22 to determine whether they operate normally. According to this configuration, the yield rate of the semiconductor package 10 can be increased.

[0103] (2-2) In the second embodiment, one or more selected from the first electronic components 22 include through wiring 23. The through wiring 23 is connected to the first wiring portion 12. With this configuration, the through wiring 23 allows a current to flow inside the first electronic component 22 in a direction perpendicular to the first main surface 10A. That is, with this configuration, a current can be passed through the first wiring portion 12 via the first electronic component 22, so there is no need to design a wiring pattern that avoids the first electronic component 22, and the wiring pattern can be prevented from becoming complicated.

[0104] (2-3) In the second embodiment, the maximum dimension of each through wiring 23 in a direction parallel to the first main surface 10A is smaller than the maximum dimension of each first via wiring 24 in a direction parallel to the first main surface 10A. With this configuration, a larger current can flow through the first via wiring 24 than through the through wiring 23. In other words, a larger current can be applied to the first component layer PT1 compared to when the maximum dimension of the first via wiring 24 in a direction parallel to the first main surface 10A and the maximum dimension of the through wiring 23 in a direction parallel to the first main surface 10A are the same.

[0105] (2-4) In the second embodiment, the volume fraction of the inorganic material in the passive component 42B is 80 vol % or more. Furthermore, the volume fraction of the inorganic material in the entire semiconductor package 10 is 90 vol % or more. This configuration makes it possible to achieve a uniform thermal expansion coefficient throughout the entire semiconductor package 10. Therefore, localized thermal deformation in the semiconductor package 10 can be suppressed.

[0106] (2-5) In the second embodiment, the first component external terminal 25 is connected to the second component external terminal 43 without any other intervening member. In other words, the second component layer PT2 is connected to the first component layer PT1 without any other wiring such as a via. Therefore, when a current flows from the first component layer PT1 to the second component layer PT2, an increase in DC resistance at the interface between these components can be suppressed.

[0107] (2-6) In the second embodiment, the maximum dimension of the passive component 42B in a direction perpendicular to the first main surface 10A is greater than the sum of the maximum dimension of the first active component 42A1 in a direction perpendicular to the first main surface 10A and the maximum dimension of the second active component 42A2 in a direction perpendicular to the first main surface 10A. With this configuration, for example, if the passive component 42B is an inductor, the core capacitance can be ensured. Therefore, the obtainable inductance can be increased. Furthermore, with this configuration, the capacitance can also be increased when a capacitor is used as the passive component.

[0108] <Modifications> The above-described first and second embodiments can be modified as follows. The above-described first and second embodiments and the following modifications can be combined and implemented to the extent that no technical contradiction occurs. In the modifications shown in FIGS. 13 to 15 below, descriptions of parts having the same configuration as the first and second embodiments may be omitted or simplified. In FIGS. 13 to 15, some of the reference numerals may be omitted for parts having the same configuration as the first and second embodiments.

[0109] In the second embodiment, a wiring layer may be further stacked on the first component layer PT1. For example, in the example shown in FIG. 13 , the semiconductor package 10 includes a third layer L3. The third layer L3 is stacked on the first negative direction X2 side of the first layer L1. In other words, the third layer L3 is stacked directly on the second main surface 10B of the first layer L1. Therefore, the third layer L3 is adjacent to the first component layer PT1 in a direction perpendicular to the first main surface 10A.

[0110] The third layer L3 has a third insulating resin portion 51, a third wiring portion 52, and a plurality of third wiring external terminals 53. Therefore, the third layer L3 is a third wiring layer LN3 including the third wiring portion 52. The third wiring layer LN3 has the same configuration as the second wiring layer in the first embodiment.

[0111] The third insulating resin portion 51 has a substantially rectangular parallelepiped outer shape and is made solely of organic resin. The third insulating resin portion 51 covers the peripheral surfaces of the first component external terminals 25 and the connection terminals 26 that protrude from the first sealing portion 21.

[0112] The third wiring portion 52 is connected to the first component external terminal 25 or the connection terminal 26. The third wiring portion 52 extends in an arbitrary pattern inside the third insulating resin portion 51. The material of the third wiring portion 52 is the same as the material of the first wiring portion 12. That is, the volume fraction of Cu in the third wiring portion 52 is 50 vol % or more.

[0113] The third wiring external terminals 53 protrude from the third insulating resin portion 51. Specifically, the third wiring external terminals 53 are exposed from the first negative direction X2 side of the third insulating resin portion 51. The material of each third wiring external terminal 53 has a three-layer structure including, from the first positive direction X1 side, a layer mainly made of Cu, a layer mainly made of Ni, and a layer mainly made of Au.

[0114] If the third insulating resin portion 51 were made of only inorganic materials, a high level of cleanliness would be required in the manufacturing environment of the semiconductor package 10. In the example shown in Fig. 13, the material of the third insulating resin portion 51 is only organic resin. Therefore, in the example shown in Fig. 13, the manufacturing environment does not require as high a level of cleanliness as when the third insulating resin portion 51 is made of only inorganic materials, and it is possible to suppress increases in manufacturing costs. Note that the same effect can be achieved not only when the third insulating resin portion 51 is made of only organic resin, but also when the third insulating resin portion 51 is made of an organic resin containing an inorganic filler.

[0115] In the second embodiment, the semiconductor package 10 may further include a member for connecting to a motherboard. In the example shown in FIG. 13 , the semiconductor package 10 includes a land portion 54. The land portion 54 is made of a conductive material such as solder. The land portion 54 is applied to some of the third wiring external terminals 53. The land portion 54 covers the surfaces of the third wiring external terminals 53 on the first negative direction X2 side. In other words, the land portion 54 is located on the third wiring external terminals 53 located on the surface facing away from the first component layer PT1 in a direction perpendicular to the first main surface 10A of the third wiring layer LN3. The land portion 54 is a member for connecting a motherboard mounted on the third wiring layer LN3.

[0116] According to this configuration, the presence of the land portion 54 makes it possible to design any wiring pattern for the third wiring portion 52. In other words, the wiring pattern for the third wiring portion 52 can be designed to be a suitable pattern in consideration of the connection between the motherboard and the first electronic component 22 on the first component layer PT1.

[0117] In the second embodiment, the sizes of the active components 42A stacked on the first component layer PT1 do not all need to be the same. In the example shown in FIG. 13 , of the active components 42A included in the second component layer PT2, the surfaces facing the first positive direction X1 of the two active components 42A located furthest from the first positive direction X1 are exposed from the second sealing portion 41. Here, the two active components 42A in the example shown in FIG. 13 are referred to as the first active component 42A1 and the second active component 42A2, respectively. The first active component 42A1 and the second active component 42A2 are stacked on the first component layer PT1 in a direction perpendicular to the first main surface 10A. In the example shown in FIG. 13 , the first active component 42A1 and the second active component 42A2 are stacked on the first component layer PT1 via the second wiring layer LN2 and other active components 42A. The first active component 42A1 and the second active component 42A2 are arranged side by side in a direction parallel to the first main surface 10A, without any other electronic component therebetween.

[0118] 13, the semiconductor package 10 includes a third active component 42A3 and a fourth wiring layer LN4. The configuration of the fourth wiring layer LN4 is similar to the configuration of the second wiring layer LN2 in the second embodiment. That is, the fourth wiring layer LN4 includes a fourth insulating resin portion 61 and a fourth wiring portion 62. The fourth wiring portion 62 extends in an arbitrary pattern inside the fourth insulating resin portion 61.

[0119] In the example shown in FIG. 13 , the fourth wiring layer LN4 and the third active component 42A3 are stacked on the first component layer PT1 in a direction perpendicular to the first main surface 10A. Specifically, the third active component 42A3 is stacked on the first active component 42A1 and the second active component 42A2 via the fourth wiring layer LN4 in a direction perpendicular to the first main surface 10A. Note that no other electronic components are interposed between the third active component 42A3 and the first active component 42A1 or the second active component 42A2. When viewed from a direction perpendicular to the first main surface 10A, the third active component 42A3 and the fourth wiring layer LN4 overlap the first active component 42A1 and the second active component 42A2. With this configuration, power is supplied to the third active component 42A3 via the first active component 42A1 and the second active component 42A2. That is, the semiconductor package 10 includes a highly integrated active component 42A.

[0120] In the second embodiment, a wiring layer may be stacked on the first component layer PT1 in the first positive direction X1. Also, a plurality of wiring layers may be stacked on the first component layer PT1.

[0121] In the example shown in Fig. 14, the second layer L2 in the second embodiment is composed only of a second wiring layer LN2. Also, in the example shown in Fig. 14, the semiconductor package 10 includes a fourth layer L4 stacked in the first positive direction X1 with respect to the second layer L2. The fourth layer L4 is composed only of a fourth wiring layer LN4. In the example shown in Fig. 14, the semiconductor package 10 includes a third wiring layer LN3 similar to the example shown in Fig. 13.

[0122] The second wiring layer LN2 includes a second insulating resin portion 31, a second wiring portion 32, and a plurality of second wiring external terminals 33. The second insulating resin portion 31 has a substantially rectangular parallelepiped outer shape. The second insulating resin portion 31 is made of an organic resin containing an inorganic filler. The second wiring portion 32 includes a plurality of second columnar wirings 32B extending in a direction intersecting the first main surface 10A and a plurality of second wirings 32A extending in a direction parallel to the first main surface 10A. Each second wiring 32A is connected to each second columnar wiring 32B. Each second columnar wiring 32B has a substantially truncated cone shape. The diameter of each second columnar wiring 32B decreases toward the first positive direction X1. That is, the maximum dimension of each second columnar wiring 32B in a direction parallel to the first main surface 10A decreases toward the fourth wiring layer LN4.

[0123] The second wiring portion 32 extends in an arbitrary pattern inside the second insulating resin portion 31. The material of the second wiring portion 32 is the same as the material of the first wiring portion 12. That is, the volume fraction of Cu in the second wiring portion 32 is 50 vol % or more.

[0124] 14 , the second wiring layer LN2 has 21 second wiring external terminals 33. The material of each second wiring external terminal 33 is the same as the material of the second wiring portion 32. Of these, 10 second wiring external terminals 33 are located on the first negative direction X2 side with respect to the second wiring portion 32. The peripheral surfaces of the 10 second wiring external terminals 33 are covered with the second insulating resin portion 31. The 10 second wiring external terminals 33 are exposed on the first negative direction X2 side of the second insulating resin portion 31. These 10 second wiring external terminals 33 are connected to the first component external terminals 25 without any other intervening member.

[0125] The remaining eleven second wiring external terminals 33 are located on the first positive direction X1 side with respect to the second wiring portion 32. The eleven second wiring external terminals 33 are exposed on the first negative direction X2 side of the second insulating resin portion 31. Specifically, the eleven second wiring external terminals 33 protrude in the first positive direction X1 with respect to the second insulating resin portion 31. That is, the second wiring external terminals 33 protrude from the surface of the second insulating resin portion 31 facing the fourth wiring layer LN4. The peripheral surfaces of these eleven second wiring external terminals 33 are not covered with other members.

[0126] 14, as described above, the fourth layer L4 is composed only of the fourth wiring layer LN4. The fourth wiring layer LN4 has a fourth insulating resin portion 61, a fourth wiring portion 62, and a plurality of fourth wiring external terminals 63.

[0127] The fourth insulating resin portion 61 has a substantially rectangular parallelepiped outer shape. The fourth insulating resin portion 61 is made of an organic resin containing an inorganic filler. The fourth wiring portion 62 includes a plurality of fourth columnar wirings 62B extending in a direction intersecting the first main surface 10A and a plurality of fourth wirings 62A extending in a direction parallel to the first main surface 10A. Each fourth wiring 62A is connected to a corresponding fourth columnar wiring 62B. Each fourth columnar wiring 62B has a substantially truncated cone shape. The diameter of each fourth columnar wiring 62B decreases toward the first negative direction X2. That is, the maximum dimension of each fourth columnar wiring 62B in a direction parallel to the first main surface 10A decreases toward the second wiring layer LN2.

[0128] 14 , the fourth wiring layer LN4 has 20 fourth wiring external terminals 63. The material of each fourth wiring external terminal 63 is the same as the material of the fourth wiring portion 62. Of these, nine fourth wiring external terminals 63 are located on the first positive direction X1 side with respect to the fourth wiring portion 62. The peripheral surfaces of the nine fourth wiring external terminals 63 are covered with the second insulating resin portion 31. The nine fourth wiring external terminals 63 are exposed on the first positive direction X1 side of the fourth insulating resin portion 61.

[0129] The remaining eleven fourth wiring external terminals 63 are located on the first negative direction X2 side with respect to the fourth wiring portion 62. The eleven fourth wiring external terminals 63 are exposed on the first negative direction X2 side of the second insulating resin portion 31. Specifically, the eleven fourth wiring external terminals 63 protrude in the first negative direction X2 with respect to the fourth insulating resin portion 61. That is, the fourth wiring external terminals 63 protrude from the surface of the fourth insulating resin portion 61 facing the second wiring layer LN2. The peripheral surfaces of the eleven fourth wiring external terminals 63 are not covered with other members. The fourth wiring external terminals 63 are connected to the second wiring external terminals 33. The peripheral surfaces of the fourth wiring external terminals 63 and the second wiring external terminals 33 are not covered with other members. Therefore, a gap is formed between the second insulating resin portion 31 and the fourth insulating resin portion 61.

[0130] 14 , a gap is formed between the second insulating resin portion 31 and the fourth insulating resin portion 61. With this configuration, even if bending stress occurs to the entire semiconductor package 10, the stress can be dispersed by the gap. In other words, with this configuration, it is possible to prevent cracks and the like from occurring in the semiconductor package 10 due to bending stress occurring to the semiconductor package 10.

[0131] In the example shown in FIG. 14 , the maximum dimension of each second columnar wiring 32B in a direction parallel to the first main surface 10A decreases toward the fourth wiring layer LN4. The maximum dimension of each fourth columnar wiring 62B in a direction parallel to the first main surface 10A decreases toward the second wiring layer LN2. That is, the shapes of the second columnar wiring 32B and the fourth columnar wiring 62B are inverted in the direction along the first axis X. When the second wiring layer LN2 and the fourth wiring layer LN4 are manufactured using the same process, the second columnar wiring 32B and the fourth columnar wiring 62B have similar tapered shapes. On the other hand, when the second wiring layer LN2 and the fourth wiring layer LN4 are formed and then stacked on top of each other, the shapes of the columnar wirings can be inverted between the second wiring layer LN2 and the fourth wiring layer LN4. According to the above configuration, it is also possible to form each wiring layer in parallel. That is, by forming each wiring layer in parallel, the manufacturing time can be reduced.

[0132] In the second embodiment, the second component layer PT2 does not have to entirely cover the adjacent layers. In the example shown in Fig. 14, the semiconductor package 10 includes a fifth layer L5 stacked on the first positive direction X1 side of the fourth layer L4. The fifth layer L5 has a first portion P1 and a second portion P2.

[0133] The first portion P1 includes a second component layer PT2, four fifth wiring layers LN5, and a dummy portion DM. In the first portion P1, the fifth wiring layer LN5, which is a layer separate from the second component layer PT2, is embedded within the second component layer PT2.

[0134] The second component layer PT2 has a second sealing portion 41 and a plurality of second electronic components 42. The outer shape of the second sealing portion 41 is a substantially rectangular parallelepiped. The four fifth wiring layers LN5 described above are located inside the second sealing portion 41. That is, the fifth wiring layer LN5 is adjacent to the second sealing portion 41 or the second electronic components 42, which are part of the second component layer PT2, in a direction perpendicular to the first main surface 10A. The material of the second sealing portion 41 is a synthetic resin containing an inorganic filler. In the example shown in FIG. 14 , the inorganic filler is silica. That is, the second sealing portion 41 contains an inorganic material.

[0135] 14, the second component layer PT2 has four second electronic components 42. All of the second electronic components 42 are active components 42A. Each active component 42A is located inside the second sealing portion 41.

[0136] Two of the four second electronic components 42 are aligned in a direction parallel to the first main surface 10A. A fifth wiring layer LN5 is stacked on each of the surfaces of these two second electronic components 42 facing the first negative direction X2. Furthermore, a stack of six elements is formed on the surface of one active component 42A facing the first positive direction X1, in this order: a fifth wiring layer LN5, another second electronic component 42, a fifth wiring layer LN5, and another second electronic component 42. In this stack, adjacent fifth wiring layers LN5 and second electronic components 42 are electrically connected to each other. Note that the fifth wiring layers LN5 are not electrically connected to each other within the first portion P1.

[0137] Two of the three second electronic components 42 included in this laminate have four through wires 44. Specifically, of the three stacked second electronic components 42, the two second electronic components 42 closest to the first negative direction X2 have four through wires 44. The four through wires 44 are aligned in a direction parallel to the first main surface 10A. Each through wire 44 penetrates the second electronic component 42 in a direction perpendicular to the first main surface 10A. Each through wire 44 also penetrates the fifth wiring layer LN5 stacked on the first positive direction X1 side of the second electronic component 42 in a direction perpendicular to the first main surface 10A. The through wires 44 of each second electronic component 42 are connected to each other. That is, in the laminate, each through wire 44 electrically connects the fifth wiring layer LN5 located closest to the first negative direction X2 to the second electronic component 42 located closest to the first positive direction X1.

[0138] 14 , a dummy part DM is located on the first positive direction X1 side of one of the four second electronic components 42 that is not stacked. The dummy part DM directly covers the entire surface of the second electronic component 42 on the first positive direction X1 side. The dummy part DM is made of a thermally conductive synthetic resin. The dummy part DM can efficiently absorb heat from the second electronic component 42 and dissipate it to the outside.

[0139] Each fifth wiring layer LN5 has a fifth wiring portion 72 and a fifth insulating resin portion 71. Note that in FIG. 14 , the fifth wiring portion 72 and the fifth insulating resin portion 71 inside the fifth wiring layer LN5 are not shown. The fifth wiring portion 72 and the fifth insulating resin portion 71 have the same configuration as the first wiring layer LN1. That is, the outer shape of each fifth insulating resin portion 71 is approximately rectangular parallelepiped. However, the dimension of each fifth insulating resin portion 71 in a direction parallel to the first main surface 10A is smaller than the dimension of the first portion P1 in a direction parallel to the first main surface 10A. Furthermore, the dimension of each fifth insulating resin portion 71 in a direction perpendicular to the first main surface 10A is smaller than the dimension of the first portion P1 in a direction perpendicular to the first main surface 10A. Each fifth insulating resin portion 71 is made of a synthetic resin containing an inorganic filler.

[0140] Each fifth wiring portion 72 extends in an arbitrary pattern inside each fifth insulating resin portion 71. The material of each fifth wiring portion 72 is the same as the material of the first wiring portion 12. That is, the volume fraction of Cu in each fifth wiring portion 72 is 50 vol % or more.

[0141] The second portion P2 is located apart from the first portion P1 in a direction parallel to the first main surface 10A. The second portion P2 is composed of only a third component layer PT3. The third component layer PT3 has a third sealing portion 81 and a plurality of third electronic components 82.

[0142] The third sealing portion 81 has an outer shape of a substantially rectangular parallelepiped. The material of the third sealing portion 81 is a synthetic resin containing an inorganic filler. However, the third sealing portion 81 contains a different inorganic filler than the second sealing portion 41. The third sealing portion 81 contains a magnetic metal filler containing Fe element. In other words, the material of the second sealing portion 41 is different from the material of the third sealing portion 81. Note that "different materials" not only refers to cases where the second sealing portion 41 and the third sealing portion 81 have different compositions, but also includes cases where the particle size of the inorganic filler contained therein is different.

[0143] 14 , the third component layer PT3 has two third electronic components 82. Each third electronic component 82 is located inside the third sealing portion 81. All of the third electronic components 82 are passive components. The two third electronic components 82 are aligned in a direction parallel to the first main surface 10A.

[0144] As described above, the second component layer PT2 and the third component layer PT3 are stacked on the first component layer PT1 via the fourth wiring layer LN4 in a direction perpendicular to the first main surface 10A. The second component layer PT2 and the third component layer PT3 are also aligned on the fourth wiring layer LN4 in a direction parallel to the first main surface 10A. That is, the second component layer PT2 and the third component layer PT3 are located at the same position in the direction perpendicular to the first main surface 10A.

[0145] 14, the second component layer PT2 and the third component layer PT3 are located on the same layer in the direction perpendicular to the first main surface 10A. That is, the second component layer PT2 and the third component layer PT3 can be formed at the same time. That is, with this configuration, the manufacturing process is not complicated, and high-density mounting can be achieved inexpensively.

[0146] 14, the second sealing portion 41 and the third sealing portion 81 are made of different materials. The material of the second sealing portion 41 can be selected to match the active components. The material of the third sealing portion 81 can be selected to match the passive components. In other words, with the above configuration, an appropriate material can be selected for each electronic component. In particular, by using a magnetic metal filler containing Fe element in the third sealing portion 81 as described above, the inductance of the passive components can be improved, noise emission can be suppressed, and heat dissipation can be enhanced.

[0147] 14, the second columnar wiring 32B and the fourth columnar wiring 62B may have the same shape. That is, the diameter of both the second columnar wiring 32B and the fourth columnar wiring 62B may become smaller in the first negative direction X2, or may become smaller in the first positive direction X1.

[0148] 14, the material of the second sealing portion 41 may be the same as the material of the third sealing portion 81. In the example shown in Fig. 14, the first portion P1 does not have to have the fifth wiring layer LN5.

[0149] 14, the first portion P1 does not necessarily have to have the dummy portion DM. Alternatively, another component layer may have the dummy portion DM. This also applies to the component layers of the first and second embodiments.

[0150] 14 , a gap does not necessarily have to be formed between the second insulating resin portion 31 and the fourth insulating resin portion 61. In the example shown in FIG. 15 , a portion of the second wiring external terminal 33 is exposed from the surface of the second insulating resin portion 31 facing the fourth wiring layer LN4. The peripheral surface of the second wiring external terminal 33 is covered by the second insulating resin portion 31. Furthermore, a portion of the fourth wiring external terminal 63 is exposed from the surface of the fourth insulating resin portion 61 facing the second wiring layer LN2. The peripheral surface of the fourth wiring external terminal 63 is covered by the fourth insulating resin portion 61. The fourth wiring external terminal 63 is connected to the second wiring external terminal 33. The peripheral surfaces of the fourth wiring external terminal 63 and the second wiring external terminal 33 are covered by the second insulating resin portion 31 and the fourth insulating resin portion 61, respectively. That is, the peripheral surfaces of the fourth wiring external terminal 63 and the second wiring external terminal 33 are covered by synthetic resin. In the example shown in FIG. 15, the second insulating resin portion 31 and the fourth insulating resin portion 61 are in contact with each other.

[0151] 15, the second wiring layer LN2 and the fourth wiring layer LN4 are connected not only by the external terminals but also by synthetic resin, thereby improving the adhesion between the second wiring layer LN2 and the fourth wiring layer LN4.

[0152] 15 , the synthetic resin covering the second wiring external terminals 33 and the peripheral surfaces of the second wiring external terminals 33 is not limited to the second insulating resin portion 31 and the fourth insulating resin portion 61. For example, the second wiring external terminals 33 and the peripheral surfaces of the second wiring external terminals 33 may be covered with a synthetic resin such as underfill.

[0153] 13, the third active component 42A3 may be located on the first negative direction X2 side relative to the first active component 42A1 and the second active component 42A2. For example, in the example shown in FIG. 15, the third active component 42A3 is stacked on the fourth wiring layer LN4 via the fifth wiring layer LN5. The first active component 42A1 is stacked on the first positive direction X1 side relative to the third active component 42A3 via the fifth wiring layer LN5. The second active component 42A2 is stacked on the first positive direction X1 side relative to the third active component 42A3 via the fifth wiring layer LN5. The first active component 42A1 and the second active component 42A2 are aligned in a direction parallel to the first main surface 10A. That is, as in the example shown in FIG. 15, a plurality of active components 42A may be stacked on one active component 42A in a direction parallel to the first main surface 10A.

[0154] In the second embodiment, the passive component 22B may include a through wiring 27. In the example shown in FIG. 15 , at least one of the first electronic components 22 is a passive component 22B. The passive component 22B includes a through wiring 27. The through wiring 27 penetrates the passive component 22B in a direction perpendicular to the first main surface 10A. The through wiring 27 is substantially cylindrical. The maximum dimension of the through wiring 27 in a direction parallel to the first main surface 10A is smaller than the maximum dimension of the first via wiring 24 in a direction parallel to the first main surface 10A. Furthermore, the maximum dimension of the through wiring 27 in the passive component 22B in a direction parallel to the first main surface 10A is larger than the maximum dimension of the through wiring 23 in the active component 22A in a direction parallel to the first main surface 10A.

[0155] 15 , the maximum dimension of the through wiring 27 in the passive component 22B in the direction parallel to the first main surface 10A may be the same as or larger than the maximum dimension of the first via wiring 24 in the direction parallel to the first main surface 10A. Also, the maximum dimension of the through wiring 27 in the passive component 22B in the direction parallel to the first main surface 10A may be the same as or smaller than the maximum dimension of the through wiring 23 in the active component 22A in the direction parallel to the first main surface 10A.

[0156] In the first embodiment, the connection terminals 13 of the first electronic component 12 may have a multi-layer structure. For example, the connection terminals 13 may include a layer whose main component is Ni, Sn, Au, or the like. However, to achieve the effect of (1-4) above, it is preferable that the volume fraction of Cu on the outer surface of each connection terminal 13 is 50 vol % or more. Alternatively, the volume fraction of Cu on the outer surface of the connection terminals 13 may be less than 50 vol %.

[0157] In the first embodiment, the volume fraction of Cu in the first wiring portion 22 may be less than 50 vol %. Furthermore, Ag, Al, and Au may be used instead of Cu in the first wiring portion 22. This also applies to the wiring portions of each wiring layer. The same also applies to the wiring portions of each wiring layer in the second embodiment.

[0158] In the first embodiment, the shape of the first columnar wiring 22B is not limited to a truncated cone shape. For example, it may be a cylindrical shape or a rectangular pillar shape. This also applies to the other columnar wirings.

[0159] In the first embodiment, the first component layer only needs to include at least one active component, and the semiconductor package 10 only needs to include at least one passive component and one active component. This also applies to the second embodiment.

[0160] In the first embodiment, it is sufficient that the first component layer has at least one first via wiring 14. Furthermore, as long as the first component layer has a first via wiring 14, the other component layers do not need to have via wirings. This also applies to the component layers of the second embodiment.

[0161] In the first embodiment, the maximum dimension of the passive component 12B in the direction perpendicular to the first main surface 10A may be the same as or smaller than the maximum dimension of the active component 12A in the direction perpendicular to the first main surface 10A.

[0162] In the first embodiment, the volume fraction of the inorganic material in the passive component 12B is not limited to the example in the first embodiment. That is, the volume fraction of the inorganic material in the passive component 12B may be less than 50 vol %. This also applies to the other passive components. The same also applies to the passive component 42B in the second embodiment.

[0163] In the first embodiment, the protrusion amount of the connection terminal 13 may be smaller than the protrusion amount of the inner terminal 13A. Furthermore, the inner terminal 13A may protrude in the first positive direction X1 beyond the surface of the component body 12M on the first positive direction X1 side, or may be recessed in the first negative direction X2.

[0164] In the second embodiment, the end of the through wiring 23 on the first positive direction X1 side may be connected to the first via wiring 24. That is, the through wiring 23 may be connected directly to the first via wiring 24 without going through the first wiring portion 12. Furthermore, when the first positive direction X1 side of the first electronic component 22 faces the first component external terminal 25, the end of the through wiring 23 on the first positive direction X1 side may be connected to the first component external terminal 25. Furthermore, in the second embodiment, the first electronic component 22 does not have to have the through wiring 23. Furthermore, the second electronic component 42 may have the through wiring.

[0165] In the second embodiment, the dimensional relationship between the through wiring 23 and the first via wiring 24 is not limited to that in the second embodiment. The maximum dimension of the through wiring 23 in the direction parallel to the first main surface 10A may be the same as or larger than the maximum dimension of the first via wiring 24 in the direction parallel to the first main surface 10A.

[0166] In the second embodiment, as long as the first wiring layer LN1 is adjacent to the first component layer PT1 in the direction perpendicular to the first main surface 10A, the position of the first wiring layer LN1 is not limited to the example of the second embodiment. For example, the first wiring layer LN1 may be stacked on the first negative direction X2 side with respect to the first electronic component 22.

[0167] In the second embodiment, the volume ratio of the inorganic material in the entire semiconductor package 10 may be less than 90 vol %. In the second embodiment, the dimensional relationship between the active component 42A and the passive component 42B in the second electronic component 42 is not limited to the example in the second embodiment. For example, the maximum dimension of the passive component 42B in the direction perpendicular to the first main surface 10A may be equal to or smaller than the sum of the maximum dimension of the first active component 42A1 in the direction perpendicular to the first main surface 10A and the maximum dimension of the second active component 42A2 in the direction perpendicular to the first main surface 10A.

[0168] In the second embodiment, another wiring layer may be located between the first layer L1 and the second layer L2. That is, another member may be interposed between the first component external terminal 25 and the second component external terminal 43.

[0169] <Supplementary Notes> Technical concepts that can be derived from the above-described embodiments and modified examples are described below. [1] A semiconductor package having a passive component and an active component, comprising: a first component layer having a first main surface and a second main surface opposite to the first main surface; and a first wiring layer adjacent to the first component layer in a direction perpendicular to the first main surface, the first component layer having a first sealing portion containing an inorganic material, at least one of the active component located inside the first sealing portion, and a plurality of first via wirings that extend inside the first sealing portion in a direction intersecting the first main surface and have ends exposed from the first sealing portion at the first main surface, the first wiring layer having a first insulating resin portion and a first wiring portion extending inside the first insulating resin portion,

[0170] [2] The semiconductor package according to [1], wherein the first wiring layer is laminated on the first main surface or the second main surface of the first component layer. [3] The semiconductor package according to [2], wherein the first wiring layer is laminated on the first main surface of the first component layer, a first end of the first via wiring is connected to the active component, and a second end of the first via wiring is connected to the first wiring portion in the first wiring layer.

[0171] [4] The semiconductor package described in [2] or [3], wherein the first wiring layer has a first wiring external terminal on a surface facing away from the first component layer in a direction perpendicular to the first main surface, and the first wiring external terminal is provided with a land portion for connecting a motherboard mounted on the first wiring layer.

[0172] [5] A semiconductor package according to [2] or [3], comprising a second wiring layer stacked on the first wiring layer in a direction perpendicular to the first main surface, the second wiring layer comprising a second insulating resin portion and a second wiring portion extending inside the second insulating resin portion, the first wiring layer having a first wiring external terminal protruding from the surface of the first insulating resin portion facing the second wiring layer, the second wiring layer having a second wiring external terminal protruding from the surface of the second insulating resin portion facing the first wiring layer and connected to the first wiring external terminal, and a gap occurring between the first insulating resin portion and the second insulating resin portion.

[0173] [6] A semiconductor package according to [2] or [3], comprising a second wiring layer stacked on the first wiring layer in a direction perpendicular to the first main surface, the second wiring layer comprising a second insulating resin portion and a second wiring portion extending inside the second insulating resin portion, the first wiring layer having a first wiring external terminal exposed from the surface of the first insulating resin portion facing the second wiring layer, the second wiring layer having a second wiring external terminal exposed from the surface of the second insulating resin portion facing the first wiring layer and connected to the first wiring external terminal, and the peripheral surfaces of the first wiring external terminal and the second wiring external terminal are covered with a synthetic resin.

[0174] [7] The semiconductor package described in [5] or [6], wherein the first wiring portion has a first pillar wiring extending in a direction intersecting the first main surface, and a first wiring connected to the first pillar wiring and extending in a direction parallel to the first main surface, and the first pillar wiring has a maximum dimension parallel to the first main surface that decreases toward the second wiring layer, and the second wiring portion has a second pillar wiring extending in a direction intersecting the first main surface, and a second wiring connected to the second pillar wiring and extending in a direction parallel to the first main surface, and the second pillar wiring has a maximum dimension parallel to the first main surface that decreases toward the first wiring layer.

[0175] [8] The semiconductor package according to any one of [1] to [7], wherein the first insulating resin portion is an organic resin. [9] The semiconductor package according to any one of [1] to [8], wherein the volume fraction of Cu is 50 vol % or more on the outer surface of the connection terminal of the active component located inside the first sealing portion, and the volume fraction of Cu is 50 vol % or more in the first wiring portion.

[0176]

[10] A semiconductor package described in any one of [1] to [9], wherein one or more selected from the active components located inside the first sealing portion have through wiring that penetrates the active component in a direction perpendicular to the first main surface, and the through wiring is connected to the first wiring portion or the first via wiring.

[0177]

[11] The semiconductor package according to

[10] , wherein the maximum dimension of the through wiring in a direction parallel to the first main surface is smaller than the maximum dimension of the first via wiring in a direction parallel to the first main surface.

[12] The semiconductor package according to any one of [1] to

[11] , wherein the passive component includes an inorganic material, and the volume fraction of the inorganic material in the passive component is 50 vol% or more.

[0178]

[13] A semiconductor package according to

[12] , wherein the volume fraction of the inorganic material in the passive components is 80 vol% or more, and the volume fraction of the inorganic material in the entire semiconductor package is 90 vol% or more.

[0179]

[14] A semiconductor package described in any one of [1] to

[13] , wherein the maximum dimension of the passive component in a direction perpendicular to the first main surface is greater than the maximum dimension of the active component in a direction perpendicular to the first main surface.

[0180]

[15] A semiconductor package according to any one of [1] to

[14] , comprising a second component layer stacked on the first component layer in a direction perpendicular to the first main surface, the second component layer having a second sealing portion containing an inorganic material, at least one of the active components located inside the second sealing portion, and a second component external terminal exposed from a surface of the second sealing portion facing the first component layer, the first component layer having a first component external terminal exposed from a surface of the first sealing portion facing the second component layer, the first component external terminal being connected to the second component external terminal without any other member therebetween.

[0181]

[16] A semiconductor package according to any one of [1] to

[15] , comprising a first active component, a second active component, and a third active component stacked on the first component layer in a direction perpendicular to the first main surface, wherein the first active component and the second active component are arranged side by side in a direction parallel to the first main surface without any other electronic components in between, and the third active component is stacked on the first active component and the second active component in a direction perpendicular to the first main surface without any other electronic components in between, and when viewed from a direction perpendicular to the first main surface, the third active component overlaps the first active component and the second active component.

[0182]

[17] A semiconductor package according to any one of [1] to

[16] , comprising a first active component, a second active component, and at least one of the passive components stacked on the first component layer in a direction perpendicular to the first main surface, wherein the first active component and the second active component are stacked on the first component layer in a direction perpendicular to the first main surface without any other electronic components in between, and wherein the maximum dimension of the passive component in the direction perpendicular to the first main surface is greater than the sum of the maximum dimension of the first active component in the direction perpendicular to the first main surface and the maximum dimension of the second active component in the direction perpendicular to the first main surface.

[0183]

[18] A semiconductor package according to any one of [1] to

[17] , comprising a second component layer and a third component layer stacked on the first component layer in a direction perpendicular to the first main surface, the second component layer having a second sealing portion containing an inorganic material and at least one of the active components located inside the second sealing portion, the third component layer having a third sealing portion containing an inorganic material and at least one of the passive components located inside the third sealing portion, and the second component layer and the third component layer being located at the same position in the direction perpendicular to the first main surface.

[0184]

[19] The semiconductor package according to

[18] , wherein the material of the second sealing portion is different from the material of the third sealing portion.

[20] The semiconductor package according to any one of [1] to

[19] , wherein the active component located inside the first sealing portion has a component body, the connection terminal protruding from the component body, and an internal terminal exposed from the component body on the opposite side from the connection terminal in a direction perpendicular to the first main surface, and the protrusion amount of the connection terminal is greater than the protrusion amount of the internal terminal.

[0185] L1: First layer L2: Second layer 10: Semiconductor package 10A: First main surface 10B: Second main surface 11: First sealing portion 12A: Active component 12B: Passive component 13: Connection terminal 14: First via wiring 21: First insulating resin portion 22: First wiring portion

Claims

1. A semiconductor package having passive components and active components, comprising: a first component layer having a first main surface and a second main surface opposite to the first main surface; and a first wiring layer adjacent to the first component layer in a direction perpendicular to the first main surface. The first component layer includes: a first encapsulation portion containing an inorganic material; at least one of the active components located inside the first encapsulation portion; and a plurality of first via wirings extending in a direction intersecting the first main surface inside the first encapsulation portion and having ends exposed from the first encapsulation portion on the first main surface. The first wiring layer includes: a first insulating resin portion; and a first wiring portion extending inside the first insulating resin portion. Connection terminals of the active components are exposed from the first encapsulation portion on the second main surface side of the first encapsulation portion.

2. The semiconductor package according to claim 1, wherein the first wiring layer is laminated on the first main surface or the second main surface of the first component layer.

3. The semiconductor package according to claim 2, wherein the first wiring layer is laminated on the first main surface of the first component layer, a first end of the first via wiring is connected to the active component, and a second end of the first via wiring is connected to the first wiring portion inside the first wiring layer.

4. The semiconductor package according to claim 2 or claim 3, wherein the first wiring layer has a first wiring external terminal on a surface facing the side opposite to the first component layer in a direction perpendicular to the first main surface, and a land portion for connecting a mother board mounted on the first wiring layer is provided on the first wiring external terminal.

5. The semiconductor package according to claim 2 or claim 3, further comprising a second wiring layer laminated on the first wiring layer in a direction perpendicular to the first main surface. The second wiring layer includes: a second insulating resin portion; and a second wiring portion extending inside the second insulating resin portion. The first wiring layer has a first wiring external terminal protruding from a surface of the first insulating resin portion on the second wiring layer side. The second wiring layer has a second wiring external terminal protruding from a surface of the second insulating resin portion on the first wiring layer side and connected to the first wiring external terminal. A gap is formed between the first insulating resin portion and the second insulating resin portion.

6. The semiconductor package according to claim 2 or claim 3, further comprising a second wiring layer laminated with respect to the first wiring layer in a direction orthogonal to the first main surface, wherein the second wiring layer includes a second insulating resin portion and a second wiring portion extending inside the second insulating resin portion, the first wiring layer has a first wiring external terminal exposed from a surface of the first insulating resin portion on the second wiring layer side, the second wiring layer has a second wiring external terminal exposed from a surface of the second insulating resin portion on the first wiring layer side and connected to the first wiring external terminal, and peripheral surfaces of the first wiring external terminal and the second wiring external terminal are covered with a synthetic resin.

7. The semiconductor package according to claim 5 or claim 6, wherein the first wiring portion has a first columnar wiring extending in a direction intersecting the first main surface and a first wiring connected to the first columnar wiring and extending in a direction parallel to the first main surface, and the maximum dimension of the first columnar wiring in the direction parallel to the first main surface becomes smaller as it approaches the second wiring layer; the second wiring portion has a second columnar wiring extending in a direction intersecting the first main surface and a second wiring connected to the second columnar wiring and extending in a direction parallel to the first main surface, and the maximum dimension of the second columnar wiring in the direction parallel to the first main surface becomes smaller as it approaches the first wiring layer.

8. The semiconductor package according to any one of claims 1 to 7, wherein the first insulating resin portion is an organic resin.

9. The semiconductor package according to any one of claims 1 to 8, wherein the volume fraction of Cu on the outer surface of the connection terminal of the active component located inside the first encapsulation portion is 50 vol% or more, and the volume fraction of Cu in the first wiring portion is 50 vol% or more.

10. The semiconductor package according to any one of claims 1 to 9, wherein one or more selected from the active components located inside the first encapsulation portion include a through-wiring penetrating the active component in a direction orthogonal to the first main surface, and the through-wiring is connected to the first wiring portion or the first via wiring.

11. The semiconductor package according to claim 10, wherein the maximum dimension of the through-wiring in the direction parallel to the first main surface is smaller than the maximum dimension of the first via wiring in the direction parallel to the first main surface.

12. The passive component includes an inorganic material, and the volume fraction of the inorganic material in the passive component is 50 vol% or more. The semiconductor package according to any one of claims 1 to 11.

13. The volume fraction of the inorganic material in the passive component is 80 vol% or more, and the volume fraction of the inorganic material in the entire semiconductor package is 90 vol% or more. The semiconductor package according to claim 12.

14. The maximum dimension in the direction orthogonal to the first main surface of the passive component is larger than the maximum dimension in the direction orthogonal to the first main surface of the active component. The semiconductor package according to any one of claims 1 to 13.

15. A second component layer laminated with respect to the first component layer in the direction orthogonal to the first main surface is provided. The second component layer includes a second sealing portion containing an inorganic material, at least one of the active components located inside the second sealing portion, and a second component external terminal exposed from a surface of the second sealing portion on the first component layer side. The first component layer has a first component external terminal exposed from a surface of the first sealing portion on the second component layer side. The first component external terminal is connected to the second component external terminal without an intervening member therebetween. The semiconductor package according to any one of claims 1 to 14.

16. The first component layer is provided with a first active component, a second active component, and a third active component laminated in the direction orthogonal to the first main surface. The first active component and the second active component are arranged side by side in the direction parallel to the first main surface without an intervening other electronic component therebetween. The third active component is laminated with respect to the first active component and the second active component in the direction orthogonal to the first main surface without an intervening other electronic component therebetween. When viewed through from the direction orthogonal to the first main surface, the third active component overlaps the first active component and the second active component. The semiconductor package according to any one of claims 1 to 15.

17. A semiconductor package according to any one of claims 1 to 16, comprising a first active component, a second active component, and at least one of the passive components stacked on the first component layer in a direction orthogonal to the first main surface, wherein the first active component and the second active component are stacked on the first component layer in a direction orthogonal to the first main surface without any other electronic components therebetween, and a maximum dimension of the passive component in a direction orthogonal to the first main surface is larger than a sum of a maximum dimension of the first active component in a direction orthogonal to the first main surface and a maximum dimension of the second active component in a direction orthogonal to the first main surface.

18. A semiconductor package according to any one of claims 1 to 17, comprising a second component layer and a third component layer stacked on the first component layer in a direction orthogonal to the first main surface, wherein the second component layer has a second sealing portion containing an inorganic material and at least one of the active components located inside the second sealing portion, and the third component layer has a third sealing portion containing an inorganic material and at least one of the passive components located inside the third sealing portion, and the second component layer and the third component layer are located at the same position in a direction orthogonal to the first main surface.

19. A semiconductor package according to claim 18, wherein a material of the second sealing portion is different from a material of the third sealing portion.

20. A semiconductor package according to any one of claims 1 to 19, wherein the active component located inside the first sealing portion has a component body, a connection terminal protruding from the component body, and an internal side terminal exposed from the component body on a side opposite to the connection terminal in a direction orthogonal to the first main surface, and a protruding amount of the connection terminal is larger than a protruding amount of the internal side terminal.