Multilayer ceramic capacitor

Abstract

The present invention provides a highly reliable multilayer ceramic capacitor (1) in which occurrence of a crack can be suppressed. The multilayer ceramic capacitor (1) comprises: a multilayer body (2) which includes a plurality of dielectric layers (30) and a plurality of internal electrode layers (40) stacked upon each other; and an external electrode (50) which is provided on a first end surface (8) and a second end surface (9), and is connected to the internal electrode layers (40). The external electrode (50) comprises a base electrode layer (53) that has a recessed part (70) which is formed on a surface (60), an organic layer (54) that is formed on the base electrode layer (53), and a plating layer (55) that is formed on the organic layer (54). A gap (80) is formed between the plating layer (55) and the organic layer (54), which are formed on the recessed part (70) of the base electrode layer (53).

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, with the miniaturization of electronic devices, there has been a demand for miniaturization of electronic components having a laminated structure (hereinafter also referred to as multilayer ceramic capacitors) mounted on circuit boards. As described in Patent Document 1, for example, a multilayer ceramic capacitor is manufactured by laminating a plurality of dielectric ceramic sheets via internal electrode layers, and then forming external electrodes and plating films of nickel, copper, solder, tin, etc. on both end surfaces of the resulting multilayer ceramic capacitor.

[0003] Japanese Patent Application Publication No. 8-191032

[0004] However, in the multilayer ceramic capacitor of Patent Document 1, when subjected to an external impact, the substrate warps, and the bending stress of the substrate propagates to the multilayer ceramic capacitor via the plating film and external electrodes, causing cracks inside the multilayer ceramic capacitor. When cracks that occur in the multilayer ceramic capacitor reach the internal electrode layers, moisture flows in from the outside through the cracks, increasing the incidence of short circuits and causing peeling of the external electrodes due to the cracks, which causes problems in reliability.

[0005] SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a highly reliable multilayer ceramic capacitor that can suppress cracks from occurring inside the multilayer ceramic capacitor.

[0006] The present inventors have discovered a multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate having first and second main surfaces opposing each other in the lamination direction, first side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction; and external electrodes provided on the first end surfaces and the second end surfaces and connected to the internal electrode layers, the external electrodes comprising a base electrode layer having a recess formed on its surface, an organic layer formed on the base electrode layer, and a plating layer formed on the organic layer, wherein a gap is formed between the organic layer formed on the recess of the base electrode layer and the plating layer, and have completed the present invention.

[0007] According to the present invention, it is possible to provide a highly reliable multilayer ceramic capacitor that can suppress cracks from occurring inside the multilayer ceramic capacitor.

[0008] FIG. 1 is a diagram showing a multilayer ceramic capacitor of the present invention. FIG. 2 is a cross-sectional view taken along line 200-200 of FIG. 1. FIG. 3 is a cross-sectional view taken along line 201-201 of FIG. 1. FIG. 4A is a diagram showing an example of a floating internal electrode layer. FIG. 4B is a diagram showing an example of a floating internal electrode layer. FIG. 4C is a diagram showing an example of a floating internal electrode layer. FIG. 5 is an enlarged view of a portion of FIG. 2. FIG. 6 is a table showing the results of Experimental Example 1. FIG. 7 is a table showing the results of Experimental Example 2. FIG. 8 is a table showing the results of Experimental Example 3.

[0009] (Multilayer Ceramic Capacitor) Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a multilayer ceramic capacitor 1 according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line 200-200 of FIG. 1. FIG. 3 is a cross-sectional view taken along line 201-201 of FIG. 1. As shown in FIG. 1, the multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes 50. The external electrodes 50 include a first external electrode 51 and a second external electrode 52.

[0010] (Laminate) As shown in Fig. 2, the laminate 2 includes a plurality of laminated dielectric layers 30 and a plurality of laminated internal electrode layers 40. As shown in Fig. 1, the direction in which the dielectric layers 30 and the internal electrode layers 40 are stacked is called the stacking direction T. The surfaces of the laminate 2 facing the stacking direction T are called the first main surface 4 and the second main surface 5. The surfaces of the laminate 2 facing the width direction W perpendicular to the stacking direction T are called the first side surface 6 and the second side surface 7. The surfaces of the laminate 2 facing the length direction L perpendicular to the stacking direction T and the width direction W are called the first end face 8 and the second end face 9.

[0011] (Laminate) The shape of the laminate 2 is approximately a rectangular parallelepiped. A portion where three surfaces of the laminate 2 intersect is called a corner. A portion where two surfaces of the laminate 2 intersect is called a ridge. The corners and ridges are preferably rounded. Some or all of the main surfaces, side surfaces, and end surfaces may have irregularities formed thereon.

[0012] (Ceramic Material) The material of the dielectric layer 30 is a ceramic material. An example of the ceramic material is a dielectric ceramic composed of a main component such as barium titanate, calcium titanate, strontium titanate, or calcium zirconate. The dielectric ceramic may be one in which a secondary component is added to the above-mentioned main component. Examples of the secondary component include a manganese compound, an iron compound, a chromium compound, a cobalt compound, and a nickel compound.

[0013] When a piezoelectric ceramic is used as the material for the laminate, the multilayer ceramic capacitor functions as a ceramic piezoelectric element. An example of the piezoelectric ceramic material is lead zirconate titanate (PZT) ceramic material.

[0014] When a semiconducting ceramic is used as the material for the laminate, the multilayer ceramic capacitor functions as a thermistor element. An example of a semiconducting ceramic material is a spinel-based ceramic material.

[0015] When a magnetic ceramic is used as the laminate material, the multilayer ceramic capacitor functions as an inductor element. When a multilayer ceramic capacitor functions as an inductor element, the internal electrode layers become coiled conductors. An example of a magnetic ceramic material is a ferrite ceramic material.

[0016] The preferred thickness of the dielectric layer 30 is 0.5 μm or more and 10 μm or less.

[0017] 2, the laminate 2 can be divided into an effective layer portion 10 and an outer layer portion 12 in a stacking direction T, which is a direction connecting the first main surface 4 and the second main surface 5. The effective layer portion 10 is a portion where the internal electrode layers 40 face each other.

[0018] The outer layer portion 12 includes a first outer layer portion 13 and a second outer layer portion 14. The first outer layer portion 13 is a portion between the first main surface 4 and the internal electrode layer 40 closest to the first main surface 4. The second outer layer portion 14 is a portion between the second main surface 5 and the internal electrode layer 40 closest to the second main surface 5.

[0019] The first outer layer portion 13 is located on the first main surface 4 side of the laminate 2. The first outer layer portion 13 is an assembly of multiple dielectric layers 30 located between the first main surface 4 and the internal electrode layer 40 closest to the first main surface 4.

[0020] The second outer layer portion 14 is located on the second main surface 5 side of the laminate 2. The second outer layer portion 14 is an assembly of a plurality of dielectric layers 30 located between the second main surface 5 and the internal electrode layer 40 closest to the second main surface 5.

[0021] The effective layer portion 10 is a region sandwiched between the first outer layer portion 13 and the second outer layer portion 14 .

[0022] (Dimensions of Laminate) The dimensions of the laminate 2 are not particularly limited. The preferred length of the laminate 2 in the longitudinal direction L is 0.2 mm or more and 10 mm or less. The preferred length of the laminate 2 in the width direction W is 0.1 mm or more and 10 mm or less. The preferred length of the laminate 2 in the stacking direction T is 0.1 mm or more and 5 mm or less.

[0023] (L Gap) As shown in Fig. 2, the laminate 2 can be divided into a counter electrode portion 20 and an end portion 23 in the longitudinal direction L. The counter electrode portion 20 is a portion where the first internal electrode layer 41 and the second internal electrode layer 42 face each other.

[0024] The end portion 23 includes a first end portion 24 and a second end portion 25. The end surfaces of the opposing electrode portion 20 in the longitudinal direction L are called opposing electrode portion end faces 21. The first end portion 24 is the portion between the opposing electrode portion end face 21 on the first end face 8 side and the first end face 8. The second end portion 25 is the portion between the opposing electrode portion end face 21 on the second end face 9 side and the second end face 9. The end portion 23 is also called the L gap.

[0025] 3, the laminate 2 can be divided into a counter electrode portion 20 and a side portion 26 in the width direction W. The counter electrode portion 20 is a portion where the first internal electrode layer 41 and the second internal electrode layer 42 face each other.

[0026] The side portion 26 includes a first side portion 27 and a second side portion 28. The end surfaces of the opposing electrode portion 20 in the width direction W are called opposing electrode portion side surfaces 22. The first side portion 27 is the portion between the opposing electrode portion side surface 22 on the first side surface 6 side and the first side surface 6. The second side portion 28 is the portion between the opposing electrode portion side surface 22 on the second side surface 7 side and the second side surface 7. The side portion 26 is also called a W gap.

[0027] (Internal Electrode Layers) The internal electrode layers 40 include a plurality of first internal electrode layers 41 and a plurality of second internal electrode layers 42. As shown in Fig. 2 , the first internal electrode layers 41 are exposed at the first end face 8. The second internal electrode layers 42 are exposed at the second end face 9.

[0028] The first internal electrode layer 41 has, in the longitudinal direction L, a first opposing electrode portion 43 and a first lead electrode portion 44. The first opposing electrode portion 43 is a portion of the first internal electrode layer 41 that faces the second internal electrode layer 42. The first lead electrode portion 44 is a portion of the first internal electrode layer 41 that is led out from the first opposing electrode portion 43 to the first end face 8.

[0029] The second internal electrode layer 42 has a second opposing electrode portion 45 and a second lead electrode portion 46 in the longitudinal direction L. The second opposing electrode portion 45 is a portion of the second internal electrode layer 42 that faces the first internal electrode layer 41. The second lead electrode portion 46 is a portion of the second internal electrode layer 42 that is led from the second opposing electrode portion 45 to the second end face 9.

[0030] The shapes of the first opposing electrode portion 43 of the first internal electrode layer 41, the second opposing electrode portion 45 of the second internal electrode layer 42, the first lead electrode portion 44 of the first internal electrode layer 41, and the second lead electrode portion 46 of the second internal electrode layer 42 are not particularly limited. A preferred shape of the first opposing electrode portion 43 of the first internal electrode layer 41, the second opposing electrode portion 45 of the second internal electrode layer 42, the first lead electrode portion 44 of the first internal electrode layer 41, and the second lead electrode portion 46 of the second internal electrode layer 42 is rectangular. However, the corners may be rounded or may be formed obliquely (tapered). Furthermore, the tapered shape may be tapered in either direction.

[0031] The width in the width direction W of the first opposing electrode portion 43 of the first internal electrode layer 41 and the width of the first lead electrode portion 44 of the first internal electrode layer 41 may be the same, or one of them may be formed to have a narrower width. Similarly, the width of the second opposing electrode portion 45 of the second internal electrode layer 42 and the width of the second lead electrode portion 46 of the second internal electrode layer 42 may be the same, or one of them may be formed to have a narrower width.

[0032] (Floating Internal Electrode Layer) The floating internal electrode layer 47 will be described with reference to Figures 4A to 4C. The floating internal electrode layer 47 is an internal electrode layer 40 that is not drawn to either the first end face 8 or the second end face 9. Figures 4A to 4C are views corresponding to the 200-200 cross-sectional view in Figure 1. However, Figures 4A to 4C do not show the external electrode 50.

[0033] 4A to 4C , a floating internal electrode layer 47 may be provided in the first internal electrode layer 41 and the second internal electrode layer 42. By providing the floating internal electrode layer 47, the internal electrode layer 40 may have a structure in which the first opposing electrode portion 43 of the first internal electrode layer 41 or the second opposing electrode portion 45 of the second internal electrode layer 42 is divided into a plurality of portions.

[0034] 4A, the first internal electrode layer 41 and the second internal electrode layer 42 are provided in the same layer. A floating internal electrode layer 47 is provided between the layer on which the first internal electrode layer 41 and the second internal electrode layer 42 are provided and another layer on which the first internal electrode layer 41 and the second internal electrode layer 42 are formed.

[0035] In the example shown in FIG. 4B, a floating internal electrode layer 47 is provided on each of the layer on which the first internal electrode layer 41 is provided and the layer on which the second internal electrode layer 42 is provided.

[0036] 4C , the first internal electrode layer 41 and the second internal electrode layer 42 are provided in the same layer. A floating internal electrode layer 47 is provided in the layer on which the first internal electrode layer 41 and the second internal electrode layer 42 are provided. In addition, the floating internal electrode layer 47 is provided between the layer on which the first internal electrode layer 41 and the second internal electrode layer 42 are provided and another layer on which the first internal electrode layer 41 and the second internal electrode layer 42 are formed.

[0037] 4C, the floating internal electrode layer 47 is not limited to being provided in two consecutive rows in the same layer in the length direction L. It goes without saying that it may have a structure in which, for example, three consecutive rows, four consecutive rows, five consecutive rows, or more than five consecutive rows.

[0038] 4A to 4C , by providing the floating internal electrode layer 47 and dividing the opposing electrode portion into a plurality of parts, a plurality of capacitor components are formed between the opposing internal electrode layers 40, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component is reduced, and the multilayer ceramic capacitor 1 can be made to withstand a high voltage.

[0039] (Material of Internal Electrode Layer) Examples of materials for the internal electrode layers 40 include appropriate conductive materials such as metals such as nickel, copper, silver, palladium, and gold, or alloys containing at least one of these metals, such as a silver-palladium alloy.

[0040] In the multilayer ceramic capacitor 1 of this embodiment, capacitance is formed by opposing portions of the internal electrode layers 40 facing each other via the dielectric layer 30. This capacitance is what gives rise to the characteristics of the capacitor.

[0041] The thickness of the internal electrode layer 40 is, for example, 0.2 μm or more and 2.0 μm or less.

[0042] (External Electrode) The external electrode 50 will be described. The external electrode 50 includes a first external electrode 51 and a second external electrode 52. The first external electrode 51 is connected to the first internal electrode layer 41. A main portion of the first external electrode 51 is disposed on the first end face 8. The first external electrode 51 may also be disposed on a portion of the first main surface 4, a portion of the second main surface 5, a portion of the first side surface 6, and a portion of the second side surface 7. In this embodiment, the first external electrode 51 is formed to extend from the first end face 8 to a portion of the first main surface 4, a portion of the second main surface 5, a portion of the first side surface 6, and a portion of the second side surface 7.

[0043] The second external electrode 52 is connected to the second internal electrode layer 42. A main portion of the second external electrode 52 is disposed on the second end face 9. The second external electrode 52 may also be disposed on part of the first main surface 4, part of the second main surface 5, part of the first side surface 6, and part of the second side surface 7. In this embodiment, the second external electrode 52 is formed to extend from the second end face 9 to part of the first main surface 4, part of the second main surface 5, part of the first side surface 6, and part of the second side surface 7.

[0044] (Base Electrode Layer, Organic Layer, and Plating) The external electrode 50 includes a base electrode layer 53, an organic layer 54 formed on the base electrode layer 53, and a plating layer 55 formed on the organic layer 54. The plating layer includes a nickel plating layer 56 and a tin plating layer 57.

[0045] (Recesses in Base Electrode Layer) In the multilayer ceramic capacitor 1 of this embodiment, recesses 70 are formed on the surface 60 of the base electrode layer 53. FIG. 5 is an enlarged view of a portion of the box 210 in FIG. 2. As shown in FIG. 5, the recesses 70 are formed on the surface 60 of the base electrode layer 53. FIG. 5 illustrates a recess 70 having a V-shaped cross section. FIG. 5 also shows two recesses 70 adjacent to each other in the longitudinal direction L. One of the recesses 70 is referred to as a first recess 71. The other recess 70 is referred to as a second recess 72. In FIG. 5, the area between the first recess 71 and the second recess 72 is omitted.

[0046] (Organic Layer) The organic layer 54 will be described. The organic layer 54 is formed on the surface 60 of the base electrode layer 53. The organic layer 54 is also formed on the surface 60 of the base electrode layer 53 in the recess 71. The organic layer 54 is formed along the surface 60 of the base electrode layer 53. Therefore, the organic layer 54 forms a concave shape in the recess 71. Figure 5 illustrates an example where the cross-sectional shape of the organic layer 54 is U-shaped.

[0047] (Plating Layer) A plating layer 55 is formed on the organic layer 54. Fig. 5 illustrates a nickel plating layer 56 as the plating layer 55. As shown in Fig. 5, the nickel plating layer 56 does not completely conform to the recesses of the organic layer 54. As a result, a gap 80 is formed between the organic layer 54 and the nickel plating layer 56.

[0048] (Dimensions of Recess) The distance in the stacking direction T from the lower end 73 of the recess 70 to the upper end 74 of the recess 70 is called the distance D1. An example of the distance D1 is 0.5 μm or more and 5 μm or less. The distance in the longitudinal direction L between the two upper ends 74 in the cross section of the recess 70 is called the distance D2. An example of the distance D2 is 2.1 μm or more and 8 μm or less.

[0049] (Spacing Between Recesses) As shown in FIG. 5 , a plurality of recesses 70 may be formed. Two recesses 70 adjacent to each other in the longitudinal direction L are designated as a first recess 71 and a second recess 72. Imaginary lines drawn perpendicularly from the two upper ends 74 of the first recess 71 are designated as imaginary lines L1 and L2, respectively. The distance D2 described above corresponds to the distance in the longitudinal direction L between the imaginary lines L1 and L2. Similarly, for the second recess 72, imaginary lines drawn parallel to the stacking direction T from the two upper ends 74 are designated as imaginary lines L1 and L2, respectively. The imaginary line located midway between the imaginary lines L1 and L2 is designated as imaginary line L3. In other words, the distance D3 shown in FIG. 5 is half the distance D2.

[0050] The shortest distance in the longitudinal direction L connecting the imaginary line L3 of the first recess 71 and the imaginary line L3 of the second recess 72 is defined as a distance D4. The distance D4 is defined as the interval between adjacent recesses. An example of the distance D4 is 0.25 μm or more and 2 μm or less.

[0051] The cross-sectional shape of the recess 70 in the base electrode layer 53 is not limited to a V-shape, but may be a U-shape, a rectangular shape, or the like.

[0052] 5 is formed between the organic layer 54 formed on the recess 70 of the base electrode layer 53 and the nickel plating layer 56, which is the plating layer 55 formed on the organic layer 54. However, the plating layer 55 that defines the gap 80 is not limited to the nickel plating layer 56. The plating layer 55 that defines the gap 80 may be a plating layer 55 of another metal type.

[0053] (Effect of Organic Layer) Consider a state in which the multilayer ceramic capacitor 1 is mounted on a substrate. In the multilayer ceramic capacitor 1 of this embodiment, the organic layer 54 is formed on the external electrode 50. Therefore, when the multilayer ceramic capacitor 1 receives an external impact, the deflection stress generated by the deflection of the substrate induces peeling between the nickel plating layer 56 and the organic layer 54. Peeling between the nickel plating layer 56 and the organic layer 54 can disperse the deflection stress generated by the deflection of the substrate. As a result, cracks occurring in the multilayer ceramic capacitor can be suppressed.

[0054] (Effect of Voids) In the multilayer ceramic capacitor 1 of this embodiment, voids 80 are formed between the organic layer 54 formed on the recesses 70 of the base electrode layer 53 and the nickel plating layer 56. This allows for better dispersion of the bending stress caused by bending of the substrate. As a result, the occurrence of cracks inside the laminate 2 can be suppressed.

[0055] The multilayer ceramic capacitor 1 of this embodiment can further reduce the incidence of short circuits in the multilayer ceramic capacitor 1. Furthermore, the multilayer ceramic capacitor 1 of this embodiment can further suppress a decrease in reliability caused by peeling of the external electrodes 50 due to cracks.

[0056] (When there is no void) On the other hand, when there is no void 80 between the plating layer 55 and the organic layer 54, the deflection stress caused by the deflection of the substrate may not be sufficiently dispersed. If the stress caused by the deflection of the substrate is not dispersed, the deflection stress may be directly transmitted to the organic layer 54 and the base electrode layer 53, and the propagation of cracks into the laminate 2 may not be suppressed.

[0057] (Method of Measuring Organic Layer and Voids) A method of measuring the dimensions of the organic layer 54 and the voids 80 of the multilayer ceramic capacitor 1 will be described. An example of the material for the organic layer 54 is polyfunctional alkoxysilane Si-(C ｎ H ２ｎ＋１ ) ３ The material of the organic layer 54 will be described later.

[0058] First, a cross section of the multilayer ceramic capacitor 1 is exposed. Specifically, cross section polishing is performed from the first side surface 6 or the second side surface 7 of the multilayer ceramic capacitor 1 to the center of the width direction W of the multilayer ceramic capacitor 1, thereby exposing a cross section parallel to the length direction L and the stacking direction T. The cross section parallel to the length direction L and the stacking direction T is called an LT cross section.

[0059] Next, the exposed LT cross section is subjected to surface precision polishing using focused ion beam (FIB) processing. The polished first external electrode 51 and second external electrode 52 are then observed and imaged using a SEM (scanning electron microscope). The observation and image capturing conditions are a magnification of 2000x, an acceleration voltage of 5 kV, and a field of view of 10 μm × 10 μm. WDX analysis is then performed, and the portion in which silicon, carbon, hydrogen, or nitrogen is detected is considered to be an organic layer. Meanwhile, the portion in which silicon, carbon, hydrogen, or nitrogen is not detected is considered to be a void 80. In this way, the void 80 portion is identified, and the dimensions of the void 80 are measured.

[0060] (Voids when no recesses are formed) The voids 80 can be formed even when no recesses 70 are formed on the surface 60 of the base electrode layer 53. The organic layer 54 may not be formed over the entire surface 60 of the base electrode layer 53. The coverage of the organic layer 54 with respect to the surface 60 of the base electrode layer 53 is, for example, 40% or more and 80% or less. The portions of the surface 60 of the base electrode layer 53 on which the organic layer 54 is not formed are recessed relative to the portions on which the organic layer 54 is formed. When these recessed portions are covered with the plating layer 55, the recessed portions can become voids 80.

[0061] (Depth Direction Dimension of the Void) The dimension of the void 80 will be described. The direction parallel to the stacking direction T, from the plating layer 55 toward the base electrode layer 53, is defined as the depth direction T1. In FIG. 5 , the depth direction T1 is indicated by an arrow T1. In the void 80, the deepest portion in the depth direction T1 is referred to as the gap lower end 81. In the void 80, the shallowest portion in the depth direction T1 is referred to as the gap upper end 82. The gap lower end 81 is typically located at the interface between the void 80 and the organic layer 54. The gap upper end 82 is typically located at the interface between the void 80 and the plating layer 55. The distance between the gap lower end 81 and the gap upper end 82 in the stacking direction T is defined as a distance D5. The distance D5 indicates the dimension of the void 80 in the depth direction T1. An example of the distance D5 is 0.3 μm or more and 2 μm or less.

[0062] (Gap Size) Regarding the dimensions of the gap 80, the gap size is defined as the length of the longest imaginary line connecting the ends of one gap 80 formed between the organic layer 54 formed on the recess 70 of the base electrode layer 53 and the plating layer 55 in the stacking direction T, the length direction L, and the width direction W. An example of a preferred gap size is 0.3 μm or more and 2 μm or less.

[0063] By setting the gap size of the gap 80 formed between the organic layer 54 formed on the recess 70 of the base electrode layer 53 and the plating layer 55 to 0.3 μm or more and 2 μm or less, the bending stress of the substrate caused by external stress can be more effectively dispersed, thereby further suppressing cracks from occurring inside the laminate 2. As a result, the incidence of short circuits in the multilayer ceramic capacitor 1 can be reduced, and a decrease in reliability caused by peeling of the external electrode 50 due to cracks can be more effectively suppressed.

[0064] By setting the gap size to 0.3 μm or more, the bending stress of the substrate caused by an external stress can be sufficiently dispersed.

[0065] Furthermore, by making the gap size 2 μm or less, peeling between the organic layer 54 and the plating layer 55 is less likely to be induced across the entire external electrode 50 due to minor impacts other than external impacts (such as bending of the substrate or thermal contraction), such as impacts that occur when the main body of the multilayer ceramic capacitor 1 is moved.

[0066] (When the gap size is outside the preferred range) If the gap size is less than 0.3 μm, the bending stress of the substrate caused by external stress cannot be sufficiently dispersed. As a result, cracks are likely to occur inside the laminate 2. If the cracks reach the internal electrode layers 40, moisture will flow in from the outside through the cracks, increasing the incidence of short circuits and reducing reliability.

[0067] If the gap size exceeds 2 μm, peeling of the organic layer 54 and the plating layer 55 is induced across the entire external electrode 50 by an external impact, such as a minor impact other than an impact caused by bending or thermal contraction of the substrate, such as an impact that occurs when the body of the multilayer ceramic capacitor 1 is moved. This results in insufficient electrical continuity between the multilayer ceramic capacitor 1 and the substrate (mounting substrate). As a result, it becomes difficult to ensure the reliability of the multilayer ceramic capacitor 1.

[0068] (Method for measuring the gap size of a gap formed between an organic layer formed on a recess 70 of an under electrode layer and a plating layer) A method for measuring the gap size will be described. As described above, the gap size refers to the length of the longest imaginary line connecting the ends of one gap 80 formed between an organic layer 54 formed on a recess 70 of an under electrode layer 53 and a plating layer 55 in the stacking direction T, the length direction L, and the width direction W. The gap size of a gap 80 formed between an organic layer 54 formed on a recess 70 of an under electrode layer 53 and a plating layer 55 is measured by the following method.

[0069] First, cross-section polishing is performed from the first side surface 6 or the second side surface 7 of the multilayer ceramic capacitor 1 to the center in the width direction W of the multilayer ceramic capacitor 1 to expose the LT cross section.

[0070] Next, the cut surface (LT cross section) is subjected to surface precision polishing by focused ion beam (FIB) processing. The polished first external electrode 51 and second external electrode 52 are then observed and imaged by SEM under the conditions of 2000x magnification, 5 kV acceleration voltage, and a field of view of 30 μm × 30 μm.

[0071] Thereafter, the portion in which silicon, carbon, hydrogen, or nitrogen elements are detected by WDX analysis is regarded as the organic layer 54. The portion in which silicon, carbon, hydrogen, or nitrogen elements are not detected is regarded as a void, thereby making it possible to measure the void size.

[0072] When analyzing the observation range and measuring the void size, the average void size within the observation range is calculated, and the average void size is defined as the void size in this embodiment: void size (μm) = (total void size within the observation range / number of voids within the observation range).

[0073] (Multiple Recesses) The recesses 70 of the base electrode layer 53 are preferably arranged at intervals of 0.25 μm to 2 μm. By arranging the adjacent recesses 70 at intervals of 0.25 μm to 2 μm, the bending stress of the substrate caused by external stress can be further dispersed. As a result, cracks occurring inside the laminate 2 can be suppressed.

[0074] By suppressing the occurrence of cracks, it is possible to prevent moisture from penetrating from the outside through the cracks, which results in a reduction in the incidence of short circuits in the multilayer ceramic capacitor 1 and further suppresses a decrease in the reliability of the multilayer ceramic capacitor 1 caused by peeling of the external electrodes 50 due to cracks.

[0075] Furthermore, in the multilayer ceramic capacitor 1 of this embodiment, the recesses 70 are not spaced apart too far apart, which allows the organic layer 54 and the plating layer 55 to be continuously peeled from each other starting from peeling at adjacent recesses 70.

[0076] When the interval between the recesses 70 is 0.25 μm or more, this is an appropriate interval, and therefore a minor external impact is unlikely to induce peeling between the organic layer 54 and the plating layer 55. Therefore, it is possible to prevent excessive peeling of the plating layer due to an external impact that does not actually require peeling.

[0077] When the distance between the recesses 70 is 2 μm or less, peeling of adjacent recesses can cause a chain reaction of peeling. Because the peeling does not stop midway, the bending stress is dispersed, and as a result, the occurrence of cracks inside the laminate 2 can be sufficiently suppressed.

[0078] (When the distance between the recesses 70 is outside the preferred range) When the distance between the recesses 70 is less than 0.25 μm, the distance between the recesses 70 becomes too narrow, and a slight external impact may induce peeling between the organic layer 54 and the plating layer 55. As a result, an external impact or the like that does not actually require peeling may cause excessive peeling of the plating layer 55, and the multilayer ceramic capacitor 1 may not be able to maintain its functionality.

[0079] On the other hand, when the distance between the recesses 70 exceeds 2 μm, no chain of peeling occurs starting from peeling of adjacent recesses 70. As a result, peeling stops midway, the bending stress is not dispersed, and cracks occurring inside the laminate 2 cannot be sufficiently suppressed.

[0080] (Method for measuring the distance between recesses 70 in the base electrode layer) A method for measuring the distance between recesses 70 in the base electrode layer 53 will be described. Regarding the method for measuring the distance between recesses 70 in the base electrode layer 53 of the multilayer ceramic capacitor 1, the distance between recesses 70 is the distance between a portion of the surface 60 of the base electrode layer 53 that extends further inward toward the effective layer 10 than the surface 60 of the base electrode layer 53 and a portion of the adjacent base electrode layer 53 that extends further inward toward the effective layer 10 than the surface 60 of the base electrode layer 53.

[0081] The distance between the recesses 70 in the base electrode layer 53 of the multilayer ceramic capacitor 1 is measured as follows. First, a cross section of the multilayer ceramic capacitor 1 is exposed. Specifically, the cross section is polished from the first side surface 6 or the second side surface 7 of the multilayer ceramic capacitor 1 to the center of the multilayer ceramic capacitor 1 in the width direction W, exposing the LT cross section. Next, the exposed LT cross section is subjected to surface precision polishing by focused ion beam (FIB) processing. The polished first external electrode 51 and second external electrode 52 are then observed and imaged using an SEM. The observation conditions are a magnification of 2000 times, an acceleration voltage of 5 kV, and a field of view of 30 μm × 30 μm.

[0082] The distance between the recesses 70 of the base electrode layer 53 is calculated based on the scale in the SEM image. Specifically, as described above, a virtual line (virtual line L3) is drawn in the center between the two ends (top ends 74) of the recesses 70 of the base electrode layer 53 within the observation range. Similarly, a virtual line (virtual line L3) is drawn in the center between the ends (top ends 74) of the recesses 70 of adjacent base electrode layers 53. The distance to each virtual line L3 is then measured. The distance D4 in FIG. 5 corresponds to the distance to each virtual line L3. The average value of the distances between the recesses 70 of the base electrode layer 53 within the observation range is then calculated, and this average value of the distances between the recesses 70 of the base electrode layer 53 is used as the distance between the recesses 70 of the base electrode layer 53 in this embodiment. Distance (μm) between the recesses 70 of the base electrode layer 53 = (total distance between the recesses 70 of the base electrode layer 53 / number of recesses 70 within the observation range)

[0083] The organic layer 54 is formed of polyfunctional alkoxysilane Si-(C ｎ H ２ｎ＋１ ) ３ It is preferable that the compound contains an organosilicon compound having the following structure and containing a nitrogen element.

[0084] (Height of Recesses 70 in Base Electrode Layer 53) It is more preferable that the height of the recesses 70 in the base electrode layer 53 is 0.5 μm or more and 5 μm or less.

[0085] (Method for Measuring Height of Recess in Base Electrode Layer) A method for measuring the height of a recess 70 in the base electrode layer 53 will be described. Here, the recess 70 is defined as a portion between a portion where the surface 60 of the base electrode layer 53 extends further toward the effective layer 10 than the surfaces 60 of the surrounding base electrode layers 53 and an adjacent portion where the surface 60 of the base electrode layer 53 extends further toward the effective layer 10 than the surfaces 60 of the surrounding base electrode layers 53. The height of the recess 70 is the length in the stacking direction T of the line segment with the longest distance connecting the portion where the surface 60 of the base electrode layer 53 extends further toward the effective layer 10 than the surfaces 60 of the surrounding base electrode layers 53 in the recess 70, to the end of the portion that extends furthest toward the effective layer 10.

[0086] 5 , the portion of the surface 60 of the base electrode layer 53 that extends further toward the effective layer 10 than the surfaces 60 of the surrounding base electrode layers 53 corresponds to the upper end 74 of the recess 70. The end of the portion that extends furthest toward the effective layer 10 from the extended portion corresponds to the lower end 73 of the recess 70. Previously, the distance D1 in the stacking direction T from the lower end 73 of the recess 70 to the upper end 74 of the recess 70 was described. The distance D1 corresponds to the height of the recess 70 of the base electrode layer 53.

[0087] The height of the recess 70 of the multilayer ceramic capacitor 1 is measured by first exposing a cross section of the multilayer ceramic capacitor 1. Specifically, the cross section is polished from the first side surface 6 or the second side surface 7 of the multilayer ceramic capacitor 1 to the center of the multilayer ceramic capacitor 1 in the width direction W, exposing the LT cross section. Next, the exposed LT cross section is subjected to surface precision polishing by focused ion beam (FIB) processing. The polished first external electrode 51 and second external electrode 52 are then observed and imaged using an SEM. The observation conditions are a magnification of 2000 times, an acceleration voltage of 5 kV, and a field of view of 10 μm × 10 μm.

[0088] Thereafter, the height of the recesses 70 in the base electrode layer 53 is measured using the scale in the SEM image. The average value of the height of the recesses 70 in the base electrode layer 53 within the observation range is calculated, and the average value of the height of the recesses 70 in the base electrode layer 53 is defined as the height of the recesses 70 in the base electrode layer 53. Height (μm) of the recesses 70 in the base electrode layer 53 = (total height of the recesses 70 in the base electrode layer 53 / total number of recesses 70 in the base electrode layer 53)

[0089] By setting the height of the recess 70 to be 0.5 μm or more and 5 μm or less, it is possible to form a sufficient gap 80 between the plating layer 55 and the organic layer 54. As a result, it is possible to induce smooth peeling between the organic layer 54 and the plating layer 55.

[0090] (When the height of the recess 70 is outside the preferred range) When the height of the recess 70 is less than 0.5 μm, it is not possible to form a void 80 of sufficient size within the recess 70. As a result, the organic layer 54 and the plating layer 55 cannot be sufficiently peeled from each other, which may result in cracks occurring inside the laminate 2.

[0091] If the height of the recess 70 exceeds 5 μm, the nickel plating layer 56 flows excessively into the recess 70, preventing smooth peeling. Therefore, when the multilayer ceramic capacitor 1 receives an external impact, the deflection stress caused by the bending of the substrate makes it difficult to induce peeling between the nickel plating layer 56 and the organic layer 54. As a result, the deflection stress caused by the bending of the substrate may not be sufficiently dispersed, which may result in cracks occurring inside the laminate 2.

[0092] The following will continue to sequentially describe the configuration of the multilayer ceramic capacitor 1. First, we will describe the external electrode 50. The external electrode 50 includes a base electrode layer 53, an organic layer 54, and a plating layer 55. The plating layer 55 includes a nickel plating layer 56 and a tin plating layer 57.

[0093] (Base Electrode Layer) The base electrode layer 53 is made of a baking layer. The baking layer contains a glass component and a metal. The glass component contains at least one selected from boron, silicon, barium, magnesium, aluminum, lithium, etc. The metal component contains at least one selected from copper, nickel, silver, palladium, a silver-palladium alloy, gold, etc.

[0094] The baked layer may be a multi-layer. The baked layer is formed by applying a conductive paste containing glass and metal to the laminate 2 and baking it. The baked layer may be one that is simultaneously baked with the internal electrode layers 40 and the dielectric layers 30, or one that is baked after the internal electrode layers 40 and the dielectric layers 30 are baked. When the conductive paste is baked simultaneously with the internal electrode layers 40 and the dielectric layers 30, it is preferable to add a dielectric material instead of the glass component to form the baked electrode.

[0095] The thickness of the baked layer serving as the base electrode layer 53 located on the first end face 8 and the second end face 9 at the center in the stacking direction T connecting the first main surface 4 and the second main surface 5, and at the center in the width direction W connecting the first side surface 6 and the second side surface 7, is preferably, for example, approximately 3 μm or more and 160 μm or less.

[0096] Furthermore, when a base electrode layer 53 (baked layer) is provided on a portion of the first principal surface 4 and a portion of the second principal surface 5, the thickness of the baked layer as the base electrode layer 53 located on the first principal surface 4 and the second principal surface 5 at the center in the length direction L and the center in the width direction W is preferably, for example, about 3 μm or more and 40 μm or less. Similarly, when a base electrode layer 53 (baked layer) is provided on a portion of the first side surface 6 and a portion of the second side surface 7, the thickness of the baked layer as the base electrode layer 53 located on the first side surface 6 and the second side surface 7 at the center in the length direction L and the center in the stacking direction T is preferably, for example, about 3 μm or more and 40 μm or less. (Organic Layer) An organic layer 54 is formed on the base electrode layer 53. The organic layer 54 is composed of, for example, a monofunctional silane coupling material. Specific examples of the silane coupling agent include decyltrimethoxysilane, n-propyltrimethoxysilane, and octyltriethoxysilane.

[0097] (Plating Layer) A plating layer 55 is formed on the organic layer 54. The material of the plating layer 55 includes at least one selected from, for example, copper, nickel, tin, silver, palladium, a silver-palladium alloy, and gold.

[0098] The plating layer 55 may be formed of multiple layers. Preferably, the plating layer 55 has a two-layer structure of nickel plating and tin plating. In the multilayer ceramic capacitor 1 of this embodiment, the plating layer 55 includes a nickel plating layer 56 and a tin plating layer 57.

[0099] The nickel plating layer 56 prevents the base electrode layer 53 from being corroded by solder when mounting a ceramic electronic component. The tin plating layer 57 improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. As a result, mounting to a substrate via solder is facilitated. The preferred thickness of each plating layer is 1 μm or more and 15 μm or less.

[0100] (Dimensions of Multilayer Ceramic Capacitor (L Dimension, T Dimension, and W Dimension)) The dimension in the length direction L of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 50 is called the L dimension. A preferred L dimension is 0.2 mm or more and 10 mm or less. The dimension in the stacking direction T of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 50 is called the T dimension. A preferred T dimension is 0.1 mm or more and 10 mm or less. The dimension in the width direction W of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 50 is called the W dimension. A preferred W dimension is 0.1 mm or more and 10 mm or less.

[0101] (Manufacturing Method) A method for manufacturing the multilayer ceramic capacitor 1 according to one embodiment of the present invention will be described. (Lamination) First, a laminate 2 having first internal electrode layers 41 and second internal electrode layers 42 is prepared. Specifically, a ceramic paste containing ceramic powder is applied in the form of a sheet by, for example, screen printing, and dried to produce a mother ceramic green sheet.

[0102] Next, a conductive paste for forming internal electrode layers is printed in a predetermined pattern on the mother ceramic green sheet by, for example, screen printing, etc., to form a conductive pattern for forming internal electrode layers of the first internal electrode layer 41. Similarly, a conductive paste for forming internal electrode layers is printed in a predetermined pattern on another mother ceramic green sheet by, for example, screen printing, etc., to form a conductive pattern for forming internal electrode layers of the second internal electrode layer.

[0103] In this way, mother ceramic green sheets on which the conductive patterns for forming the first internal electrode layers 41 are formed, mother ceramic green sheets on which the conductive patterns for forming the second internal electrode layers 42 are formed, and mother ceramic green sheets on which the conductive patterns for forming the internal electrode layers are not formed are prepared. Note that the ceramic paste and the conductive paste for forming the internal electrode layers may contain, for example, well-known binders and solvents.

[0104] Next, a mother laminate is produced. The mother laminate is produced as follows. A predetermined number of mother ceramic green sheets for outer layers, on which no conductive pattern for forming internal electrode layers is printed, are laminated, and on top of these, mother ceramic green sheets, on which a conductive pattern for forming internal electrode layers of the first internal electrode layer 41 is printed, and mother ceramic green sheets, on which a conductive pattern for forming internal electrode layers of the second internal electrode layer 42 is printed, are laminated alternately in order. Further on top of these, a predetermined number of mother ceramic green sheets for outer layers, on which no conductive pattern for forming internal electrode layers is printed, are laminated to produce the mother laminate.

[0105] The mother laminate may be pressed in the lamination direction T by means of a hydrostatic press or the like, if necessary.

[0106] (Cutting) Next, the mother laminate is cut at predetermined positions to cut out a plurality of raw laminates of predetermined dimensions. At this time, the corners and ridges of the raw laminates may be rounded by barrel polishing or the like.

[0107] (Firing) Next, the green laminate 2 is fired to obtain a laminate 2 in which the first internal electrode layers 41 and the second internal electrode layers 42 are disposed therein, the first lead electrode portions 44 of the first internal electrode layers 41 are exposed at the first end face 8, and the second lead electrode portions 46 of the second internal electrode layers 42 are exposed at the second end face 9. The firing temperature is set appropriately depending on the types of ceramic material and conductive material. The firing temperature is set, for example, within a range of 900°C or higher and 1300°C or lower.

[0108] (Formation of Base Electrode Layer) Next, base electrode layers 53 of the external electrodes 50 are formed on both ends of the fired laminate 2. A conductive paste for the external electrodes is applied to both ends of the fired laminate 2 and baked. This forms the base electrode layers 53. A preferred baking temperature is 700°C or higher and 900°C or lower.

[0109] (Formation of Recesses in Base Electrode Layer) After firing, recesses 70 are formed in the base electrode layer 53. The method for forming the recesses 70 is to polish the surface of the laminate 2. Blasting is used for the polishing. To obtain the desired recesses 70, the particle size of the blasting material, the discharge pressure, the blasting time, and the like are adjusted. Note that the polishing method may be at least one of laser irradiation, barrel polishing, polishing with abrasive paper, abrasives, grinding stones, buffs, and the like, and chemical polishing, in addition to blasting.

[0110] (Forming Spacing Between Recesses in Base Electrode Layer) Similar to the method of forming the recesses 70, the spacing between the recesses 70 in the base electrode layer 53 can be formed by polishing the surface of the laminate 2. Blasting is used for polishing. To obtain the desired spacing between the recesses 70, the particle size of the blasting material, the discharge pressure, the blasting time, and the like are adjusted. Note that the polishing method may be at least one of laser irradiation, barrel polishing, polishing with abrasive paper, abrasives, grinding stones, buffs, and the like, and chemical polishing, in addition to blasting.

[0111] (Method of Forming Organic Layer) Next, the organic layer 54 is formed. The organic layer 54 is formed as follows. The organic layer 54 is formed by applying or immersing an organic treatment liquid so as to cover predetermined surfaces of the base electrode layer 53 and the laminate 2. In the step of forming the organic layer 54, the organic treatment liquid is applied to the base electrode layer 53, etc. Specifically, the laminates 2 to which the base electrode layers 53 of the external electrodes 50 have been baked are aligned in the longitudinal direction, and the surfaces of the external electrodes 50 (surfaces 60 of the base electrode layers 53) are immersed in the organic treatment liquid.

[0112] Thereafter, the laminate 2 is dried at a temperature of 100°C or higher and 200°C or lower, thereby forming a portion of the organic layer 54 that covers the base electrode layer 53. The organic treatment liquid is made of a monofunctional silane coupling material. Specifically, the organic treatment liquid may include decyltrimethoxysilane, n-propyltrimethoxysilane, octyltriethoxysilane, or the like. The organic treatment liquid is made by diluting these materials in an alcohol solvent to a concentration of 3% by weight or less.

[0113] (Formation of Voids) The voids 80 between the organic layer 54 and the plating layer 55 are formed as follows. A void is formed by applying a resin onto the organic layer 54 formed in the recesses 70 of the base electrode layer 53. The resin applied onto the organic layer 54 is mainly a binder. Therefore, the resin disappears during the firing process. As a result, the voids 80 are formed. By adjusting the amount of resin applied onto the organic layer 54, the size of the voids 80 formed between the base electrode layer 53 and the organic layer 54 can be controlled.

[0114] Next, the plating layers 55 of the external electrodes 50 are formed on both ends of the laminate 2. The plating layers 55 of the external electrodes 50 are formed so as to cover almost the entire surface 60 of the base electrode layer 53 of the external electrodes 50.

[0115] By the above method, it is possible to easily manufacture a multilayer ceramic capacitor that can suppress the occurrence of cracks, deformation, etc. in the ceramic portion and the effective layer portion of the laminate 2 and can improve performance and reliability.

[0116] The method for manufacturing a multilayer ceramic capacitor having voids 80 is not limited to the above-described method. For example, by forming a plating layer 55 on the organic layer 54, voids 80 can be formed without using a binder. As described above, there are portions of the surface 60 of the base electrode layer 53 where the organic layer 54 is not formed. The coverage rate of the organic layer 54 with respect to the surface 60 of the base electrode layer 53 is not 100%. Furthermore, the coverage rate can be changed by adjusting the concentration of the organic treatment liquid used when forming the organic layer 54. The portions of the surface 60 of the base electrode layer 53 where the organic layer 54 is not formed can become voids 80 by forming the plating layer 55 after forming the organic layer 54. Therefore, voids 80 can be formed without using a binder by, for example, adjusting the coverage rate of the organic layer 54 with respect to the surface 60 of the base electrode layer 53 when forming the organic layer 54.

[0117] (Test Method (Experimental Example 1)) The details of Experimental Example 1 will be described below. In Experimental Example 1, Comparative Example 1, Comparative Example 2, and Example 1 were compared. Example 1 is a multilayer ceramic capacitor according to an embodiment of the present invention. Hereinafter, the multilayer ceramic capacitor of Example 1 may be simply referred to as Example 1. The same applies to the comparative examples and other experimental examples. Also, FIG. 6 is a table showing the results of Experimental Example 1.

[0118] Example 1 has voids. Comparative Examples 1 and 2 do not have voids. Comparative Example 2 is the same as Example 1 except that it does not have voids. Comparative Example 1 does not have voids and also does not have an organic layer.

[0119] In Experimental Example 1, the crack occurrence rate, short circuit rate, and peeling rate of the multilayer ceramic capacitors of Comparative Example 1, Comparative Example 2, and Example 1 after thermal stress were measured.

[0120] The test method for Experimental Example 1 was as follows: LF solder was applied to a thickness of 150 μm on a JEITA land FR4 board having a width of 40 mm, a length of 100 mm, and a thickness of 1.6 mm, and then a multilayer ceramic capacitor was placed on the board and passed through a reflow furnace at 240° C. to mount the multilayer ceramic capacitor.

[0121] Next, the substrate on which the multilayer ceramic capacitor was mounted was subjected to a bending and retention test in which a pressing tool with a radius R of 1 mm was pressed against the rear surface of the substrate at a speed of 1 mm / sec, and the substrate was held in a state where it was bent 2 mm for 5 seconds.

[0122] The number of substrates tested was 100 for each of Comparative Example 1, Comparative Example 2, and Example 1. One multilayer ceramic capacitor was mounted on each substrate. The number of multilayer ceramic capacitors mounted on the substrate was 100 for each of Comparative Example 1, Comparative Example 2, and Example 1.

[0123] After mounting on the substrate, each tested substrate was placed on a hot plate at 240° C. to melt the solder, and the multilayer ceramic capacitor was removed from the substrate.

[0124] Next, the cross section was polished from the surface perpendicular to the mounting surface of the substrate, i.e., from the first side surface or the second side surface to the center of the multilayer ceramic capacitor (halfway along the width direction W). After the cross section was polished, the polished cross section was observed with a SEM (electron microscope) focusing on cracks that started at the end of the external electrode and progressed from the outer layer portion toward the effective layer portion.

[0125] (Crack occurrence rate) The rate of cracks observed in 100 samples for each of Comparative Example 1, Comparative Example 2 and Example 1 was taken as the crack occurrence rate.

[0126] (Short Circuit Rate) In measuring the short circuit rate of the multilayer ceramic capacitor, the resistance value after applying a rated voltage of 6 V was measured with a multimeter, and samples with a resistance value of 10 kΩ or less were determined to have short circuits. The rate of short circuit occurrence was calculated as the proportion of samples determined to have short circuits out of 100 samples for each of Comparative Example 1, Comparative Example 2, and Example 1.

[0127] (Peeling Rate) In measuring the peeling rate of the multilayer ceramic capacitor 1, a capacitor that peeled off from the solder-mounted substrate in the deflection test and lost electrical continuity on the substrate was judged to have peeled. The peeling rate was calculated as the percentage of 100 samples judged to have peeled off for each of Comparative Example 1, Comparative Example 2, and Example 1. Peeling rate = Number of multilayer ceramic capacitors that peeled off from the solder-mounted substrate and lost electrical continuity on the substrate / Number of samples (100) / 100

[0128] The specifications of the sample multilayer ceramic capacitors for the samples of Comparative Example 1, Comparative Example 2, and Example 1 are described below. (Comparative Example 1) The specifications of the multilayer ceramic capacitor (Comparative Example 1) are as follows: Dimensions: Length L (L dimension) 1.0 mm, width W (W dimension) 0.5 mm, height H (T dimension) 0.5 mm Ceramic material: barium titanate Capacitance: 10 nF Rated voltage: 16 V The specifications of the external electrodes are as follows: Base electrode layer material: material containing conductive metal (copper) and glass component Base electrode layer thickness: 30 μm at the center of the end face Base electrode layer and plating layer: two layers consisting of a nickel plating layer (3 μm) and a tin plating layer (3 μm) Organic layer formation: none Voids formed between the organic layer and the plating layer As described above, Comparative Example 1 has no organic layer and no voids.

[0129] (Comparative Example 2) The specifications of the multilayer ceramic capacitor (Comparative Example 1) are as follows: Dimensions: Length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10 nF Rated voltage: 16 V The specifications of the external electrodes are as follows: Base electrode layer material: Material containing conductive metal (copper) and glass component Base electrode layer thickness: 30 μm at the center of the end face Base electrode layer / plating layer: Two layers consisting of a nickel plating layer (3 μm) and a tin plating layer (3 μm) The specifications of the organic layer are as follows: Organic layer material: Polyfunctional alkoxysilane Si-(C ｎ H ２ｎ＋１ ) ３ Recess height: 0.5 μm Distance between recesses: 2.5 μm Comparative Example 2 has an organic layer, no voids, a recess height of 0.5 μm, and a distance between recesses of 0.25 μm.

[0130] (Example 1) The specifications of the multilayer ceramic capacitor (Example 1) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10 nF Rated voltage: 16 V The specifications of the external electrodes are as follows: Base electrode layer material: material containing conductive metal (copper) and glass component Base electrode layer thickness: 30 μm at the center of the end face Base electrode layer / plating layer: two layers of nickel plating layer (3 μm) + tin plating layer (3 μm) The specifications of the organic layer are as follows: Organic layer material: polyfunctional alkoxysilane Si-(C ｎ H ２ｎ＋１ ) ３ Recess height: 0.5 μm Distance between recesses: 2.5 μm Example 1 has an organic layer, a gap, a gap size of 0.2 μm, a recess height of 0.5 μm, and a gap between recesses of 0.25 μm.

[0131] As shown in Figure 6, the results of Experimental Example 1 show that the crack occurrence rate, short circuit rate, and peeling rate of the multilayer ceramic capacitor are reduced by forming a gap between the base electrode layer and the nickel plating layer. This shows that the formation of a gap between the base electrode layer and the nickel plating layer further distributes the deflection stress caused by substrate deflection, thereby further suppressing cracks from forming inside the laminate. It can be seen that Example 1 is a highly reliable multilayer ceramic capacitor in which cracks generated in the laminate are less likely to reach the internal electrode layer, the rate of short circuit occurrence caused by moisture entering from the outside through the cracks is reduced, and peeling of the external electrodes is suppressed.

[0132] (Experimental Example 2) Experimental Example 2 will be described. FIG. 7 is a table showing the results of Experimental Example 2. In Experimental Example 2, differences in characteristics due to differences in void size were evaluated in a multilayer ceramic capacitor according to an embodiment of the present invention. Examples 2 to 9 were fabricated to have the same configuration as Example 1 except for the void size between the organic layer and the plating layer. In Experimental Example 2, the crack occurrence rate, short-circuit rate, and peeling rate of the multilayer ceramic capacitor after thermal stress were measured in the same manner as in Experimental Example 1.

[0133] The test method for Experimental Example 2 was as follows: LF solder was applied to a thickness of 150 μm on a JEITA land FR4 board having a width of 40 mm, a length of 100 mm, and a thickness of 1.6 mm, and then a multilayer ceramic capacitor was placed on the board and passed through a reflow furnace at 240° C. to mount the multilayer ceramic capacitor.

[0134] Next, the substrate on which the multilayer ceramic capacitor was mounted was subjected to a bending and retention test in which a pressing tool with a radius R of 1 mm was pressed against the rear surface of the substrate at a speed of 1 mm / sec, and the substrate was held in a state where it was bent 2 mm for 5 seconds.

[0135] The number of substrates tested was 100 for each example. One multilayer ceramic capacitor was mounted on each substrate. The number of multilayer ceramic capacitors mounted on the substrates was 100 for each example.

[0136] The tested substrate is then placed on a hot plate at 240° C. to melt the solder, and the multilayer ceramic capacitor is removed from the substrate.

[0137] Next, the cross section was polished from the surface perpendicular to the mounting surface of the substrate, i.e., from the first side surface or the second side surface to the center of the multilayer ceramic capacitor (the position half the width W), and then the polished cross section was observed with a SEM (electron microscope) focusing on cracks that started at the end of the external electrode and progressed from the outer layer portion toward the effective layer portion. In Experimental Example 2, as in Experimental Example 1, the short-circuit rate and peeling rate of the multilayer ceramic capacitor were confirmed in addition to the crack occurrence rate of the multilayer ceramic capacitor.

[0138] In measuring the short-circuit rate of the multilayer ceramic capacitor, the resistance value after applying a rated voltage of 6 V was measured with a multimeter, and samples with a resistance value of 1 MΩ or less were judged to have short-circuited. The proportion of samples judged to have short-circuited out of 100 samples in each example was calculated as the short-circuit rate.

[0139] In measuring the peeling rate of multilayer ceramic capacitors, those that peeled off from the solder-mounted substrate in the deflection test and lost continuity on the substrate were judged to have peeled. The peeling rate was calculated as the percentage of 100 samples judged to have peeled off for each example. Peeling rate = Number of multilayer ceramic capacitors that peeled off from the solder-mounted substrate and lost continuity on the substrate / Number of samples (100) / 100

[0140] The specifications of the sample multilayer ceramic capacitors for the samples of Examples 2 to 9 are described below. (Example 2) The specifications of the multilayer ceramic capacitor (Example 2) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10 nF Rated voltage: 16 V Gap size: 0.1 μm Recess height 0.5 μm Distance between recesses 2.5 μm Example 2 has an organic layer, gaps, a gap size of 0.1 μm, a recess height of 0.5 μm, and a distance between recesses of 0.25 μm.

[0141] Example 3 The specifications of the multilayer ceramic capacitor (Example 3) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10 nF Rated voltage: 16 V Gap size: 0.2 μm Recess height 0.5 μm Distance between recesses 2.5 μm Example 3 has an organic layer, gaps, a gap size of 0.2 μm, a recess height of 0.5 μm, and a distance between recesses of 0.25 μm.

[0142] Example 4 The specifications of the multilayer ceramic capacitor (Example 4) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10 nF Rated voltage: 16 V Gap size: 0.3 μm Recess height 0.5 μm Distance between recesses 2.5 μm Example 4 has an organic layer, gaps, a gap size of 0.3 μm, a recess height of 0.5 μm, and a distance between recesses of 0.25 μm.

[0143] Example 5 The specifications of the multilayer ceramic capacitor (Example 5) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10 nF Rated voltage: 16 V Gap size: 1 μm Recess height 0.5 μm Distance between recesses 2.5 μm Example 5 has an organic layer, gaps, a gap size of 1 μm, a recess height of 0.5 μm, and a distance between recesses of 0.25 μm.

[0144] Example 6 The specifications of the multilayer ceramic capacitor (Example 6) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10 nF Rated voltage: 16 V Gap size: 1.5 μm Recess height 0.5 μm Distance between recesses 2.5 μm Example 6 has an organic layer, gaps, a gap size of 1.5 μm, a recess height of 0.5 μm, and a distance between recesses of 0.25 μm.

[0145] Example 7 The specifications of the multilayer ceramic capacitor (Example 7) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10 nF Rated voltage: 16 V Gap size: 2 μm Recess height 0.5 μm Distance between recesses 2.5 μm Example 7 has an organic layer, gaps, a gap size of 2 μm, a recess height of 0.5 μm, and a distance between recesses of 0.25 μm.

[0146] Example 8 The specifications of the multilayer ceramic capacitor (Comparative Example 8) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate, capacitance: 10 nF Rated voltage: 16 V Gap size: 2.1 μm Recess height 0.5 μm Distance between recesses 2.5 μm Example 8 has an organic layer, gaps, a gap size of 2.1 μm, a recess height of 0.5 μm, and a distance between recesses of 0.25 μm.

[0147] Example 9 The specifications of the multilayer ceramic capacitor (Comparative Example 8) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10 nF Rated voltage: 16 V Gap size: 2.1 μm Recess height 0.5 μm Distance between recesses 2.5 μm Example 9 has an organic layer, gaps, a gap size of 2.5 μm, a recess height of 0.5 μm, and a distance between recesses of 0.25 μm.

[0148] As shown in FIG. 7 , the results of Experimental Example 2 show that the rate of crack occurrence inside the laminate can be reduced by setting the size of the gap formed between the base electrode layer and the nickel plating layer in the range of 0.3 μm or more and 2.0 μm or less, as in Examples 4 to 7.

[0149] In Examples 2 and 3 of Experimental Example 2, the gap size was less than 0.3 μm, and the dispersion of the deflection stress caused by the substrate stress was insufficient, which confirmed that the crack occurrence rate and short-circuit rate increased.

[0150] In Examples 8 and 9 of Experimental Example 2, the crack occurrence rate was similar to that in Examples 4 to 7, but the void size was large, exceeding 2.0 μm, which sometimes resulted in insufficient bonding between the base electrode layer and the plating layer. In Examples 8 and 9, the peeling rate increased, and it was confirmed that the reliability of the multilayer ceramic capacitor was reduced.

[0151] Furthermore, from Experimental Example 2, it was confirmed that the crack occurrence rate and the short circuit rate were in a proportional relationship, and it was also confirmed that the peeling rate was also high.

[0152] From the above results, it was confirmed that by setting the gap size in the range of 0.3 μm or more and 2 μm or less in Examples 4 to 7, it is possible to reduce the crack occurrence rate, thereby reducing the short circuit occurrence rate, and suppress peeling of the external electrodes, thereby realizing a more reliable multilayer ceramic capacitor.

[0153] (Experimental Example 3) Experimental Example 3 will be described. FIG. 8 is a table showing the results of Experimental Example 3. In Experimental Example 3, differences in characteristics due to differences in the spacing between recesses in a multilayer ceramic capacitor according to an embodiment of the present invention were evaluated. Examples 10 to 18 were fabricated to have the same configuration as Example 4 except for the spacing between recesses. In Experimental Example 3, the crack occurrence rate, short circuit rate, and peeling rate of the multilayer ceramic capacitor after thermal stress were measured in the same manner as in Experimental Example 2. The crack occurrence rate, short circuit rate, and peeling rate of the multilayer ceramic capacitor were measured using the same methods as in Experimental Example 2.

[0154] As shown in Figure 8, in Experimental Example 3, the peeling rate was suppressed in Examples 12 to 18, but the crack occurrence rate increased in Examples 17 and 18. This result shows that when the intervals between the recesses are too large, the stress generated by the bending of the substrate is difficult to disperse, and excessive stress is concentrated in each recess. As a result, cracks are generated, and it is thought that short circuits caused by the cracks occur.

[0155] In Experimental Examples 10 and 11, the crack occurrence rate and short circuit rate were suppressed, but the peeling occurrence rate increased. From these results, it is thought that if the distance between the recesses is too narrow, the deflection stress caused by the substrate stress is not only dispersed, but also excessive peeling of the plating layer occurs, resulting in an increase in the peeling rate.

[0156] From the above, it was confirmed that by setting the distance between the recesses to 0.25 μm or more and 2 μm or less as shown in Examples 12 to 16, the crack occurrence rate of the multilayer ceramic capacitor can be further reduced, and a highly reliable multilayer ceramic capacitor with low crack occurrence rate, short circuit rate, and peeling rate can be realized.

[0157] As described above, in the multilayer ceramic capacitor of this embodiment, an organic layer is formed on the base electrode layer, a nickel plating layer is formed on the organic layer, and a void is formed between the organic layer and the nickel plating layer. The presence of the organic layer prevents the deflection stress caused by the bending of the substrate when the multilayer ceramic capacitor is subjected to an external impact, which induces delamination between the nickel plating layer (plating layer) and the organic layer. The delamination between the plating layer and the organic layer allows the generated deflection stress to be dispersed, thereby suppressing cracks from occurring in the multilayer ceramic capacitor. Furthermore, the formation of a void between the organic layer and the nickel plating layer further disperses the deflection stress caused by the bending of the substrate. Therefore, the multilayer ceramic capacitor of this embodiment can further suppress the occurrence of cracks within the laminate. It is believed that the presence of the void facilitates the generated stress to be evenly dispersed at the interface between the plating layer and the base electrode layer or the organic layer.

[0158] As described above, the multilayer ceramic capacitor of this embodiment can reduce the incidence of short circuits in the multilayer ceramic capacitor and suppress deterioration in reliability caused by peeling of the external electrodes due to cracks, making it possible to provide a highly reliable multilayer ceramic capacitor.

[0159] Although the present invention has been described above with reference to the preferred embodiment, it is to be understood that the present invention is not limited to the preferred embodiment described above and that various modifications, variations, and combinations are possible.

[0160] <1> A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate having a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; and external electrodes provided on the first end surface and the second end surface and connected to the internal electrode layers, the external electrodes comprising a base electrode layer, an organic layer formed on the base electrode layer, and a plating layer formed on the organic layer, wherein a gap is formed between the organic layer of the base electrode layer and the plating layer.

[0161] <2> The multilayer ceramic capacitor according to <1>, wherein a recess is formed on the surface of the base electrode layer, and a gap is formed between the organic layer formed on the recess and the plating layer.

[0162] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the size of the void is 0.3 μm or more and 2 μm or less.

[0163] <4> The multilayer ceramic capacitor according to <2> or <3>, wherein a plurality of the recesses are formed, and the recesses are arranged at intervals of 0.25 μm or more and 2 μm or less.

[0164] <5> The organic layer is formed by adding a polyfunctional alkoxysilane Si—(C ｎ H ２ｎ＋１ ) ３ <4> The multilayer ceramic capacitor according to any one of <1> to <4>, which contains an organosilicon compound having the structure shown below and containing a nitrogen element.

[0165] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 30 Dielectric layer 40 Internal electrode layer 50 External electrode 53 Base electrode layer 54 Organic layer 55 Plating layer 70 Recess 80 Void

Claims

1. a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate having a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; external electrodes provided on the first end surface and the second end surface and connected to the internal electrode layers; the external electrodes each include a base electrode layer, an organic layer formed on the base electrode layer, and a plating layer formed on the organic layer; A multilayer ceramic capacitor in which a gap is formed between the organic layer and the plating layer of the base electrode layer.

2. a recess formed on the surface of the base electrode layer; 2. The multilayer ceramic capacitor according to claim 1, wherein a gap is formed between the organic layer formed on the recess and the plating layer.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein the size of the void is 0.3 μm or more and 2 μm or less.

4. A plurality of the recesses are formed, 3. The multilayer ceramic capacitor according to claim 2, wherein the recesses are arranged at intervals of 0.25 μm to 2 μm.

5. 3. The multilayer ceramic capacitor according to claim 1, wherein the organic layer has a structure of polyfunctional alkoxysilane Si-(CnH2n+1)3 and contains an organosilicon compound containing a nitrogen element.