Sample and hold circuit and analog-to-digital conversion device
Patent Information
- Application Number
- JP2024531011
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2024-03-08
- Publication Date
- 2026-02-10
- Estimated Expiration
- 2044-03-08
AI Technical Summary
Existing sample-and-hold circuits improve quantization accuracy by increasing the frequency of the local signal, which leads to deteriorated signal-to-noise ratio due to increased phase noise.
A sample-and-hold circuit with multiple paths and an output circuit that includes switching elements controlled by local signals with different phases, and common drain transistors with a constant current source, to enhance quantization accuracy without increasing local signal frequency.
The proposed solution increases quantization accuracy of the IF signal while reducing phase noise and spurious signals, maintaining a high signal-to-noise ratio.
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Abstract
Description
[Technical field]
[0001] The present disclosure relates to a sample-and-hold circuit and an analog-to-digital conversion device. [Background technology]
[0002] There is a sample-and-hold circuit that converts a high-frequency signal (hereinafter referred to as an "RF signal") into an intermediate-frequency signal (hereinafter referred to as an "IF signal"). As such a sample-and-hold circuit, for example, Patent Document 1 discloses a sample-and-hold circuit that includes a switching element having one end to which a high-frequency signal is applied, and a capacitor having one end connected to the other end of the switching element and the other end grounded, in which the opening and closing of the switching element is controlled in accordance with a local signal. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Japanese Utility Model Application Publication No. 57-166202 Summary of the Invention [Problem to be solved by the invention]
[0004] The sample-and-hold circuit disclosed in Patent Document 1 can improve the quantization accuracy of the IF signal by increasing the frequency of the local signal. However, increasing the frequency of the local signal increases phase noise, which causes a degradation of the signal-to-noise ratio of the IF signal.
[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a sample-and-hold circuit that can improve the quantization accuracy of an IF signal without increasing the frequency of the local signal. [Means for solving the problem]
[0006] The sample-and-hold circuit according to the present disclosure includes a plurality of sample-and-hold paths to which a high-frequency signal is applied, connected in parallel, and an output circuit to output the sum of signals output from the plurality of sample-and-hold paths. Each sample-and-hold path of the sample-and-hold circuit includes a switching element to which a high-frequency signal is applied at one end, and a capacitor having one end connected to the other end of the switching element and the other end grounded, and the switching elements of the plurality of sample-and-hold paths are controlled to open and close in accordance with local signals having different phases from each other. Furthermore, the output circuit of the sample and hold circuit according to the present disclosure includes a plurality of drain-grounded transistors, each having a gate terminal connected to one end of the capacitor and a drain terminal grounded, and a constant current source that supplies a constant current to the source terminals of the plurality of drain-grounded transistors. Effect of the Invention
[0007] According to the present disclosure, it is possible to improve the quantization accuracy of an IF signal without increasing the frequency of a local signal. [Brief description of the drawings]
[0008] [Figure 1] 1 is a configuration diagram showing an analog-to-digital conversion device including a sample-and-hold circuit 1 according to a first embodiment. [Diagram 2] 10A to 10C are explanatory diagrams showing the signal waveforms of an RF signal, an IF signal, and an LO signal when N=4. [Diagram 3] FIG. 1 is an explanatory diagram showing a desired signal contained in an IF signal output from a sample-and-hold circuit disclosed in Patent Document 1 when the frequency of an RF signal is 16.1 GHz, and LO spurious and aliasing spurious contained in the IF signal. [Figure 4] FIG. 2 is an explanatory diagram showing a desired signal contained in an IF signal output from the sample-and-hold circuit 1 shown in FIG. 1 when N=4 and the frequency of the RF signal is 16.1 GHz, and LO spurious and aliasing spurious contained in the IF signal. [Diagram 5] 1 is an explanatory diagram showing the relative signal-to-noise ratio of an IF signal when N=1, 2, 4 and the frequency of an LO signal is 4 GHz. [Figure 6]1 is a configuration diagram showing an analog-to-digital conversion device including a sample-and-hold circuit 1 according to a second embodiment. [Figure 7] 10A to 10C are explanatory diagrams showing the signal waveforms of an RF signal, an IF signal, and an LO signal when N=4. [Figure 8] 7 is an explanatory diagram showing the maximum change in gain and the minimum noise in the analog-to-digital conversion device shown in FIG. 1 and the maximum change in gain and the minimum noise in the analog-to-digital conversion device shown in FIG. 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0009] In order to describe the present disclosure in more detail, embodiments of the present disclosure will be described below with reference to the accompanying drawings.
[0010] Embodiment 1 FIG. 1 is a configuration diagram showing an analog-to-digital conversion device including a sample-and-hold circuit 1 according to a first embodiment. The analog-to-digital conversion device shown in FIG. 1 includes a sample-and-hold circuit 1 and an analog-to-digital converter (hereinafter referred to as an “AD converter”) 2. The sample and hold circuit 1 converts a high frequency signal (hereinafter referred to as an “RF signal”) into an intermediate frequency signal (hereinafter referred to as an “IF signal”), and outputs the IF signal to an AD converter 2 . The AD converter 2 converts the IF signal output from the sample and hold circuit 1 from an analog signal to a digital signal.
[0011] The sample and hold circuit 1 includes N sample and hold paths 11-1 to 11-N, and an output circuit 12 that outputs the sum of the signals output from the sample and hold paths 11-1 to 11-N as an IF signal to the AD converter 2. N is an integer equal to or greater than 2. An example where N=4 is shown in FIG. The N sample-and-hold paths 11-1 to 11-N are connected in parallel and are supplied with the same RF signal. The sample-and-hold path 11-n (n=1, . . . , N) includes a switching element 11a-n and a capacitor 11b-n.
[0012] The switching elements 11a-n (n=1, . . . , N) are realized by, for example, transistors. An RF signal is applied to one end of each of the switching elements 11a-n. The other end of the switching element 11a-n is connected to one end of a capacitor 11b-n and an input end of an adder 12a of the output circuit 12, which will be described later. The N switching elements 11a-1 to 11a-N are controlled to open and close in accordance with local signals (hereinafter referred to as "LO signals") that are out of phase with each other.
[0013] One end of the capacitor 11b-n (n=1, . . . , N) is connected to the other end of the switching element 11a-n and the input end of the adder 12a. The other end of the capacitor 11b-n is grounded. When the switching element 11a-n is in a closed state, the capacitor 11b-n is charged by the RF signal that has passed through the switching element 11a-n. The capacitor 11b-n discharges the electric charge when the switching element 11a-n is in an open state.
[0014] The output circuit 12 includes an adder 12a. The input terminal of the adder 12a is connected to the other terminal of each of the switching elements 11a-n (n=1, . . . , N) and one terminal of the capacitor 11b-n. The output terminal of the adder 12 a is connected to the AD converter 2 . The adder 12a adds up the voltages at one end of the N capacitors 11b-1 to 11b-N, and outputs the sum of the voltages to the AD converter 2.
[0015] Next, the operation of the analog-to-digital conversion device shown in FIG. 1 will be described. Of the LO signals that control the opening and closing of the N switching elements 11a-1 to 11a-N, the phase difference between LO signals that are adjacent in phase is 2π / N, and each LO signal has a duty of 1 / N. For example, if N=4, the phase difference between the LO signal that controls switching element 11a-1 (hereinafter referred to as the "LO1 signal") and the LO signal that controls switching element 11a-2 (hereinafter referred to as the "LO2 signal") is 2π / N, and the phase difference between the LO2 signal and the LO signal that controls switching element 11a-3 (hereinafter referred to as the "LO3 signal") is 2π / N. Furthermore, the phase difference between the LO3 signal and the LO signal (hereinafter referred to as the "LO4 signal") that controls the switching element 11a-4 is 2π / N, and the phase difference between the LO4 signal and the LO1 signal is 2π / N. The LO1 to LO4 signals have a duty of 25 (=1 / N=1 / 4×100)%.
[0016] Specifically, when the phase of the LO1 signal is used as a reference, for example, if the phase of the LO1 signal is 0 degrees, the phase of the LO2 signal is 90 degrees, the phase of the LO3 signal is 180 degrees, and the phase of the LO4 signal is 270 degrees. The period during which the switching elements 11a-n (n=1, . . . , N) are in the open state is one fourth of the entire period. During the period when switching element 11a-1 is in the open state due to the LO1 signal, switching elements 11a-2, 11a-3, and 11a-4 are in the closed state, and during the period when switching element 11a-2 is in the open state due to the LO2 signal, switching elements 11a-1, 11a-3, and 11a-4 are in the closed state. In addition, during the period when switching element 11a-3 is in the open state due to the LO3 signal, switching elements 11a-1, 11a-2, and 11a-4 are in the closed state, and during the period when switching element 11a-4 is in the open state due to the LO4 signal, switching elements 11a-1, 11a-2, and 11a-3 are in the closed state.
[0017] FIG. 2 is an explanatory diagram showing the signal waveforms of an RF signal, an IF signal, and an LO signal when N=4. L.O. n During the period in which switching element 11a-n (n=1,...,4) is closed by the signal, a charge corresponding to the voltage of the RF signal is stored in capacitor 11b-n. During the period in which switching element 11a-n is closed, the voltage at one end of capacitor 11b-n tracks the voltage of the RF signal. This mode in which the voltage at one end of capacitor 11b-n tracks the voltage of the RF signal is called a sample mode. Then, L.O. n When the switching element 11a-n transitions to the open state by a signal, the voltage at one end of the capacitor 11b-n is fixed according to the charge stored in the switching element 11a-n until it becomes the open state. In other words, the voltage of the RF signal immediately before the transition to the open state is held by the capacitor 11b-n, and the voltage at one end of the capacitor 11b-n is fixed to the voltage of the RF signal immediately before it becomes the open state. The mode in which the voltage at one end of the capacitor 11b-n is fixed to the voltage of the RF signal immediately before it becomes the open state is called a hold mode. Therefore, during the period when the switching elements 11a-n are in the closed state, the voltage of the RF signal is applied to the input terminal of the adder 12a, and during the period when the switching elements 11a-n are in the open state, the voltage of the RF signal immediately before transitioning to the open state is applied to the input terminal of the adder 12a.
[0018] During the period when the switching element 11a-1 is in the open state, the capacitor 11 b The voltage held by -1, the voltage of the RF signal that has passed through switching element 11a-2, the voltage of the RF signal that has passed through switching element 11a-3, and the voltage of the RF signal that has passed through switching element 11a-4 are applied to the input terminal of adder 12a. During the period when switching element 11a-2 is in the open state, the voltage of the RF signal that has passed through switching element 11a-1, the voltage held by capacitor 11b-2, the voltage of the RF signal that has passed through switching element 11a-3, and the voltage of the RF signal that has passed through switching element 11a-4 are applied to the input terminal of adder 12a. During the period when switching element 11a-3 is in the open state, the voltage of the RF signal that has passed through switching element 11a-1, the voltage of the RF signal that has passed through switching element 11a-2, the voltage held by capacitor 11b-3, and the voltage of the RF signal that has passed through switching element 11a-4 are applied to the input terminal of adder 12a. During the period when switching element 11a-4 is in the open state, the voltage of the RF signal that has passed through switching element 11a-1, the voltage of the RF signal that has passed through switching element 11a-2, the voltage of the RF signal that has passed through switching element 11a-3, and the voltage held by capacitor 11b-4 are applied to the input terminal of adder 12a.
[0019] Therefore, the input terminal of the adder 12a is applied with the voltage held by a capacitor having one end connected to the other end of any one of the switching elements 11a-1 to 11a-4 that is in the open state, and the voltage of the RF signal that has passed through each of the three switching elements that are in the closed state. The adder 12a adds the four applied voltages. As shown in FIG. 2, the adder 12a outputs the voltage addition result to the AD converter 2 as an IF signal. In the example of FIG. 2, the frequency of the IF signal is one-fourth the frequency of the RF signal.
[0020] The AD converter 2 acquires the IF signal from the sample and hold circuit 1 . The AD converter 2 converts the IF signal from an analog signal to a digital signal, and outputs the digital signal to, for example, a receiver (not shown). The signal waveform of the IF signal output from the sample-and-hold circuit 1 to the AD converter 2 differs from the signal waveform of the IF signal output from the sample-and-hold circuit of Patent Document 1 when the frequency of the local signal is multiplied by N. The AD converter 2 can convert the analog signal into a digital signal by the same AD conversion process even if the waveform of the IF signal output from the sample and hold circuit 1 is different from the signal waveform of the IF signal output from the sample and hold circuit of Patent Document 1.
[0021] FIG. 3 is an explanatory diagram showing a desired signal contained in an IF signal output from the sample-and-hold circuit disclosed in Patent Document 1 when the frequency of the RF signal is 16.1 GHz, and LO spurious and aliasing spurious contained in the IF signal. FIG. 4 is an explanatory diagram showing a desired signal contained in the IF signal output from the sample-and-hold circuit 1 shown in FIG. 1 when N=4 and the frequency of the RF signal is 16.1 GHz, and the LO spurious and aliasing spurious contained in the IF signal. 3 and 4, the horizontal axis represents the frequency [GHz] of the IF signal, and the vertical axis represents the power [dBm] of the IF signal. In the case of the sample-and-hold circuit disclosed in Patent Document 1, as shown in FIG. 3, large LO spurious and large aliased spurious are generated at 4 GHz, 8 GHz, 12 GHz, 16 GHz, and 20 GHz in addition to the desired signal. In the case of the sample and hold circuit 1 shown in FIG. 1, as shown in FIG. 4, the LO spurious and the aliasing spurious are reduced compared to the sample and hold circuit disclosed in Patent Document 1.
[0022] FIG. 5 is an explanatory diagram showing the relative signal-to-noise ratio (hereinafter referred to as "relative SN") of the IF signal when N=1, 2, 4 and the frequency of the LO signal is 4 GHz. FIG. 5 shows that when N=1, the higher the frequency of the RF signal, the more the relative SNR deteriorates. FIG. 5 shows that when N=2, degradation of the relative SNR is suppressed more than when N=1. FIG. 5 shows that when N=4, degradation of the relative SNR is suppressed more than when N=2. When the frequency of the RF signal is RF, the frequency of the LO signal is LO, and the number of sample-and-hold paths 11 is N, a high relative SN can be obtained if the sample-and-hold circuit 1 is provided with as many sample-and-hold paths 11 as N such that the frequency RF of the RF signal satisfies the following equation (1). LO×N <RF<LO×(N+1) (1)
[0023] In the above-described first embodiment, the sample-and-hold circuit 1 is configured to include a plurality of sample-and-hold paths 11-1 to 11-N connected in parallel to receive a high-frequency signal, and an output circuit 12 that outputs the sum of signals output from the plurality of sample-and-hold paths 11-1 to 11-N. Also, the sample-and-hold path 11-n (n=1, . . . , N) of the sample-and-hold circuit 1 includes a switching element 11a-n having one end to which a high-frequency signal is received, and a capacitor 11b-n having one end connected to the other end of the switching element 11a-n and the other end grounded, and the switching elements 11a-n included in the plurality of sample-and-hold paths 11-1 to 11-N are configured to be opened and closed in accordance with local signals having mutually different phases. Therefore, the sample-and-hold circuit 1 can improve the quantization accuracy of the IF signal without increasing the frequency of the local signal.
[0024] Embodiment 2 In the second embodiment, a sample and hold circuit 1 in which an output circuit 12 includes a plurality of common-drain transistors 12b-1 to 12b-N and a constant current source 12c will be described.
[0025] FIG. 6 is a configuration diagram showing an analog-to-digital conversion device including a sample-and-hold circuit 1 according to the second embodiment. The output circuit 12 includes drain-grounded transistors 12b-1 to 12b-N and a constant current source 12c. In FIG.
[0026] The common-drain transistors 12b-n (n=1, . . . , N) form a source-follower circuit. The gate terminal of the common-drain transistor 12b-n is connected to the other end of the switching element 11a-n and one end of the capacitor 11b-n. The source terminal of the common-drain transistor 12b-n is connected to a constant current source 12c. The drain terminal of the common-drain transistor 12b-n is grounded.
[0027] The constant current source 12c is realized by, for example, a current mirror circuit. The constant current source 12c supplies a constant current to the source terminals of the common-drain transistors 12b-1 to 12b-N.
[0028] Next, the operation of the analog-to-digital conversion device shown in FIG. 6 will be described. Except for the common-drain transistors 12b-n (n=1, . . . , N) and the constant current source 12c, the analog-to-digital conversion device is the same as that shown in Fig. 1. Therefore, only the operations of the common-drain transistors 12b-n and the constant current source 12c will be described here.
[0029] In the analog-to-digital conversion device shown in Fig. 1, the output circuit 12 is realized by an adder 12a. Therefore, when the sample-and-hold path 11-n is in the hold mode, the charge stored in the capacitor 11b-n may leak to other sample-and-hold paths via the adder 12a. When the charge leaks to other sample-and-hold paths, the signal-to-noise ratio of the IF signal is degraded.
[0030] The constant current source 12c supplies a constant current to the source terminals of the common-drain transistors 12b-1 to 12b-N. When the voltage of the RF signal that has passed through the switching element 11a-n or the voltage held by the capacitor 11b-n is applied to the gate terminal of the drain-grounded transistor 12b-n (n = 1,...,N), the drain-grounded transistor 12b-n outputs the voltage applied to the gate terminal to the source terminal side. On the other hand, the common-drain transistor 12b-n does not output the voltage of the source terminal to the gate terminal side. Therefore, when the sample-and-hold path 11-n is in the hold mode, there is almost no possibility that the charge stored in the capacitor 11b-n will leak to other sample-and-hold paths via the common-drain transistor 12b-n, causing degradation of the signal-to-noise ratio of the IF signal. FIG. 7 is an explanatory diagram showing the signal waveforms of an RF signal, an IF signal, and an LO signal when N=4.
[0031] As is clear from a comparison between Fig. 7 and Fig. 2, the analog-digital conversion device shown in Fig. 6 has reduced waveform distortion of the IF signal compared to the analog-digital conversion device shown in Fig. 1. For this reason, the analog-digital conversion device shown in Fig. 6 has an improved S / N ratio of the IF signal compared to the analog-digital conversion device shown in Fig. 1.
[0032] FIG. 8 is an explanatory diagram showing the maximum change in gain and the minimum noise in the analog-to-digital conversion device shown in FIG. 1 and the maximum change in gain and the minimum noise in the analog-to-digital conversion device shown in FIG. Figure 8 shows that the maximum change gain of the analog-digital conversion device shown in Figure 6 is improved compared to the maximum change gain of the analog-digital conversion device shown in Figure 1, and the minimum noise of the analog-digital conversion device shown in Figure 6 is lower than the minimum noise of the analog-digital conversion device shown in Figure 1.
[0033] In the above-described second embodiment, the sample-and-hold circuit 1 shown in Fig. 6 is configured so that the output circuit 12 includes a plurality of common-drain transistors 12b-1 to 12b-N, each of which has a gate terminal connected to one end of each of the capacitors 11b-n and a grounded drain terminal, and a constant current source 12c that supplies a constant current to the source terminals of the plurality of common-drain transistors 12b-1 to 12b-N. Therefore, the sample-and-hold circuit 1 shown in Fig. 6 can increase the quantization accuracy of the IF signal without increasing the frequency of the local signal, and can increase the SNR of the IF signal more than the sample-and-hold circuit 1 shown in Fig. 1.
[0034] 6, the sample-and-hold path 11-n includes a capacitor 11b-n. However, this is merely an example, and instead of the capacitor 11b-n, the parasitic capacitance of a common-drain transistor 12b-n may serve as the capacitor 11b-n.
[0035] 6, the output circuit 12 includes a plurality of common-drain transistors 12b-1 to 12b-N. However, this is merely an example, and the output circuit 12 may use, for example, common-source transistors instead of the common-drain transistors 12b-n.
[0036] In addition, the present disclosure allows free combination of the respective embodiments, modification of any of the components of each embodiment, or omission of any of the components of each embodiment. [Industrial Applicability]
[0037] The present disclosure is suitable for a sample-and-hold circuit and an analog-to-digital conversion device. [Explanation of symbols]
[0038] 1 sample and hold circuit, 2 AD converter, 11-1 to 11-4 sample and hold paths, 11a-1 to 11a-4 switching elements, 11b-1 to 11b-4 capacitors, 12 output circuit, 12a adder, 12b-1 to 12b-4 drain-grounded transistors, 12c constant current source.
Claims
1. a plurality of sample-and-hold paths to which high-frequency signals are applied are connected in parallel, and an output circuit is provided to output a sum of signals output from the plurality of sample-and-hold paths; Each of the sample and hold paths comprises: a switching element to one end of which the high-frequency signal is applied; a capacitor having one end connected to the other end of the switching element and the other end grounded, the switching elements included in the plurality of sample-and-hold paths are controlled to be opened or closed in accordance with local signals that are out of phase with each other; The output circuit a plurality of drain-grounded transistors, each having a gate terminal connected to one end of the capacitor and a drain terminal grounded; a constant current source that supplies a constant current to the source terminals of the plurality of common-drain transistors. Sample and hold circuit.
2. The output circuit an adder that adds up voltages at one end of the plurality of capacitors and outputs the sum of the voltages; 2. The sample and hold circuit according to claim 1.
3. When the frequency of the high frequency signal is RF, the frequency of the local signal is LO, and the number of sample-and-hold paths is N, The number of sample-and-hold paths provided is N, which satisfies LO×N<RF<LO×(N+1).
2. The sample and hold circuit according to claim 1.
4. Among the plurality of local signals that control the opening and closing of each of the switching elements, the phase difference between signals having adjacent phases is 2π / N, and each of the local signals has a duty of 1 / N.
4. The sample-and-hold circuit according to claim 3.
5. A sample-and-hold circuit according to any one of claims 1 to 4; an analog-to-digital converter that converts the signal output from the sample-and-hold circuit from an analog signal to a digital signal, Analog-to-digital conversion device.