Semiconductor device

Abstract

Provided is a semiconductor device in which excessive wetting and spreading of solder is suppressed. This semiconductor device comprises: an insulating circuit board (1) having an insulating substrate (11), and an upper conductor layer (12a) and an upper conductor layer (12b) that are provided separated from each other on the upper surface of the insulating substrate (11); a semiconductor chip (3) mounted, using solder, on the upper conductor layer (12a); an external terminal (4) having a bonding section (41), the bonding section (41) being bonded, using solder (2b), to a first bonding region (14), which is one region of the upper surface of the upper conductor layer (12b); a printed circuit board (6) disposed above the semiconductor chip (3); a pin terminal (51) inserted into the printed circuit board (6) and bonded, using solder (9a), to a second bonding region (15), which is another region of the upper surface of the upper conductor layer (12b); and a solder resist (7) provided on the upper surface side of the upper conductor layer (12b) and adjacent to the first bonding region (14).

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device (semiconductor module) equipped with a power semiconductor chip.

[0002] Semiconductor devices equipped with power semiconductor chips (hereinafter simply referred to as "semiconductor chips") are primarily used for variable speed drive applications such as motors and inverters, and for power conversion applications. In addition to the semiconductor chip, components constituting the wiring are also bonded to the substrate of the semiconductor device. Laser light is sometimes irradiated onto the top surface of a metal layer disposed on such a substrate to form a resist.

[0003] Patent Document 1 describes a technique in which one end of an external terminal is bonded to the top surface of an upper conductive layer via a bonding material such as solder, and also describes a technique in which a semiconductor chip is disposed at the center of a semiconductor device and the external terminals are disposed at the periphery of the semiconductor device.

[0004] Patent document 2 describes a power semiconductor device that includes a lower substrate on which a power semiconductor element is mounted, an upper substrate arranged opposite the lower substrate, a plate-shaped connecting member that electrically connects element electrodes formed on the power semiconductor element with a circuit pattern formed on the upper substrate, and a control terminal.

[0005] Patent Document 3 describes a metal plate, a wire, a die pad, a pad, and the like.

[0006] Patent Document 4 describes a technique in which a gate connection terminal and an emitter signal terminal are fixed to a circuit pattern on a printed circuit board, and the ends are also fixed to a first copper plate on an insulating plate.

[0007] Patent document 5 describes a technology in which a low-wettability portion with low wettability to solder is formed on an electrode pad of a semiconductor chip, solder paste containing flux is printed so as to cover the top of the low-wettability portion, and the solder paste is reflowed to form a solder bump that is conductive to the electrode pad, and gas generated from the flux comes into contact with and remains on the top of the low-wettability portion, forming a void in the solder bump.

[0008] Patent Document 6 describes a technology in which a nickel (Ni) plating layer is formed on the surface of a circuit layer of a circuit board for a semiconductor device, and a solder joint portion where a semiconductor element is to be soldered and a portion that has been altered by laser irradiation are arranged adjacent to each other in the planar direction on the formed nickel plating layer.

[0009] Patent Document 7 describes a technology in which a substrate is joined to one main surface of a heat sink with a solder layer, a semiconductor element is joined to one main surface of the substrate with a solder layer, a case is adhered to one main surface of the heat sink so as to surround the substrate, the inner periphery of the case includes an internal electrode that is electrically connected to the semiconductor element, and the bonding surface of one main surface of the heat sink that is bonded to the case has a first region where a resist layer is formed and a second region where no resist layer is formed, and the second region is formed to include a region that overlaps with the internal electrode in a planar view.

[0010] Patent Document 8 describes a technology in which a cell unit is formed by soldering a semiconductor chip to one side of an insulating circuit board having conductive patterns on both sides, and a metal-based cell unit that dissipates heat generated by the semiconductor chip is formed by bonding an insulating inorganic layer using a metal mask to the non-soldered portion, and then the cell unit is soldered to the metal base and sealed with insulating resin.

[0011] Patent Document 9 describes providing a liquid-repellent portion formed by laser irradiation on a circuit board of a ceramic circuit substrate. Patent Document 1 describes a technique in which a liquid-repellent portion is provided between areas where a semiconductor chip and a contact component are respectively arranged.

[0012] Japanese Patent No. 7409035 JP 2015-142018 A JP 2021-068783 A JP 5644440 A JP 2015-076429 A JP 2014-167983 A JP 2019-197831 A JP 2008-172066 A JP 2021-118350 A

[0013] When pin terminals are used instead of wires to form wiring, a portion of the pin terminal is joined to a metal layer of a substrate via a joining material such as solder. The melted solder may spread during reflow.

[0014] In view of the above problems, an object of the present invention is to provide a semiconductor device in which excessive spreading of solder is suppressed.

[0015] One aspect of the present invention is summarized as a semiconductor device comprising: (a) an insulating circuit board having an insulating substrate and a first conductor layer and a second conductor layer provided separately from each other on an upper surface of the insulating substrate; (b) a semiconductor chip mounted on the first conductor layer via solder; (c) an external terminal having a bonding portion, the bonding portion being bonded via solder to a first bonding region that is a region on the upper surface of the second conductor layer; (d) a printed circuit board arranged above the semiconductor chip; (e) a first pin terminal inserted into the printed circuit board and bonded via solder to a second bonding region that is another region on the upper surface of the second conductor layer; and (f) a solder resist provided on the upper surface side of the second conductor layer and adjacent to the first bonding region.

[0016] Furthermore, the second conductor layer is arranged close to a first edge, which is one edge of the insulating substrate, and when the edge of the second conductor layer closer to the first edge is defined as the second edge and the edge opposite the second edge is defined as the third edge, the first bonding region may be a region closer to the second edge, and the second bonding region may be a region closer to the third edge.

[0017] The solder resist may be provided between the first bonding region and the second bonding region.

[0018] The solder resist may be provided between the first bonding region and the second side.

[0019] The external terminals may also be separated from the printed circuit board.

[0020] The joint may also be provided with a boss that protrudes toward the second conductor layer.

[0021] The thickness of the solder interposed between the joint portion and the second conductor layer may be 50 μm or more and 500 μm or less in the portion of the joint portion where the boss is not provided.

[0022] The insulating substrate may also include a resin material.

[0023] Copper may be exposed on the surfaces of the first and second conductor layers.

[0024] The solder resist may also be a laser resist formed by irradiating the upper surface of the second conductor layer with laser light.

[0025] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0026] According to the present invention, it is possible to provide a semiconductor device in which excessive spreading of solder is suppressed.

[0027] FIG. 1 is a cross-sectional view showing a longitudinal cross-sectional configuration of a portion of the semiconductor device according to the first embodiment; FIG. 2 is a plan view showing a portion of an insulating circuit board included in the semiconductor device according to the first embodiment; FIG. 3 is a plan view showing the positional relationship between a first bonding region, a second bonding region, and a solder resist on an upper conductor layer according to the first embodiment; FIG. 4 is a cross-sectional view showing a longitudinal cross-sectional configuration of a portion of a semiconductor device according to a comparative example; FIG. 5 is a plan view showing the positional relationship between a first bonding region, a second bonding region, and a solder resist on an upper conductor layer according to a first modified example of the first embodiment; and FIG. 6 is a plan view showing the positional relationship between a first bonding region, a second bonding region, and a solder resist on an upper conductor layer according to a second modified example of the first embodiment.

[0028] The first embodiment and its modifications will be described below with reference to the drawings. In the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant description will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first embodiment and its modifications shown below are examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components described below.

[0029] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0030] 1, the semiconductor device according to the first embodiment includes an insulating circuit board 1, a semiconductor chip (semiconductor element) 3a mounted on the insulating circuit board 1 via solder 2a, external terminals 4 connected to the insulating circuit board 1 via solder 2b, and a printed circuit board 6 disposed above and spaced apart from the semiconductor chip 3a. The peripheries of the semiconductor chip 3a and the printed circuit board 6 are sealed with a sealing member 8, and are electrically insulated from the surroundings.

[0031] <Insulated Circuit Board> The insulated circuit board 1 includes an insulating substrate 11, upper conductor layers 12a and 12b arranged on the upper surface of the insulating substrate 11, which is the circuit side, and a lower conductor layer 13 arranged on the lower surface of the insulating substrate 11, which is the cooling side. As shown in FIG. 2 , the upper conductor layers 12a and 12b are provided separately from each other and are not electrically conductive to each other. The upper conductor layer 12a is an example of a first conductor layer, and the upper conductor layer 12b is an example of a second conductor layer. Upper conductor layers other than the upper conductor layers 12a and 12b may be provided on the upper surface of the insulating substrate 11. The number of upper conductor layers separated from each other may be three or more.

[0032] The insulating circuit board 1 may be, for example, a direct copper bond (DCB) board or an active matrix brazing (AMB) board. The insulating substrate 11 may be, for example, an aluminum oxide (Al ２ O ３ ), aluminum nitride (AlN), silicon nitride (Si ３ N ４ The insulating substrate 11 may be a ceramic substrate made of a material such as a ceramic material, or a resin insulating substrate made of a resin material such as a polymer material. The resin insulating substrate may contain a ceramic filler such as boron nitride. In this embodiment, the insulating substrate 11 is described as being made of a resin insulating substrate. The upper conductor layers 12a, 12b and the lower conductor layer 13 are made of a conductor foil or conductive plate made of, for example, copper (Cu) or aluminum (Al). The metal (e.g., copper or aluminum) constituting the upper conductor layers 12a, 12b may be exposed on the surfaces (top surfaces) of the upper conductor layers 12a, 12b, or a nickel (Ni) plating layer may be formed thereon. The upper conductor layers 12a, 12b form a predetermined circuit pattern. As shown in FIGS. 1 and 2 , a solder resist 7 is provided on the top surface of the upper conductor layer 12b. The solder resist 7 is a laser resist.

[0033] As shown in Fig. 1, a semiconductor chip 3a is bonded onto the upper conductor layer 12a via solder 2a. An external terminal 4 is bonded onto the upper conductor layer 12b via solder 2b. For example, the semiconductor chip 3a is mounted only on the upper conductor layer 12a out of the upper conductor layers 12a and 12b. The solders 2a and 2b are bonding materials. For example, tin-antimony (SnSb)-based or tin-silver (SnAg)-based solders can be used as the solder.

[0034] The type of the semiconductor chip 3a varies depending on the application, but for example, power semiconductor elements such as insulated gate bipolar transistors (IGBTs), reverse conducting IGBTs (RC-IGBTs), field effect transistors (FETs), static induction (SI) thyristors, gate turn-off (GTO) thyristors, rectifying elements such as free wheel diodes (FWDs), etc. can be used. The semiconductor chips 3a, 3b, and 3c may be made of, for example, a silicon (Si) substrate, or may be made of silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga２ O ３ The semiconductor chip 3a may be, for example, a power semiconductor chip.

[0035] 1 illustrates one semiconductor chip 3a mounted on the upper conductor layer 12a, but the number of semiconductor chips is not particularly limited. For example, as shown in FIG. 2, four semiconductor chips 3a, 3b, 3c, and 3d may be mounted on the upper conductor layer 12a, or five or more semiconductor chips may be mounted. Furthermore, the semiconductor chips may be provided on an upper conductor layer other than the upper conductor layer 12b. When the semiconductor chips 3a, 3b, 3c, and 3d are not to be distinguished from one another, they may be simply referred to as semiconductor chips 3.

[0036] For example, if the semiconductor chip 3 is a field-effect transistor, the semiconductor chip 3 has a control electrode (gate electrode) and a first main electrode (source electrode) on the upper surface and a second main electrode (drain electrode) on the lower surface. If the semiconductor chip 3 is an IGBT or RC-IGBT, the semiconductor chip 3 has a control electrode (gate electrode) and a first main electrode (emitter electrode) on the upper surface and a second main electrode (collector electrode) on the lower surface. If the semiconductor chip 3 is a static induction thyristor, gate turn-off thyristor, or freewheeling diode, the semiconductor chip 3 has a first main electrode (e.g., an anode electrode) on the upper surface and a second electrode (e.g., a cathode electrode) on the lower surface. Of the first and second main electrodes, the first main electrode is the main electrode that is joined to a pin terminal (described later) via solder. In this embodiment, the semiconductor chip 3 is described as a field-effect transistor. As shown in FIG. 2 , the semiconductor chip 3 has a source electrode 31 and a gate electrode 32 on the upper surface.

[0037] 1, a printed circuit board 6 is disposed above the semiconductor chip 3. The printed circuit board 6 includes an insulating layer 61, an upper wiring layer (not shown) disposed on the upper surface of the insulating layer 61, and a lower wiring layer (not shown) disposed on the lower surface of the insulating layer 61. The upper wiring layer and the lower wiring layer form a predetermined circuit pattern.

[0038] The insulating layer 61 is made of, for example, aluminum oxide (Al２ O ３ ), aluminum nitride (AlN), silicon nitride (Si ３ N ４ The upper wiring layer 61 is made of an insulating material such as ceramics or resin mainly composed of copper (Cu) or aluminum (Al). The insulating layer 61 may be a resin substrate made of a combination of glass fiber and epoxy resin. The upper wiring layer and the lower wiring layer are made of conductive foil made of copper (Cu), aluminum (Al), or the like.

[0039] 1 , the printed circuit board 6 is provided with a plurality of through holes (via holes) 6x that penetrate an insulating layer 61, an upper wiring layer, and a lower wiring layer. A plurality of pin terminals (post electrodes) 50 are inserted (press-fitted) into the plurality of through holes 6x of the printed circuit board 6 and fixed therein. The printed circuit board 6 and the pin terminals 50 constitute an implant substrate (6, 50). A conductive layer (not shown) that connects the upper wiring layer and the lower wiring layer may be formed on the inner surface of the through hole 6x, and the conductive layer on the inner surface may be electrically connected to the inserted pin terminals 50, thereby causing the upper wiring layer and the lower wiring layer to have the same potential.

[0040] The pin terminals 50 may be, for example, rod-shaped (pin-shaped) or column-shaped, and may specifically be in the form of a polygonal prism such as a circular cylinder, an elliptical cylinder, a triangular prism, or a square prism. A conductive material such as copper (Cu) can be used as the material for the pin terminals 50. The pin terminals 50 include pin terminals 51 and 52 shown in FIG. 1 and a pin terminal 53 shown in FIG. 2. As shown in FIG. 1, the lower end of the pin terminal 51 is bonded to the upper conductor layer 12b via solder 9a. The pin terminal 51 is an example of a first pin terminal. As shown in FIG. 2, a plurality of pin terminals 51 are provided, and may be arranged in a line, for example, but not limited to, this arrangement. The pin terminals 51 are bonded to the upper conductor layer 12b, which is the upper conductor layer to which the external terminal 4 is bonded, among the plurality of upper conductor layers. Note that the number of pin terminals 51 is not limited to the number shown in FIG. 2. As shown in FIG. 2, the lower end of the pin terminal 52 is bonded to the source electrode 31 of the semiconductor chip 3a via solder 9b. 2 shows solder 2b and 9a before reflow (heat treatment). Four pin terminals 52 are joined to source electrode 31, but the number of pin terminals 52 joined to semiconductor chip 3a may be three or less, or five or more.

[0041] As shown in FIG. 2 , the lower end of pin terminal 53 is bonded to gate electrode 32 of semiconductor chip 3a via solder 9c. A drain electrode (not shown) on the lower surface of semiconductor chip 3a is bonded to upper conductor layer 12a shown in FIG. 1 via solder 2a. Solder 9a, 9b, and 9c are bonding materials. Examples of solder that can be used include tin-antimony (SnSb)-based and tin-silver (SnAg)-based solders. The configurations of semiconductor chips 3b, 3c, and 3d are similar to those of semiconductor chip 3a, and the configurations of pin terminals 50 connected to semiconductor chips 3b, 3c, and 3d are also similar to those of semiconductor chip 3a, so a description thereof will be omitted. Pin terminal 50 may include pin terminals other than pin terminals 51 to 53. For example, pin terminal 50 may include positioning pin terminals (not shown) used to fix the relative positions of insulating circuit board 1 and printed circuit board 6.

[0042] <External Terminal> As shown in FIG. 1 , the external terminal 4 is separated from and not connected to the printed circuit board 6. While the pin terminal 50 is fixed in the through-hole 6x of the printed circuit board 6, the external terminal 4 is not fixed to the printed circuit board 6. The external terminal 4 has a joint portion 41 that is joined to the upper conductor layer 12b via solder 2b, a connection portion 42 that is connected to an external circuit, and an intermediate portion 43 that connects the joint portion 41 and the connection portion 42. The joint portion 41 extends in a direction parallel to the upper conductor layer 12b, and its lower surface is joined to the upper conductor layer 12b via solder 2b. The joint portion 41 has a boss 41a that protrudes (is formed convexly) toward the upper conductor layer 12b. During reflow, the external terminal 4 is pressed toward the upper conductor layer 12b while being fixed with a jig. At this time, the boss 41a approaches the upper conductor layer 12b. The portion of the joint 41 where the boss 41a is not provided cannot approach the upper conductor layer 12b as closely as the boss 41a, even when pressed. By providing the boss 41a in this way, the distance between the portion of the joint 41 where the boss 41a is not provided and the upper conductor layer 12b is prevented from becoming too small. This prevents the amount of solder 2b interposed between the joint 41 and the upper conductor layer 12b from becoming too small. The thickness of the solder 2b in the portion of the joint 41 where the boss 41a is not provided is, for example, approximately 50 μm or more and 500 μm or less.

[0043] The connection portion 42 is located above the joint portion 41. The connection portion 42 extends in a direction parallel to the joint portion 41, and at least a portion of the connection portion 42 is exposed to the outside of the sealing member 8. An external circuit is connected to the portion of the connection portion 42 exposed to the outside of the sealing member 8. The intermediate portion 43 extends in a direction perpendicular to the upper conductor layer 12b, and one end along the perpendicular direction is connected to the joint portion 41, and the other end is connected to the connection portion 42. Note that the joint portion 41 to the connection portion 42 may be formed continuously and integrally. The external terminal 4, the pin terminal 51, and the upper conductor layer 12b form an external terminal connection structure (4, 51, 12b).

[0044] For example, if the semiconductor device according to the first embodiment is a three-terminal inverter, the external terminal 4 may be any one of the anode side (P side) terminal, the cathode side (N side) terminal, and the output terminal. Furthermore, for example, the above-described external terminal connection structure (4, 51, 12b) may be provided for each or some of the anode side (P side) terminal, the cathode side (N side) terminal, and the output terminal. If the semiconductor device according to the first embodiment is a four-terminal inverter, the above-described external terminal connection structure (4, 51, 12b) may be provided for the M terminal. Furthermore, a conductive material such as copper (Cu) can be used as the material for the external terminal 4.

[0045] <First Bonding Region and Second Bonding Region> As shown in FIG. 2 , the upper conductor layer 12b is provided adjacent to the first edge 11a, which is one edge of the insulating substrate 11 in a plan view. "Adjacent" means that no other upper conductor layer is provided between the upper conductor layer 12b and the first edge 11a. The top surface of the insulating substrate 11 is exposed around the upper conductor layer 12b and between the upper conductor layer 12b and the first edge 11a. The upper conductor layer 12a is provided on the top surface of the insulating substrate 11, on the side opposite the first edge 11a, with the upper conductor layer 12b in between. The upper conductor layer 12a is adjacent to the upper conductor layer 12b with a gap therebetween. FIG. 3 is an enlarged plan view showing the upper conductor layer 12b. The joint portion 41 (not shown) of the external terminal 4 is joined via solder 2b to a first joint region 14, which is one region on the top surface of the upper conductor layer 12b. The lower end of the pin terminal 51 (not shown) is joined via solder 9a to a second joint region 15, which is another region on the top surface of the upper conductor layer 12b. If, among the sides of the upper conductor layer 12b in a plan view, the side closer to the first side 11a is defined as a second side 12b1 and the side opposite the second side 12b1 is defined as a third side 12b2, the first joint region 14 is the region closer to the second side 12b1 and the second joint region 15 is the region closer to the third side 12b2.

[0046] The first and second bonding regions 14 and 15 are regions where the external terminals 4 and pin terminals 51 are expected to be connected. While the first and second bonding regions 14 and 15 are shown as rectangular regions using dashed lines in FIG. 3 , the shapes of the first and second bonding regions 14 and 15 are not limited to this. The first and second bonding regions 14 and 15 are regions where the solder 2b and 9a are disposed. FIG. 3 shows the solder 2b and 9a before reflow. The solder 2b and 9a may wet and spread to the outside of the first and second bonding regions 14 and 15 by reflow. Furthermore, the multiple solders 9a provided for each pin terminal 51 may wet and spread and connect to each other by reflow.

[0047] <Solder Resist> As shown in FIG. 3 , a solder resist 7 is provided on the upper surface of the upper conductor layer 12 b. More specifically, the solder resist 7 is provided adjacent (close to) the first bonding region 14 on the upper surface of the upper conductor layer 12 b. In this embodiment, the solder resist 7 is provided between the first bonding region 14 and the second bonding region 15. As shown in FIG. 2 , the solder resist 7 extends along the X direction. The dimension of the solder resist 7 along the X direction (longitudinal dimension) may be equal to or greater than the width of the bonding portion 41 of the external terminal 4 along the X direction, or may be equal to or greater than the width of the lower ends of the pin terminals 51 along the X direction. Furthermore, for example, the longitudinal dimension of the solder resist 7 may be equal to or greater than the larger of the width of the bonding portion 41 of the external terminal 4 along the X direction and the width of the lower ends of the multiple pin terminals 51 along the X direction. In addition, when there are multiple pin terminals 51, the width occupied by the lower end of each pin terminal 51 in the X direction is the width occupied by the multiple pin terminals 51 in the X direction. The dimension of the solder resist 7 in the Y direction (the dimension in the short direction) may be determined depending on the distance between the joint portion 41 of the external terminal 4 and the pin terminal 51. In other words, the dimension in the short direction of the solder resist 7 may be determined depending on the distance between the first joint region 14 and the second joint region 15. To save space, it is desirable to make the distance between the joint portion 41 of the external terminal 4 and the pin terminal 51 as small as possible. The dimension in the short direction of the solder resist 7 is set to, for example, approximately 0.1 mm or more and 1 mm or less. The provision of the solder resist 7 makes it difficult for the solder 2b and the solder 9a melted by reflow to connect to each other.

[0048] <Method for Manufacturing Solder Resist> The method for manufacturing the solder resist 7 will be described below. As shown in FIG. 1, the solder resist 7 is a laser resist formed by irradiating the upper surface of the upper conductor layer 12b with laser light. Two examples of the wavelength, power, and frequency of the laser, and the scanning conditions of the laser light, are shown below. The solder resist 7 is configured, for example, by arranging a plurality of lines formed by laser irradiation along the longitudinal direction. Condition Example 1: Wavelength: 1064 (nm) Power: 5 (W) Frequency: 5 (kHz) Scanning speed: 8 (mm / s) Line pitch: 100 (μm) Condition Example 2: Wavelength: 532 (nm) Power: 4.8 (W) Frequency: 30 (kHz) Scanning speed: 300 (mm / s) Line pitch: 10 (μm)

[0049] When the upper surface of the upper conductor layer 12b is irradiated with laser light, irregularities are formed on the upper surface of the upper conductor layer 12b, reducing the wettability of the solder. In addition, an oxide film is formed on the upper surface of the upper conductor layer 12b, reducing the wettability of the solder.

[0050] Comparative Example A comparative example shown in FIG. 4 will now be described. In the semiconductor device according to the comparative example, solder resist 7 is not formed on the upper surface of the upper conductor layer 12b. Without solder resist 7, the melted solder 2b and the melted solder 9a may spread and connect to each other after reflow. If the melted solder 2b and the melted solder 9a connect, the solder may be attracted from either the external terminal 4 side or the pin terminal 51 side to the other. For example, the solder may be attracted and move from the external terminal 4 side to the pin terminal 51 side. If the solder is attracted and moves, the solder may be unevenly distributed between the external terminal 4 side and the pin terminal 51 side. Furthermore, the solder 2b and the solder 9a may become thinner overall as they spread. This thinning of the solder 2b and the solder 9a may reduce the reliability of the solder joint and the bondability between the external terminal 4 and the pin terminal 51 and the upper conductor layer 12b.

[0051] Furthermore, if electrical connection is made using wire bonding, it is possible to increase the degree of freedom and to suppress the influence of solder flow, but wire bonding requires a certain amount of wiring space.

[0052] 3 , the semiconductor device according to the first embodiment of the present disclosure includes a solder resist 7 provided on the upper surface of the upper conductor layer 12b and adjacent to the first bonding region 14. Because the wettability of the solder resist 7 is lower than that of the upper surfaces of the other upper conductor layers 12b, the solders 2b, 9a are prevented from spreading too much and are less likely to connect to each other (to form bridges). This prevents the film thickness of the solders 2b, 9a from becoming too thin, stabilizes the fillet shapes of the solders 2b, 9a, and prevents a decrease in the yield rate of the semiconductor device.

[0053] 3 , the solder resist 7 is provided between the first bonding region 14 and the second bonding region 15. The solders 2b, 9a are unlikely to move beyond the solder resist 7 and are unlikely to connect to each other. This prevents the film thickness of the solders 2b, 9a from becoming too thin, stabilizes the fillet shape of the solders 2b, 9a, and prevents a decrease in the yield rate of the semiconductor device.

[0054] Furthermore, the semiconductor device according to the first embodiment of the present technology includes the printed circuit board 6 arranged above the semiconductor chip 3, and the pin terminals 51 inserted into the printed circuit board 6 and joined via solder 9 a to the second joining region 15, which is another region on the top surface of the upper conductor layer 12 b. Therefore, wiring can be configured with a higher density than when electrical connection is made using wire bonding.

[0055] Furthermore, according to the semiconductor device according to the first embodiment of the present technology, the solder resist 7 is a laser resist, so the step of forming the solder resist 7 can be easily carried out.

[0056] 5, the semiconductor device according to the first modification of the first embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that the solder resist 7 is provided both between the first bonding region 14 and the second bonding region 15 and between the first bonding region 14 and the second side 12b1. The other configurations of the semiconductor device according to the first modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0057] As shown in FIG. 1 , external terminals 4 connected to an external circuit must be located near the end (first side 11 a) of insulating circuit board 1 (insulating substrate 11) in a plan view. Furthermore, lower conductor layer 13 overlaps the entire lower surface of insulating substrate 11. The area of ​​lower conductor layer 13 in a plan view is the same as that of insulating substrate 11, and it is located so as to cover the entire lower surface of insulating substrate 11. End 13 a of lower conductor layer 13 overlaps first side 11 a of insulating substrate 11 in a plan view. Upper conductor layer 12 b does not extend to first side 11 a, and as shown in FIG. 2 , the upper surface of insulating substrate 11 is exposed between first side 11 a and second side 12 b 1. By exposing the upper surface of insulating substrate 11 between first side 11 a and second side 12 b 1, the distance between lower conductor layer 13 and upper conductor layer 12 b is increased, ensuring insulation.

[0058] The melted solder 2b during reflow may wet and spread onto the insulating substrate 11 exposed between the first side 11a and the second side 12b1. If the solder 2b wets and spreads onto the insulating substrate 11, the distance that ensures insulation between the lower conductor layer 13 and the upper conductor layer 12b becomes smaller.

[0059] In contrast to this, according to the semiconductor device according to the first modification of the first embodiment of the present technology, the solder resist 7 is provided between the first bonding region 14 and the second side 12b1, so that it is possible to prevent the solder 2b from wetting and spreading onto the insulating substrate 11, and it is possible to prevent a decrease in the insulation between the lower conductor layer 13 and the upper conductor layer 12b. Furthermore, even the semiconductor device according to the first modification of the first embodiment has the same effects as the semiconductor device according to the first embodiment.

[0060] 6, the semiconductor device according to the second modification of the first embodiment differs from the semiconductor device according to the first modification of the first embodiment shown in Fig. 5 in that the solder resist 7 is provided only between the first bonding region 14 and the second side 12b1. The other configurations of the semiconductor device according to the second modification of the first embodiment are the same as those of the semiconductor device according to the first modification of the first embodiment, and therefore, redundant explanations will be omitted.

[0061] As described above, the present invention has been described by the first embodiment and its modifications, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0062] For example, the configurations disclosed in the first embodiment and its modifications can be combined as appropriate within the scope of not causing any contradiction. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description.

[0063] 3, 3a, 3b, 3c, 3d Semiconductor chip 6 Printed circuit board 7 Solder resist 1 Insulated circuit board 11 Insulated substrate 11a First side 12a Upper conductor layer (first conductor layer) 12b Upper conductor layer (second conductor layer) 12b1 Second side 12b2 Third side 13 Lower conductor layer 13a End 14 First bonding area 15 Second bonding area 4 External terminal 41 Bonding portion 41a Boss 50, 52, 53 Pin terminal 51 Pin terminal (first pin terminal)

Claims

1. A semiconductor device comprising: an insulating circuit board having an insulating substrate, and a first conductor layer and a second conductor layer provided separately from each other on the upper surface of the insulating substrate; a semiconductor chip mounted on the first conductor layer via solder; an external terminal having a bonding portion, the bonding portion being bonded via solder to a first bonding area that is one area on the upper surface of the second conductor layer; a printed circuit board arranged above the semiconductor chip; a first pin terminal inserted into the printed circuit board and bonded via solder to a second bonding area that is another area on the upper surface of the second conductor layer; and a solder resist provided on the upper surface of the second conductor layer and adjacent to the first bonding area.

2. The semiconductor device according to claim 1, wherein the second conductor layer is provided adjacent to a first edge which is one edge of the insulating substrate, and when the edge of the second conductor layer closer to the first edge is defined as a second edge and the edge opposite the second edge is defined as a third edge, the first bonding region is a region closer to the second edge and the second bonding region is a region closer to the third edge.

3. The semiconductor device according to claim 1 or 2, wherein the solder resist is provided between the first bonding region and the second bonding region.

4. The semiconductor device according to claim 2, wherein the solder resist is provided between the first bonding region and the second side.

5. The semiconductor device according to claim 1 or 2, wherein the external terminals are separated from the printed circuit board.

6. The semiconductor device according to claim 1 or 2, wherein the joint portion is provided with a boss that protrudes toward the second conductor layer.

7. The semiconductor device according to claim 6, wherein the thickness of the solder interposed between the joint portion and the second conductor layer is 50 μm or more and 500 μm or less in the portion of the joint portion where the boss is not provided.

8. The semiconductor device according to claim 1 or 2, wherein the insulating substrate includes a resin material.

9. The semiconductor device according to claim 1 or 2, wherein copper is exposed on the surfaces of the first conductor layer and the second conductor layer.

10. The semiconductor device according to claim 1 or 2, wherein the solder resist is a laser resist formed by irradiating the upper surface of the second conductor layer with laser light.