Receiver circuit

Abstract

A receiving circuit includes a plurality of data lane modules, a clock lane module, a bias current controller, and a link layer, each of which receives data signals. The clock lane module receives a clock signal and provides a divided clock signal to each of the plurality of data lanes based on the clock signal. The bias current controller controls the bias current provided to the clock lane. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module based on the levels of low-power data signals output from the plurality of data lane modules and the low-power clock signal output from the clock lane module. Based on the bias control signal, the bias current controller blocks the bias current in a first power mode, provides the bias current having a first magnitude to the clock lane module in a second power mode, and provides the bias current having a second magnitude greater than the first magnitude to the clock lane module in a third power mode.

Description

Technology Field

[0001] The present invention relates to a receiving circuit, and more specifically, to a receiving circuit based on the MIPI (mobile industry processor interface) protocol. Background Technology

[0002] Recently, various types of electronic devices are being used. Electronic devices perform specific functions according to the operations of the electronic circuits included in them. Electronic devices operate independently or while communicating with other electronic devices. Electronic devices may adopt interface protocols to communicate with other electronic devices.

[0003] For example, a transmitting device can transmit a signal to a receiving device according to an interface protocol. The receiving device can process the received signal to obtain data corresponding to the received signal. Accordingly, the transmitting device and the receiving device can communicate with each other according to an interface protocol to exchange data. The power mode of the receiving device may be changed based on the received signal. When the power mode of the receiving device is changed, the power consumption of the receiving device may increase. The problem to be solved

[0004] One objective of the present invention is to provide a receiving circuit capable of reducing power consumption when the power mode is changed. means of solving the problem

[0005] To achieve the above objective, a receiving circuit according to embodiments of the present invention comprises a plurality of data lane modules, a clock lane module, a bias current controller, and a link layer, each of which receives data signals. The clock lane module receives a clock signal and provides a divided clock signal to each of the plurality of data lanes based on the clock signal. The bias current controller controls the bias current provided to the clock lane. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module based on the levels of low-power data signals output from the plurality of data lane modules and the low-power clock signal output from the clock lane module. Based on the bias control signal, the bias current controller blocks the bias current in a first power mode, provides the bias current having a first magnitude to the clock lane module in a second power mode, and provides the bias current having a second magnitude greater than the first magnitude to the clock lane module in a third power mode.

[0006] A receiving circuit according to embodiments of the present invention comprises a plurality of trio modules, each receiving three or more signals, a bias current controller, and a link layer. The bias current controller controls the bias current provided to each of the plurality of trio modules. The link layer provides a bias control signal to the bias current controller based on the levels of low-power signals output from the plurality of trio modules. Based on the bias control signal, the bias current controller blocks the bias current in a first power mode, outputs a bias current having a second magnitude in a second power mode, and outputs a bias current having a third magnitude in a third power mode.

[0007] A receiving circuit according to embodiments of the present invention includes a plurality of data lane modules, a clock lane module, a bias current controller, and a link layer, each of which receives data signals. The clock lane module receives a clock signal and provides a divided clock signal to each of the plurality of data lanes based on the clock signal. The bias current controller controls the bias current provided to the clock lane. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module based on a power mode of the clock lane module and the data lane modules, which is determined by the levels of low-power data signals output from the plurality of data lane modules and the low-power clock signal output from the clock lane module. Based on the bias control signal, the bias current controller blocks the bias current in a first power mode, provides the bias current having a first magnitude to the clock lane module in a second power mode, and provides the bias current having a second magnitude greater than the first magnitude to the clock lane module in a third power mode. The clock lane module gates the divided clock signals provided to the data lane modules based on the clock gating signal in the second power mode, and in the second power mode, the clock lane module operates in a high-speed mode and the data lane modules operate in a low-power mode. Effects of the invention

[0008] In a receiving circuit or electronic device according to the MIPI D-HPY or MIPI C-PHY protocol according to embodiments of the present invention, in a second power mode in which only the clock lane module operates in a high-speed mode, a bias current having a first size is provided to the high-speed receiver of the clock lane module and the high-speed clock signals provided to the high-speed receivers of the data lane modules are gated, and in a second power mode in which the clock lane module and the data lane modules operate in a high-speed mode, a bias current having a second size larger than the first size is provided to the high-speed receiver of the clock lane module and a bias current having a third size equal to the second size is provided to the high-speed receivers of the data lane modules, thereby reducing current consumption in the second power mode and reducing skew between the clock lane module and the data lane modules in the third power mode. Brief explanation of the drawing

[0009] FIGS. 1 and FIGS. 2 are block diagrams showing an electronic device including an interface circuit according to embodiments of the present invention. FIGS. 3 and FIGS. 4 are drawings provided to explain the operation of an interface circuit according to an embodiment of the present invention. FIG. 5 is a block diagram showing a display system according to embodiments of the present invention. Figure 6 shows the Universal Lane Module Functions of MIPI. FIG. 7 is a block diagram showing the DDI of FIG. 5 according to embodiments of the present invention. FIG. 8 shows the configuration of the physical layer and the link layer in the DDI of FIG. 6 according to embodiments of the present invention. FIG. 9 is a circuit diagram showing the configuration of one of the data lane modules in the physical layer of FIG. 8 according to embodiments of the present invention. FIG. 10 is a circuit diagram showing the configuration of a clock lane module in the physical layer of FIG. 8 according to embodiments of the present invention. FIG. 11 is a circuit diagram showing the configuration of a third receiver in the clock lane module of FIG. 10 according to embodiments of the present invention. FIG. 12 is a timing diagram showing signals of the physical layer and the link layer of FIG. 8 according to embodiments of the present invention. FIG. 13 is a flowchart illustrating the operation method of a receiving circuit according to embodiments of the present invention. FIG. 14 is a block diagram showing the configuration of a display in the display system of FIG. 5 according to embodiments of the present invention. FIG. 15 shows an electronic device according to embodiments of the present invention. FIG. 16 is a block diagram showing the configuration of a receiving circuit in the electronic device of FIG. 15 according to embodiments of the present invention. FIG. 17 is a circuit diagram showing the configuration of one of the trio modules in the physical layer of FIG. 16 according to embodiments of the present invention. FIG. 18 is a circuit diagram showing the configuration of a first high-speed receiver in the trio module of FIG. 17 according to embodiments of the present invention. FIG. 19 is a timing diagram showing signals of the physical layer and the link layer of FIG. 16 according to embodiments of the present invention. FIG. 20 is a block diagram showing an example of an interface used in a computing system according to embodiments of the present invention. Specific details for implementing the invention

[0010] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions of identical components are omitted.

[0011] FIGS. 1 and FIGS. 2 are block diagrams showing an electronic device including an interface circuit according to embodiments of the present invention.

[0012] Referring to FIG. 1, the electronic device (10) may include an application processor (20) and a display driving integrated circuit (hereinafter 'DDI', 30).

[0013] The interface circuit (21) of the application processor (20) can exchange data with the interface circuit (31) of the DDI (30). The interface circuits (21, 31) can exchange data with each other according to a predetermined protocol. For example, the interface circuit (21) of the application processor (20) and the interface circuit (31) of the DDI (30) can exchange data according to a protocol defined in the MIPI standard. Each of the interface circuits (21, 31) may include a transmitting circuit and a receiving circuit.

[0014] Next, referring to FIG. 2, an application processor (50) in an electronic device (40) can exchange data with an image sensor (60). An interface circuit (51) of the application processor (50) and an interface circuit (61) of the image sensor (60) can exchange data with each other. Similar to what was described with reference to FIG. 1, each of the interface circuits (51, 61) may include a transmitting circuit and a receiving circuit.

[0015] FIGS. 3 and FIGS. 4 are drawings provided to explain the operation of an interface circuit according to an embodiment of the present invention.

[0016] First, FIG. 3 may be a diagram for explaining the operation of an interface circuit (70) that transmits data and clock signals using a differential signal method. For example, an embodiment described with reference to FIG. 3 may be applied to a D-PHY interface according to the MIPI standard, etc.

[0017] Referring to FIG. 3, a plurality of transmitters (TX0-TX9) can output data (D0P-D3P, D0N-D3N) and clock signals (CKN, CKP) through a plurality of transmission pads (TP0-TP9).

[0018] Transmission pads (TP0~TP9) can be connected to multiple reception pads (RP0~RP9) through multiple lanes (L0~L9) of data lanes (L0~L3, L5~L9) and clock lanes (L4, L5), and the reception pads (RP0~RP9) can be connected to multiple receivers (RX0~RX4). For example, each of the receivers (RX0~RX4) can be connected to one pair of the reception pads (RP0~RP9), and the receivers (RX0~RX4) can generate data (D0~D3) and clock signal (CK) using a differential signal method.

[0019] Accordingly, in one embodiment illustrated in FIG. 3, 10 transmission pads (TP0–TP9), 10 data lanes (L0–L9), and 10 reception pads (RP0–RP9) may be required to transmit data using a differential signal method. Depending on the embodiment, dummy pads may be added to the transmission pads (TP0–TP9) and reception pads (RP0–RP9) to achieve an electrical shielding effect.

[0020] For example, the interface circuit (70) illustrated in FIG. 3 can be applied to an application processor, a display driver, an image sensor, etc.

[0021] Next, FIG. 4 may be a drawing provided to explain the operation of an interface device (80) that transmits data using a single-ended signal method. For example, an embodiment described with reference to FIG. 4 may be applied to a C-phy interface according to the MIPI standard, etc.

[0022] Referring to FIG. 4, a plurality of transmitters (TX0 to TX8) can output data (A0 to C0, A1 to C1, A2 to C2) through a plurality of transmission pads (TP0 to TP8). Since image data is output using a single-ended signal method, there may not be a separate lane for outputting a clock signal in the interface according to the embodiment shown in FIG. 4.

[0023] Transmission pads (TP0~TP8) can be connected to multiple reception pads (RP0~RP8) through multiple data lanes (L0~L8), and reception pads (RP0~RP8) can be connected to multiple receivers (RX0~RX8). Transmission pads (TP0~TP8) can be divided into multiple groups (TP0~TP2, TP3~TP5, TP6~TP8) according to data (A0~C0, A1~C1, A2~C2), and reception pads (RP0~RP8) can also be divided into multiple groups (RP0~RP2, RP3~RP5, RP6~RP8).

[0024] Each of the receivers (RX0~RX8) can receive a pair of receiving pads (RP0~RP8) included in each of the groups (RP0~RP2, RP3~RP5, RP6~RP8). For example, the first receiver (RX0) can output the difference (AB0) between signal A0 and signal B0, and the second receiver (RX1) can output the difference (BC0) between signal B0 and signal C0. Additionally, the third receiver (RX2) can output the difference (CA0) between signal C0 and signal A0.

[0025] In the embodiment illustrated in FIG. 4, nine transmission pads (TP0~TP8), nine data lanes (L0~L8), and nine receiving pads (RP0~RP8) may be required to transmit data using a single-ended signal method. However, even in the single-ended signal method, dummy pads may be added to achieve an electrical shielding effect depending on the embodiment. The interface circuit (80) illustrated in FIG. 4 can also be applied to an application processor, DDI, image sensor, etc.

[0026] Meanwhile, the interface circuits (70, 80) according to the embodiments described with reference to FIGS. 3 and 4 can also be applied to communication between the application processor and devices other than the DDI and image sensor. For example, the interface circuits (70, 80) can also be applied to interfaces such as PCI-Express, USB, and DisplayPort.

[0027] Each of the transmission pads (TP0~TP8) can be referred to as a transmission terminal, and each of the reception pads (RP0~RP8) can be referred to as a reception terminal.

[0028] FIG. 5 is a block diagram showing a display system according to embodiments of the present invention, and FIG. 6 and FIG. 7 show Universal Lane Module Functions of MIPI.

[0029] Referring to FIG. 5, the display system (100) may include a host (200), a DDI (300), and a display (500). The display system (100) may be implemented as a mobile device capable of using MIPI or the MIPI protocol.

[0030] The above mobile device may be implemented as a mobile phone, smartphone, tablet PC, PDA (personal digital assistant), EDA (enterprise digital assistant), digital still camera, digital video camera, PMP (portable multimedia player), PND (personal navigation device or portable navigation device), mobile internet device (MID), or wearable computer, etc.

[0031] The host (200) can control the operation of the DDI (300). The host (200) and the DDI (300) can communicate with each other through a MIPI interface (215). For example, the host (200) can be implemented as an integrated circuit, a system on chip (SoC), an application processor (AP), or a mobile AP.

[0032] In this specification, for convenience of explanation, a MIPI interface or a MIPI protocol is described as an example, but the technical concept of the present invention (i.e., a technique for transmitting information regarding whether an interface connected between a host and a timing controller is abnormal and / or information regarding whether the DDI is abnormal to the host) may be applied to a display system including an interface other than a MIPI interface.

[0033] The host (200) includes a central processing unit (hereinafter CPU; 2105), a MIPI master side transmission interface (hereinafter referred to as 'MIPI TX'; 220), an interrupt detector (230), and a data processing circuit (240).

[0034] The CPU (210) can control the MIPI TX (220), interrupt detector (230), and / or data processing circuit (240) via the bus (201). The CPU (210) may include one or more cores. The MIPI TX (220) may include one clock lane module and one or more data lane modules.

[0035] Each lane module may include a high-speed transmitter (HS-TX), a high-speed receiver (HS-RX), a low-power transmitter (LP-TX), a low-power receiver (LP-RX), and a low-power contention detector (LP-CD), as illustrated in FIG. 6.

[0036] The transmitter (TX) includes LP-TX and HS-TX, the receiver (RX) includes HS-RX, LP-RX, and a termination resistor (or termination impedance; RT), and the contention detector (CD) includes LP-CD. The termination resistor (RT) can be enabled only when each lane is in HS receive mode.

[0037] The D-PHY transceiver of Fig. 6 can be controlled by lane control and interface logic.

[0038] This specification refers to the specification provided by the MIPI alliance.

[0039] The interrupt detector (230) receives the interrupt (ITR) transmitted from the DDI (300) through a dedicated line (301) and can transmit a signal corresponding to the interrupt (ITR) to the CPU (210) and / or MIPI TX (220).

[0040] The CPU (210) can interpret a signal corresponding to an interrupt (ITR), determine the state of the MIPI interface (215) and / or the state of the DDI (300) based on the result of the interpretation, and control the operation of the MIPI TX (220) and / or the operation of the data processing circuit (240) based on the result of the determination.

[0041] The data processing circuit (240) may refer to a functional circuit capable of processing data (e.g., still image data, video data, or parameters) to be transmitted to the DDI (300) via the MIPI TX (220).

[0042] A MIPI interface (215) connected between a host (200) and a DDI (300) includes one clock lane and one or more data lanes. The clock lane transmits a MIPI clock (CK) to the DDI (300) having different frequencies and swing levels depending on the operating mode (e.g., lower power (LP) mode and high-speed (HS) mode). Each data lane transmits MIPI data (DATA0, DATA1, ...) to the DDI (300) having different frequencies and swing levels depending on the operating mode.

[0043] The DDI (300) includes a MIPI slave side receiving interface (hereinafter referred to as MIPI RX, 400) and a display controller (350). The detailed structure and operation of the DDI (300) will be explained with reference to FIG. 7.

[0044] The MIPI RX (400) includes one clock lane module and one or more data lane modules. Each lane module includes HS-TX, HS-RX, LP-TX, LP-RX, and LP-CD, as illustrated in FIG. 7. The DDI (300) transmits display data to the display (500) through the display interface (360). The DDI (300) can be implemented as a chip.

[0045] For example, the display interface (360) may be implemented as an eRVDS (enhanced reduced voltage differential signal transmission), but this is an example for convenience of explanation and the technical concept of the present invention is not limited thereto.

[0046] Additionally, the DDI (300) can retransmit the previous line data of the current line data being transmitted to the display (500) in response to an activated event signal (DETP) transmitted from the display (500) via a dedicated line (361).

[0047] The display (500) includes a display panel (510), a receiving interface (515), a clock generator (520), and a detector (530). The display panel (510) can display an image corresponding to the display data received through the receiving interface (515).

[0048] The receiving interface (515) can convert display data into a form suitable for the display panel (401). The clock generator (520) supplies a display clock (DCLK) to a processing circuit (not shown) capable of processing the display data. For example, the clock generator (520) can be implemented as a PLL (phase-locked loop) or a DLL (delay-locked loop).

[0049] The detector (530) monitors whether the clock generator (520) maintains a lock state and can generate an activated event signal (DETP) when the lock state is lost. For example, when the clock generator (520) is affected by external noise, the clock generator (520) may lose the lock state. The external noise may be transient noise such as electrostatic discharge (ESD).

[0050] FIG. 7 is a block diagram showing the DDI of FIG. 5 according to embodiments of the present invention.

[0051] Referring to FIGS. 5 and 7, the DDI (300) includes a MIPI RX (400), an interrupt generation circuit (310), a second detection circuit (315), a data processing circuit (320), a register bank (330), a checksum circuit (335), a processing circuit (340), a line memory (345), and a display controller (350). The DDI (300) may be implemented as an integrated circuit or a semiconductor chip.

[0052] The MIPI RX (400) can receive the MIPI clock (CK) and data (DATA0, DATA1, ...) transmitted from the host (200) through the MIPI interface (215). The MIPI RX (400) can transmit the data transmitted through the MIPI interface (215) as a video stream to the display (500) through the display controller (350).

[0053] The MIPI RX (400) includes a PHY layer (410), a first detection circuit (467), a data link layer (or link layer, 480), and an application layer (490).

[0054] The structure and function of each layer (410, 480 and 490), excluding the first detection circuit (467), may be substantially identical or similar to the structure and function of the corresponding layer as defined in the MIPI specification.

[0055] The first detection circuit (467) detects whether there is an abnormality in the MIPI interface (215) and / or the DDI (300), generates a first detection signal (DET1) based on the result of the detection, and can transmit the first detection signal (DET1) to the PHY layer (410) and / or the interrupt circuit (310). The abnormality may be determined based on external noise.

[0056] In the embodiments, the first detection circuit (310) may be implemented in the same layer as the PHY layer (410), in the same layer as the data link layer (480), or between the PHY layer (410) and the data link layer (480).

[0057] The second detection circuit (315) can analyze data output from the MIPI RX (400) (e.g., still image data, video data, or video stream) and generate a second detection signal (DET2) based on the result of the analysis.

[0058] The data processing circuit (320) may include a write controller (321), a frame memory (323), a read controller (325), and a CRC circuit (327).

[0059] The data processing circuit (320) can write data output from the MIPI RX (400) to the frame memory (323) or read data written to the frame memory (323). According to embodiments, the data may mean still image data, video data, or a video stream.

[0060] The write controller (321) can perform the function of writing data output from the MIPI RX (400) to the frame memory (323).

[0061] The read controller (325) can perform the function of reading data written in the frame memory (323) and transmitting the read data to the processing circuit (340).

[0062] According to an embodiment, the write controller (321) and the read controller (325) may be implemented as a single controller.

[0063] The CRC circuit (327) can perform a cyclic redundancy check (CRC) on data (e.g., still image data, video data, or video stream) stored in the frame memory (323) and generate an error detection signal (DET3) based on the result of the check.

[0064] The register bank (330) can store parameter(s) required for the operation of the DDI (300). Depending on the embodiment, the register bank (330) may be implemented as a special function register (SFR) or a special purpose register (SPR).

[0065] The above parameter(s) may include information about the frame rate of the data to be processed by the DDI (300), information about the setting of the clock generator (e.g., phase-locked loop (PLL)) implemented in the DDI (300), and / or information about the resolution of the display panel (510).

[0066] When the parameters stored in the register bank (330) are changed by external noise, the DDI (300) cannot perform normal operation depending on the importance of the parameters.

[0067] The checksum circuit (335) periodically scans (scans or reads) parameters stored in the register bank (330) and can compare a first checksum currently calculated for the parameters with a second checksum previously calculated for the parameters. The checksum circuit (335) outputs an activated error detection signal (DET4) based on the comparison.

[0068] The processing circuit (340) processes the data output from the data processing circuit (320) and can transmit the processed data to the line memory (345).

[0069] The processing circuit (340) can control the operation of the line memory (345) in response to an activated event signal (DETP) output from the display (500) and received through the dedicated line (361).

[0070] The display controller (350) can transmit line data (e.g., display data) output line by line from the line memory (345) to the interface (515) of the display (510) through the display interface (360).

[0071] FIG. 8 shows the configuration of the physical layer and the link layer in the DDI of FIG. 6 according to embodiments of the present invention.

[0072] In FIG. 8, the physical layer (410) and the link layer (480) may be referred to as a receiving circuit. That is, the receiving circuit may include the physical layer (410) and the link layer (480).

[0073] Referring to FIG. 8, the physical layer (410) may include a plurality of data lane modules (420a, 420b, 420c, 420d), a clock lane module (450), and a bias current controller (477), and the link layer (480) may include control / interface logic (CIL, 481), clock gating signal generators (483a, 483b, 483c, 483d), and a bias signal generator (487).

[0074] The data lane module (420a) can receive data signals (D0P, D0N), output low-power data signals (D0LPP, D0LPN) in low-power mode, and output parallel data signals (D0_DTA) and data clock signals (D0_CLK) in high-speed mode. The data lane module (420a) can receive a second activation signal (D_HS_EN0), a data bias current (ID0), and a divided clock signal (HS_CK0).

[0075] The data lane module (420b) can receive data signals (D1P, D1N), output low-power data signals (D1LPP, D1LPN) in low-power mode, and output parallel data signals (D1_DTA) and data clock signals (D1_CLK) in high-speed mode. The data lane module (420b) can receive a second activation signal (D_HS_EN1), a data bias current (ID1), and a divided clock signal (HS_CK1).

[0076] The data lane module (420c) can receive data signals (D2P, D2N), output low-power data signals (D2LPP, D2LPN) in low-power mode, and output parallel data signals (D2_DTA) and data clock signals (D2_CLK) in high-speed mode. The data lane module (420c) can receive a second activation signal (D_HS_EN2), a data bias current (ID2), and a divided clock signal (HS_CK2).

[0077] The data lane module (420d) can receive data signals (D3P, D3N), output low-power data signals (D3LPP, D3LPN) in low-power mode, and output parallel data signals (D3_DTA) and data clock signals (D3_CLK) in high-speed mode. The data lane module (420d) can receive a second activation signal (D_HS_EN3), a data bias current (ID3), and a divided clock signal (HS_CK3).

[0078] The clock lane module (450) receives clock signals (CKP, CKN), outputs low-power clock signals (CKLPP, CKLPN) in low-power mode, outputs a high-speed clock signal (HS_CK) in high-speed mode, and can generate a reference clock signal (REF_CLK). The clock lane module (450) can receive a first activation signal (CK_HS_EN) and a clock bias current (ICK).

[0079] The clock signals (CKP, CKN) and the data signals (D0P, D0N, D1P, D1N, D2P, D2N, D3P, D3N) may be based on the MIPI D-PHY protocol.

[0080] The bias current generator (477) generates a clock bias current (ICK) provided to the clock lane module (450) based on a bias control signal (ICKC) and can adjust the magnitude of the bias current (ICK). The bias current generator (477) can generate clock bias currents (ID) provided to the data lane modules (420a, 420b, 420c, 420d).

[0081] The link layer (480) can provide a bias control signal (ICKC) to the bias current controller (477) and a clock gating signal (CGC) to the clock lane module (450) based on the levels of low-power data signals (D0LPP, D0LPN, D1LPP, D1LPN, D2LPP, D2LPN, D3LPP, D3LPN) and low-power clock signals (CKLPP, CKLPN). The link layer (480) can determine the power mode of the data lane modules (420a, 420b, 420c, 420d) and the clock lane module (450) based on the levels of low-power data signals (D0LPP, D0LPN, D1LPP, D1LPN, D2LPP, D2LPN, D3LPP, D3LPN) and low-power clock signals (CKLPP, CKLPN).

[0082] The above power mode can be divided into a first power mode in which the clock lane module (450) and data lane modules (420a, 420b, 420c, 420d) operate in a low power mode, a second power mode in which the clock lane module (450) operates in a high power mode and the data lane modules (420a, 420b, 420c, 420d) operate in a low power mode, and a third power mode in which the clock lane module (450) and data lane modules (420a, 420b, 420c, 420d) operate in a high power mode.

[0083] The bias current controller (477) can block the clock bias current (ICK) provided to the clock lane module (450) in a first power mode based on the bias control signal (ICKC), provide a clock bias current (ICK) having a first size to the clock lane module (450) in a second power mode, and provide a clock bias current (ICK) having a second size larger than the first size to the clock lane module (450) in a third power mode. The clock bias current (ICK) may also be referred to as the bias current.

[0084] The control / interface logic (CIL, 481) can generate a first activation signal (CK_HS_EN) that activates the end circuit and high-speed receiver of the clock lane module (450) and second activation signals (D_HS_EN) that activate the end circuit and high-speed receiver of each of the data lane modules (420a, 420b, 420c, 420d) based on low-power data signals (D0LPP, D0LPN, D1LPP, D1LPN, D2LPP, D2LPN, D3LPP, D3LPN) and low-power clock signals (CKLPP, CKLPN).

[0085] Clock gating signal generators (483a, 483b, 483c, 483d) can each generate clock gating signals (CGC) in response to each of the second activation signals (D_HS_EN).

[0086] The clock gating signal generator (483a) may include a variable delayer (484) and an OR gate (485). The variable delayer (484) delays the corresponding activation signal (D_HS_EN0) among the second activation signals (D_HS_EN), and the OR gate (485) can output a corresponding clock gating signal among the clock gating signals (CGC) by performing an OR operation on the output of the variable delayer (484) and the activation signal (D_HS_EN0).

[0087] The configuration of each of the clock gating signal generators (483b, 483c, 483d) may be substantially the same as the configuration of the clock gating signal generator (483a).

[0088] The bias signal generator (487) can generate a bias control signal (ICKC) based on the second activation signals (D_HS_EN). The bias signal generator (487) can generate the bias control signal (ICKC) such that the clock bias current (ICK) has a first magnitude in response to the second activation signals (D_HS_EN) indicating a second power mode, and the clock bias current (ICK) has a second magnitude in response to the second activation signals (D_HS_EN) indicating a third power mode.

[0089] The bias signal generator (487) may include an AND gate (488) and a multiplexer (489).

[0090] The AND gate (488) can output a selection signal (SEL) by performing an OR operation on the second activation signals (D_HS_EN). The multiplexer (489) receives a first bias control signal (ICKC_LP) associated with a first size and a second bias control signal (ICKC_HS) associated with a second size, and in response to the selection signal (SEL), can provide one of the first bias control signal (ICKC_LP) and the second bias control signal (ICKC_HS) to the bias current controller (477) as a bias control signal (ICKC).

[0091] FIG. 9 is a circuit diagram showing the configuration of one of the data lane modules in the physical layer of FIG. 8 according to embodiments of the present invention.

[0092] Although FIG. 9 shows the configuration of the data lane module (420a), the configuration of each of the data lane modules (420b, 420c, 420d) may be substantially the same as the configuration of the data lane module (420a).

[0093] Referring to FIG. 9, the data lane module (420a) may include a terminal circuit (440), a first receiver (421), a second receiver (423), a third receiver (430), and a parallelizer (425).

[0094] The terminal circuit (440) can be connected between a first receiving terminal (RP0) where a first data signal (D0P) is received and a second receiving terminal (RP1) where a second data signal (D0N) is received.

[0095] The first receiver (421) can receive a first data signal (D0P) and output a first low-power data signal (D0LPP) in low-power mode. The second receiver (423) can receive a second data signal (D0N) and output a second low-power data signal (D0LPN) in low-power mode.

[0096] The third receiver (430) receives the first data signal (D0P) and the second data signal (D0N) and outputs the high-speed data signal (HS_D0) to the parallelizer (425) in high-speed mode based on the data bias current (ID0).

[0097] The terminal circuit (440) and the third receiver (430) can be activated in high-speed mode in response to the second activation signal (D_HS_EN0).

[0098] The parallelizer (425) can parallelize the high-speed data signal (HS_D0) based on the divided clock signal (HS_CK0) in high-speed mode to output a parallel data signal (D0_DTA) and output a data clock signal (D0_CLK).

[0099] The termination circuit (440) includes a first transistor (441), a first termination resistor (RT11), a second transistor (443), and a second termination resistor (RT12) connected in series between a first receiving terminal (RP0) and a second receiving terminal (RP1), and may further include a capacitor (445).

[0100] The first transistor (441) is connected between the first receiving terminal (RP0) and the first termination resistor (RT11), the first termination resistor (RT11) is connected between the first transistor (441) and the first node (N11), the second termination resistor (RT12) is connected between the first node (N11) and the second transistor (443), the second transistor (443) is connected between the second termination resistor (RT12) and the second receiving terminal (RP1), and the capacitor (445) can be connected between the first node (N11) and the ground voltage (VSS).

[0101] The first transistor (441) and the second transistor (443) may each be NMOS transistors having a gate that receives the second activation signal (D_HS_EN0).

[0102] When the first transistor (441) and the second transistor (443) are turned on in high-speed mode in response to the second activation signal (D_HS_EN0), the first termination resistor (RT11) and the second termination resistor (RT12) can be connected in series between the first receiving terminal (RP0) and the second receiving terminal (RP1).

[0103] FIG. 10 is a circuit diagram showing the configuration of a clock lane module in the physical layer of FIG. 8 according to embodiments of the present invention.

[0104] Referring to FIG. 10, the clock lane module (450) may include a termination circuit (470), a first receiver (451), a second receiver (453), a third receiver (460), a divided clock generator (475), and a reference clock generator (476).

[0105] The terminal circuit (470) can be connected between the first receiving terminal (RP4) where the first clock signal (CKP) is received and the second receiving terminal (RP5) where the second clock signal (CKN) is received.

[0106] The first receiver (451) can receive a first clock signal (CKP) and output a first low-power clock signal (CKLPP) in low-power mode. The second receiver (453) can receive a second clock signal (CKN) and output a second low-power clock signal (CKLPN) in low-power mode.

[0107] The third receiver (460) receives the first clock signal (CKP) and the second clock signal (CKN) and, based on the clock bias current (ICK), can output a high-speed clock signal (HS_CK) in high-speed mode to the divided clock generator (475) and the reference clock generator (476).

[0108] The terminal circuit (470) and the third receiver (460) can be activated in high-speed mode in response to the first activation signal (CK_HS_EN).

[0109] The reference clock generator (476) can generate a reference clock signal (REF_CLK) based on a high-speed clock signal (HS_CK).

[0110] The termination circuit (470) includes a first transistor (471), a first termination resistor (RT21), a second transistor (473), and a second termination resistor (RT22) connected in series between a first receiving terminal (RP4) and a second receiving terminal (RP5), and may further include a capacitor (475).

[0111] The first transistor (471) is connected between the first receiving terminal (RP4) and the first termination resistor (RT21), the first termination resistor (RT21) is connected between the first transistor (471) and the first node (N21), the second termination resistor (RT22) is connected between the first node (N21) and the second transistor (473), the second transistor (473) is connected between the second termination resistor (RT22) and the second receiving terminal (RP5), and the capacitor (475) can be connected between the first node (N21) and the ground voltage (VSS).

[0112] The first transistor (471) and the second transistor (473) may each be an NMOS transistor having a gate that receives the first activation signal (CK_HS_EN).

[0113] When the first transistor (471) and the second transistor (473) are turned on in high-speed mode in response to the first activation signal (CK_HS_EN), the first termination resistor (RT21) and the second termination resistor (RT22) can be connected in series between the first receiving terminal (RP4) and the second receiving terminal (RP5).

[0114] The clock divider generator (475) may include a plurality of AND gates (475a, 475b, 475c, 475d) that perform an AND operation on the high-speed clock signal (HS_CK) and the clock gating signals (CGC) to output the clock divider signals (HS_CK0, HS_CK1, HS_CK2, HS_CK3), respectively. Accordingly, in response to the clock gating signals (CGC) being at a low level in low-power mode, the AND gates (475a, 475b, 475c, 475d) may gate the high-speed clock signal (HS_CK), and thus may not toggle the clock divider signals (HS_CK0, HS_CK1, HS_CK2, HS_CK3) in low-power mode.

[0115] FIG. 11 is a circuit diagram showing the configuration of a third receiver in the clock lane module of FIG. 10 according to embodiments of the present invention.

[0116] Referring to FIG. 11, the third receiver (460) may include a source current generating circuit (460a) and amplification stages (460b, 460c, 460d).

[0117] The source current generating circuit (460a) may include PMOS transistors (461, 462, 463, 464).

[0118] The PMOS transistor (461) may have a source connected to a power supply voltage (VDD), a gate connected to a first node (N31) that receives a bias current (ICK), and a drain connected to the first node (N31). The PMOS transistor (462) may have a source connected to a power supply voltage (VDD), a gate connected to the first node (N31), and a drain connected to a second node (N32).

[0119] The PMOS transistor (463) may have a source connected to the power supply voltage (VDD), a gate connected to the first node (N31), and a drain connected to the fifth node (N35). The PMOS transistor (464) may have a source connected to the power supply voltage (VDD), a gate connected to the first node (N31), and a drain connected to the eighth node (N38).

[0120] The amplification stage (460b) may include PMOS transistors (466, 467) and resistors (R11, R12).

[0121] The PMOS transistor (466) may have a source connected to the second node (N32), a gate receiving the first clock signal (CKP), and a drain connected to the third node (N33). The PMOS transistor (464) may have a source connected to the second node (N32), a gate receiving the second clock signal (CKN), and a drain connected to the fourth node (N34). A resistor (R11) may be connected between the third node (N33) and the ground voltage (VSS), and a resistor (R12) may be connected between the fourth node (N34) and the ground voltage (VSS).

[0122] The amplification stage (460c) may include PMOS transistors (468, 469) and resistors (R13, R14).

[0123] The PMOS transistor (468) may have a source connected to the fifth node (N35), a gate connected to the third node (N33), and a drain connected to the sixth node (N36). The PMOS transistor (469) may have a source connected to the fifth node (N35), a gate connected to the fourth node (N34), and a drain connected to the seventh node (N37). A resistor (R13) may be connected between the sixth node (N36) and the ground voltage (VSS), and a resistor (R14) may be connected between the seventh node (N34) and the ground voltage (VSS).

[0124] The amplification stage (460d) may include PMOS transistors (470, 471) and NMOS transistors (472, 473).

[0125] The PMOS transistor (470) may have a source connected to the 8th node (N38), a gate connected to the 6th node (N36), and a drain connected to the 9th node (N39). The PMOS transistor (471) may have a source connected to the 8th node (N38), a gate connected to the 7th node (N37), and a drain connected to the 10th node (N40). The NMOS transistor (472) may have a drain and a gate connected to the 8th node (N38), and a source connected to the ground voltage (VSS). The NMOS transistor (473) may have a drain connected to the 10th node (N40), a gate connected to the 9th node (N39), and a source connected to the ground voltage (VSS). The NMOS transistors (472, 473) may form a current mirror. A high-speed clock signal (HS_CK) may be provided at the 10th node (N40).

[0126] The amplification stage (460b) can amplify the difference between the first clock signal (CKP) and the second clock signal (CKN) based on the source current provided to the second node (N32), the amplification stage (460c) can amplify the difference between the output signals of the amplification stage (460b) based on the source current provided to the fifth node (N35), and the amplification stage (460d) can amplify the difference between the output signals of the amplification stage (460c) based on the source current provided to the eighth node (N38) to output a high-speed clock signal (HS_CK).

[0127] Each of the PMOS transistors (462, 463, 464) forms a current mirror with the PMOS transistor (461), so source currents equal to or proportional to the bias current (ICK) can be provided to each of the nodes (N32, N35, N38). That is, by adjusting the magnitude of the bias current (ICK), the magnitude of the source currents provided to the nodes (N32, N35, N38) can be adjusted. Thus, if a bias current (ICK) having a first magnitude is provided in the second power mode and a bias current (ICK) having a third magnitude is provided in the third power mode, the third receiver (460) can generate a high-speed clock signal (HS_CK) based on bias currents (ICK) of different magnitudes in the second power mode and the third power mode.

[0128] FIG. 12 is a timing diagram showing signals of the physical layer and the link layer of FIG. 8 according to embodiments of the present invention.

[0129] Referring to FIG. 12, in the first section (INT11), the clock lane module (450) and the data lane modules (420a, 420b, 420c, 420d) operate in a low-power mode, and the clock signals (CKP, CK) swing between the ground voltage (VSS) and a first voltage level (VL1) higher than the ground voltage (VSS), and the data signals (DxP, DxN) swing between the ground voltage (VSS) and a second voltage level (VL2) higher than the ground voltage (VSS). Additionally, the first enable signal (CK_HS_EN) and the second enable signals (Dx_HS_EN) are at a low level, the clock bias current (ICK) is blocked, and the data bias currents (ID0, ID1, ID2, ID3) are blocked. Additionally, the division clock signals (HS_CK[0:3]), data clock signals (Dx_CLK), and reference clock signal (REF_CLK) do not toggle.

[0130] In the second section (INT12), the clock lane module (450) operates in high-speed mode and the data lane modules (420a, 420b, 420c, 420d) operate in low-power mode, the clock signals (CKP, CKP) swing between a voltage level higher than the ground voltage (VSS) and a voltage level lower than the first voltage level (LV1), and the data signals (DxP, DxN) can swing between the ground voltage (VSS) and the second voltage level (LV2). Also, the first enable signal (CK_HS_EN) is enabled to a high level, the second enable signals (Dx_HS_EN) are at a low level, the clock bias current (ICK) has a first magnitude (I11), and the data bias currents (ID0, ID1, ID2, ID3) are blocked. Additionally, the division clock signals (HS_CK[0:3]) and data clock signals (Dx_CLK) do not toggle, and the reference clock signal (REF_CLK) does not toggle.

[0131] In the third section (INT13), the clock lane module (450) operates in high-speed mode and the data lane modules (420a, 420b, 420c, 420d) operate in high-speed mode, the clock signals (CKP, CKP) swing between a voltage level higher than the ground voltage (VSS) and a voltage level lower than the first voltage level (LV1), the data signals (DxP, DxN) swing between a level higher than the ground voltage (VSS) and a level lower than the second voltage level (VL2), and packet data can be transmitted through the data signals (DxP, DxN). SOT indicates the start of the transmission packet. Additionally, the first activation signal (CK_HS_EN) is maintained at a high level, the second activation signals (Dx_HS_EN) are activated at a high level, the clock bias current (ICK) has a second size (I12) which is larger than the first size (I11), and the data bias currents (ID0, ID1, ID2, ID3) have a third size (I13) which is substantially the same as the second size (I12). Thus, the skew between the clock lane module (450) and the data lane modules (420a, 420b, 420c, 420d) can be reduced. Additionally, the divided clock signals (HS_CK[0:3]), data clock signals (Dx_CLK), and reference clock signal (REF_CLK) toggle to their respective frequencies.

[0132] The operation of the fourth section (INT14) is similar to the operation of the second section (INT12), and the divided clock signals (HS_CK[0:3]) are the section (T) required for packet data recovery. CK_POST Toggles for ) and stops toggling.

[0133] The operation of the 5th section (INT15) is substantially the same as the operation of the 3rd section (INT31), and the operation of the 6th section (INT16) is substantially the same as the operation of the 4th section (INT14).

[0134] FIG. 13 is a flowchart illustrating the operation method of a receiving circuit according to embodiments of the present invention.

[0135] Referring to FIGS. 5 to 13, the link layer (480) determines the power mode of the clock lane module (450) and data lane modules (420a, 420b, 420c, 420d) based on low-power data signals (D0LPP, D0LPN, D1LPP, D1LPN, D2LPP, D2LPN, D3LPP, D3LPN) and low-power clock signals (CKLPP, CKLPN) (S110).

[0136] In the first power mode, the clock lane module (450) generates low-power clock signals (CKLPP, CKLPN), and the bias current generator (477) blocks the clock bias current (ICK) provided to the clock lane module (450) (S120). In the second power mode, the clock lane module (450) generates a high-speed clock signal (HS_CK), and the bias current generator (477) provides a clock bias current (ICK) having a first magnitude to the clock lane module (450) and gates the clock signals provided to the high-speed receivers of each of the data lane modules (420a, 420b, 420c, 420d) (S130). In the third power mode, the clock lane module (450) generates a high-speed clock signal (HS_CK), and the bias current generator (477) provides a clock bias current (ICK) having a second magnitude to the clock lane module (450) and provides a bias current having a third magnitude to each of the high-speed receivers of the data lane modules (420a, 420b, 420c, 420d) (S140).

[0137] FIG. 14 is a block diagram showing the configuration of a display in the display system of FIG. 5 according to embodiments of the present invention. An OLED panel will be described as an example of a display panel (510).

[0138] Referring to FIG. 14, the display (500) may include a display panel (510), a data driver (540), a scan driver (560), and a light emission control driver (570).

[0139] The display panel (510) may include a plurality of data lines (DL1~DLm), a plurality of scan lines (SL0~SLn), a plurality of light emission control lines (EL1~Eln), and a plurality of pixels (PX) disposed between said lines. Each of the plurality of pixels (PX) may be connected to a corresponding scan line (SL), data line (DL), and light emission control line (EL).

[0140] Each of the multiple pixels (PX) can output light of a preset color, and two or more pixels (PX) (e.g., red, blue, and green pixels) that are placed adjacent to each other on the same or adjacent lines and output light of different colors can constitute a single unit pixel. In this case, the two or more pixels (PX) constituting the unit pixel may be referred to as sub-pixels. The display panel (510) may have an RGB structure in which red, blue, and green pixels constitute a single unit pixel. However, it is not limited thereto, and the display panel (300) may have an RGBW structure in which the unit pixel further includes a white pixel for brightness enhancement. Alternatively, the unit pixel of the display panel (510) may be composed of a combination of pixels of colors other than red, green, and blue.

[0141] The scan driver (560) is connected to a plurality of scan lines (SL0~SL1) and sequentially applies a scan signal to the pixels (PX) line by line to sequentially select the pixels (PX).

[0142] The light emission control driver (570) is connected to a plurality of light emission control lines (EL1~ELn) and sequentially applies light emission control signals (E1~En) to pixels (PX) to control the light emission time of the pixels (PX).

[0143] The data driver (540) can generate multiple video signals and provide multiple video signals to pixels (PX) through each of the multiple data lines (DL1~DLm).

[0144] FIG. 15 shows an electronic device according to embodiments of the present invention.

[0145] Referring to FIG. 15, the electronic device (600) may include a transmitting circuit (610) and a receiving circuit (650).

[0146] The transmission circuit (610) may include a signal generator (620), a first transmitter (631), a second transmitter (633), and a third transmitter (635). The signal generator (620) may generate signals (S1, S2, S3). The first transmitter (631), the second transmitter (633), and the third transmitter (635) may output signals (S1, S2, S3) through three communication lines (ML).

[0147] The first transmitter (631), the second transmitter (633), and the third transmitter (635) can transmit signals based on one of various communication protocols. For example, the first transmitter (631), the second transmitter (633), and the third transmitter (635) can transmit signals based on the C-PHY protocol defined in MIPI. The transmitting circuit (610) and the receiving circuit (650) can follow any physical layer specification and any interface protocol related to communication through three or more communication lines.

[0148] A receiving circuit (650) can receive signals (S1, S2, S3) through three communication lines (ML). The receiving circuit (650) may include a physical layer (700) and a link layer (900). The physical layer (700) provides low-power signals (TLPs) to the link layer (900) based on the signals (S1, S2, S3), and the link layer (900) can provide a bias control signal (ICKC1) to the physical layer (700) based on the low-power signals (TLPs).

[0149] FIG. 16 is a block diagram showing the configuration of a receiving circuit in the electronic device of FIG. 15 according to embodiments of the present invention.

[0150] Referring to FIG. 16, the receiving circuit (650) may include a physical layer (700) and a link layer (900), and the physical layer (700) may include a plurality of trio modules (710a, 710b, 710c), a selection circuit (810), and a bias current controller (820).

[0151] The trio module (710a) receives signals (S1, S2, S3), outputs low-power signals (T0LPA, T0LPB, T0LPC) in low-power mode, and outputs a parallel data signal (T0_DTA), a data clock signal (T0_CLK), and a reference clock signal (REF_W_CLK0) in high-speed mode. The trio module (710a) can receive a high-speed mode enable signal (T0_HS_EN) and a bias current (ICK11).

[0152] The trio module (710b) receives signals (S1, S2, S3), outputs low-power signals (T1LPA, T1LPB, T1LPC) in low-power mode, and outputs a parallel data signal (T1_DTA), a data clock signal (T1_CLK), and a reference clock signal (REF_W_CLK1) in high-speed mode. The trio module (710b) can receive a high-speed mode enable signal (T1_HS_EN) and a bias current (ICK12).

[0153] The trio module (710c) receives signals (S1, S2, S3), outputs low-power signals (T2LPA, T2LPB, T2LPC) in low-power mode, and outputs a parallel data signal (T2_DTA), a data clock signal (T2_CLK), and a reference clock signal (REF_W_CLK2) in high-speed mode. The trio module (710c) can receive a high-speed mode enable signal (T2_HS_EN) and a bias current (ICK13).

[0154] The selection circuit (810) receives reference clock signals (REF_W_CLK0, REF_W_CLK1, REF_W_CLK3) and, in response to the first selection signal (SEL1), can provide one of the reference clock signals (REF_W_CLK0, REF_W_CLK1, REF_W_CLK3) to the link layer (900) as a selected reference clock signal (REF_W_CLK).

[0155] The signals (S1, S2, S3) can be based on the MIPI C-PHY protocol.

[0156] The bias current generator (820) generates a bias current (ICK1) provided to the trio modules (710a, 710b, 710c) based on a bias control signal (ICKC1) and can adjust the magnitude of the bias current (ICK1). The bias current (ICK1) may include bias currents (ICK11, ICK12, ICK13) provided to each of the trio modules (710a, 710b, 710c).

[0157] The link layer (900) can provide a bias control signal (ICKC1) to the bias current controller (775) based on the levels of low-power signals (T0LPA, T0LPB, T0LPC, T1LPA, T1LPB, T1LPC, T2LPA, T2LPB, T2LPC). The link layer (900) can determine the power mode of the trio modules (710a, 710b, 710c) based on the levels of the low-power signals (T0LPA, T0LPB, T0LPC, T1LPA, T1LPB, T1LPC, T2LPA, T2LPB, T2LPC).

[0158] The above power mode may include a first power mode in which the trio modules (710a, 710b, 710c) operate in a low power mode, a second power mode in which one of the trio modules (710a, 710b, 710c) (e.g., the first trio modules (710a)) operates in a high power mode and the remaining trio modules (e.g., the trio modules (710b, 710c)) operate in a low power mode, and a third power mode in which all of the trio modules (710a, 710b, 710c) operate in a high power mode.

[0159] The bias current controller (820) can block the bias currents (ICK1) provided to the trio modules (710a, 710b, 710c) in the first power mode based on the bias control signal (ICKC1), provide a bias current (ICK11) having a first size to the first trio module (710a) in the second power mode, and provide a clock bias current (ICK11) having a second size larger than the first size to the first trio module (710a) in the third power mode.

[0160] The physical layer (900) may include control interface logic (CIL, 910) and a bias signal generator (930).

[0161] The control / interface logic (910) can generate high-speed mode enable signals (T_HS_EN) that selectively enable the end circuits and high-speed receivers of each of the trio modules (710a, 710b, 710c) based on the levels of low-power signals (T0LPA, T0LPB, T0LPC, T1LPA, T1LPB, T1LPC, T2LPA, T2LPB, T2LPC), and provide the high-speed mode enable signals (T_HS_EN) to the trio modules (710a, 710b, 710c).

[0162] The bias signal generator (930) can generate a bias control signal (ICKC1) based on high-speed mode activation signals (T_HS_EN). The bias signal generator (930) can generate the bias control signal (ICKC1) such that the bias current (ICK11) has a first magnitude in response to the high-speed mode activation signals (T_HS_EN) indicating a second power mode, and the bias current (ICK11) has a second magnitude in response to the high-speed mode activation signals (T_HS_EN) indicating a third power mode.

[0163] The bias signal generator (930) may include an AND gate (931) and a multiplexer (933).

[0164] The AND gate (931) can perform an AND operation on the high-speed mode enable signals (T_HS_EN) to output a second selection signal (SEL2). The multiplexer (933) receives a first bias control signal (ICKC1_LP) associated with a first size and a second bias control signal (ICKC1_HS) associated with a second size, and in response to the second selection signal (SEL), can provide one of the first bias control signal (ICKC1_LP) and the second bias control signal (ICKC1_HS) to the bias current controller (820) as a bias control signal (ICKC1).

[0165] FIG. 17 is a circuit diagram showing the configuration of one of the trio modules in the physical layer of FIG. 16 according to embodiments of the present invention.

[0166] Although FIG. 17 shows the configuration of the trio module (710a), the configuration of each of the trio modules (710b, 710c) may be substantially the same as the configuration of the trio module (710a).

[0167] Referring to FIG. 17, the trio module (710a) may include a termination circuit (720), low-power receivers (731, 733, 735), high-speed receivers (740a, 740b, 740c), a clock and data recovery circuit (790), and a reference clock generator (795).

[0168] The terminal circuit (720) can be connected to a first receiving terminal (RP0) where the first signal (S1) among the three signals (S1, S2, S3) is received, a second receiving terminal (RP1) where the second signal (S2) is received, and a third receiving terminal (RP2) where the third signal (S3) is received.

[0169] The first low-power receiver (731) can receive the first signal (S1) and output the first low-power signal (T0LPA) in low-power mode. The second low-power receiver (733) can receive the second signal (S2) and output the second low-power signal (T0LPB) in low-power mode. The third low-power receiver (735) can receive the third signal (S3) and output the third low-power signal (T0LPC) in low-power mode.

[0170] The first high-speed receiver (740a) receives the first signal (S1) and the second signal (S2), and in high-speed mode, can output the first high-speed signal (T0HSA) by amplifying the difference between the first signal (S1) and the second signal (S2) based on the bias current (ICK11). The second high-speed receiver (740b) receives the second signal (S2) and the second signal (S3), and in high-speed mode, can output the second high-speed signal (T0HSB) by amplifying the difference between the second signal (S2) and the third signal (S3) based on the bias current (ICK11). The third high-speed receiver (740c) receives the third signal (S3) and the first signal (S1), and in high-speed mode, can output the third high-speed signal (T0HSC) by amplifying the difference between the third signal (S3) and the first signal (S1) based on the bias current (ICK11).

[0171] The terminal circuit (720) and the first to third high-speed receivers (740a, 740b, 740c) can be activated in high-speed mode in response to a high-speed mode activation signal (T0_HS_EN).

[0172] The clock and data recovery circuit (790) can recover a parallel data signal (T0_DTA) and a data clock signal (T0_CLK) based on the first to third high-speed mode signals (T0HSA, T0HSB, T0HSC).

[0173] The reference clock generator (795) can generate a reference clock signal (REF_W_CLK0) based on the first to third high-speed mode signals (T0HSA, T0HSB, T0HSC).

[0174] The termination circuit (720) may include transistors (721, 723, 725) and termination resistors (RT31, RT32, RT33).

[0175] A transistor (721) may be connected to a first receiving terminal (RP0) and may have a gate that receives a high-speed mode activation signal (T0_HS_EN). A termination resistor (RT31) may be connected between the transistor (721) and the ground voltage (VSS). A transistor (723) may be connected to a second receiving terminal (RP1) and may have a gate that receives a high-speed mode activation signal (T0_HS_EN). A termination resistor (RT32) may be connected between the transistor (723) and the ground voltage (VSS). A transistor (725) may be connected to a third receiving terminal (RP2) and may have a gate that receives a high-speed mode activation signal (T0_HS_EN). A termination resistor (RT33) may be connected between the transistor (725) and the ground voltage (VSS).

[0176] When turned on in response to the high-speed mode enable signal (T0_HS_EN), each of the termination resistors (RT31, RT32, RT33) can be connected between each of the receiving terminals (RP0, RP1, RP2) and the ground voltage (VSS).

[0177] FIG. 18 is a circuit diagram showing the configuration of a first high-speed receiver in the trio module of FIG. 17 according to embodiments of the present invention.

[0178] FIG. 18 shows the configuration of the first high-speed receiver (740a), but the configurations of the second and third high-speed receivers (740b, 740c), respectively, may be substantially the same as the configuration of the first high-speed receiver (740a).

[0179] Referring to FIG. 18, the first high-speed receiver (740a) may include a source current generating circuit (750) and amplification stages (760, 770, 780).

[0180] The source current generating circuit (750) may include PMOS transistors (751, 752, 753, 754).

[0181] The PMOS transistor (751) may have a source connected to a power supply voltage (VDD), a gate connected to a first node (N41) that receives a bias current (ICK11), and a drain connected to the first node (N41). The PMOS transistor (752) may have a source connected to a power supply voltage (VDD), a gate connected to the first node (N41), and a drain connected to a second node (N42).

[0182] The PMOS transistor (753) may have a source connected to the power supply voltage (VDD), a gate connected to the first node (N41), and a drain connected to the fifth node (N45). The PMOS transistor (754) may have a source connected to the power supply voltage (VDD), a gate connected to the first node (N41), and a drain connected to the eighth node (N48).

[0183] The amplification stage (760) may include PMOS transistors (761, 763) and resistors (R21, R22).

[0184] The PMOS transistor (761) may have a source connected to the second node (N42), a gate receiving the first signal (S1), and a drain connected to the third node (N43). The PMOS transistor (763) may have a source connected to the second node (N42), a gate receiving the second signal (S2), and a drain connected to the fourth node (N44). A resistor (R21) may be connected between the third node (N43) and the ground voltage (VSS), and a resistor (R22) may be connected between the fourth node (N44) and the ground voltage (VSS).

[0185] The amplification stage (770) may include PMOS transistors (771, 773) and resistors (R23, R24).

[0186] The PMOS transistor (771) may have a source connected to the fifth node (N45), a gate connected to the third node (N43), and a drain connected to the sixth node (N46). The PMOS transistor (773) may have a source connected to the fifth node (N45), a gate connected to the fourth node (N44), and a drain connected to the seventh node (N47). A resistor (R23) may be connected between the sixth node (N46) and the ground voltage (VSS), and a resistor (R24) may be connected between the seventh node (N47) and the ground voltage (VSS).

[0187] The amplification stage (780) may include PMOS transistors (781, 782) and NMOS transistors (783, 784).

[0188] The PMOS transistor (781) may have a source connected to the 8th node (N48), a gate connected to the 6th node (N46), and a drain connected to the 9th node (N49). The PMOS transistor (782) may have a source connected to the 8th node (N48), a gate connected to the 7th node (N47), and a drain connected to the 10th node (N50).

[0189] The NMOS transistor (783) may have a drain and a gate connected to the eighth node (N48), and a source connected to the ground voltage (VSS). The NMOS transistor (784) may have a drain connected to the tenth node (N50), a gate connected to the ninth node (N49), and a source connected to the ground voltage (VSS). The NMOS transistors (783, 784) may form a current mirror. A high-speed signal (T0HSA) may be provided at the tenth node (N50).

[0190] The amplification stage (760) amplifies the difference between the first signal (S1) and the second signal (S2) based on the source current provided to the second node (N42), the amplification stage (770) amplifies the difference between the output signals of the amplification stage (760) based on the source current provided to the fifth node (N45), and the amplification stage (780) amplifies the difference between the output signals of the amplification stage (770) based on the source current provided to the eighth node (N48) to output a high-speed signal (T0HSA).

[0191] Each of the PMOS transistors (752, 753, 754) forms a current mirror with the PMOS transistor (751), so source currents equal to or proportional to the bias current (ICK11) can be provided to each of the nodes (N42, N45, N48). That is, by adjusting the magnitude of the bias current (ICK11), the magnitude of the source currents provided to the nodes (N42, N45, N48) can be adjusted. Thus, if a bias current (ICK11) having a first magnitude is provided in the second power mode and a bias current (ICK11) having a third magnitude is provided in the third power mode, the first high-speed receiver (730a) can generate a high-speed signal (T0HSA) based on the bias current (ICK11) having different magnitudes in the second power mode and the third power mode.

[0192] FIG. 19 is a timing diagram showing signals of the physical layer and the link layer of FIG. 16 according to embodiments of the present invention.

[0193] Referring to FIGS. 16 and 19, in the first interval (INT21), the trio modules (710a, 710b, 710c) operate in low-power mode, and the signals (T0_A / B / C) and signals (T1_A / B / C, T2_A / B / C) can swing between a ground voltage (VSS) and a first voltage level (VL21) higher than the ground voltage (VSS). Also, the high-speed mode enable signals (T0_HS_EN, T1_HS_EN, T2_HS_EN) are at a low level, and the clock bias currents (ICK11, ICK12, ICK13) are blocked. Additionally, the data clock signals (Tx_W_CLK) and the reference clock signal (REF_W_CLK) do not toggle.

[0194] In the second section (INT22), the trio module (710a) operates in high-speed mode, and the trio modules (710b, 710c) operate in low-power mode. Thus, the signals (T0_A / B / C) can swing between a level higher than the ground voltage (VSS) and a level lower than the first voltage level (VL21) to transmit the preamble and SOT. The signals (T1_A / B / C, T2_A / B / C) can swing between the ground voltage (VSS) and the first voltage level (VL21). Also, the high-speed mode enable signal (T0_HS_EN) is at a high level, the high-speed mode enable signals (T1_HS_EN, T2_HS_EN) are at a low level, the clock bias current (ICK11) has a first magnitude (I21), and the clock bias currents (ICK12, ICK13) are blocked. Additionally, the data clock signals (Tx_W_CLK) do not toggle, and the reference clock signal (REF_W_CLK) starts toggling.

[0195] In the third section (INT33), it operates in high-speed mode, and the trio modules (710a, 710b, 710c) operate in low-power mode. Thus, the signals (T0_A / B / C) can transmit preamble, SOT, and packet data by swinging between a level higher than the ground voltage (VSS) and a level lower than the first voltage level (VL21), and the signals (T1_A / B / C, T2_A / B / C) can transmit preamble, SOT, packet data, and postamble by swinging between a level higher than the ground voltage (VSS) and a level lower than the first voltage level (VL21). Additionally, the high-speed mode enable signals (T0_HS_EN, T1_HS_EN, T2_HS_EN) are at a high level, the clock bias current (ICK11) has a second magnitude (I22), and the clock bias currents (ICK12, ICK13) may have a third magnitude (I23). Furthermore, the data clock signals (Tx_W_CLK) and the reference clock signal (REF_W_CLK) toggle at their respective frequencies.

[0196] The operation of the fourth section (INT24) is similar to the operation of the second section (INT22), and the signals (T0_A / B / C) transmit SOT and postamble by swinging between a level higher than the ground voltage (VSS) and a level lower than the first voltage level (VL21).

[0197] The operation of the 5th section (INT25) is substantially the same as the operation of the 1st section (INT21).

[0198] Accordingly, according to embodiments of the present invention, in a second power mode in which only the clock lane module operates in a high-speed mode in a receiving circuit or electronic device according to the MIPI D-HPY or MIPI C-PHY protocol, a clock bias current having a first size is provided to the high-speed receiver of the clock lane module and the high-speed clock signals provided to the high-speed receivers of the data lane modules are gated, and in a second power mode in which the clock lane module and the data lane modules operate in a high-speed mode, a clock bias current having a second size larger than the first size is provided to the high-speed receiver of the clock lane module and a bias current having a third size equal to the second size is provided to the high-speed receivers of the data lane modules, thereby reducing current consumption in the second power mode and reducing skew between the clock lane module and the data lane modules in the third power mode.

[0199] FIG. 20 is a block diagram showing an example of an interface used in a computing system according to embodiments of the present invention.

[0200] Referring to FIG. 20, the computing system (1100) may be implemented as a data processing device capable of using or supporting a MIPI interface and may include an application processor (1110), an image sensor (1140), and a display (1150). A CSI host (1112) of the application processor (1110) may perform serial communication with a CSI device (1111) of the image sensor (1140) through a Camera Serial Interface (CSI). In one embodiment, the CSI host (1112) may include a deserializer (DES), and the CSI device (1111) may include a serializer (SER). A DSI host (1111) of the application processor (1110) may perform serial communication with a DSI device (1151) of the display (1150) through a Display Serial Interface (DSI).

[0201] In one embodiment, the DSI host (1111) may include a serializer (SER), and the DSI device (1151) may include a deserializer (DES). Furthermore, the computing system (1100) may further include a Radio Frequency (RF) chip (1160) capable of communicating with an application processor (1110). The PHY (1113) of the computing system (1100) and the PHY (1161) of the RF chip (1160) may perform data transmission and reception according to MIPI (Mobile Industry Processor Interface) DigRF. Additionally, the application processor (1110) may further include a DigRF MASTER (1114) that controls data transmission and reception according to MIPI DigRF of the PHY (1161).

[0202] Meanwhile, the computing system (1100) may include a Global Positioning System (GPS) (1120), storage (1170), a microphone (1180), Dynamic Random Access Memory (DRAM) (1185), and a speaker (1190). Additionally, the computing system (1100) may perform communication using Ultra WideBand (UWB) (1210), Wireless Local Area Network (WLAN) (1220), and Worldwide Interoperability for Microwave Access (WIMAX) (1230), etc. However, the structure and interface of the computing system (1100) are examples and are not limited thereto. Industrial applicability

[0203] Embodiments of the present invention can be usefully utilized in devices requiring high-speed data communication and systems including the same.

[0204] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims.

Claims

Claim 1 A plurality of data lane modules, each receiving data signals; a clock lane module receiving a clock signal and providing a divided clock signal to each of the plurality of data lanes based on the clock signal; a bias current controller controlling a bias current provided to the clock lane; and a link layer providing a bias control signal to the bias current controller and providing clock gating signals to the clock lane module based on low-power data signals output from the plurality of data lane modules and levels of a low-power clock signal output from the clock lane module, wherein the bias current controller blocks the bias current in a first power mode, provides the bias current having a first magnitude in a second power mode, and provides the bias current having a second magnitude larger than the first magnitude in a third power mode, comprising a receiving circuit. Claim 2 A receiving circuit according to claim 1, wherein the link layer determines the power mode of the clock lane module and the data lane modules as one of the first power mode, the second power mode, and the third power mode based on the levels of the data signals and the clock signal, and in the second power mode, the clock lane module gates the divided clock signals provided to the data lane modules based on the clock gating signals, and in the first power mode, the clock lane module and the data lane modules operate in a low power mode, and in the second power mode, the clock lane module operates in a high power mode and the data lane modules operate in the low power mode, and in the third power mode, the clock lane module and the data lane modules operate in the high power mode. Claim 3 A receiving circuit according to claim 2, wherein in the low-power mode, the clock signal swings between a ground voltage and a first voltage level higher than the ground voltage, in the high-speed mode, the clock signal swings between a level higher than the ground voltage and a level higher than the first voltage level, in the low-power mode, each of the low-power data signals swings between the ground voltage and a second voltage level higher than the ground voltage, and in the high-speed mode, packet data is transmitted through the data signals. Claim 4 In claim 1, the clock lane module comprises: a terminal circuit connected between a first receiving terminal receiving a first clock signal among the clock signals and a second receiving terminal receiving a second clock signal among the clock signals; a first receiver receiving the first clock signal and outputting a first low-power clock signal; a second receiver receiving the second clock signal and outputting a second low-power clock signal; a third receiver receiving the first clock signal and the second clock signal and outputting a high-speed clock signal; a reference clock generator generating a reference clock signal based on the high-speed clock signal and providing the reference clock signal to the link layer; and a divided clock generator generating divided clock signals based on the high-speed clock signal. Claim 5 A receiving circuit according to claim 4, wherein the link layer activates the termination circuit and the third receiver in the second power mode and the third power mode, and the termination circuit includes a first transistor connected to the first receiving terminal; a first termination resistor connected between the first transistor and the first node; a second transistor connected to the second receiving terminal; a second termination resistor connected between the second transistor and the first node; and a capacitor connected between the first node and the ground voltage, wherein the first transistor and the second transistor are turned on in the second power mode and the third power mode in response to a first activation signal. Claim 6 In claim 4, the divider clock generator comprises a plurality of AND gates that perform an AND operation on the high-speed clock signal and the clock gating signals to output the divider clock signals respectively, and the third receiver comprises: a first PMOS transistor having a source connected to a power supply voltage, a gate connected to a first node receiving the bias current, and a drain connected to the first node; a second PMOS transistor having a source connected to the power supply voltage, a gate connected to the first node, and a drain connected to a second node; a third PMOS transistor having a source connected to the second node, a gate receiving the first clock signal, and a drain connected to a third node; a fourth PMOS transistor having a source connected to the second node, a gate receiving the second clock signal, and a drain connected to a fourth node; a first resistor connected between the third node and the ground voltage; and a second resistor connected between the fourth node and the ground voltage, and is characterized by providing the high-speed clock signal at the fourth node. Claim 7 A receiving circuit according to claim 1, wherein the link layer comprises: control / interface logic that generates a first activation signal that activates the termination circuit and high-speed receiver of the clock lane module and a second activation signal that activates the termination circuit and high-speed receiver of each of the data lane modules based on the low-power data signals and the low-power clock signal; clock gating signal generators that generate the clock gating signals based on the second activation signals; and a bias signal generator that generates the bias control signal based on the second activation signals, wherein the bias signal generator generates the bias control signal such that the bias current has the first magnitude in response to the second activation signals indicating the second power mode, and the bias current has the second magnitude in response to the second activation signals indicating the third power mode, and wherein the clock signal and the data signal are based on the MIPI (mobile industry processor interface) D-PHY protocol. Claim 8 A receiving circuit comprising: a plurality of trio modules, each receiving three or more signals; a bias current controller for controlling a bias current provided to each of the plurality of trio modules; and a link layer providing a bias control signal to the bias current controller based on the levels of low-power signals output from the plurality of trio modules, wherein the bias current controller blocks the bias current in a first power mode, outputs the bias current having a first magnitude in a second power mode, and outputs the bias current having a second magnitude larger than the first magnitude in a third power mode. Claim 9 In claim 8, the link layer determines the power mode of the trio modules as one of the first power mode, the second power mode, and the third power mode based on the levels of the low-power signals, and in the first power mode, the plurality of trio modules operate in the low-power mode, and in the second power mode, the first trio module among the plurality of trio modules operates in the low-power mode, and the remaining trio modules excluding the first trio module among the plurality of trio modules operate in the high-speed mode, and in the third power mode, the plurality of trio modules operate in the high-speed mode, and each of the plurality of trio modules is a terminal circuit connected to a first receiving terminal where a first signal among the three or more signals is received, a second receiving terminal where a second signal among the three or more signals is received, and a third receiving terminal where a third signal among the three or more signals is received; a first low-power receiver that receives the first signal and outputs a first low-power signal; a second low-power receiver that receives the second signal and outputs a second low-power signal; and a third low-power signal that receives the third signal and outputs a third low-power signal A third low-power receiver that outputs; a first high-speed receiver that receives the first signal and the second signal, amplifies the difference between the first signal and the second signal, and outputs a first high-speed signal; a second high-speed receiver that receives the second signal and the third signal, amplifies the difference between the second signal and the third signal, and outputs a second high-speed signal; a third high-speed receiver that receives the third signal and the first signal, amplifies the difference between the third signal and the first signal, and outputs a third high-speed signal; a clock and data recovery circuit that recovers a data signal and a data clock signal based on the first high-speed signal, the second high-speed signal, and the third high-speed signal;A receiving circuit characterized by including a reference clock generator that generates a reference clock signal based on the first high-speed signal, the second high-speed signal, and the third high-speed signal. Claim 10 In claim 8, the link layer comprises control / interface logic that generates activation signals to activate each of the termination circuits and high-speed mode receivers of the plurality of trio modules based on the levels of the low-power signals; and a bias signal generator that generates the bias control signal based on the activation signals, wherein the bias signal generator generates the bias control signal such that the bias current has the first magnitude in response to the activation signals indicating the second power mode, and the bias current has the second magnitude in response to the activation signals indicating the third power mode, and the three or more signals are based on the protocol of MIPI (mobile industry processor interface) C-PHY.

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