Thermal cooling element for memory devices of a memory subsystem

Abstract

A memory subsystem may include a plurality of memory devices and a thermal cooling element. The thermal cooling element includes a lower surface coupled to the upper surface of each of the memory devices. Additionally, the thermal cooling element further has an upper surface including protrusions extending over the upper surface of the thermal cooling element for dissipating heat generated from the memory devices.

Description

Technology Field

[0001] The present disclosure generally relates to a memory subsystem, and more specifically to a thermal cooling element for memory devices of a memory subsystem. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data in memory devices and retrieve data from memory devices. Brief explanation of the drawing

[0003] The present disclosure will be more fully understood from the detailed description below and the accompanying drawings of various embodiments of the present disclosure. FIG. 1 illustrates an exemplary computing system including a memory subsystem according to some embodiments of the present disclosure. FIG. 2 illustrates an exemplary memory subsystem having a thermal cooling element according to some embodiments. FIG. 3 illustrates an overhead view of an exemplary thermal cooling element according to some embodiments of the present disclosure. FIG. 4 illustrates another exemplary thermal cooling element for a memory subsystem according to some embodiments. FIG. 5 illustrates another exemplary thermal cooling element for a memory subsystem according to some embodiments. FIG. 6 is an exemplary method for assembling an exemplary thermal cooling element for a memory subsystem according to some embodiments of the present disclosure. FIG. 7 is a block diagram of an exemplary computer system in which implementations of the present disclosure can be operated. Specific details for implementing the invention

[0004] Aspects of the present disclosure relate to thermal cooling elements for memory devices of a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of a storage device and a memory module are described below together with FIG. 1. Generally, a host system may utilize a memory subsystem comprising one or more memory components, such as memory devices that store data. The host system may provide data to be stored in the memory subsystem and request data to be retrieved from the memory subsystem.

[0005] A conventional memory subsystem may include a case that encloses multiple memory devices. For example, the memory subsystem may be covered by a metal case or enclosure that isolates the memory devices of the memory subsystem from the external environment. The case may also be used to provide thermal cooling for the memory devices of the memory subsystem. For example, a thermal pad may be attached to the memory devices in the metal case or enclosure so that the metal case or enclosure also serves as a heatsink for the memory subsystem. Heat generated by the memory devices may be dissipated through contact with the metal case or enclosure of the memory subsystem.

[0006] Certain memory subsystems, such as Peripheral Component Interconnect Express (PCIe) memory subsystems, have a form factor that does not include a metal case or enclosure for the memory subsystem. For example, the memory devices in the memory subsystem may be exposed to the external environment because the memory subsystem does not use a case or enclosure. The height of these form factors may also be more restricted than that of conventional memory subsystems. For example, these memory subsystems may be used in computing environments where the available height for the memory subsystem is limited. Because the available height is limited, conventional heat sinks or fans cannot be placed over the memory devices to remove any heat generated by the memory devices. Therefore, since metal cases or enclosures and conventional heat sinks or fans cannot be used with these memory subsystems, heat generated by the operation of the memory subsystem may remain within the memory subsystem and affect the performance of the memory devices.

[0007] Aspects of the present disclosure address the above and other drawbacks by utilizing a thermal cooling element for memory devices of a memory subsystem. The thermal cooling element may be a metallic (or other material capable of transferring heat) tape layered over the memory devices of the memory subsystem. The metallic tape may transfer heat from the memory devices to the ends of the metallic tape. For example, heat may be transferred from one end of the metallic tape where the memory devices are located to the other end of the metallic tape where the memory devices are not located. Additionally, the metallic tape may include bumps or other protrusions that contribute to steady movement of air over the metallic tape to dissipate heat from the memory devices. For example, the bumps or protrusions of the metallic tape may allow more heat to be dissipated from the memory tape.

[0008] The advantages of the present disclosure include, but are not limited to, increased performance of the memory subsystem due to improved heat dissipation. For example, since the form factor of the memory subsystem cannot accommodate a metallic case, conventional heat sink, or fan, a metallic tape (i.e., a thermal cooling element) may dissipate heat from the memory devices of the memory subsystem while meeting the requirements of the form factor. Consequently, the performance of the memory subsystem may be improved as heat is dissipated from the memory devices.

[0009] FIG. 1 illustrates an exemplary computing system (100) comprising a memory subsystem (110) according to some embodiments of the present disclosure. The memory subsystem (110) may include a medium such as one or more volatile memory devices (e.g., memory device (140)), one or more non-volatile memory devices (e.g., memory device (130)), or a combination thereof.

[0010] The memory subsystem (110) may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include a Solid-State Drive (SSD), a flash drive, a Universal Serial Bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a Dual In-Line Memory Module (DIMM), a Small Outline Memory Module (SO-DIMM), and various types of Non-Volatile Dual In-Line Memory Modules (NVDIMM).

[0011] The computing system (100) may be a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, an unmanned aerial vehicle, a train, a car, or other means of transportation), an Internet of Things (IoT) capable device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or a computing device such as a computing device including memory and a processing unit.

[0012] A computing system (100) may include a host system (120) coupled to one or more memory subsystems (110). In some embodiments, the host system (120) is coupled to other types of memory subsystems (110). FIG. 1 illustrates an example of a host system (120) coupled to one memory subsystem (110). As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which may be an indirect communication connection, wired or wireless, or a direct communication connection (e.g., not interfering with the components), including connections such as electrical, optical, magnetic, etc.

[0013] The host system (120) may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system (120) writes data to the memory subsystem (110) and reads data from the memory subsystem (110), for example, using the memory subsystem (110).

[0014] A host system (120) may be coupled to a memory subsystem (110) via a physical host interface. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-Line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system (120) and the memory subsystem (110). The host system (120) may further utilize an NVM Express (NVMe) interface to access components (e.g., memory device (130)) when the memory subsystem (110) is coupled to the host system (120) by a PCIe interface. A physical host interface may provide an interface for transmitting control, address, data, and other signals between the memory subsystem (110) and the host system (120). FIG. 1 illustrates a memory subsystem (110) as an example. Generally, the host system (120) may access multiple memory subsystems through the same communication connection, multiple individual communication connections, and / or a combination of communication connections.

[0015] The memory devices (130, 140) may include any combination of different types of non-volatile memory devices and / or volatile memory devices. A volatile memory device (e.g., memory device (140)) may be a random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM), but is not limited thereto.

[0016] Some examples of non-volatile memory devices (e.g., memory device (130)) include negative-and (NAND) type flash memory and write-in-place memory, such as 3D crosspoint ("3D crosspoint") memory. A crosspoint array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Additionally, unlike many flash-based memories, crosspoint non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without being previously erased. NAND type flash memory includes, for example, 2D NAND and 3D NAND.

[0017] Each memory device (130) may include one or more memory cell arrays. For example, one type of memory cell, such as a single-level cell (SLC), may store 1 bit per cell. Other types of memory cells, such as a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC), may store multiple bits per cell. In some embodiments, each memory device (130) may include SLCs, MLCs, TLCs, QLCs, or any combination thereof. In some embodiments, a specific memory device may include an SLC portion of memory cells, and an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory devices (130) may be grouped into pages, which may be logic units of the memory device used to store data. In some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0018] Although nonvolatile memory components such as NAND-type flash memory (e.g., 2D NAND, 3D NAND) and 3D crosspoint arrays of nonvolatile memory cells are described, memory station (130) may be based on any other type of nonvolatile memory cells such as read-only memory (ROM), phase change memory (PCM), self-selection memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), negative-or (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0019] A memory subsystem controller (115) (or a controller (115) for simplification) may communicate with memory devices (130) to perform operations such as reading data, writing data, or erasing data, and other such operations on memory devices (130). The memory subsystem controller (115) may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include a digital circuit having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller (115) may be a microcontroller, a special-purpose logic circuit (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0020] The memory subsystem controller (115) may include a processor (117) (e.g., a processing unit) configured to execute instructions stored in local memory (119). In the illustrated example, the local memory (119) of the memory subsystem controller (115) includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem (110), including handling communication between the memory subsystem (110) and the host system (120).

[0021] In some embodiments, the local memory (119) may include memory registers that store memory pointers, fetched data, etc. The local memory (119) may also include read-only memory (ROM) for storing microcode. Although the exemplary memory subsystem (110) of FIG. 1 is illustrated as including a memory subsystem controller (115), in other embodiments of the present disclosure, the memory subsystem (110) may not include a memory subsystem controller (115) and instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0022] Generally, the memory subsystem controller (115) can receive commands or operations from the host system (120) and convert the commands or operations into commands or appropriate commands to achieve desired access to the memory device (130). The memory subsystem controller (115) may be responsible for wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and other operations such as address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device (130). The memory subsystem controller (115) may further include a host interface circuit for communicating with the host system (120) through a physical host interface. The host interface circuit can convert commands received from the host system into command instructions for accessing the memory device (130), as well as convert responses related to the memory device (130) into information about the host system (120).

[0023] The memory subsystem (110) may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem (110) may include a cache or buffer (e.g., DRAM) capable of receiving an address from a memory subsystem controller (115) and decoding an address for accessing a memory device (130), and an address circuitry (e.g., a row decoder and a column decoder).

[0024] In some embodiments, the memory device (130) includes a local media controller (135) that operates with a memory subsystem controller (115) to perform operations on one or more memory cells of the memory device (130). An external controller (e.g., memory subsystem controller (115)) may manage the memory device (130) externally (e.g., perform media management operations on the memory device (130)). In some embodiments, the memory device (130) is a managed memory device, which is a raw memory device coupled with a local controller (e.g., local controller (135)) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0025] The memory subsystem (110) may include a thermal cooling element (113) used to dissipate heat from memory devices (130 and 140) and / or a memory subsystem controller (115). For example, the thermal cooling element (113) may be coupled to the memory devices (130 and 140) to dissipate heat from the memory devices (130 and 140) during the operation of the memory subsystem (110). Further details regarding the thermal cooling element are described below.

[0026] FIG. 2 illustrates an exemplary memory subsystem (200) having a thermal cooling element according to some embodiments. Generally, the memory subsystem (200) may correspond to the memory subsystem (100) of FIG. 1.

[0027] The memory subsystem (200) may include memory devices (220, 221, and 222) on a board (210). Examples of memory devices (220, 221, and 222) include, but are not limited to, non-volatile memory devices and / or volatile memory devices. In some embodiments, one of the memory devices (220, 221, or 222) may be a memory subsystem controller that operates on other memory devices corresponding to the non-volatile memory devices and volatile memory devices. The board (210) may be a circuit board, logic board, or motherboard to which the memory devices (220, 221, and 222) are coupled together. For example, the board (210) may include connections between the various memory devices (220, 221, and 222).

[0028] As illustrated in FIG. 2, the memory subsystem (200) may further include a thermal cooling element (230) for memory devices (220, 221, and 222). The thermal cooling element (230) may be used to dissipate heat from the memory devices (220, 221, and 222). For example, during the operation of the memory subsystem (200), the memory devices (220, 221, and 222) may each generate heat. The thermal cooling element (230) may be considered as a type of heat sink or passive heat exchange element that transfers the heat generated from the memory devices (220, 221, and 222) to the air above the memory subsystem (200). The thermal cooling element (230) may be any material capable of conducting heat. Such materials include, but are not limited to, copper, aluminum, gold, steel, carbon, carbon nanotubes, or any metallic material. In some embodiments, the thermal cooling element (230) may be a copper tape. Alternatively, the thermal cooling element (230) may be an aluminum tape, a steel tape, a carbon tape, etc. According to one example, the thermal cooling element (230) may be a thin metallic material that is lower than the height of the memory devices (220, 221, and 222). According to another example, the thermal cooling element (230) may have protrusions spaced apart between the memory devices (220, 221, and 222) and may be pressed against the surface of the board (210), which allows for higher protrusions that result in better cooling without violating the height limit of the memory subsystem (200). Various other configurations of the thermal cooling element (230) are also possible.

[0029] A thermal cooling element (230) may be placed on top of memory devices (220, 221 and 222). For example, the thermal cooling element (230) may be fixed to the memory devices (220, 221 and 222) through a thermal adhesive layer or thermal adhesive.

[0030] Additionally, as illustrated, the thermal cooling element (230) may include a plurality of elements to create a pattern or texture on the thermal cooling element (230). For example, the thermal cooling element (230) may include a plurality of bumps (240) used to create a turbulent effect on the air passing over the thermal cooling element (230). The bumps (240) may allow air to flow through the bumps (240) and allow additional heat to be dissipated from the thermal cooling element (230). Since heat from the memory devices (220, 221, and 222) can be dissipated at each bump, excessive heat from one of the memory devices (220, 221, or 222) may not contribute to the heat generation of the other memory device (220, 221, or 222). For example, in the case of a heat sink that does not include any of these bumps (240), heat can be transferred from one end of the heat sink to the other end of the heat sink, so that heat generated from the memory device (220) can be added to the heat generated from the memory device (221), and as a result, the memory device (221) may become excessively hot. However, by means of the bumps (240), heat from the memory device (220) may be dissipated by the bumps on the memory device (220), so that less heat is transferred to the memory device (221) or no heat is transferred at all.

[0031] Although the thermal cooling element (230) is illustrated with bumps (240), any other type of protrusion or texture may be used for the thermal cooling element (230). The bumps (240) may be spread along the entire length of the thermal cooling element (230). In some embodiments, the bumps (240) may be located on portions above the memory devices (220, 221, and 222), whereas portions of the thermal cooling element (230) between the memory devices (220, 221, and 222) do not include the bumps (240), which are described in more detail below. Additionally, the bumps (240) may be of a height that meets the height requirements of the form factor for the memory subsystem (200). For example, the height of the bumps (240) may be smaller than the height of the memory devices (220, 221, and 222).

[0032] In this way, the thermal cooling element may include a flat surface (e.g., copper tape) and a plurality of protrusions (e.g., bumps) extending over the flat surface of the thermal cooling element.

[0033] FIG. 3 illustrates an overhead view of an exemplary thermal cooling element (300) according to some embodiments of the present disclosure. Generally, a memory subsystem corresponding to the memory subsystem (100) of FIG. 1 may include a thermal cooling element (300).

[0034] As previously described, the memory subsystem (300) may include a number of bumps (310) or other elements or protrusions. The bumps (310) may be a pattern that facilitates heat transfer from the thermal cooling element (300). For example, the bumps (310) may be a staggered pattern so that air over the thermal cooling element (300) does not flow in a straight line over the thermal cooling element (300). In some embodiments, the bumps (310) may be a diamond pattern or a series of offset rows (i.e., an offset grid pattern) or any other pattern. In the same or alternative embodiments, the bumps (310) may be a random pattern on the thermal cooling element (300).

[0035] FIG. 4 illustrates another exemplary thermal cooling element (430) for a memory subsystem (400) according to some embodiments. Generally, the memory subsystem (400) may correspond to the memory subsystem (100) of FIG. 1.

[0036] As illustrated in FIG. 4, the memory subsystem (400) may include bumps (440) or other elements at locations on a thermal cooling element (430) located directly above memory devices (420, 421, 422). For example, bumps (440) may be located on the thermal cooling element (430) above the memory device (420), whereas bumps are not located on the thermal cooling element (430) between the memory device (420) and the memory device (421), or in the space (450) between them. Bumps (440) may be located on parts above the memory devices (421 and 422), while bumps are not located on parts between the memory devices (421 and 422).

[0037] In some embodiments, the material of the thermal cooling element (430) in the space (450) (e.g., between memory devices (420 and 421) and memory devices (421 and 422)) may be made of or configured with a different type of material than the parts of the thermal cooling element (430) over the memory devices (420, 421 and 422). For example, as previously mentioned, the thermal cooling element (430) may be a copper tape having bumps (440) that are not made of copper in the space (450) between the memory devices. For example, the parts of the thermal cooling element (430) between the memory devices (e.g., in the space (450)) may be made of any type of insulating material.

[0038] In this way, the thermal cooling element (430) can be made of a combination of a thermally conductive material and an insulating material. For example, parts of the thermal cooling element (430) fixed above the memory devices (420, 421 and 422) may be based on a thermally conductive material containing bumps (440), whereas parts of the thermal cooling element (430) not above the memory devices (420, 421 and 422) may be based on an insulating material and do not contain bumps (440).

[0039] FIG. 5 illustrates another exemplary thermal cooling element for a memory subsystem (500) according to some embodiments. Generally, the memory subsystem (500) may correspond to the memory subsystem (100) of FIG. 1.

[0040] As illustrated in FIG. 5, the thermal cooling element may include an adhesive layer (530) and thermal conductive elements (540, 541, and 542). For example, the thermal conductive elements (540, 541, and 542) may be bumps placed on the adhesive layer over the memory devices (520, 521, and 522) or copper tape with such other textures. Thus, a single adhesive layer (530) may be located across the memory devices (520, 521, and 522), while the thermal conductive elements (540, 541, and 542) are bonded to the adhesive layer (530) at locations over the memory devices (520, 521, and 522).

[0041] In some embodiments, the thermal conductive elements may be based on the memory device located beneath each thermal conductive element. For example, different memory devices may generate different amounts of heat. In such cases, the thermal conductive element above the memory device may be different from other thermal conductive elements above other memory devices. In some embodiments, a memory device including a memory subsystem controller may generate a different amount of heat during operation than another memory device that is non-volatile memory (or volatile memory). In the same or alternative embodiments, the same thermal cooling element may include different thermal conductive elements for different types of memory devices of the same memory subsystem. In some embodiments, different thermal conductive elements may be made of different materials or may include protrusions of different patterns in which one type of material or pattern dissipates more heat than another type of material or pattern.

[0042] FIG. 6 is a flowchart of an exemplary method (600) for assembling an exemplary thermal cooling element for a memory subsystem according to some embodiments of the present disclosure. The method (600) may be performed by a machine or processing logic that may include hardware (e.g., a processing unit, circuitry, dedicated logic, programmable logic, microcode, hardware of the device, integrated circuit, etc.), software (e.g., instructions performed or executed by a processing unit), or a combination thereof. Although indicated in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in all embodiments. Other process flows are possible.

[0043] As illustrated in FIG. 6, in operation (610), processing logic determines the locations of memory devices in the memory subsystem. For example, the locations of memory devices on the motherboard of the memory subsystem may be identified. In operation (620), thermal cooling elements may be assembled based on the locations of memory devices in the memory subsystem. For example, thermal conductive elements may be fixed to an adhesive layer based on the locations of memory devices so that each thermal conductive element is placed on a different memory device. In some embodiments, the adhesive layer may include adhesive surfaces on both sides so that one surface of the adhesive layer is fixed to the upper surfaces of different memory devices, while the other surface of the adhesive layer is fixed to the lower surfaces of different thermal conductive elements. In operation (630), processing logic attaches the thermal cooling elements to the upper surfaces of memory devices in the memory subsystem. For example, a manufacturing machine may be used to attach the thermal cooling elements containing thermal conductive elements to the upper surfaces of memory devices located on the motherboard of the memory subsystem.

[0044] FIG. 7 illustrates an exemplary machine of a computer system (700) on which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system (700) may correspond to a host system (e.g., the host system (120) of FIG. 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., the memory subsystem (110) of FIG. 1), or may be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to the memory subsystem controller (115) of FIG. 1) or the operations of the method (600) of FIG. 6. In alternative embodiments, the machine may be connected (e.g., networked) to other machines on a LAN, intranet, extranet and / or the Internet. The machine can be operated with the capacity of a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0045] A machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web device, server, network router, switch or bridge, digital or non-digital circuitry, or any machine capable of executing a set of instructions (sequential or non-sequential) that specifies actions to be taken by the machine. Additionally, although a single machine is exemplified, the term “machine” should be considered to include any set of machines that execute a set of instructions (or multiple sets) individually or jointly to perform any one or more of the methodologies discussed herein.

[0046] An exemplary computer system (700) includes a processing unit (702), a main memory (704) (e.g., dynamic random access memory (DRAM), such as read-only memory (ROM), flash memory, synchronous DRAM (SDRAM), or Rambus DRAM (RDRAM)), a static memory (706) (e.g., flash memory, static random access memory (SRAM)), and a data storage system (718) that communicates with each other via a bus (730).

[0047] The processing unit (702) represents one or more general-purpose processing units, such as a microprocessor, a central processing unit, etc. More specifically, the processing unit may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing another instruction set, or a processor implementing a combination of instruction sets. The processing unit (702) may also be one or more special-purpose processing units, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing unit (702) is configured to execute instructions (726) for performing the operations and steps described herein. The computer system (700) may further include a network interface device (708) for communicating through a network (720).

[0048] The data storage system (718) may include a machine-readable storage medium (724) (also known as a computer-readable medium) in which software implementing one or more instruction sets (726) or any one or more of the methodologies or functions described herein is stored. The instructions (726) may also exist wholly or at least partially in the main memory (704) and / or the processing unit (702) during execution by the computer system (700), and the main memory (704) and the processing unit (702) also constitute a machine-readable storage medium. The machine-readable storage medium (724), the data storage system (718), and / or the main memory (704) may correspond to the memory subsystem (110) of FIG. 1.

[0049] In one embodiment, the instructions (726) include instructions for implementing a function corresponding to the method (600). Although the machine-readable storage medium (724) is depicted as a single medium in an exemplary embodiment, the term “machine-readable storage medium” should be considered to include a single medium or multiple media storing one or more sets of instructions. The term “machine-readable storage medium” should be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and enabling the machine to perform any one or more of the methodologies of the present disclosure. Accordingly, the term “machine-readable storage medium” should be considered to include solid-state memory, optical media, and magnetic media, but not limited thereto.

[0050] Parts of the previous detailed description were presented in terms of algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are methods used by technicians in the field of data processing technology to most effectively communicate the content of their work to others in the same field. In this document, an algorithm is generally considered to be a self-consistent sequence of operations leading to a desired result. Operations are operations that require the physical manipulation of physical quantities. Generally, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and, for other purposes, manipulated. For general use, it has often proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0051] However, it should be kept in mind that all such terms and similar terms must relate to appropriate physical quantities and are merely convenient labels applied to such quantities. The present disclosure may refer to actions and processes of a computer system or similar electronic computer device that manipulate and convert data expressed as physical (electronic) quantities within the registers and memory of a computer system into other data quantities similarly expressed as physical quantities within the computer system memory or registers or other information storage systems.

[0052] The present disclosure also relates to an apparatus for performing the operations of the present invention. The apparatus may include a general-purpose computer that is specifically configured for an intended purpose or is selectively activated or reconfigured by a computer program stored in the computer. Such computer programs may be stored on computer-readable storage media, such as floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus, but is not limited thereto.

[0053] The algorithms and displays presented herein are not inherently related to any specific computer or other device. Various general-purpose systems may be used with programs according to the teachings of this application, or it may be convenient to configure more specialized devices to perform the methods. The structures of such various systems will appear as described below. Additionally, this disclosure is not described by reference to any specific programming language. It will be understood that various programming languages ​​may be used to implement the teachings of this disclosure as described herein.

[0054] The present disclosure may be provided as a computer program product or software comprising a machine-readable medium storing instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium comprises any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium comprises a machine-readable (e.g., computer-readable) storage medium such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage medium, optical storage medium, flash memory components, etc.

[0055] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications may be made without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. Accordingly, the present specification and drawings should be regarded as illustrative rather than restrictive.

Claims

Claim 1 A system comprising: a plurality of memory devices; and a thermal cooling element comprising a lower surface coupled to the upper surface of each of the plurality of memory devices, wherein the thermal cooling element further comprises an upper surface and a plurality of protrusions, wherein the plurality of protrusions are connected to the upper surface and extend over the upper surface of the thermal cooling element, and wherein the plurality of protrusions dissipate heat generated from the plurality of memory devices using a plurality of thermal conductive elements located below the plurality of protrusions, and wherein the thermal conductive elements among the plurality of thermal conductive elements are based on a different material from other thermal conductive elements among the plurality of thermal conductive elements. Claim 2 A system according to claim 1, wherein the plurality of protrusions are arranged in an offset grid pattern. Claim 3 A system according to claim 1, wherein the upper surface of the thermal cooling element comprises a portion located above each of the plurality of memory devices and another portion located above the separation space between a pair of the plurality of memory devices, and wherein the plurality of protrusions are arranged in a pattern corresponding to the protrusions located in the portion located above each of the memory devices and the protrusions located in the other portion located above the separation space between the pair of memory devices are not. Claim 4 A system according to claim 1, wherein the thermal cooling element further comprises a thermal adhesive layer corresponding to the lower surface that is coupled to the upper surface of each of the plurality of memory devices. Claim 5 delete Claim 6 In paragraph 4, a system in which a heat conduction element among the plurality of heat conduction elements is based on a pattern different from that of another heat conduction element among the plurality of heat conduction elements. Claim 7 In claim 1, the thermal cooling element corresponds to at least one of copper tape, aluminum tape, steel tape, or carbon tape, in a system. Claim 8 A system comprising: a plurality of memory devices; and a thermal cooling element, wherein the thermal cooling element comprises: a flat surface coupled to the upper surface of the plurality of memory devices; and a plurality of protrusions extending over the flat surface of the thermal cooling element to dissipate heat generated from the plurality of memory devices, wherein the plurality of protrusions are in a pattern for dissipating the heat generated from the plurality of memory devices using a plurality of thermal conductive elements located below the plurality of protrusions, and wherein the thermal conductive elements among the plurality of thermal conductive elements are based on a different material from other thermal conductive elements among the plurality of thermal conductive elements. Claim 9 In paragraph 8, the above pattern corresponds to an offset grid pattern, a system. Claim 10 In claim 8, the pattern comprises a portion located above each of the plurality of memory devices and another portion located above the separation space between a pair of the plurality of memory devices, wherein the pattern corresponds to protrusions located in the portion located above each of the memory devices and does not have protrusions located in the other portion located above the separation space between the pair of memory devices. Claim 11 In claim 8, the thermal cooling element further comprises a thermal adhesive layer corresponding to the planar surface, and the thermal adhesive layer is bonded to the upper surface of each of the plurality of memory devices, a system. Claim 12 delete Claim 13 In claim 11, a system in which a heat conduction element among the plurality of heat conduction elements is based on a pattern different from that of another heat conduction element among the plurality of heat conduction elements. Claim 14 In claim 8, the thermal cooling element corresponds to at least one of copper tape, aluminum tape, steel tape, or carbon tape, in a system. Claim 15 A heat sink for a memory subsystem, wherein the heat sink comprises a thermal cooling element having a lower surface coupled to the upper surface of each of a plurality of memory devices of the memory subsystem, the thermal cooling element further comprises an upper surface and a plurality of protrusions, the plurality of protrusions being connected to the upper surface and extending over the upper surface of the thermal cooling element, the plurality of protrusions dissipating heat generated from the plurality of memory devices of the memory subsystem using a plurality of thermal conductive elements located below the plurality of protrusions, and wherein the thermal conductive elements among the plurality of thermal conductive elements are based on a different material from other thermal conductive elements among the plurality of thermal conductive elements. Claim 16 In item 15, the heat sink wherein the plurality of protrusions are arranged in an offset grid pattern. Claim 17 A heat sink according to claim 15, wherein the upper surface of the heat cooling element comprises a portion located over each of the plurality of memory devices and another portion located over the separation space between a pair of the plurality of memory devices, and wherein the plurality of protrusions are arranged in a pattern corresponding to the protrusions located in the portion located over each of the memory devices and the protrusions located in the other portion located over the separation space between the pair of memory devices are not. Claim 18 In claim 15, the heat sink further comprises a heat adhesive layer bonded to the upper surface of each of the plurality of memory devices. Claim 19 In paragraph 15, the heat cooling element corresponds to at least one of copper tape, aluminum tape, steel tape, or carbon tape, a heat sink. Claim 20 In paragraph 15, a heat sink in which a heat-conducting element among the plurality of heat-conducting elements is based on a pattern different from that of another heat-conducting element among the plurality of heat-conducting elements.

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