Mask for photoresist

Abstract

The present invention relates to a photoresist mask for extreme ultraviolet (EUV) lithography. The photoresist mask of the present invention comprises a main area where a main pattern is formed, a first dummy area surrounding the main area where a first dummy pattern is formed, and a plurality of second dummy areas disposed in corner areas and spaced apart from the first dummy area, where a second dummy pattern with a width greater than that of the first dummy pattern is formed, wherein the second dummy area is an area where a lithography process is performed at least three times.

Description

Technology Field

[0001] The present invention relates to a photoresist mask for extreme ultraviolet (EUV) lithography and a semiconductor device manufactured using the same. Background Technology

[0002] Advanced lithography processes are being developed to manufacture semiconductor devices with shrinking pitch. For example, extreme ultraviolet (EUV) lithography processes are being proposed to manufacture semiconductor devices with small pitch. Due to the excessive absorption of EUV radiation, EUV lithography systems generally use reflective optics apparatus to perform the lithography process.

[0003] However, conventional extreme ultraviolet (EUV) lithography systems can cause pattern uniformity issues and generate shadow effects that degrade lithography performance. Therefore, while conventional EUV lithography devices and processes are generally suitable for their intended purposes, they are not entirely satisfactory in all aspects.

[0004] In particular, when using a mask for extreme ultraviolet (EUV) lithography, there may be areas where the mask overlaps and is exposed two or more times. If exposure is performed multiple times, defects may occur in the pattern formed in the area. The problem to be solved

[0005] The technical problem that the present invention aims to solve is to provide a mask for photoresist with improved reliability.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0007] A mask for a photoresist according to some embodiments of the present invention for achieving the above technical problem comprises a main area where a main pattern is formed, a first dummy area surrounding the main area where a first dummy pattern is formed, and a plurality of second dummy areas disposed in corner areas and spaced apart from the first dummy area, where a second dummy pattern with a width greater than that of the first dummy pattern is formed, and the second dummy area is an area where a lithography process is performed at least three times.

[0008] A mask for a photoresist according to some embodiments of the present invention for achieving the above technical problem comprises: a first mask including a first main area where a first main pattern is formed, a first dummy area surrounding the first main area where a first dummy pattern is formed, and a plurality of second dummy areas spaced apart from the first dummy area where a second dummy pattern larger than the width of the first dummy pattern is formed, and a second mask including a second main area in contact with the first mask where a second main pattern is formed, a third dummy area surrounding the second main area where a third dummy pattern is formed, and a plurality of fourth dummy areas spaced apart from the third dummy area where a fourth dummy pattern larger than the width of the third dummy pattern is formed, wherein the second dummy area is placed in the corner area of ​​the first mask and the fourth dummy area is placed in the corner area of ​​the second mask, and the second and fourth dummy areas are areas where a lithography process is performed at least three times.

[0009] A mask for a photoresist according to some embodiment of the present invention for achieving the above technical problem comprises first to fourth masks aligned in a first direction and a second direction, wherein each of the first to fourth masks comprises a main area where a main pattern is formed, a first dummy area surrounding the main area where a first dummy pattern is formed, and a plurality of second dummy areas spaced apart from the first dummy area and including a second dummy pattern that is larger than the width of the first dummy pattern, wherein the width of the second dummy area in the first direction and the second direction is greater than 7 μm and less than 10 μm, respectively, the first mask is in contact with the second to fourth masks, the second mask is not in contact with the third mask, and the fourth mask is in contact with the first to third masks, and a part of the second dummy area is disposed in the corner area of ​​the second mask and the corner area of ​​the fourth mask at the part where the first mask, the second mask, and the fourth mask are in contact, and another part of the second dummy area is disposed in the corner area of ​​the third mask and the corner area of ​​the fourth mask at the part where the first mask, the third mask, and the fourth mask are in contact The first to fourth masks are each masks for extreme ultraviolet (EUV) lithography, and the second dummy area is an area where the extreme ultraviolet (EUV) lithography process is performed at least three times.

[0010] Specific details of other embodiments are included in the description of the invention and the drawings. Brief explanation of the drawing

[0011] FIG. 1 is a schematic plan view illustrating a mask for a photoresist according to some embodiments of the present invention. Figure 2 is a drawing for explaining the shape of a mask for photoresist of Figure 1. Figure 3 is an enlarged view of the P region of Figure 1. Figure 4 is an enlarged view of the Q region of Figure 1. Figure 5 is an enlarged view of the P and R regions of Figure 1. Figure 6 is an enlarged view of the P and S regions of Figure 1. FIGS. 7 and FIGS. 8 are drawings for illustrating masks for photoresist according to some embodiments. FIG. 9 is a schematic plan view illustrating a mask for a photoresist according to some embodiments of the present invention. FIG. 10 is a drawing for explaining the shape of the mask for the photoresist of FIG. 9. Figure 11 is an enlarged view of the T region of Figure 9. Figure 12 is an enlarged view of the U region of Figure 9. FIGS. 13 and FIGS. 14 are drawings for illustrating masks for photoresist according to some embodiments. FIG. 15 is a schematic cross-sectional view illustrating a mask for a photoresist according to some embodiments. FIG. 16 is an exemplary plan view of a semiconductor device manufactured using a mask for photoresist according to some embodiments. FIGS. 17a and FIGS. 17b are exemplary cross-sectional views cut along the AA line and BB line of FIG. 16. FIGS. 18a and FIGS. 18b are exemplary cross-sectional views cut along the CC line and DD line of FIG. 16. Specific details for implementing the invention

[0012] Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings.

[0013] FIG. 1 is a schematic plan view for illustrating a mask for a photoresist according to some embodiment of the present invention. FIG. 2 is a drawing for illustrating the shape of the mask for a photoresist of FIG. 1.

[0014] First, referring to FIG. 2, a mask (100) for photoresist according to some embodiments may include a first region (100a), a second region (100b), a third region (100c), and a fourth region (100d). In some embodiments, the mask (100) for photoresist may be a mask for extreme ultraviolet (EUV) lithography, but is not limited thereto.

[0015] The first region (100a), the second region (100b), the third region (100c), and the fourth region (100d) can be sequentially aligned in the first direction (D1). For example, the first region (100a) and the fourth region (100d) can be placed in the edge region, and the second region (100b) and the third region (100c) can be placed between the first region (100a) and the fourth region (100d). Specifically, the second region (100b) can be provided between the first region (100a) and the third region (100c), and the third region (100c) can be provided between the second region (100b) and the fourth region (100d).

[0016] The first region (100a), the second region (100b), the third region (100c), and the fourth region (100d) may each extend in a second direction (D2). The second direction (D2) may be a direction that intersects the first direction (D1). The second direction (D2) may be substantially perpendicular to the first direction (D1).

[0017] In some embodiments, the first region (100a) may completely overlap with the second region (100b) in the first direction (D1). Additionally, the width of the first region (100a) in the second direction (D2) may be smaller than the width of the second region (100b) in the second direction (D2). A portion of the third region (100c) may protrude in the second direction (D2) from the end of the second region (100b). A portion of the second region (100b) may protrude in the second direction (D2) from the end of the third region (100c). The left portion of the second region (100b) may protrude in the second direction (D2) from the third region (100c), and the right portion of the third region (100c) may protrude in the second direction (D2) from the second region (100b). The fourth region (100d) may completely overlap with the third region (100c) in the first direction (D1). A portion of the end of the third region (100c) may be provided coplanar with a portion of the end of the fourth region (100d).

[0018] In some embodiments, the mask (100) for photoresist may include edge regions (100e). "Edge" means line segments that form the boundaries of each face in a polyhedron. The edge regions (100e) may be some of the multiple edges of the mask (100) for photoresist.

[0019] A second dummy area (130) may be placed in the corner area (100e). The corner area (100e) may include a first corner (100e1), a second corner (100e2), a third corner (100e3), and a fourth corner (100e4). The first corner (100e1) may be part of the four corners of the first area (100a). For example, the first corner (100e1) may be a corner placed at the top-left end of the first area (100a). The first corner (100e1) may be provided in a portion where the first area (100a) and the second area (100b) do not touch. A first sub-dummy area (131) may be placed in the first corner (100e1).

[0020] The second corner (100e2) and the fourth corner (100e4) may be some of the four corners of the second area (100b). For example, the second corner (100e2) may be a corner positioned at the upper left of the second area (100b). The fourth corner (100e4) may be a corner positioned at the upper right of the second area (100b). The second corner (100e2) and the fourth corner (100e4) may be provided in the extended portion of the line where the first area (100a) and the second area (100b) meet. A second sub-dummy area (132) may be positioned at the second corner (100e2). A fourth sub-dummy area (134) may be positioned at the fourth corner (100e4).

[0021] The third corner (100e3) may be part of the four corners of the third area (100c). For example, the third corner (100e3) may be a corner positioned at the lower left end of the third area (100c). The third corner (100e3) may be provided in the part where the third area (100c) and the second area (100b) do not meet. The third corner (100e3) may be provided in the part where the line where the third area (100c) and the fourth area (100d) meet extends. A third sub-dummy area (133) may be positioned at the third corner (100e3).

[0022] Next, referring to FIGS. 1 and FIGS. 2, a mask (100) for a photoresist according to some embodiments may include a main region (110), a first dummy region (120), and a second dummy region (130).

[0023] The main region (110) may be a region where a main pattern is formed. The main pattern may include a main gate pattern and a main active pattern. The main pattern may, for example, be the gate electrode and active pattern of a transistor that is actually in operation. The main region (110) may be placed in the central part of the photoresist mask (100). For example, the main region (110) may be placed in the second region (100b) of the photoresist mask (100), but is not limited thereto. Although the main region (110) is depicted as being one, this is merely for convenience of explanation and the technical concept of the present invention is not limited thereto. Of course, the main region (110) may be one or more. For convenience of explanation, the main region (110) is described as being one in this specification.

[0024] A first dummy region (120) may be provided around the main region (110). The first dummy region (120) may surround the main region (110). The first dummy region (120) may be an area where a first dummy pattern is formed. The first dummy pattern may include a first dummy gate pattern and a first dummy active pattern. The first dummy pattern may be, for example, a gate electrode and an active pattern of a transistor that is not actually operating. Although the first dummy region (120) surrounding the main region (MR) is depicted as having two or more, the number, size, and shape of the first dummy region (120) are not limited thereto.

[0025] A second dummy region (130) may be provided in the corner region (100e) of the mask (100) for photoresist. The second dummy region (130) may be spaced apart from the first dummy region (120). That is, the second dummy region (130) may be spaced apart from the first dummy region (120) in a first direction (D1) and a second direction (D2).

[0026] In some embodiments, the second dummy area (130) may be four. For example, the second dummy area (130) may include a first sub-dummy area (131), a second sub-dummy area (132), a third sub-dummy area (133), and a fourth sub-dummy area (134). The first sub-dummy area (131) may be placed in the first area (100a). The first sub-dummy area (131) may be placed in the first corner (100e1). The second sub-dummy area (132) and the fourth sub-dummy area (134) may each be placed in the second area (100b). The second sub-dummy area (132) may be placed in the second corner (100e2). The fourth sub-dummy area (134) may be placed in the fourth corner (100e4). The third sub-dummy area (133) can be placed in the third area (100c). The third sub-dummy area (133) can be placed in the third corner (100e3).

[0027] In some embodiments, the second dummy region (130) is not placed in all corner regions of the mask (100) for photoresist. For example, the second dummy region (130) is not placed in the upper right, lower left, and lower right corner portions of the first region (100a), the lower left and lower right corner portions of the second region (100b), and the upper left, upper right, and lower left corner portions of the third region (100c). Additionally, the second dummy region (130) is not placed in the corner portions of the fourth region (100d).

[0028] In some embodiments, the second dummy region (130) may be a region where a second dummy pattern is formed. The second dummy pattern may include a second dummy gate pattern and a second dummy active pattern. The second dummy pattern may be a gate electrode and an active pattern of a transistor that is not actually operating.

[0029] In some embodiments, the second dummy region (130) may be an area where a lithography process is performed at least three times. That is, the second dummy region (130) may be an area where a lithography process is performed at least three times. The width of the second dummy pattern may be greater than the width of the main pattern and the width of the first dummy pattern. Therefore, even if a plurality of lithography processes are performed on the second dummy region (130), defects may not occur in the gate electrode and active pattern formed in the second dummy region (130).

[0030] FIG. 3 is an enlarged view of the P area of ​​FIG. 1. For reference, FIG. 3 may be an enlarged view of the first sub-dummy area (131) of FIG. 1. The first sub-dummy area (131) may be substantially identical to the second sub-dummy area (132), the third sub-dummy area (133), and the fourth sub-dummy area (134).

[0031] Referring to FIG. 3, the first sub-dummy region (131) may include a first sub-dummy gate pattern (131GP) and a first sub-dummy active pattern (131AP). The first sub-dummy gate pattern (131GP) may be a second dummy gate pattern, and the first sub-active pattern (131AP) may be a second dummy active pattern.

[0032] The first sub-dummy gate pattern (131GP) can be extended in a first direction (D1). The first sub-active pattern (131AP) can be extended in a second direction (D2). The first sub-dummy gate pattern (131GP) can intersect with the first sub-active pattern (131AP).

[0033] In some embodiments, the first sub-dummy gate pattern (131GP) may have a first width (W1) in the second direction (D2). The first width (W1) may be, for example, 100 nm or more and 150 nm or less. Preferably, the first width (W1) may be 120 nm, but is not limited thereto. The first sub-dummy active pattern (131AP) may have a second width (W2) in the first direction (D1). The second width (W2) may be, for example, 100 nm or more and 150 nm or less. Preferably, the second width (W2) may be 120 nm, but is not limited thereto. Of course, the first width (W1) and the second width (W2) may be the same or different from each other.

[0034] Since the first sub-dummy gate pattern (131GP) and the first sub-dummy gate pattern (131AP) are each larger than 100 nm, even if multiple lithography processes are performed on the second dummy region (130), defects may not occur in the pattern formed on the substrate.

[0035] In some embodiments, the width of the first subdummy area (131) in the second direction (D2) may have a first length (d1). The width of the first subdummy area (131) in the first direction (D1) may have a second length (d2). The first length (d1) may be the same as the second length (d2). For example, the first subdummy area (131) may have a square shape. However, the technical concept of the present invention is not limited thereto.

[0036] In some embodiments, the first length (d1) and the second length (d2) may each be, for example, greater than 7 μm and less than 10 μm. Preferably, the first length (d1) and the second length (d2) may each be 8 μm, but are not limited thereto. In other words, the area of ​​the first sub-dummy region (131) in the plane extending from the first direction (D1) and the second direction (D2) is 49 μm 2 Larger than 100㎛ 2 It may be smaller. Preferably, the area of ​​the first sub-dummy region (131) in the plane extending from the first direction (D1) and the second direction (D2) is 60 μm. 2 Larger than 70㎛ 2 It may be smaller. However, the technical concept of the present invention is not limited thereto.

[0037] FIG. 4 is an enlarged view of the Q region of FIG. 1. For reference, FIG. 4 may be an enlarged view of the first sub-dummy region (131) and the first dummy region (120).

[0038] Referring to FIG. 4, the first sub-dummy region (131) may be spaced apart from the first dummy region (120). The first sub-dummy region (131) is spaced apart from the first dummy region (120) in a first direction (D1) and a second direction (D2).

[0039] The first dummy region (120) may include a first dummy gate pattern (120GP) and a first dummy active pattern (120AP). The first dummy gate pattern (120GP) may extend in a first direction (D1). The first dummy active pattern (120AP) may extend in a second direction (D2). The first dummy gate pattern (120GP) and the first dummy active pattern (120AP) may intersect each other.

[0040] The first dummy gate pattern (120GP) may have a third width (W3) in the second direction (D2). The third width (W3) of the first dummy gate pattern (120GP) may be smaller than the first width (W1) of the first sub-dummy gate pattern (131GP). For example, the third width (W3) of the first dummy gate pattern (120GP) may be 1 nm or more and 10 nm or less. Preferably, the third width (W3) of the first dummy gate pattern (120GP) may be 2 nm, but is not limited thereto.

[0041] The first dummy active pattern (120AP) may have a fourth width (W4) in the first direction (D1). The fourth width (W4) of the first dummy active pattern (120AP) may be smaller than the second width (W2) of the first sub-dummy active pattern (131GP). For example, the fourth width (W4) of the first dummy active pattern (120AP) may be 20 nm or more and 50 nm or less. Preferably, the fourth width (W4) of the first dummy active pattern (120AP) may be 30 nm, but is not limited thereto.

[0042] FIG. 5 is an enlarged view of the P region and R region of FIG. 1. For reference, FIG. 5 may be an enlarged view of a first sub-dummy region and a part of the main region.

[0043] Referring to FIG. 5, a main pattern may be formed on the main region (MR). The main pattern may include a main gate pattern (110GP) and a main active pattern (110AP). The main gate pattern (110GP) may extend in a first direction (D1). The main active pattern (110AP) may extend in a second direction (D2). The main gate pattern (110GP) and the main active pattern (110AP) may intersect each other.

[0044] The main gate pattern (110GP) may have a fifth width (W5) in the second direction (D2). The fifth width (W5) of the main gate pattern (110GP) may be smaller than the first width (W1) of the first sub-dummy gate pattern (131GP). For example, the fifth width (W5) of the main gate pattern (110GP) may be 1 nm or more and 10 nm or less. Preferably, the fifth width (W5) of the main gate pattern (110GP) may be 2 nm, but is not limited thereto.

[0045] The main active pattern (110AP) may have a sixth width (W6) in the first direction (D1). The sixth width (W6) of the main active pattern (110AP) may be smaller than the second width (W2) of the first sub-dummy active pattern (131GP). For example, the sixth width (W6) of the main active pattern (110AP) may be 20 nm or more and 50 nm or less. Preferably, the sixth width (W6) of the main active pattern (110AP) may be 30 nm, but is not limited thereto.

[0046] FIG. 6 is an enlarged view of the P and S regions of FIG. 1. For reference, FIG. 6 may be an enlarged view of the first sub-dummy region (131) and the third sub-dummy region (133).

[0047] Referring to FIG. 6, the size of the first sub-dummy area (131) and the size of the third sub-dummy area (133) may be the same. Although not illustrated, the size of the first sub-dummy area (131) may be the same as the size of the second sub-dummy area (132) and the size of the fourth sub-dummy area (134).

[0048] For example, the width of the third sub-dummy area (133) in the second direction (D2) may have a third length (d3). The width of the third sub-dummy area (133) in the first direction (D1) may have a fourth length (d4). The third length (d3) may be the same as the fourth length (d4).

[0049] In some embodiments, the width of the first subdummy area (131) in the second direction (D2) may be the same as the width of the third subdummy area (133) in the second direction (D2). That is, the first length (d1) may be the same as the third length (d3). The width of the first subdummy area (131) in the first direction (D1) may be the same as the width of the third subdummy area (133) in the first direction (D1). That is, the second length (d2) may be the same as the fourth length (d4).

[0050] In some embodiments, the third length (d3) and the fourth length (d4) may each be, for example, greater than 7 μm and less than 10 μm. Preferably, the third length (d3) and the fourth length (d4) may each be 8 μm, but are not limited thereto.

[0051] In some embodiments, the area of ​​the third sub-dummy region (133) in the plane extending the first direction (D1) and the second direction (D2) may be the same as the area of ​​the first sub-dummy region (131). For example, the area of ​​the third sub-dummy region (133) in the plane extending the first direction (D1) and the second direction (D2) is 49 μm 2 Larger than 100㎛ 2 It may be smaller. Preferably, the area of ​​the third sub-dummy region (133) in the plane extending from the first direction (D1) and the second direction (D2) is 60 μm. 2 Larger than 70㎛ 2 It may be smaller. However, the technical concept of the present invention is not limited thereto.

[0052] In some embodiments, the width of the first sub-dummy gate pattern (131GP) and the width of the third sub-dummy gate pattern (133GP) may be the same. For example, the third sub-dummy gate pattern (133GP) may have a seventh width (W7) in the second direction (D2). The seventh width (W7) may be the same as the first width (W1). The seventh width (W7) may be, for example, 100 nm or more and 150 nm or less. Preferably, the seventh width (W7) may be 120 nm, but is not limited thereto.

[0053] The width of the first sub-dummy active pattern (131AP) and the width of the third sub-dummy active pattern (133AP) may be the same. For example, the third sub-dummy active pattern (133AP) may have an eighth width (W8) in the first direction (D1). The eighth width (W8) may be, for example, 100 nm or more and 150 nm or less. Preferably, the eighth width (W8) may be 120 nm, but is not limited thereto.

[0054] FIGS. 7 and 8 are drawings illustrating masks for photoresist according to some embodiments. For convenience of explanation, the explanation will focus on the differences from the explanation using FIGS. 1 to 6.

[0055] First, referring to FIG. 7, the width of the first sub-dummy gate pattern (131GP) and the width of the third sub-dummy gate pattern (133GP) may be different from each other. The width of the first sub-dummy active pattern (131AP) and the width of the third sub-dummy active pattern (133AP) may be different from each other. That is, the widths of the second dummy patterns formed in the second dummy area (130) may be different from each other.

[0056] For example, the first width (W1) may be different from the seventh width (W7). The second width (W2) may be different from the eighth width (W8). The widths of the first to fourth sub-dummy patterns may be different from each other. For example, the first width (W1) may be larger than the seventh width (W7) and the second width (W2) may be larger than the eighth width (W8), but is not limited thereto.

[0057] Referring to FIG. 8, the size of the first sub-dummy area (131) may differ from the size of the third sub-dummy area (133).

[0058] For example, the width of the first sub-dummy area (131) in the second direction (D2) may be greater than the width of the third sub-dummy area (133) in the second direction (D2). That is, the first length (d1) may be greater than the third length (d3). The width of the first sub-dummy area (131) in the first direction (D1) may be greater than the width of the third sub-dummy area (133) in the first direction (D1). That is, the second length (d2) may be greater than the fourth length (d4). However, the technical concept of the present invention is not limited thereto.

[0059] FIG. 9 is a schematic plan view illustrating a mask for a photoresist according to some embodiments of the present invention. FIG. 10 is a drawing illustrating the shape of the mask for a photoresist of FIG. 9. For convenience of explanation, the explanation will focus on the differences from the explanation using FIG. 1 to 6.

[0060] Referring to FIG. 9 and FIG. 10, a mask (200) for a photoresist according to some embodiments may include first to fourth masks (210, 220, 230, 240). Each of the first to fourth masks (210, 220, 230, 240) may be a mask for extreme ultraviolet (EUV) lithography, but is not limited thereto.

[0061] The first to fourth masks (210, 220, 230, 240) can be aligned with each other in a first direction (D1) and a second direction (D2). For example, the first mask (210) and the second mask (220) can be aligned in the second direction (D2). The third mask (230) and the fourth mask (240) can be aligned in the second direction (D2). The first mask (210) and the third mask (230) can be aligned in the first direction (D1). The second mask (220) and the fourth mask (240) can be aligned in the first direction (D1).

[0062] The first to fourth masks (210, 220, 230, 240) can come into contact with each other. For example, the first mask (210) can come into contact with the second to fourth masks (220, 230, 240). The second mask (220) can come into contact with the first mask (210) and the fourth mask (240). The second mask (220) does not come into contact with the third mask (230). The third mask (230) can come into contact with the first mask (210) and the fourth mask (240). The third mask (230) does not come into contact with the second mask (220). The fourth mask (240) can come into contact with the first to third masks (210, 220, 230).

[0063] The first mask (210) may include first to fourth regions (210a, 210b, 210c, 210d). The second mask (220) may include first to fourth regions (220a, 220b, 220c, 220d). The third mask (230) may include first to fourth regions (230a, 230b, 230c, 230d). The fourth mask (240) may include first to fourth regions (240a, 240b, 240c, 240d). The first to fourth masks (210, 220, 230, 240) may all have the same shape.

[0064] In some embodiments, the second region (210b) of the first mask (210) may be in contact with the second region (220b) of the second mask (220). The third region (210c) of the first mask (210) may be in contact with the third region (220c) of the second mask (220) and the first region (230a) of the third mask (230). The fourth region (210d) of the first mask (210) may be in contact with the first region (230a) of the third mask (230), the second region (230b) of the third mask (230), the first region (240a) of the fourth mask (240), and the second region (240b) of the fourth mask (240).

[0065] In some embodiments, the first mask (210) may include a first main area (MR1), a first dummy area (DR1), and a second dummy area (DR2). The second mask (220) may include a second main area (MR2), a third dummy area (DR3), and a fourth dummy area (DR4). The third mask (230) may include a third main area (MR3), a fifth dummy area (DR5), and a sixth dummy area (DR6). The fourth mask (240) may include a fourth main area (MR4), a seventh dummy area (DR7), and an eighth dummy area (DR8).

[0066] The first to fourth main regions (MR1, MR2, MR3, MR4) may be regions where transistors that actually operate are formed. The first to eighth dummy regions (DR1, DR2, DR3, DR4, DR5, DR6, DR7, DR8) may be regions where dummy transistors that do not actually operate are formed.

[0067] The second dummy area (DR2) may be spaced apart from the first dummy area (DR1). The second dummy area (DR2) may be placed in the corner area of ​​the first mask (210). The fourth dummy area (DR4) may be spaced apart from the third dummy area (DR3). The fourth dummy area (DR4) may be placed in the corner area of ​​the second mask (220). The sixth dummy area (DR6) may be spaced apart from the fifth dummy area (DR5). The sixth dummy area (DR6) may be placed in the corner area of ​​the third mask (230). The eighth dummy area (DR8) may be spaced apart from the seventh dummy area (DR7). The eighth dummy area (DR8) may be placed in the corner area of ​​the fourth mask (240).

[0068] FIG. 11 is an enlarged view of the T region of FIG. 9. With reference to FIG. 11, overlapping exposure regions according to some embodiments will be described.

[0069] Referring to FIG. 11, the first to fourth masks (210, 220, 230, 240) of the photoresist mask (200) according to some embodiments may be in contact with each other centered on the fourth region (210d) of the first mask (210).

[0070] In some embodiments, an exposure overlap region (250, 255) may be formed at the portion where the first to fourth masks (210, 220, 230, 240) come into contact with each other. The exposure overlap region (250, 255) may be an area where a lithography process is performed multiple times. For example, the exposure overlap region (250, 255) may include a double overlap region (255) and a triple overlap region (250). The double overlap region (255) may be an area where a lithography process is performed twice. The triple overlap region (250) may be an area where a lithography process is performed three times.

[0071] For example, when a lithography process is performed using a photoresist mask (200) according to some embodiments as an etching mask, a total of four lithography processes may be performed. Sequentially, a lithography process may be performed once using a first mask (210), a lithography process may be performed twice using a second mask (220), a lithography process may be performed three times using a third mask (230), and a lithography process may be performed four times using a fourth mask (240).

[0072] In FIG. 11, the first line (200ML) may be a line where the first mask (210), the second mask (220), the third mask (230), and the fourth mask (240) meet. The second line (200OL) may be a boundary line where exposure is irradiated when performing a lithography process using the first to fourth masks (210, 220, 230, 240) as etching masks. For example, even if a lithography process is performed using the first mask (210) as an etching mask, exposure may be irradiated up to the area of ​​the second line (200OL).

[0073] In some embodiments, the first line (200ML) and the second line (200OL) may be spaced apart from each other by a fifth length (d5). The fifth length (d5) may be, for example, greater than 7㎛ and less than 10㎛. Preferably, the fifth length (d5) may each be 8㎛, but is not limited thereto.

[0074] That is, when a lithography process is performed using a photoresist mask (200) according to some embodiments as an etching mask, the area separated by a fifth length (d5) from the boundary of the photoresist mask (200), for example, a first line (200ML), for example, up to a second line (200OL).

[0075] In some embodiments, the double overlap area (255) includes an area exposed twice using the first mask (210) and the second mask (220), an area exposed twice using the first mask (210) and the third mask (230), and an area exposed twice using the first mask (210) and the fourth mask (240). The triple overlap area (250) includes an area exposed three times using the first mask (210), the second mask (220), and the fourth mask (240), and an area exposed three times using the first mask (210), the third mask (230), and the fourth mask (240).

[0076] Referring to FIGS. 9 and FIGS. 11, a fourth dummy area (DR4), a sixth dummy area (DR6), and an eighth dummy area (DR8) may be placed in the triple overlapping area (250). Although not illustrated, a second dummy area (DR2) may also be placed in the triple overlapping area (250).

[0077] FIG. 12 is an enlarged view of the U region of FIG. 9. For reference, FIG. 12 may be an enlarged view of a portion of the 6th dummy region (DR6) and the 8th dummy region (DR8).

[0078] Referring to FIG. 12, the size of the sixth dummy area (DR6) and the size of the eighth dummy area (DR8) may be the same. Although not illustrated, the size of the second dummy area (DR2) and the size of the fourth dummy area (DR4) may be the same as the size of the sixth dummy area (DR6).

[0079] For example, the width of the sixth dummy area (DR6) in the second direction (D2) may have a sixth length (d6). The width of the sixth dummy area (DR6) in the first direction (D1) may have a seventh length (d7). The sixth length (d6) may be the same as the seventh length (d7).

[0080] The width of the eighth dummy region (DR8) in the second direction (D2) may have an eighth length (d8). The width of the eighth dummy region (DR8) in the first direction (D1) may have a ninth length (d9). The eighth length (d8) may be the same as the ninth length (d9).

[0081] In some embodiments, the width of the sixth dummy region (DR6) in the second direction (D2) may be the same as the width of the eighth dummy region (DR8) in the second direction (D2). The width of the sixth dummy region (DR6) in the first direction (D1) may be the same as the width of the eighth dummy region (DR8) in the first direction (D1). That is, the sixth length (d6) may be the same as the eighth length (d8). The seventh length (d7) may be the same as the ninth length (d9).

[0082] In some embodiments, the sixth length (d6), the seventh length (d7), the eighth length (d8), and the ninth length (d9) may each be, for example, greater than 7 μm and less than 10 μm. Preferably, the sixth length (d6), the seventh length (d7), the eighth length (d8), and the ninth length (d9) may each be 8 μm, but are not limited thereto.

[0083] In some embodiments, the area of ​​the sixth dummy region (DR6) in the plane extending the first direction (D1) and the second direction (D2) may be equal to the area of ​​the eighth dummy region (DR8). For example, in the plane extending the first direction (D1) and the second direction (D2), the area of ​​the sixth dummy region (DR6) and the area of ​​the eighth dummy region (DR8) are each 49 μm 2 Larger than 100㎛ 2 It may be smaller. Preferably, the area of ​​the sixth dummy region (DR6) and the area of ​​the eighth dummy region (DR8) in the plane extending from the first direction (D1) and the second direction (D2) are each 60 μm 2 Larger than 70㎛ 2 It may be smaller. However, the technical concept of the present invention is not limited thereto.

[0084] In some embodiments, the sixth dummy region (DR6) may include a sixth dummy gate pattern (GP6) and a sixth dummy active pattern (AP6). The eighth dummy region (DR8) may include an eighth dummy gate pattern (GP8) and an eighth dummy active pattern (AP8).

[0085] The width of the 6th dummy gate pattern (GP6) and the width of the 8th dummy gate pattern (GP8) may be the same. For example, the 6th dummy gate pattern (GP6) may have a 9th width (W9) in the 2nd direction (D2). The 8th dummy gate pattern (GP8) may have an 11th width (W11) in the 2nd direction (D2). The 9th width (W9) may be the same as the 11th width (W11). The 9th width (W9) and the 11th width (W11) may each be, for example, 100 nm or more and 150 nm or less. Preferably, the 9th width (W9) and the 11th width (W11) may each be 120 nm, but are not limited thereto.

[0086] The width of the 6th dummy active pattern (AP6) and the width of the 8th dummy active pattern (AP8) may be the same. For example, the 6th dummy active pattern (AP6) may have a 10th width (W10) in the 1st direction (D1). The 8th dummy active pattern (AP8) may have a 12th width (W12) in the 1st direction (D1). The 10th width (W10) and the 12th width (W12) may each be, for example, 100 nm or more and 150 nm or less. Preferably, the 10th width (W10) and the 12th width (W12) may each be 120 nm, but are not limited thereto.

[0087] FIGS. 13 and 14 are drawings illustrating masks for photoresist according to some embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIGS. 9 to 12.

[0088] First, referring to FIG. 13, the width of the 6th dummy gate pattern (GP6) and the width of the 8th dummy gate pattern (GP8) may be different from each other. The width of the 6th dummy active pattern (AP6) and the width of the 8th dummy active pattern (AP8) may be different from each other.

[0089] For example, the ninth width (W9) may be different from the eleventh width (W11). The tenth width (W10) may be different from the twelfth width (W12). The ninth width (W9) may be larger than the eleventh width (W11), and the tenth width (W10) may be larger than the twelveth width (W12), but is not limited thereto.

[0090] Referring to FIG. 14, the size of the sixth dummy region (DR6) may differ from the size of the eighth dummy region (DR8).

[0091] For example, the width of the sixth dummy area (DR6) in the second direction (D2) may be greater than the width of the eighth dummy area (DR8) in the second direction (D2). That is, the sixth length (d6) may be greater than the eighth length (d8). The width of the sixth dummy area (DR6) in the first direction (D1) may be greater than the width of the eighth dummy area (DR8) in the first direction (D1). That is, the seventh length (d7) may be greater than the ninth length (d9). However, the technical concept of the present invention is not limited thereto.

[0092] FIG. 15 is a schematic cross-sectional view illustrating a mask for a photoresist according to some embodiments.

[0093] Referring to FIG. 15, a simplified schematic partial cross-sectional view of a photoresist mask (300) is shown. The photoresist mask (300) can be implemented as an embodiment of a multilayer mask for a mask device.

[0094] In some embodiments, the photoresist mask (300) may include a silicon substrate (310). A plurality of silicon layers (320) and a molybdenum layer (330) may be provided on the silicon substrate (310). The plurality of silicon layers (320) and the plurality of molybdenum layers (330) may be alternately stacked on the silicon substrate (310). That is, a molybdenum layer (330) may be disposed on a silicon layer (320), and another silicon layer (320) may be disposed on a molybdenum layer (330). A ruthenium layer (340) may be disposed on the alternately stacked silicon layers (320) and molybdenum layers (330).

[0095] The photoresist mask (300) may also include a plurality of layout patterns (350). The layout patterns (350) may represent semiconductor device features to be patterned on a semiconductor wafer, for example, gate lines for a metal oxide semiconductor (MOS) transistor. For example, the layout patterns (350) may include a tantalum boron nitride layer (360) and a lawrencium layer (370).

[0096] However, this is only for the convenience of explanation, and the composition of the components and materials of the photoresist mask (300) may be changed.

[0097] In an extreme ultraviolet (EUV) lithography system, light (380) can be irradiated toward a mask (300) for photoresist. The light (380) may be, for example, an extreme ultraviolet (EUV) radiation beam generated by a light source device. The light (380) may be irradiated toward the mask (300) for photoresist at a non-incident angle.

[0098] That is, light (380) can be irradiated obliquely toward the photoresist mask (300) to form a vertical axis (395) and an angle of incidence (390) perpendicular to the surface of the photoresist mask (300). The light (380) can be reflected from the surface of the ruthenium layer (340) to form reflected light (385). The reflected light (385) is projected toward a projection optical system (not shown) to perform an extreme ultraviolet (EUV) lithography process that continues in the range of about 5° to about 7°. However, since the layout pattern (350) has a constant vertical height and the light (380) or reflected light (385) can form a vertical axis (395) and an angle of incidence (390), a shadow (375) can be formed on the surface of the photoresist mask (300). This is called a shadow effect or shadow bias.

[0099] FIG. 16 is an exemplary plan view of a semiconductor device manufactured using a mask for a photoresist according to some embodiments. FIG. 17a and FIG. 17b are exemplary cross-sectional views cut along the AA and BB lines of FIG. 16. FIG. 18a and FIG. 18b are exemplary cross-sectional views cut along the CC and DD lines of FIG. 16.

[0100] Referring to FIGS. 16 to 18b, a semiconductor device manufactured using a mask for photoresist according to some embodiments may include a first region (I) and a second region (II). The first region (I) may be the main region (110) of FIG. 1, and the second region (II) may be the second dummy region (130) of FIG. 1.

[0101] A semiconductor device according to some embodiments may include a substrate (400), a field insulating film (405), a main gate electrode (420a), a dummy gate electrode (420b), a main active pattern (MAP), and a dummy active pattern (DAP).

[0102] Although not illustrated, the substrate (400) may include an active region and a field region. The field region may be formed between adjacent active regions. The active region may be an area where a main active pattern (MAP) and a dummy active pattern (DAP) are placed. The field region may be bordered by the active region. The active region may be separated by the field region.

[0103] Alternatively, a device isolation layer may be disposed around multiple spaced-apart active regions. In this case, the portion of the device isolation layer located between the active regions may be a field region. For example, the portion where the channel region of a transistor, which can be an example of a semiconductor device, is formed may be an active region, and the portion separating the channel region of the transistor formed in the active region may be a field region. Alternatively, the active region may be a portion where a fin-shaped pattern or nanosheet used as the channel region of the transistor is formed, and the field region may be a portion where the fin-shaped pattern or nanosheet used as the channel region is not formed.

[0104] The substrate (400) may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate (400) may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0105] The main active pattern (MAP) may protrude from the substrate (400) of the first region (I). The main active pattern (MAP) may extend along the third direction (X) on the substrate (400) of the first region (I). For example, the main active pattern (MAP) may include a long side extending in the third direction (X) and a short side extending in the fourth direction (Y). Here, the third direction (X) may intersect with the fourth direction (Y) and the fifth direction (Z). Additionally, the fourth direction (Y) may intersect with the fifth direction (Z).

[0106] The dummy active pattern (DAP) may protrude from the substrate (400) of the second region (II). The dummy active pattern (DAP) may be extended along a third direction (X) on the substrate (400) of the second region (II). For example, the dummy active pattern (DAP) may include a long side extending in the third direction (X) and a short side extending in the fourth direction (Y).

[0107] The main active pattern (MAP) and the dummy active pattern (DAP) may each be a multi-channel active pattern. In a semiconductor device according to some embodiments, the main active pattern (MAP) and the dummy active pattern (DAP) may each be a pin-shaped pattern and may include a bottom pattern and a sheet pattern.

[0108] For example, in FIGS. 17a and FIGS. 18a, the main active pattern (MAP) and the dummy active pattern (DAP) may each be pin-shaped patterns. In FIGS. 17b and FIGS. 18b, the main active pattern (MAP) may include a main lower pattern (MBP) and a plurality of main sheet patterns (MSP). The main sheet pattern (MSP) may be spaced apart from the main lower pattern (MBP) in the fifth direction (Z). The main dummy active pattern (DAP) may include a dummy lower pattern (DBP) and a plurality of dummy sheet patterns (DSP). The dummy sheet pattern (DSP) may be spaced apart from the dummy lower pattern (DBP) in the fifth direction (Z). Although the main sheet pattern (MSP) and the dummy sheet pattern (DSP) are each depicted as having three, this is merely for convenience of explanation and the technical concept of the present invention is not limited thereto.

[0109] When forming a main active pattern (MAP) and a dummy active pattern (DAP) using a mask for a photoresist according to some embodiments, the width (MAP_W) of the main active pattern (MAP) in the fourth direction (Y) may be smaller than the width (DAP_W) of the dummy active pattern (DAP) in the fourth direction (Y). For example, the width (MAP_W) of the main active pattern (MAP) in the fourth direction (Y) may be 20 nm or more and 50 nm or less. The width (DAP_W) of the dummy active pattern (DAP) in the fourth direction (Y) may be 100 nm or more and 150 nm or less.

[0110] The main active pattern (MAP) and the dummy active pattern (DAP) may each be part of the substrate (400) and may include an epitaxial layer grown from the substrate (400). The main active pattern (MAP) and the dummy active pattern (DAP) may include, for example, elemental semiconductor materials such as silicon or germanium. Additionally, the main active pattern (MAP) and the dummy active pattern (DAP) may include compound semiconductors, for example, group IV-IV compound semiconductors or group III-V compound semiconductors.

[0111] Group IV-IV compound semiconductors may be, for example, binary compounds, ternary compounds containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds doped with a Group IV element.

[0112] A III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimonium (Sb).

[0113] In FIG. 18a, the field insulating film (405) may be formed on a portion of the sidewall of the main active pattern (MAP) and a portion of the sidewall of the dummy active pattern (DAP). In FIG. 18b, the field insulating film (405) may be formed on a portion of the sidewall of the main lower pattern (MBP) and a portion of the sidewall of the dummy lower pattern (DBP). The main lower pattern (MBP) and the dummy lower pattern (DBP) may each protrude above the upper surface of the field insulating film (405). The field insulating film (405) may comprise, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0114] The main gate structure (MGS) may be placed on the substrate (400) of the first region (I). The main gate structure (MGS) may extend in the fourth direction (Y). The main gate structure (MGS) may be placed on the field insulating film (405). The main gate structure (MGS) may be placed on the main active pattern (MAP). The main gate structure (MGS) may intersect with the main active pattern (MAP).

[0115] A dummy gate structure (DGS) can be placed on the substrate (400) of the second region (II). The dummy gate structure (DGS) can be extended in the fourth direction (Y). The dummy gate structure (DGS) can be placed on the field insulating film (405). The dummy gate structure (DGS) can be placed on the dummy active pattern (DAP). The dummy gate structure (DGS) can intersect with the dummy active pattern (DAP).

[0116] The main gate structure (MGS) may include, for example, a main gate electrode (420a), a main gate insulating film (430a), a main gate spacer (440a), and a main gate capping pattern (450a). The dummy gate structure (DGS) may include, for example, a dummy gate electrode (420b), a dummy gate insulating film (430b), a dummy gate spacer (440b), and a dummy gate capping pattern (450b).

[0117] A main gate electrode (420a) may be formed on a main active pattern (MAP). The main gate electrode (420a) may intersect with the main active pattern (MAP). In FIG. 17a, the main gate electrode (420a) is formed on the main active pattern (MAP). In FIG. 17b, the main gate electrode (420a) may be placed on a main lower pattern (MBP) to wrap around a main sheet pattern (MSP). A dummy gate electrode (420b) may be formed on a dummy active pattern (DAP). The dummy gate electrode (420b) may intersect with the dummy active pattern (DAP). In FIG. 17a, the dummy gate electrode (420b) is formed on the dummy active pattern (DAP). In FIG. 17b, the dummy gate electrode (420b) may be placed on a dummy lower pattern (DBP) to wrap around a dummy sheet pattern (DSP).

[0118] In some embodiments, the width (420a_W) of the main gate electrode (420a) in the third direction (X) may be smaller than the width (420b_W) of the dummy gate electrode (420b) in the third direction (X). For example, when the main gate electrode (420a) and the dummy gate electrode (420b) are formed using a mask for photoresist according to some embodiments, the width of the main gate electrode (420a) may be smaller than the width (420b) of the dummy gate electrode. The width (420b_W) of the main gate electrode (420a) in the third direction (X) may be, for example, 1 nm or more and 10 nm or less. The width (420b_W) of the dummy gate electrode (420b) in the third direction (X) may be, for example, 100 nm or more and 150 nm or less.

[0119] The main gate electrode (420a) and the dummy gate electrode (420b) are each, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), It may include at least one of molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof.

[0120] The main gate spacer (440a) may be placed on the sidewall of the main gate electrode (420b). The dummy gate spacer (440b) may be placed on the sidewall of the dummy gate electrode (440b).

[0121] The main gate spacer (440a) and the dummy gate spacer (440b) may each include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0122] The main gate insulating film (430a) may extend along the sidewalls and bottom surfaces of the main gate electrode (420a). The main gate insulating film (430a) may be formed on the main active pattern (MAP). The main gate insulating film (430a) may be formed between the main gate electrode (420a) and the main gate spacer (440a). In FIG. 18b, the main gate insulating film (430a) may extend along the top surface of the main bottom pattern (MBP) and the top surface of the field insulating film (405). The main gate insulating film (430a) may wrap around the perimeter of the main sheet pattern (MSP).

[0123] The dummy gate insulating film (430b) may extend along the sidewalls and bottom surfaces of the dummy gate electrode (420b). The dummy gate insulating film (430b) may be formed on the dummy active pattern (DAP). The dummy gate insulating film (430b) may be formed between the dummy gate electrode (420b) and the dummy gate spacer (440b). In FIG. 18b, the dummy gate insulating film (430b) may extend along the top surface of the dummy bottom pattern (DBP) and the top surface of the field insulating film (405). The dummy gate insulating film (430b) may wrap around the perimeter of the dummy sheet pattern (DSP).

[0124] The main gate insulating film (430a) and the dummy gate insulating film (430b) may each include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. High dielectric constant materials may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0125] A semiconductor device according to some embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the main gate insulating film (430a) and the dummy gate insulating film (430b) may each include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0126] Ferroelectric film materials can have negative capacitance, while paraelectric film materials can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be smaller than the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance will have a positive value and may be greater than the absolute value of each individual capacitance.

[0127] When a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0128] Ferroelectric material films may have ferroelectric properties. Ferroelectric material films may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0129] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0130] When the ferroelectric material film contains hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0131] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0132] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0133] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0134] Ferroelectric and paraelectric film layers may contain the same material. Ferroelectric film layers possess ferroelectric properties, whereas paraelectric film layers may not. For example, if both ferroelectric and paraelectric film layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film layer is different from the crystal structure of the hafnium oxide contained in the paraelectric film layer.

[0135] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0136] In some embodiments, the main gate insulating film (430a) and the dummy gate insulating film (430b) may each include a single ferroelectric material film. In other embodiments, the main gate insulating film (430a) and the dummy gate insulating film (430b) may each include a plurality of ferroelectric material films spaced apart from each other. The main gate insulating film (430a) and the dummy gate insulating film (430b) may each have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0137] The main gate capping pattern (450a) may be disposed on the upper surface of the main gate electrode (420a) and the upper surface of the main gate spacer (440a). The dummy gate capping pattern (450b) may be disposed on the upper surface of the dummy gate electrode (420b) and the upper surface of the dummy gate spacer (440b). The main gate capping pattern (450a) and the dummy gate capping pattern (450b) may each include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof.

[0138] A semiconductor device according to some embodiments may further include a source / drain pattern (460). The source / drain pattern (460) may be placed on the side of a main gate structure (MGS) or on the side of a dummy gate structure (DGS).

[0139] The source / drain pattern (460) may include an epitaxial pattern. The source / drain pattern (460) may be included in the source / drain region of a transistor using a main active pattern (MAP) or a dummy active pattern (DAP) as the channel region.

[0140] A semiconductor device according to some embodiments may further include an etch stop layer (465). The etch stop layer (465) may be disposed on the upper surface of the source / drain pattern (460), the sidewall of the main gate structure (MGS), and the sidewall of the dummy gate structure (DGS). Although not illustrated, the etch stop layer (465) may be disposed along the sidewall of the source / drain pattern (460) and the upper surface of the field insulating layer (405). The etch stop layer (465) may include, for example, a material having an etch selectivity ratio with respect to the first interlayer insulating layer (470). The etch stop layer (465) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0141] The first interlayer insulating film (470) may be formed on the source / drain pattern (460) and the field insulating film (405). The first interlayer insulating film (470) may be placed between adjacent main gate structures (MGS) or between dummy gate structures (DGS). The upper surface of the first interlayer insulating film (470) may be placed in the same plane as the upper surface of the main gate capping pattern (450a) and the upper surface of the dummy gate capping pattern (450b).

[0142] The first interlayer insulating film (470) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Low dielectric constant materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate) Glass), SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, It may include mesoporous silica or a combination thereof, but is not limited thereto.

[0143] The second interlayer insulating film (480) may be placed on the first interlayer insulating film (470). The second interlayer insulating film (480) may be placed on the main gate capping pattern (450a) and the dummy gate capping pattern (450b). The second interlayer insulating film (480) may cover the first interlayer insulating film (470), the main gate capping pattern (450a), and the dummy gate capping pattern (450b).

[0144] The second interlayer insulating film (480) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0145] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0146] 100: Mask for photoresist 110: Main area 120: 1st Dummy Area 130: 2nd Dummy Area 100e: Corner area 200: Mask for photoresist 210: 1st Mask 220: 2nd Mask 230: 3rd Mask 240: 4th Mask 250: Triple nested area 255: Double nested area 400: Substrate 405: Field insulating film MAP: Main active pattern DAP: Dummy active pattern 420a: Main gate electrode 420b: Dummy gate electrode

Claims

Claim 1 A photoresist mask comprising: a main area where a main pattern is formed; a first dummy area surrounding the main area where a first dummy pattern is formed; and a plurality of second dummy areas disposed in corner areas and spaced apart from the first dummy area, wherein a second dummy pattern having a width greater than that of the first dummy pattern is formed, wherein the second dummy area is an area where a lithography process is performed at least three times, wherein the photoresist mask comprises first to fourth areas aligned in a first direction and extending in a second direction, wherein the first area completely overlaps with the second area in the first direction, a part of the third area protrudes from the end of the second area in the second direction, and the fourth area completely overlaps with the third area in the first direction. Claim 2 A mask for a photoresist according to claim 1, wherein the main pattern includes a main gate pattern, the second dummy pattern includes a second dummy gate pattern, and the width of the second dummy gate pattern is greater than the width of the main gate pattern. Claim 3 A mask for photoresist according to claim 1, wherein the width of the second dummy region is greater than 7㎛ and less than 10㎛. Claim 4 In claim 1, the area of ​​the second dummy region is 49㎛ 2 Larger than, 100㎛ 2 A smaller mask for photoresist. Claim 5 delete Claim 6 In claim 1, the photoresist mask is a photoresist mask that is an extreme ultraviolet (EUV) lithography mask. Claim 7 A mask for a photoresist comprising: a first mask including a first main area where a first main pattern is formed, a first dummy area surrounding the first main area where a first dummy pattern is formed, and a plurality of second dummy areas spaced apart from the first dummy area where a second dummy pattern larger than the width of the first dummy pattern is formed; and a second mask including a second main area in contact with the first mask where a second main pattern is formed, a third dummy area surrounding the second main area where a third dummy pattern is formed, and a plurality of fourth dummy areas spaced apart from the third dummy area where a fourth dummy pattern larger than the width of the third dummy pattern is formed, wherein the second dummy area is disposed in the corner area of ​​the first mask and the fourth dummy area is disposed in the corner area of ​​the second mask, and the second and fourth dummy areas are areas where a lithography process is performed at least three times. Claim 8 A mask for a photoresist according to claim 7, wherein the first mask comprises first to fourth regions aligned in a first direction and extending in a second direction, the first region of the first mask completely overlaps with the second region of the first mask in the first direction, a part of the third region of the first mask protrudes in the second direction from the end of the second region of the first mask, and the fourth region of the first mask completely overlaps with the third region of the first mask in the first direction, and the first mask comprises first to fourth regions aligned in a first direction and extending in a second direction, the first region of the second mask completely overlaps with the second region of the second mask in the first direction, a part of the third region of the second mask protrudes in the second direction from the end of the second region of the second mask, and the fourth region of the second mask completely overlaps with the third region of the second mask in the first direction. Claim 9 A mask for a photoresist according to claim 8, wherein some of the second dummy regions are disposed on the second region of the first mask at the portion where the second region of the first mask and the second region of the second mask meet, and some of the fourth dummy regions are disposed on the second region of the second mask at the portion where the second region of the first mask and the second region of the second mask meet. Claim 10 It includes first to fourth masks aligned in a first direction and a second direction, wherein each of the first to fourth masks includes a main area where a main pattern is formed, a first dummy area surrounding the main area where a first dummy pattern is formed, and a plurality of second dummy areas spaced apart from the first dummy area and including a second dummy pattern that is larger than the width of the first dummy pattern, wherein the width of the second dummy area in the first direction and the second direction is greater than 7 μm and less than 10 μm, respectively, the first mask is in contact with the second to fourth masks, the second mask is not in contact with the third mask, and the fourth mask is in contact with the first to third masks, and a part of the second dummy area is disposed in the corner area of ​​the second mask and the corner area of ​​the fourth mask at the part where the first mask, the second mask, and the fourth mask are in contact, and another part of the second dummy area is disposed in the corner area of ​​the third mask and the fourth mask at the part where the first mask, the third mask, and the fourth mask are in contact. A photoresist mask disposed in the corner region of the mask, wherein the first to fourth masks are each masks for extreme ultraviolet (EUV) lithography, and the second dummy region is a region where the extreme ultraviolet (EUV) lithography process is performed at least three times.

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