Enhanced High Parallel Test Method and System for Mass Production

Abstract

A semiconductor parallel test method and system considering a mass production environment are presented. The semiconductor parallel test system considering a mass production environment proposed in the present invention includes an analog signal control module that checks the status of a Device Under Test (DUT) in an Automated Test Equipment (ATE), excludes failed DUTs, and masks them to diagnose the DUTs, and a digital signal control module that checks the status of the Device Under Test (DUT) in the ATE, receives a Site Variable (SV) containing information on failed DUTs, and controls the input of a failure detection module by passing through a DUT control module using the SV.

Description

Technology Field

[0001] The present invention relates to a method and system for maximizing test parallelism in consideration of a mass production environment. Background Technology

[0002] ATE (Automated Test Equipment) is generally used for wafer testing and package testing, and is equipment used to filter out defective products and ensure product performance during the semiconductor manufacturing process.

[0003] The DIB (Device Interface Board) is a board that serves as an interface between the ATE and the DUT (Device Under Test), and is designed to optimize signal transmission between the ATE and the DUT to obtain accurate test results.

[0004] Various tests are executed through ATE, ranging from DC parametric tests including Open / short / leakage, to functional tests to verify whether the DUT's functions operate normally.

[0005] As ICs become more highly integrated, the time required for testing has increased, and this increase in testing time leads to higher testing costs. A representative method proposed to address this is the parallel testing technique. Prior art literature

[0006] [1] J. Shenoy, K. Ockunzzi, K. Kamal and V. Singh, "Test cost reduction through increase in multi-site testing with reduced scan-out pins," 2019 IEEE International Test Conference India (ITC India), Bangalore, India, 2019, pp. 1-5.[2] S. Seo, Y.-W. Lee, H. Lim and S. Kang, "Advanced Low Pin Count Test Architecture for Efficient Multi-Site Testing," in IEEE Transactions on Semiconductor Manufacturing, vol. 33, no. 3, pp. 391-403, Aug. 2020.[3] B. Li, B. Zhang and V. D. Agrawal, "Adopting multi-valued logic for reduced pin-count testing," 2015 16th Latin-American Test Symposium (LATS), Puerto Vallarta, Mexico, 2015, pp. 1-6.[4] H. Kim and Y. LEE "Output compression scheme for Multi-Site Testing for System-on-Chip" in Proc. Asia-Pacific Workshop on Advanced Semiconductor Devices (AWAD), Yokohama, Japan, July 2023.[5] J. Shin, J. Bae, and Y. Lee, "Reduced Pin-Count Test Scheme for High parallel Test Capabilities" in Proc.Asia-pacific Workshop on Advanced Semiconductor Devices (AWAD), Yokohama, Japan, July 2023. The problem to be solved

[0007] The technical problem that the present invention aims to solve is to provide a method and system for maximizing test parallelism considering the mass production environment, in order to address the issue where the time required for testing increases as ICs become more highly integrated, and this increase in test time leads to higher test costs. The test interface aims to improve parallel processing efficiency by reducing test resources and to ensure high reliability through mutual complementarity between the analog signal control module and the digital signal control module. means of solving the problem

[0008] In one aspect, the semiconductor parallel test system proposed in the present invention, considering a mass production environment, includes an analog signal control module that checks the status of a Device Under Test (DUT) in an Automated Test Equipment (ATE), excludes failed DUTs, masks, and diagnoses the DUTs, and a digital signal control module that checks the status of a Device Under Test (DUT) in the ATE, receives a Site Variable (SV) containing information on failed DUTs, and controls the input of a failure detection module by passing through a DUT control module using the SV.

[0009] The analog signal control module checks the DUT status in the ATE, excludes the failed test DUT based on the check result, masks the failed test DUT with an 'X' bit, determines whether the masking has ended, and diagnoses the DUT if it has ended.

[0010] The analog signal control module performs an XOR operation on the test data of the DUT and the expected output of the ATE to check the DUT status in the ATE, and uses the result of the XOR operation as the input to the DAC to detect the location and number of test failure DUTs according to the voltage level of the voltage value converted through the DAC.

[0011] The digital signal control module includes a DUT controllable module that fixes the clock by connecting pull-up and pull-down resistors to the clock of the D-FF to maintain internal data of the D-FF, and fixes the input of the MUX connected to the flip-flop output and the enable signal; wherein the DUT controllable module masks the input to the DUT controllable module with a logic 'HIGH' corresponding to a failure value for the DUT corresponding to the test failure DUT; and a failure detection module that outputs a signal with the test result compressed to the ATE.

[0012] In another aspect, the semiconductor parallel test method proposed in the present invention, considering a mass production environment, includes the step of diagnosing the DUT by masking and excluding the failed DUT by checking the DUT status in the Automated Test Equipment (ATE) through an analog signal control module, and the step of checking the DUT status in the ATE through a digital signal control module to receive a Site Variable (SV) containing information on the failed DUT, and controlling the input of a failure detection module by passing through a DUT control module using the SV.

[0013] The step of diagnosing the DUT by checking the DUT status in the ATE through the analog signal control module, excluding the failed test DUT, and masking it includes the step of checking the DUT status in the ATE, the step of excluding the failed test DUT according to the result of the check, the step of masking the failed test DUT with an 'X' bit, and the step of determining whether the masking has ended and, if it has ended, diagnosing the DUT. Effects of the invention

[0014] According to embodiments of the present invention, the test interface improves parallel processing efficiency by reducing test resources and has a structure applicable to mass production environments. High reliability is ensured through mutual complementarity between the analog signal control module and the digital signal control module, and no additional test costs are incurred because diagnosis is performed by utilizing functions built into the ATE equipment. In addition, by utilizing analog devices that are not used during digital function testing, test throughput can be maximized within the limited environment of the equipment. Brief explanation of the drawing

[0015] FIG. 1 is a diagram showing the configuration of a parallel test system considering a mass production environment according to one embodiment of the present invention. FIG. 2 is a flowchart illustrating a parallel test method considering a mass production environment according to an embodiment of the present invention. FIG. 3 is a diagram illustrating an analog signal control module and an operation method according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a digital signal control module and an operation method according to an embodiment of the present invention. FIG. 5 is a diagram showing the 16-bit DAC simulation results according to one embodiment of the present invention. FIG. 6 is a diagram showing the simulation results of a digital signal control module according to one embodiment of the present invention. Specific details for implementing the invention

[0016] RPCT (Reduced Pin Count Test) is a representative technique used to reduce test costs. It tests the DUT by applying designs and methodologies that reduce the number of pins required for testing. When used in conjunction with parallel testing, it can effectively reduce the resources required for testing.

[0017] The Test Output Compression Scheme according to the prior art maximized parallel test efficiency by inputting test data from 16 DUTs into a 16-bit DAC and then analyzing the converted values ​​in a DSP within an ATE operating in the background.

[0018] Another conventional test output comparison technique is a circuit containing a simple gate and FF that compresses two DUTs into a single output and detects the location of the defective DUT by capturing two values ​​in one cycle.

[0019] When a test item fails, the DUT is turned off to proceed with the test for failure analysis; however, during parallel testing, the two test modules located in the DIB do not recognize the off-dUT, resulting in a problem where the off-dUT is included in the test.

[0020] If the ATE recognizes the garbage value output from the corresponding DUT and judges the test item of the DUT as a failure rather than a failure, and applies this to an actual mass production environment, the reliability of the test cannot be guaranteed, so improvement and supplementation are required. Below, an embodiment of the present invention will be described in detail with reference to the attached drawings.

[0022] FIG. 1 is a diagram showing the configuration of a parallel test system considering a mass production environment according to one embodiment of the present invention.

[0023] A parallel test system for a mass production environment according to an embodiment of the present invention includes an analog signal control module (110) and a digital signal control module (120).

[0024] An analog signal control module (110) according to an embodiment of the present invention checks the status of a Device Under Test (DUT) in an Automated Test Equipment (ATE) (130), excludes the failed test DUT, and masks the DUT to diagnose it.

[0025] An analog signal control module (110) according to an embodiment of the present invention checks the DUT status in the ATE (130), excludes the test failure DUT according to the result of the check, masks the test failure DUT with an 'X' bit, determines whether the masking has ended, and diagnoses the DUT if it has ended.

[0026] An analog signal control module (110) according to an embodiment of the present invention performs an XOR operation on the test data of the DUT and the expected output of the ATE (130) to check the DUT status in the ATE (130), and uses the result of the XOR operation as an input to the DAC to detect the location and number of test failure DUTs according to the voltage level of the voltage value converted through the DAC.

[0027] A digital signal control module (120) according to an embodiment of the present invention checks the status of the Device Under Test (DUT) from the ATE (130) and receives a Site Variable (SV) containing information on the failed DUT test, and uses the SV to control the input of the failure detection module by passing through the DUT control module.

[0028] A digital signal control module (120) according to an embodiment of the present invention includes a DUT controllable module (121) and a failure detection module (122).

[0029] A DUT controllable module (121) according to an embodiment of the present invention maintains internal data of a D-FF by fixing the clock by connecting pull-up and pull-down resistors to the clock of the D-FF, and fixes the input and enable signal of a MUX connected to the flip-flop output.

[0030] According to an embodiment of the present invention, the DUT corresponding to the test failure DUT is always masked with a logic 'HIGH' corresponding to a failure value when input to the DUT controllable module (121).

[0031] A failure detection module (122) according to an embodiment of the present invention outputs a signal in which the test result is compressed to the ATE (130).

[0033] FIG. 2 is a flowchart illustrating a parallel test method considering a mass production environment according to an embodiment of the present invention.

[0034] A parallel test method considering a mass production environment according to one embodiment of the present invention includes a DUT-off control step (210) through an analog signal, a test failure DUT detection step (220) through an analog signal, a DUT-off control step (230) through a digital signal, and a test failure DUT detection step (240) through a digital signal.

[0035] In the DUT-off control step (210) using an analog signal, the status of the DUT (Device Under Test) in the Automated Test Equipment (ATE) is checked through the analog signal control module, and the failed test DUT is excluded.

[0036] According to an embodiment of the present invention, the DUT status is checked in the ATE, and the test failed DUT is excluded based on the result of the check.

[0037] In the test failure DUT detection step (220) using an analog signal, the test failure DUT is masked to diagnose the DUT.

[0038] After masking the above-mentioned test failure DUT with an 'X' bit, determine whether the masking has ended, and if it has ended, diagnose the DUT.

[0039] According to an embodiment of the present invention, in order to check the DUT status in the ATE, the test data of the DUT and the expected output of the ATE are XORed, and the result of the XOR operation is used as the input to the DAC, and the location and number of test failure DUTs are detected according to the voltage level of the voltage value converted through the DAC.

[0040] In the DUT-off control step (230) using a digital signal, the DUT status is checked from the ATE through the digital signal control module and a Site Variable (SV) containing test failure DUT information is received.

[0041] According to an embodiment of the present invention, the DUT controllable module maintains the internal data of the D-FF by fixing the clock by connecting pull-up and pull-down resistors to the clock of the D-FF, and fixes the input and enable signal of the MUX connected to the flip-flop output, so that the input to the DUT controllable module for the DUT corresponding to the test failure DUT is always masked with a logic 'HIGH' corresponding to a failure value.

[0042] In the test failure DUT detection step (240) using a digital signal, the input of the failure detection module is controlled by passing through the DUT controllable module using the SV.

[0043] According to an embodiment of the present invention, a signal in which the test result is compressed is output to the ATE through a failure detection module.

[0045] FIG. 3 is a diagram illustrating an analog signal control module and an operation method according to an embodiment of the present invention.

[0046] FIG. 3(a) is a drawing showing an analog signal control module according to an embodiment of the present invention, and FIG. 3(b) is a flowchart for explaining the operation method of an analog signal control module according to an embodiment of the present invention.

[0047] The DUT-off control operation process of an analog signal control module according to an embodiment of the present invention is described.

[0048] The DUT-off control algorithm operates as software, and when the test starts, the ATE checks the DUT status (310), excludes the failed DUT (320), and operates in a sequence of masking the off-DUT with an 'X' bit (330). Afterwards, it determines whether the masking has ended (340), and if it has ended, diagnoses the DUT (350).

[0049] The DUT-off control algorithm is designed to operate in two ways: a foreground mode that runs on the ATE host PC and a background mode that runs on the DSP.

[0050] In the foreground, the off-DUT is masked and the P / F results of the test are analyzed whenever each test item is finished, and in the background, while the test is in progress, the previous test item is masked and the P / F is diagnosed.

[0051] FIG. 3(c) is a diagram showing each bit representation of a DUT according to one embodiment of the present invention.

[0052] The test failure detection process of the analog signal control module according to an embodiment of the present invention first performs an XOR operation between the DUT test data and the expected output of the ATE and uses the result as the input to the 16-bit DAC.

[0053] The voltage value converted through the DAC can detect the location and number of failures of the DUT based on the voltage level.

[0054] By utilizing a DAC with a speed of 500 Msps, which is faster than the 250 MHz test clock of a commercial ATE, two DACs are made to operate on a single test clock, and the output value is controlled through a MUX to maximize parallel test efficiency.

[0055] Considering that the lower 3 bits in the datasheet of the DAC used in the design are susceptible to errors, the design is made by fixing the inputs of those bits to GND.

[0057] FIG. 4 is a diagram illustrating a digital signal control module and an operation method according to an embodiment of the present invention.

[0058] The DUT-off control operation process and the test failure DUT detection process of a digital signal control module according to an embodiment of the present invention are described.

[0059] FIG. 4(a) shows a digital signal control module according to one embodiment of the present invention, and FIG. 4(b) shows a masking result of a digital signal control module according to one embodiment of the present invention.

[0060] In the case of DUT-off control operation, it first receives a SiteVariable (SV) containing DUT-off information from the ATE, passes through the DUT controllable module (410), and operates by controlling the input of the failure detection module (420).

[0061] At this time, the ATE transmits the SV value using a dual mode that transmits two data in one clock cycle.

[0062] The DUT controllable module (410) fixes the clock by connecting pull-up and pull-down resistors to the clock of the D-FF to maintain the internal data of the D-FF, and fixes the input and enable signal of the 2:1 MUX connected to the flip-flop output.

[0063] That is, the DUT corresponding to DUT-off is always masked with a logic 'HIGH' corresponding to a fail value as input to the DUT controllable module (410), and then passes through the failure detection module (420) and outputs a signal with compressed test results of DUT1 and 2 to the ATE.

[0065] FIG. 5 is a diagram showing the 16-bit DAC simulation results according to one embodiment of the present invention.

[0066] FIG. 5(a) shows the case of one failure per test cycle of a 16-bit DAC according to one embodiment of the present invention, and FIG. 5(b) shows the case of a random failure per test cycle of a 16-bit DAC according to one embodiment of the present invention.

[0067] A 16-bit DAC according to an embodiment of the present invention was designed and a simulation was performed to verify that the 16-bit DAC outputs different voltage values ​​depending on the number and location of failed DUTs and that the DUT failure detection operation is performed according to the voltage level.

[0068] For the case of one failure per test cycle, this is the waveform of the simulation result conducted under the assumption that only one failure occurred; for the case of random failure per test cycle, this is the waveform of the simulation result conducted by randomly setting the location and number of DUT failures.

[0069] The waveform (DAC output) is a voltage value converted through the DAC; it can be observed that the voltage value is output higher as the MSB increases, and it can be confirmed that the location and number of failures can be detected based on the voltage level.

[0070] In the case of random failure per test cycle, the location and number of failed DUTs are randomly set, and the resulting waveform confirms that the location and number of failed DUTs can be detected according to the voltage level.

[0072] FIG. 6 is a diagram showing the simulation results of a digital signal control module according to one embodiment of the present invention.

[0073] According to an embodiment of the present invention, in the first test clock cycle, the masking status for DUT1 and DUT2 is received through the SV value, and the DUT corresponding to the SV value low is always determined to be a test failure regardless of subsequent test results.

[0074] It can be confirmed that the pass / fail status is determined by performing an XOR operation between DUT1, 2 and the expected data output, and a voltage value corresponding to the location of the failed DUT is output to Tout. (i.e., All pass: mid-band (Fig. 6(a)), All fail: toggled value (Fig. 6(b)), DUT1 fail: High (Fig. 6(c)), DUT2 fail: Low (Fig. 6(d)))

[0076] The device described above may be implemented as a hardware component, a software component, and / or a combination of a hardware component and a software component. For example, the device and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and one or more software applications executed on said operating system. Additionally, the processing unit may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing unit may be described as being used as a single unit, but those skilled in the art will understand that the processing unit may include a plurality of processing elements and / or a plurality of types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are also possible.

[0077] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or instruct the processing unit independently or collectively. Software and / or data may be embodied in any type of machine, component, physical device, virtual equipment, computer storage medium, or device so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0078] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc., either alone or in combination. The program instructions recorded on the medium may be those specifically designed and configured for the embodiment, or they may be those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.

[0079] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results can be achieved even if the described techniques are performed in a different order than described, and / or the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

[0080] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.

Claims

Claim 1 A semiconductor parallel test system comprising: an analog signal control module that diagnoses DUTs by checking the status of DUTs (Device Under Test) in Automated Test Equipment (ATE), excluding failed DUTs, and masking them; a digital signal control module that checks the status of DUTs (Device Under Test) in ATE, receives a Site Variable (SV) containing information on failed DUTs, and controls the input of a failure detection module by passing through a DUT control module using the SV; wherein the digital signal control module fixes the clock to maintain internal data of the D-FF by connecting pull-up and pull-down resistors to the clock of the D-FF, and fixes the input of a MUX connected to the flip-flop output and the enable signal of the DUT control module - wherein the input to the DUT control module for the failed DUT is always masked to a logic 'HIGH' corresponding to a failure value; and a failure detection module that outputs a signal with compressed test results to ATE. Claim 2 A semiconductor parallel test system according to claim 1, wherein the analog signal control module checks the DUT status in the ATE, excludes the test failure DUT according to the check result, masks the test failure DUT with an 'X' bit, determines whether the masking has ended, and diagnoses the DUT if it has ended. Claim 3 In paragraph 2, the analog signal control module performs an XOR operation on the test data of the DUT and the expected output of the ATE to check the DUT status in the ATE, and uses the result of the XOR operation as the input to the DAC to detect the location and number of test failure DUTs according to the voltage level of the voltage value converted through the DAC in a semiconductor parallel test system. Claim 4 delete Claim 5 A step of diagnosing the DUT by checking the status of the DUT in the Automated Test Equipment (ATE) through an analog signal control module, excluding test-failed DUTs, and masking them; A semiconductor parallel test method comprising the step of checking the DUT status in the ATE through a digital signal control module to receive a Site Variable (SV) containing test failure DUT information, and using the SV to control the input of a failure detection module passing through a DUT controllable module, wherein the step of checking the DUT (Device Under Test) status in the ATE through the digital signal control module to receive a Site Variable (SV) containing test failure DUT information, and using the SV to control the input of a failure detection module passing through a DUT controllable module, wherein the DUT controllable module maintains internal data of the D-FF by fixing the clock by connecting pull-up and pull-down resistors to the clock of the D-FF, and fixes the input of a MUX connected to the flip-flop output and the enable signal, so that the input to the DUT controllable module corresponding to the test failure DUT is always masked with a logic 'HIGH' corresponding to a failure value, and subsequently passes through the failure detection module and outputs a signal with the test result compressed to the ATE. Claim 6 In claim 5, the step of diagnosing the DUT by checking the DUT status in the ATE through the analog signal control module, excluding the test-failed DUT, and masking it comprises: a step of checking the DUT status in the ATE; a step of excluding the test-failed DUT according to the result of the check; a step of masking the test-failed DUT with an 'X' bit; and a step of determining whether the masking has ended and, if it has ended, diagnosing the DUT. Claim 7 In claim 6, the step of checking the DUT status in the ATE is a semiconductor parallel test method that performs an XOR operation on the test data of the DUT and the expected output of the ATE, uses the result of the XOR operation as the input to a DAC, and detects the location and number of test failure DUTs according to the voltage level of the voltage value converted through the DAC. Claim 8 delete

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