METHODS AND APPARATUS FOR SIGNALING SYNTAX ELEMENTS IN VIDEO CODING

Abstract

Methods and apparatus for video encoding are provided. The method includes a decoder determining whether a disable flag is present in a picture header (PH) associated with a picture, where the disable flag specifies whether an encoding tool is disabled in one or more segments associated with the PH. Additionally, the method includes the decoder inferring the value of the disable flag based on one or more enable flags signaled in sequence parameter sets (SPS) of the picture in response to determining that the disable flag is not present in the PH, inferring via the decoder.

Description

METHODS AND APPARATUS FOR SIGNALING SYNTAX ELEMENTS IN VIDEO CODING FIELD OF INVENTION This disclosure relates to video encoding and compression, and in particular, but not limited to, methods and apparatus for signaling syntax elements in video encoding. BACKGROUND OF THE INVENTION Several video coding techniques can be used to compress video data. Video coding is performed according to one or more video coding standards. Examples of video coding standards include Versatile Video Coding (VVC), Joint Scan Test Model (JEM), High Efficiency Video Coding (H.265 / HEVC), Advanced Video Coding (H.264 / AVC), Moving Picture Expert Group (MPEG) coding, and similar standards. Video coding typically uses predictive methods (e.g., inter-prediction, intra-prediction, and similar methods) that take advantage of redundancy present in images or video sequences. A key objective of video coding techniques is to compress video data in a way that uses a lower bit rate while avoiding or minimizing degradation to video quality. BRIEF DESCRIPTION OF THE INVENTION This disclosure provides examples of techniques related to signaling syntax elements in video coding. Pursuant to the first aspect of this disclosure, a method for video encoding is provided. The method includes a decoder determining whether a disable flag is present in a picture header (PH) associated with a picture, where the disable flag specifies whether an encoding tool is disabled in one or more segments associated with the PH. Additionally, the method includes the decoder inferring the value of the disable flag based on one or more enable flags signaled in sequence parameter sets (SPS) of the picture in response to determining that the disable flag is not present in the PH. Pursuant to a second aspect of this disclosure, a method for video encoding is provided. The method includes a decoder determining whether a cue is present in a picture frame (PH) associated with an image, and the cue specifies whether the image used for time-motion vector prediction (TMVP) is derived from a reference image list from a plurality of reference image lists associated with the image. Additionally, the method includes the decoder inferring the cue's value from a number of reference images in the reference image list in response to determining that the cue is not present in the PH. Pursuant to a third aspect of this disclosure, a method for video encoding is provided. The method includes a decoder determining whether an indicator is present in RQQZ ίη / ZZΖΠZ / E / YΙΛΙ a PH associated with an image, the indicator specifies a number of weights signaled in a list of reference images according to a first weighted prediction (WP) indicator in image parameter sets (PPS) of the image and a second WP indicator in the PH of the image, and the indicator is in a WP syntax associated with the image. Additionally, the method includes that the decoder infers the value of the indicator according to a number of reference images in a list of reference images from among a plurality of reference image lists associated with the image in response to determining that the indicator is not present in the PH. Pursuant to a fourth aspect of this disclosure, a method for video encoding is provided. The method includes that a decoder uses an enabled flag to specify whether one or more temporal motion vector predictors are used for interprediction for one or more segments associated with a frame of reference (PH) of an image. Additionally, the method includes that the decoder constrains the value of the enabled flag according to a plurality of offsets applied to an image size for scaling ratio calculation. Pursuant to a fifth aspect of this disclosure, a video encoding apparatus is provided. The apparatus includes one or more processors and memory configured to store instructions executable by the processor(s). The processor(s), at the time of instruction execution, are configured to execute the video encoding method in accordance with the first aspect of this disclosure. Pursuant to a sixth aspect of this disclosure, a video encoding apparatus is provided. The apparatus includes one or more processors and memory configured to store instructions executable by the processor(s). The processor(s), at the time of instruction execution, are configured to execute the video encoding method according to the second aspect of this disclosure. Pursuant to a seventh aspect of this disclosure, a video encoding apparatus is provided. The apparatus includes one or more processors and memory configured to store instructions executable by the processor(s). The processor(s), at the time of instruction execution, are configured to execute the video encoding method in accordance with the third aspect of this disclosure. Pursuant to an eighth aspect of this disclosure, a video encoding apparatus is provided. The apparatus includes one or more processors and memory configured to store instructions executable by the processor or processors. The processor or processors, at the time of instruction execution, are configured to execute the video encoding method in accordance with the fourth aspect of this disclosure. Pursuant to a ninth aspect of this disclosure, a non-transient, computer-readable storage medium is provided for video encoding by storing computer-executable instructions. When executed by one or more computer processors, these instructions cause the computer processor(s) to execute the video encoding method in accordance with the first aspect of this disclosure. RQQZ ίη / ΖΖΠΖ / Ε / ΥΙΛΙ Pursuant to a tenth aspect of this disclosure, a non-transient, computer-readable storage medium is provided for video encoding by storing computer-executable instructions. When executed by one or more computer processors, these instructions cause the computer processor(s) to execute the video encoding method in accordance with the second aspect of this disclosure. Pursuant to an eleventh aspect of this disclosure, a non-transient, computer-readable storage medium is provided for video encoding by storing computer-executable instructions. When executed by one or more computer processors, these instructions cause the computer processor(s) to execute the video encoding method in accordance with the third aspect of this disclosure. Pursuant to a twelfth aspect of this disclosure, a non-transient, computer-readable storage medium is provided for video encoding by storing computer-executable instructions. When executed by one or more computer processors, these instructions cause the computer processor(s) to execute the video encoding method in accordance with the fourth aspect of this disclosure. BRIEF DESCRIPTION OF THE FIGURES A more specific description of the examples in this disclosure will be provided by reference to specific examples illustrated in the accompanying figures. Since these figures show only some examples and are therefore not considered a limitation of scope, the examples will be described and explained with additional specificity and detail through the use of the accompanying figures. Figure 1 is a block diagram illustrating an exemplary video encoder according to some implementations of this disclosure. Figure 2 is a block diagram illustrating an exemplary video decoder according to some implementations of the present disclosure. Figure 3 illustrates an example of an image split into multiple encoding tree units (CTUs) according to some implementations of this disclosure. Figures 4A to 4D are schematic diagrams illustrating multitype tree splitting modes according to some implementations of this disclosure. Figure 5 is a block diagram illustrating an exemplary apparatus for video encoding according to some implementations of the present disclosure. Figure 6 is a flowchart illustrating an exemplary video encoding process according to some implementations of this disclosure. Figure 7 is a flowchart illustrating an exemplary video encoding process according to some implementations of this disclosure. Figure 8 is a flowchart illustrating an exemplary video encoding process according to some implementations of this disclosure. Figure 9 is a flowchart illustrating an exemplary video encoding process according to some implementations of this disclosure. RQQZ ίη / ΖΖΠΖ / Ε / ΥΙΛΙ DETAILED DESCRIPTION OF THE INVENTION Specific implementations will now be discussed in detail, examples of which are illustrated in the accompanying figures. The following detailed description sets forth numerous non-limiting specifics to aid in understanding the subject matter presented here. However, it will be apparent to those skilled in the art that several alternatives may be used. For example, it will be apparent to someone skilled in the art that the subject matter presented here can be implemented in many types of electronic devices with digital video capabilities. References in this specification to “a modality,” “the modality,” “an example,” “some modalities,” “some examples,” or similar language mean that a particular characteristic, structure, or feature described is included in at least one modality or example. Characteristics, structures, elements, or features described in connection with one or some modalities are also applicable to other modalities, unless expressly specified otherwise. Through disclosure, the terms “first,” “second,” “third,” and so on are all used as nomenclature solely for references to relevant elements, such as devices, components, compositions, steps, and so forth, without implying any spatial or chronological order, unless expressly stated otherwise. For example, a “first device” and a “second device” may refer to two separately formed devices, or to two parts, components, or operating states of the same device, and may be named arbitrarily. The terms “module,” “sub-module,” “circuit,” “sub-circuit,” “sub-circuitry,” “unit,” or “subunit” may include memory (shared, dedicated, or pooled) that stores code or instructions that can be executed by one or more processors. A module may include one or more circuits with or without stored code or instructions. The module or circuit may include one or more components that are directly or indirectly connected. These components may or may not be physically connected or located adjacent to each other. As used herein, the terms “if” or “when” can be understood to mean “at the time of” or “in response to,” depending on the context. These terms, if they appear in a claim, may not imply that the relevant limitations or features are conditional or optional. For example, a method may comprise the steps of: i) when or if condition X is present, function or action X' is executed; ii) when or if condition Y is present, function or action Y' is executed. The method may be implemented with the capability to execute function or action X' and the capability to execute function or action Y'. Therefore, functions X' and Y' may be executed, at different times, in multiple executions of the method. A unit or module can be implemented purely in software, purely in hardware, or by a combination of hardware and software. In a purely software implementation, for example, the unit or module may include functionally related blocks of code or software components that are directly or indirectly linked in order to perform a particular function. Figure 1 shows a block diagram illustrating an exemplary block-based hybrid video encoder 100, which can be used in conjunction with many standards of RQQZ iη / ZZΖΠZ / E / YΙΛΙ video coding using block-based processing. In the 100 encoder, a video frame is partitioned into a plurality of video blocks for processing. For each given video block, a prediction is formed based on either an inter-prediction or an intra-prediction approach. In inter-prediction, one or more predictors are formed through motion estimation and motion compensation, based on pixels from previously reconstructed frames. In intra-prediction, predictors are formed based on pixels reconstructed in a current frame. Through mode decision, a better predictor can be chosen to predict a current block. A prediction residual, representing the difference between a current video block and its predictor, is sent to Transform circuitry 102. The transform coefficients are then sent from Transform circuitry 102 to Quantization circuitry 104 for entropic reduction. The quantized coefficients are then fed to Entropic Encoding circuitry 106 to generate a compressed video bitstream. As shown in Figure 1, prediction-related information 110 from inter-prediction and / or intra-prediction circuitry 112, such as video block partitioning information, motion vectors, reference frame index, and intra-prediction mode, is also fed through Entropic Encoding circuitry 106 and stored in a compressed video bitstream 114. In the encoder 100, circuitry related to the decoder is also necessary to reconstruct pixels for prediction purposes. First, a prediction residual is reconstructed using Inverse Quantization 116 and Inverse Transform circuitry 118. This reconstructed prediction residual is then combined with a Block Predictor 120 to generate unfiltered reconstructed pixels for a current video block. Intra-prediction (also referred to as "spatial prediction") uses pixels from samples of neighboring blocks already encoded (called reference samples) in the same image and / or video portion to predict the current video block. Spatial prediction reduces the spatial redundancy inherent in the video signal. Interprediction (also referred to as “temporal prediction”) uses reconstructed pixels from previously encoded video images to predict the current video block. Temporal prediction reduces the inherent temporal redundancy in the video signal. The temporal prediction signal for a given encoding unit (CU) or encoding block is typically signaled by one or more motion vectors (MVs), which indicate the amount and direction of motion between the current CU and its temporal reference. Additionally, if multiple reference images are supported, a reference image index is also sent, which is used to identify which reference image, in the reference image storage, the temporal prediction signal originates from. After the spatial and / or temporal prediction is executed, an intra / inter mode decision circuit 121 in the encoder 100 chooses the best prediction mode, for example based on the RQQZ ίΠ / ZZηZ / E / YILI rate-distortion optimization method. Block predictor 120 is then subtracted from the current video block; and the resulting prediction residual is decorrelated using transform circuitry 102 and quantization circuitry 104. The resulting quantized residual coefficients are inversely quantized by inverse quantization circuitry 116 and inversely transformed by inverse transform circuitry 118 to form the reconstructed residual, which is then added back to the prediction block to form the reconstructed CU signal. In addition, loop filtering 115, such as an unblocking filter, sample-adaptive compensation (SAO), and / or an adaptive loop filter (ALF), can be applied to the rebuilt CU before it is put into the image reference storage of the image buffer memory 117 and used to encode future video blocks.To form the output video bitstream 114, the encoding mode (inter or intra), prediction mode information, motion information, and quantized residual coefficients are all sent to the entropic encoding unit 106 to be further compressed and packed to form the bitstream. For example, an unblocking filter is available in AVC, HEVC, and the current version of VVC. In HEVC, an additional loop filter called SAO (Adaptive Sample Compensation) is defined to further improve encoding efficiency. In the current version of the VVC standard, another loop filter called ALF (Adaptive Loop Filter) is being actively researched and has a good chance of being included in the final standard. These loop-filter operations are optional. Running these operations helps improve coding efficiency and visual quality. They can also be turned off by the coder to save computational complexity. It should be noted that intra-prediction is generally based on unfiltered reconstructed pixels, while inter-prediction is based on filtered reconstructed pixels if these filter options are turned on by the encoder 100. Figure 2 is a block diagram illustrating an exemplary block-based video decoder 200, which can be used in conjunction with many video coding standards. This decoder 200 is similar to the reconstruction-related section in the encoder 100 of Figure 1. In the decoder 200, an incoming video bit stream 201 is first decoded via an Entropic Decode 202 to derive quantized coefficient levels and prediction-related information. The quantized coefficient levels are then processed via an Inverse Quantization 204 and an Inverse Transform 206 to obtain a reconstructed prediction residual. A block predictor mechanism, implemented in an Intra / Inter Mode Selector 212, is configured to execute either an Intra prediction 208 or a Motion Compensation 210, based on the decoded prediction information.A set of unfiltered reconstructed pixels is obtained by summing the reconstructed prediction residual from the Inverse Transform 206 and a predictive output generated by the block predictor mechanism, using a summing machine 214. The rebuilt block can also pass through a 209 Loop Filter before it is RQQZ ίη / ZZΖΠZ / E / YΙΛΙ is stored in an image buffer memory 213, which functions as a reference image storage. The reconstructed video in the image buffer memory 213 can be sent to trigger a display device, and can also be used to predict future video blocks. In situations where the Loop Filter 209 is turned on, a filtering operation is performed on these reconstructed pixels to derive a final reconstructed Video Output 222. The aforementioned video encoding / decoding standards, such as VVC, JEM, HEVC, and MPEG-4 Part 10, are conceptually similar. For example, they all utilize block-based processing. The block partitioning schemes for some of these standards are detailed below. Versatile Video Coding (VVC) At the 10th JVET meeting, held from April 10-20, 2018, in San Diego, USA, JVET defined the first proposal for Versatile Video Coding (VVC) and the VVC Test Model 1 (VTM1) as its reference software implementation. It was decided to include a quaternary tree with a nested multi-type tree as the initial new encoding feature of VVC. The multi-type tree is a block-splitting structure for encoding, including binary and ternary splitting. Since then, the VTM reference software, with its implemented encoding and decoding process, has been developed and updated through subsequent JVET meetings. In VVC, an input video image is divided into blocks called CTUs. A CTU is further divided into CUs using a quaternary tree with a nested multi-type tree structure, with a CU defining a region of pixels that share the same prediction mode (e.g., intra or inter). The term 'unit' can define a region of an image encompassing all components, such as luma and chroma. The term 'block' can be used to define a region encompassing a particular component (e.g., luma), and blocks of different components (e.g., luma versus chroma) can differ in spatial location when considering the chroma sampling format, such as 4:2:0. Partitioning the image into CTUs Figure 3 illustrates an example of an image 300 divided into multiple CTUs 302 according to some implementations of this disclosure. The images are divided into a sequence of CTUs. The concept of a CTU is the same as that of HEVC. For an image that has three sample arrays, a CTU consists of an NxN block of luma samples along with two corresponding blocks of chroma samples. The maximum allowed size of the luma block in a CTU is specified to be 128x128 (although the maximum size of luma transform blocks is 64x64). Partitioning the CTUs using a tree structure In HEVC, a CTU is divided into CUs using a quaternary tree structure denoted as the coding tree to accommodate various local features. The decision as to whether to encode an image area using inter-image (temporal) or intra-image (spatial) prediction is made at the leaf CU level. Each leaf CU can be further divided into one, two, or four PUs. RQQ7 ίη / ZZΖΠZ / E / YΙΛΙ according to the PU division type. Within a PU, the same prediction process is applied and the relevant information is transmitted to the decoder on a PU basis. After obtaining the residual block by applying the prediction process based on the PU division type, a leaf CU can be partitioned into transform units (TUs) according to another quaternary tree structure similar to the encoding tree for the CU. One of the key features of the HEVC structure is that it has multiple partitioning concepts including CU, PU, ​​and TU. In VVC, a nested multi-type quaternary tree using a binary-ternary splitting structure replaces the concepts of multiple partition unit types; that is, it eliminates the separation of CU, PU, ​​and TU concepts except as needed for CUs that are too large for the maximum transform length, and it supports more flexibility for CU partition shapes. In the encoding tree structure, a CU can be either square or rectangular. A CTU is first partitioned by a quaternary tree structure. Then, the leaf nodes of the quaternary tree can be further partitioned by a multi-type tree structure. Figures 4A through 4D are schematic diagrams illustrating multitype tree splitting modes according to some implementations of this disclosure. As shown in Figures 4A through 4D, there are four split types in multitype tree structure: vertical binary split 402 (SPLIT_BT_VER), horizontal binary split 404 (SPLIT_BT_HOR), vertical ternary split 406 (SPLIT_TT_VER), and horizontal ternary split 408 (SPLIT_TT_HOR). Leaf nodes in multitype trees are called CUs, and unless the CU is too large for the maximum transform length, this segmentation is used for prediction and transform processing without any further partitioning. This means that, in most cases, the CU, PU, ​​and TU have the same block size in the quaternary tree with the nested multitype tree encoding block structure.The exception occurs when the maximum supported transform length is smaller than the width or height of the color component of the CU. Syntax in VVC In VVC, the first syntax signaling bitstream layer is the Network Abstraction Layer (NAL), where the bitstream is divided into a set of NAL units. Some NAL units signal control parameters common to the decoder, such as the Sequence Parameter Set (SPS) and the Picture Parameter Set (PPS). Others contain video data. The Video Encoding Layer (VCL) NAL units contain encoded video segments. An encoded image is called an access unit and can be encoded as one or more segments. A video-encoded sequence begins with an Instant Decoder Refresh (IDR) image. All subsequent video images are encoded as segments. A new IDR image signals that the previous video segment has ended, and a new one begins. Each NAL unit starts with a one-byte header followed by the Raw Byte Sequence Payload (RBSP). The RBSP contains encoded segments. The segments are binary-encoded so they can be padded with zero bits to ensure the length is an integer. RQQZ ίΠ / ZZηZ / E / YILI of bytes. A segment consists of a segment header and segment data. Segment data is specified as a series of CUs. The concept of the Picture Header (PH) was adopted at the 16th JVET meeting to be transmitted once per image as the first NAL VCL unit of an image. It was also proposed to group some syntax elements previously in the segment header into this Picture Header. Syntax elements that functionally only need to be transmitted once per image could be moved to the Picture Header instead of being transmitted multiple times in segments for a given image. In the VVC specification, syntax tables specify a superset of the syntax for all allowed bitstreams. Additional restrictions on syntax can be specified, directly or indirectly, in other clauses. Table 1 below is a syntax table for the segment header and image header in VVC. The semantics of certain syntax are also illustrated in relation to the syntax table. TABLE 1 RQQ7 ίη / ΖΖΠΖ / Ε / ΥΙΛΙ slice_header() { Descriptor picture_header_in_slice_header_flag u(1) if( picture_headerjn_slice_header_flag) picture_header_structure() if( subpic_info_present_flag) slice_subpic_id u(v) if( ( rect_slice_flag && NumSliceslnSubpic[ CurrSubpicIdx ] > 1 ) | | ( !rect_slice_flag && NumTilesinPic > 1 )) slice_address u(v) for( i = 0; i < NumExtraShBits; i++ ) sh_extra_bit[ i ] u(1) if( !rect_slice_flag && NumTilesinPic > 1 ) num_tiles_in_slice_minus1 ue(v) if( ph_inter_slice_allowed_flag) slice_type ue(v) if( sps_alf_enabled_flag && !alf_info_in_ph_flag ) { slice_alf_enabled_flag u(1) if( slice_alf_enabled_flag ) { slice_num_alf_aps_ids_luma u(3) for( i = 0; i < slice_num_alf_aps_ids_luma; i++ ) slice_alf_aps_id_luma[ i ] u(3) if( ChromaArrayType != 0 ) slice_alf_chroma_idc u(2) if( slice_alf_chroma_idc) slice_alf_aps_id_chroma u(3) if( sps_ccalf_enabled_flag) { slice_cc_alf_cb_enabled_flag u(1) if( slice_cc_alf_cb_enabled_flag) slice_cc_alf_cb_aps_id u(3) slice_cc_alf_cr_enabled_flag u(1) if( slíce_cc_alf_cr_enabled_flag) slice_cc_alf_cr_aps_id u(3)}}} if( separate_colour_plane_flag = = 1 ) colour_plane_id u(2) if( !rpl_infojn_ph_flag && (( nal_unit_type != IDR_W_RADL && nal_unit_type != IDR_N_LP ) | | sps_idr_rpl_present_flag ) ) ref_pic_lists() if( (rpl_info_in_ph_flag ( ( nal_unit_type != IDR W RADL && nal_unit_type != IDR_N_LP ) | | sps_idr_rpl_present_flag )) && (( slice_type != I && num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] > 1 ) ( slice_type - - B && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 1 ) ) ) { num_ref_idx_active_overr¡de_flag u(1) if( num_ref_idx_act¡ve_ovemde_flag ) RQQ7 in / ZZPZ / E / YILI for( i = 0; i < ( slice_type = = B ? 2: 1 ); Í++ ) if( num_ref_entries[ i ][ Rplsldx[ i ] ] > 1 ) num_ref_idx_active_minus1[ i ] ue(v)} if( slice_type != I) { if( cabac init present flag ) cabac_init_flag u(1) if( ph_temporal_mvp_enabled_flag && !rpl_info_in_ph_flag ) { if( slice_type = = B ) slice_collocated_from_IO_flag u(1) if( ( slice_collocated_from_IO_flag && NumRefldxActive[ 0 ] > 1 ) ( ! slice_collocated_from_IO_flag && NumRefldxActive[ 1 ] > 1 ) ) slice_collocated_ref_idx ue(v)} if( !wp_info_in_ph_flag && (( pps_weighted_pred_flag && slicejype = = p) II ( pps_weighted_bipred_flag && slice_type = = B ))) pred_weight_table()} if( !qp_delta_info_in_ph_flag) sliceqpdelta se(v) if( pps_slice_chroma_qp_offsets_present_flag ) { slice_cb_qp_offset se(v) slice_cr_qp_offset se(v) if( spsjoint_cbcr_enabled_flag ) slicejoint_cbcr_qp_offset se(v)} if( pps_cu_chroma_qp_offset_list_enabled_flag ) cu_chroma_qp_offset_enabled_flag u(1) if( sps_sao_enabled_flag && !saojnfo_in_ph_flag ) { RQQ7 in / ZZPZ / E / YILI slice_sao_luma_flag u(1) if( ChromaArrayType != 0 ) slice_sao_chroma_flag u(1)} if( deblocking_filter_overr¡de_enabled_flag && !dbf_info_in_ph_flag ) slice_deblocking_filter_override_flag u(1) if( slice_deblock¡ng_f¡lter_override_flag ) { slice_deblocking_filter_disabled_flag u(1) if( !slice_deblock¡ng_filter_d¡sabled_flag ) { s I i ce_beta_of f s et_d i v2 se(v) s 1 i ce_tc_of f set_d i v2 se(v) si i ce_cb_beta_of f set_d i v2 se(v) si i ce_cb_tc_off set_d i v2 se(v) slice_cr_beta_offset_div2 se(v) s 1 i ce_c r_t c_of f set_d i v2 se(v)}} slice_ts_residual_coding_d¡sabled_flag u(1) if( ph_lmcs_enabled_flag) slice_lmcs_enabled_flag u(1) if( ph_explicit_scaling_l¡st_enabled_flag ) slice_expl¡c¡t_scalingj¡st_used_flag u(1) if( NumEntryPoints > 0 ) { offset_len_minus1 ue(v) for( i = 0; i < NumEntryPoints; i++ ) entry_point_offset_minus1[ i ] u(v)} if( slice_header_extension_present_flag ) { slice_header_extension_length ue(v) for( i = 0; i < slice_header_extension_length; i++) RQQ7 ίη / ΖΖΠΖ / Ε / ΥΙΛΙ slice_header_extension_data_byte[ i ] u(8)} byte_alignment()} picture_header_structure() { Descriptor gdrorjrappicflag u(1) if( gdr_or_irap_pic_flag ) gdr_pic_flag u(1) ph_inter_slice_allowed_flag u(1) if( ph_inter_slice_allowed_flag ) ph_intra_slice_allowed_flag u(1) non_reference_picture_flag u(1) ph_pic_parameter_setjd ue(v) ph_pic_order_cnt_lsb u(v) if( gdr_or_irap_pic_flag ) no_output_of_prior_pics_flag u(1) if( gdr_pic_flag ) recovery_poc_cnt ue(v) for( i = 0; i < NumExtraPhBits; i++ ) ph_extra_bit[ i ] u(1) if( sps_poc_msb_flag ) { ph_poc_msb_present_flag u(1) if( ph_poc_msb_present_flag) poc_msb_val u(v)} if( sps_alf_enabled_flag && alf_info_in_ph_flag ) { ph_alf_enabled_flag u(1) if( ph_alf_enabled_flag) { ph _num_alf_apsjds_luma u(3) for( i = 0; i < ph_num_alf_aps_ids_luma; i++ ) RQQ7 ίη / ΖΖΠΖ / Ε / ΥΙΛΙ ph_alf_aps_id_luma[ i ] u(3) if( ChromaArrayType != 0 ) ph_alf_chroma_idc u(2) if( ph_alf_chroma_idc > 0 ) ph_alf_aps_id_chroma u(3) if( sps_ccalf_enabled_flag ) { ph_cc_alf_cb_enabled_flag u(1) if( ph_cc_alf_cb_enabled_flag ) ph_cc_alf_cb_aps_id u(3) ph_cc_alf_cr_enabled_flag u(1) if( ph_cc_alf_cr_enabled_flag ) ph_cc_alf_cr_aps_id u(3)}}} if( sps_lmcs_enabled_flag ) { ph_lmcs_enabled_flag u(1) if( ph_lmcs_enabled_flag) { ph_lmcs_aps_id u(2) if( ChromaArrayType != 0 ) ph_chroma_residual_scale_flag u(1)}} if( sps_explic¡t_scal¡ng_list_enabled_flag) { ph explicit scaling list enabled flag u(1) if( ph_explic¡t_scal¡ng_list_enabled_flag ) ph_scaling_l¡st_aps_id u(3)} if( sps_virtual_boundaries_enabled_flag && !sps_virtuaLboundar¡es_present_flag) { RQQ7 ίη / ΖΖΠΖ / Ε / ΥΙΛΙ ph_virtual_boundaries_present_flag u(1) if( ph_virtual_boundaries_present_flag ) { ph_num_ver_virtual_boundaries u(2) for( i = 0; i < ph_num_ver_virtual_boundaries; i++ ) ph_virtual_boundaries_pos_x[ i ] u(13) ph_num_hor_virtual_boundaries u(2) for( i = 0; i < ph_num_hor_virtual_boundaries;i++ ) ph_virtual_boundaries_pos_y[ i ] u(13)}} if ( output_flag_present_flag ) pic_output_flag u(1) if( rpl_info_in_ph_flag ) ref_pic_lists() if( partition_constra¡nts_overr¡de_enabled_flag ) partition_constraints_override_flag u(1) if( ph_intra_slice_allowed_flag ) { if( partition_constra¡nts_overr¡de_flag ) { ph_log2_d iff_m i n_qt_m in_cb_¡ ntra_sl ice_l u ma ue(v) ph_max_mtt_hierarchy_depth_intra_sl¡cejuma ue(v) if( ph_max_mtt_hierarchy_depth_¡ntra_sl¡ce_luma != 0 ) { ph_log2_diff_max_bt_min_qt_¡ntra_sl¡cejuma ue(v) ph_log2_d¡ff_max_tt_m¡n_qtjntra_slice_luma ue(v)} if( qtbtt_dual_treejntra_flag) { ph_log2_diff_m¡n_qt_min_cb_¡ntra_sl¡ce_chroma ue(v) ph_max_mtt_hierarchy_depth_intra_sl¡ce_chroma ue(v) if( ph_max_mtt_h¡erarchy_depthjntra_slice_chroma != 0 ) { ph_log2_d¡ff_max_bt_min_qtjntra_sl¡ce_chroma ue(v) ph_log2_diff_max_tt_min_qt_intra_slice_chroma ue(v); RQQ7 ίη / ΖΖΠΖ / Ε / ΥΙΛΙ }}} if(cu_qp_delta_enabled_flag) ph_cu_qp_delta_subdivjntra_slice ue(v) if( pps_cu_chroma_qp_offset_list_enabled_flag ) ph_cu_chroma_qp_offset_subdivjntra_slice ue(v)} if( ph_inter_slice_allowed_flag) { if( partition_constra¡nts_overr¡de_flag) { ph_log2_diff_m¡n_qt_min_cb_inter_sl¡ce ue(v) ph_max_mtt_hierarchy_depth_inter_sl¡ce ue(v) if( ph_max_mtt_hierarchy_depthjnter_sl¡ce != 0 ) { ph_log2_diff_max_bt_min_qt_¡nter_sl¡ce ue(v) p h J o g 2_d i ff_m ax_tt_m i n_qt_i nte r_s I i c e ue(v)}} if( cu_qp_delta_enabled_flag) ph_cu_qp_delta_subdivjnter_slice ue(v) if( pps_cu_chroma_qp_offset_list_enabled_flag ) ph_cu_chroma_qp_offset_subdiv_¡nter_sl¡ce ue(v) if( sps_temporal_mvp_enabled_flag) { ph_temporal_mvp_enabled_flag u(1) if( ph_temporal_mvp_enabled_flag && rpl_info_in_ph_flag ) { ph collocated-fromJOJIag u(1) if( ( ph_collocated_from_IO_flag && num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] > 1 ) | | ( !ph_collocated_from_IO_flag && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 1 ))ph_collocated_ref_idx ue(v) RQQ7 ίη / ΖΖΠΖ / Ε / ΥΙΛΙ }} mvdJ1_zero_flag u(1) if( sps_fpel_mmvd_enabled_flag) ph_fpel_mmvd_enabled_flag u(1) if( sps_bdof_pic_present_flag ) ph_disable_bdof_flag u(1) if( sps_dmvr_pic_present_flag) ph_disable_dmvr_flag u(1) if( sps_prof_pic_present_flag) ph_disable_prof_flag u(1) if( ( pps_weighted_pred_flag | | pps_weighted_bipred_flag ) && wp_info_in_ph_flag ) pred_weight_table()} if( qp_delta_info_in_ph_flag ) ph_qp_delta se(v) if( spsjoint_cbcr_enabled_flag) phjoint_cbcr_sign_flag u(1) if( sps_sao_enabled_flag && sao_info_in_ph_flag ) { ph_sao_luma_enabled_flag u(1) if( ChromaArrayType != 0 ) ph_sao_chroma_enabled_flag u(1)} if( sps_dep_quant_enabled_flag ) ph_dep_quant_enabled_flag u(1) if( sps_sign_data_hiding_enabled_flag && !ph_dep_quant_enabled_flag ) pic_sign_data_h¡d¡ng_enabled_flag u(1) if( deblocking_filter_override_enabled_flag && dbf_info_in_ph_flag ) { ph deblocking filter override_flag u(1) RQQ7 ίη / ΖΖΠΖ / Ε / ΥΙΛΙ if( ph_deblocking_f¡lter_overr¡de_flag ) { ph_deblocking_f¡lter_d¡sabled_flag u(1) if( !ph_deblocking_filter_d¡sabled_flag ) { ph_beta_offset_div2 se(v) ph_tc_offset_div2 se(v) ph_cb_beta_offset_div2 se(v) ph_cb_tc_offset_d iv2 se(v) ph_cr_beta_offset_div2 se(v) ph_cr_tc_offset_div2 se(v)}}} if( picture_header_extension_present_flag ) { ph_extension_length ue(v) for( i = 0; i < ph_extension_length; i++) ph_extension_data_byte[ i ] u(8)}} RQQZ ίη / ΖΖΠΖ / Ε / ΥΙΛΙ The semantics of selected syntax elements: `ph_temporal_mvp_enabled_flag` specifies whether temporal motion vector predictors can be used for interprediction for segments associated with the PH. If `ph_temporal_mvp_enabled_flag` is equal to 0, the syntax elements of the segments associated with the PH should be restricted so that no temporal motion vector predictors are used in decoding the segments. Otherwise, if `ph_temporal_mvp_enabled_flag` is equal to 1, temporal motion vector predictors can be used in decoding the segments associated with the PH. When it is not present, the value of ph_temporal_mvp_enabled_flag is inferred to be equal to 0. When no reference image in the Decoded Image Buffer (DPB) Memory has the same spatial resolution as the current image, the value of ph_temporal_mvp_enabled_flag should be equal to 0. The maximum number of subblock-based merge MVP candidates, MaxNumSubblockMergeCand, is derived as follows: if (sps_affine_enabled_flag) MaxNumSubblockMergeCand = 5 - five_minus_max_num_subblock_merge_cand otherwise MaxNumSubblockMergeCand=sps_sbtmvp_enabled_flag && ph_temporal_mvp_enabled_flag; where the value of MaxNumSubblockMergeCand should be in the range of 0 to 5, inclusive. slice_collocated_from_IO_flag equal to 1 specifies that the placed image used for temporal motion vector prediction is derived from reference image list 0. slice_collocated_from_IO_flag equal to 0 specifies that the placed image used for temporal motion vector prediction is derived from reference image list 1. When slicejype equals B or P, ph_temporal_mvp_enabled_flag equals 1, and slice_collocated_from_IO_flag is not present, the following applies: - If rpl_info_in_ph_flag is equal to 1, sl¡ce_collocated_from_IO_flag is inferred to be equal to ph_collocated_from_IO_flag. - Otherwise (rpljnfo_in_ph_flag is equal to 0 and slice_type is equal to P), the value of slice_collocated_from_IO_flag is inferred to be equal to 1. slice_collocated_ref_idx specifies the reference index of the placed image used for temporal motion vector prediction. When slice_type equals P or when slice_type equals B and slice_collocated_from lOJIag equals 1, slice_collocated_ref_idx refers to an entry in the reference image list 0, and the value of slice_collocated_ref_idx should be in the range of 0 to NumRefldxActive[ 0 ] - 1, inclusive. When slice_type is equal to B and slice_collocated_from_IO_flag is equal to 0, slice_collocated_ref_dx refers to an entry in the reference image list 1, and the value of slice_collocated_ref_dx should be in the range of 0 to NumRefldxActive[ 1 ] - 1, inclusive. When slice_collocated_ref_idx is not present, the following applies: - If rpl_info_in_ph_flag is equal to 1, the value of slice_collocated_refjdx is inferred to be equal to ph_collocated_ref_idx. - Otherwise (rpl_info_in_ph_flag is equal to 0), the value of slice_collocated_ref_idx is inferred to be equal to 0. It is a requirement of bitstream compliance that the image referenced by slice_collocated_ref_dx should be the same for all segments of an encoded image. It is a bitstream compliance requirement that the values ​​of p¡c_w¡dth_in_luma_samples and pic_height_¡n_luma_samples of the reference image referenced by slice_collocated_ref_¡dx should be equal to the values ​​of p¡c_w¡dth_in_luma_samples and pic_height_in_luma_samples, respectively, of the current image, and RprConstraintsActive[slice_collocated_from_IO_flag ? 0:1 ][slice_collocated_ref_idx] should be equal to 0. The values ​​of RprConstraintsActive[i][j] are derived in section 8.3.2 of the VVC specification. The derivation of the values ​​of RprConstraintsActive[i][j] is described below. Decoding Process for Building Reference Image Lists The decoding process for building reference image lists is consulted at the beginning of the decoding process for each segment of a non-IDR image. Reference images are addressed through reference indexes. An index of RQQ7 ίη / ZZΖΠZ / E / YΙΛΙ reference is an index within a reference image list. When decoding an I-segment, no reference image list is used in decoding the segment data. When decoding a P-segment, only reference image list 0 (i.e., RefPicList[0]) is used in decoding the segment data. When decoding a B-segment, both reference image list 0 and reference image list 1 (i.e., RefPicList[1]) are used in decoding the segment data. At the beginning of the decoding process for each segment of a non-IDR image, the reference image lists RefPicList[0] and RefPicList[1] are derived. These reference image lists are used in marking reference images as specified in video coding standards or in decoding segment data. For a segment I of a non-IDR image that is not the first segment of the image, RefPicList[0] and RefPicList[1] can be derived for the purpose of checking bitstream conformity, but their derivation is not necessary to decode the current image or images that follow the current image in the decoding order. For a segment P that is not the first segment of an image, RefPicList[1] can be derived for the purpose of checking bitstream conformity, but its derivation is not necessary to decode the current image or images that follow the current image in the decoding order. The reference image lists RefPicList[0] and RefPicList[1], the reference image scaling relations RefPicScale[i][j][0] and RefPicScale[i][j][1], and the reference image scaling indicators RprConstraintsActive[0][j] and RprConstraintsActive[1][] are derived as follows: for( i = 0; i < 2; i++ ) { for( j = 0, k = 0, pocBase = PicOrderCntVal; j < num_ref_entries[ i ][ Rplsldx[ i ] ]; j++) { if( !¡nterjayer_ref_picjlag[ i ][ Rplsldx[ i ] ][j ]) { s¡( st_ref_pic_flag[ i ][ Rplsldx[ i ] ][ j ]) { RefPicPocList[ i ][ j ] = pocBase - DeltaPocValSt[ i ][ Rplsldx[ i ] ][ j ] if there is a reference image picA in the DPB with the same nuhjayerjd as the current image and PicOrderCntVal equal to RefPicPocList[ i ][ j ]) RefPicList[ i ][ j ] = picA else RefPicList[ i ][j ] = no reference picture pocBase = RefPicPocList[ i ][j ]} de lo contarlo { si¡( !delta_poc_msb_cycle_lt[ i ][ k ]) { si( hay una picA de referencia en la DPB con mismo nuhjayerjd que la imagen actual y PicOrderCntVal & ( MaxPicOrderCntLsb - 1 ) igual a PocLsbL$(i)i[ k ]) RefPicList[ i ][ j ] = picA de lo contarlo RQQZ ίη / ΖΖΠΖ / Ε / ΥΙΛΙ RefPicList[ i ][ j ] = no reference picture RefPicLtPocList[ i ][ j ] = PocLsbLt[ i ][ k ]} otherwise { if there is a reference picA in the DPB with the same nuhjayerjd as the current image and PicOrderCntVal equal to FullPocLt[ i ][ k ]) RefPicList[ i ][ j ] = picA otherwise RefPicList[ i ][ j ] = no reference picture RefPicLtPocList[ i ][ j ] = FullPocLt[ i ][ k ]} k++}} otherwise { layerldx = DirectRefLayerldx[ GeneralLayerldx[ nuhjayerjd ] ][ ilrpjdx[ i ][ Rplsldx ][ j ] ] refPicLayerld = vpsjayerid[ layerldx ] if ( there is a reference picture picA in the DPB with nuhjayerjd equal to refPicLayerld and the same PicOrderCntVal as the current picture) RefPicList[ i ][ j ] = picA else RefPicList[ i ][ j ] = no reference picture} fRefWidth is set equal to the PicOutputWidthL of the reference image RefPicList[ i ][ j ] fRefHeight is set equal to the PicOutputHeightL of the reference image RefPicList[ i ][ j ] refScalingWinRightOffset, refScalingWinTopOffset, and refScalingWinBottomOffset, are set equal to the values ​​of pic_widthjnjuma_samples, pic_heightjnjuma_samples, scaling_winjeft_offset, scaling_win_off_offset, scaling_win_offset, yjop_winset scaling_win_bottom_offset, respectively, of the reference image RefPicList[ i ][ j ] RefPicScale[ i ][ j ][ 0 ]=( (fRefWidth « 14) + ( PicOutputWidthL » 1 )) / PicOutputWidthL RefPicScale[ i ][ j ][ 1 ]=( (fRefHeight « 14) + ( PicOutputHeightL » 1 )) / PicOutputHeight L RprConstraintsActive[ i ][ j ] = ( pic_widthjnjuma_samples != refPicWidth | | RQQZ ίη / ΖΖΠΖ / Ε / ΥΙΛΙ p¡c_he¡ght_¡n_luma_samples != refPicHeight | | scaling_win_left_offset != refScalingWinLeftOffset | | scaling_win_right_offset != refScalingWinRightOffset | | scaling_win_top_offset != refScalingWinTopOffset | | scaling_win_bottom_offset != refScalingWinBottomOffset)} scaling win left_offset, caling_win_right_offset, scaling_win_top_offset, y scaling_win_bottom_offset especifican las compensaciones que son aplicadas al tamaño de imagen para cálculo de relación de escalación. Cuando no están presentes, los valores de scaling_w¡n_left_offset, scaling_win_r¡ght_offset, scaling_win_top_offset, y scaling_win_bottom_offset son inferidos para ser ¡guales a pps_conf_w¡n_left_offset, pps_conf_win_right_offset, pps_conf_win_top_offset, y pps_conf_win_bottom_offset, respectivamente. The value of SubWidthC * ( scaling_win_left_offset + scaling_win_right_offset) should be less than pic_w¡dth_in_luma_samples, and the value of SubHeightC * ( scaling win top_offset + scaling win bottom offset) should be less than pic_height_in_luma_samples. The variables PicOutputWidthL and PicOutputHeightL are derived as follows: PicOutputWidthL = pic_widthjn luma_samples SubWidthC * ( scaling_win_right_offset + scaling_winjeft_offset) PicOutputHeightL = picheightjnjumasamples - (78) SubWidthC * ( scaling_win_bottom_offset + scaling_win_top_offset). Assume that refPicOutputWidthL and refPicOutputHeightL are PicOutputWidthL and PicOutputHeightL, respectively, of a reference image of a current image referring to this PPS. It is a requirement of bitstream compliance that all of the following conditions are met: PicOutputWidthL * 2 should be greater than or equal to refPicWidthlnLumaSamples. - PicOutputHeightL * 2 should be greater than or equal to refPicHeightlnLumaSamples. - PicOutputWidthL should be less than or equal to refPicWidthlnLumaSamples * 8. - PicOutputHeightL should be less than or equal to refPicHeightlnLumaSamples * 8. - PicOutputWidthL * pic_width_maxjnjuma_samples should be greater than or equal to refPicOutputWidthL * (pic_widthjn luma_samples - Max( 8, MinCbSizeY )). - PicOutputHeightL *pic_height_max_injuma_samples should be greater than or equal to refPicOutputHeightL * (foot height inJuma samples - Max( 8, MinCbSizeY )). In current VVC, mvdJ1_zero_flag is signaled in the PH without any conditional restrictions. However, the feature controlled by the mvdJ1_zero_flag flag is only applicable when the segment is a predictive B-segment (B-segment). Therefore, flag signaling is redundant when the segment associated with the image header is not a B-segment. In another example, ph_disable_bdof_fl3g and ph_disable_dmvr_flag are signaled in the PH RQQ7 ίη / ZZΖΠZ / E / YΙΛΙ only when the corresponding enable flags (sps_bdof_pic_present_flag, sps_dmvr_pic_present_flag) signaled in the sequence parameter set (SPS) are true, respectively. As shown in Table 2 below, however, the features controlled by the ph_disable_bdof_flag and ph_disable_dmvr_flag flags are only applicable when the segment is a bi-predictive segment (B-segment). Therefore, signaling these two flags is redundant or useless when the segment associated with the image header is not a B-segment. Table 2 if( sps_bdof_pic_present_flag) ph_disable_bdof_flag if( sps_dmvr pic_present_flag) ph_disable_dmvr_flag RQQZ Ln / Zznz / E / YIAI Another example can be seen in the syntax elements ph_collocated_from_IO_flag, which indicates that the placed image is from ready or Iist1. And another example can be seen in the syntax pred_weight_table(), which are the syntax elements related to the weighting table for bi-predictive, as shown below. if( ph_temporal_mvp_enabled_flag && rpl_info_in_ph_flag ) { ph_collocated_from_IO_flag if( ( pps_weighted_pred_flag | | pps_weighted_bipred_flag ) && wp_info_in_ph_flag ) pred_weight_table() pred_weight_table() { Descriptor Iuma_log2_weight_denom ue(v) if( ChromaArrayType != 0 ) delta_chroma_log2_weight_denom se(v) if( wp_info_in_ph_flag ) num_IO_weights ue(v) for( i = 0; i < NumWeightsLO; Í++ ) luma_weight_IO_flag[ i ] u(1) if( ChromaArrayType != 0 ) for( i = 0; i < NumWeightsLO; Í++ ) chroma_weight_IO_flag[ i ] u(1) for( i = 0; NumWeightsLO; Í++ ) { if( luma_weight_IO_flag[ i ]) { delta_luma_weight_IO[ i ] se(v) luma_offset_IO[ i ] se(v)} if( chroma_weight_IO_flag[ i ]) for( j = 0; j < 2; j++) { delta_chroma_weight_IO[ i ][ j ] se(v) delta_chroma_offset_IO[ i ][ j ] se(v)}} if( pps_weighted_bipred_flag && wp_info_in_ph_flag) numHweights ue(v) for( i = 0; i < NumWeightsLI; i++ ) Iuma_weight_l1_flag[ i ] u(1) if( ChromaArrayType != 0 ) for( i = 0; i < NumWeightsLI; i++ ) chroma_weight_l1_flag[ i ] u(1) for( i = 0; i < NumWeightsLI; i++ ) { if( Iuma_weight_l1_flag[ i ]) { delta_luma_weight_l1[ i ] se(v) Iuma_offset_l1[ i ] se(v)} if( chroma_weight_l1_flag[ i ]) for( j = 0; j < 2; j++ ) { delta_chroma_weight_l1[ i ][ j ] se(v) delta_chroma_offset_H[ i ][ j ] se(v)}}} RQQZ ίΠ / ΖΖηΖ / Ε / ΥΙΛΙ A third problem is associated with the syntax ph_temporal_mvp_enabled_flag. In current VVC, because the resolution of the placed image selected for TMVP derivation should be the same as the resolution of the current image, there is a bitstream compliance constraint for checking the value of ph_temporal_mvp_enabled_flag, as illustrated below. When no reference image in the DPB has the same spatial resolution as the current image, the value of ph_temporal_mvp_enabled_flag should be equal to 0. However, in current VVC, not only does the resolution of the placed image affect TMVP enablement, but also the offsets applied to the image size for scaling ratio calculation. In current VVC, however, these offsets are not considered in the bitstream compliance of ph_temporal_mvp_enabled_flag. Furthermore, there is a bitstream compliance requirement that the image referenced by slice_collocated_ref_idx should be the same for all segments of an encoded image. However, when an encoded image has multiple segments and there is no common reference image among all these segments, this bitstream compliance cannot be met. In such a case, ph_temporal_mvp_enabled_flag should be restricted to 0. Several methods are proposed to address the problems described above. The proposed methods could be applied independently or in combination. Because the features controlled by the mvd_l1_zero_flag, ph_disable_bdof_flag, and ph_disable_dmvr_flag flags are only applicable when the segment is a bi-predictive (B-segment), according to a disclosure method, it is proposed to signal these flags only when the associated segments are B-segments. It is noted that when the reference image lists are signaled in PH (e.g., rpl infojn ph flag=1), this means that all segments of the encoded image use the same reference images signaled in PH. Therefore, when the reference image lists are signaled in PH and the signaled reference image lists indicate that the current image is not bi-predictive, the mvdJ1_zero_flag, ph_disable_bdof_flag, and ph_disable_dmvr_flag flags do not need to be signaled. In some examples, certain conditions are added to the syntax established in PH to prevent redundant signaling or undefined decoding behavior due to inappropriate values ​​sent for some of the syntax in the image header. The following examples illustrate the number of reference images in list i, where the variables num_ref_entries[i][Rplsldx[i]] represent the number of reference images in list i. In some examples, the condition may be as shown below: if (rpljnfo_in_ph_flag && num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] > 1 && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 1 ) mvdJ1_zero_flag In some examples, the condition may be as shown below: if (!rpl_info_in_ph_flag || (rpl_¡nfo_¡n_ph_flag && num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] > 1 && num ref entries[ 1 ][ Rplsldx[ 1 ] ] > 1 )) mvdJ1_zero_flag In some examples, the condition may be as shown below: if (!rpl_info_in_ph_flag || (rpljnfo_in_ph_flag && num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] > 0 && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0 ) mvdJ1_zero_flag RQQ7 ίη / ΖΖΠΖ / Ε / ΥΙΛΙ Alternatively, the conditions can be written in a more compact form that provides the same results. Because a bi-predictive segment (B-segment) or bi-predictive image must have at least one listl reference image, this can only check if the current segment / image has the listl reference image. An example of checking the alternative condition is illustrated below: if (!rpl_info_in_ph_flag || (rpl_info_in_ph_flag && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0 )) vd_l1_zero_flag The semantics of mvdJ1_zero_flag are also modified to handle the case when it is not flagged. A value of mvd_H_zero_flag equal to 1 indicates that the syntax structure mvd_coding( xO, yO, 1 ) is not parsed, and MvdL1 [ xO ][ yO ][ compldx ] and MvdCpLI [ xO ][ yO ][ cpldx ][ compldx ] are set to 0 for compldx = 0..1 and cpldx = 0..2. A value of mvd_H_zero_flag equal to 0 indicates that the syntax structure mvd_coding( xO, yO, 1 ) is parsed. When it is not present, the value of mvdJ1_zero_flag is inferred to be 0. The following illustrates several examples of conditional signaling of the ph disable_dmvr flag syntax element: If (sps_dmvr_pic_present_flag && rplinfojnphflag && num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] > 1 && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 1 ) ph_disable_dmvr_flag or If (sps_dmvr_pic_present_flag && (!rpl_info_in_ph_flag || (rpl Jnfo Jn_ph Jlag && num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] > 1 && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 1))) ph_disable_dmvr_flag or Yes (sps_dmvr_pic_present_flag && (!rpl_info_in_ph_flag || (rpl infojn ph flag && num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] > 0 && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0))) ph_disable_dmvr_flag The following illustrates another example of alternative condition checking: if (sps_dmvr_pic_present_flag && (!rpl info in ph flag || (rpl_info_in_ph_flag && num_ref_entries[ 1 ][ Rplsldxf 1 ] ] > 0)) ) ph_disable_dmvr_flag The semantics of ph_disable_dmvr_flag are also modified to handle the case when it is not signaled. ph_disable_dmvr_flag equal to 1 specifies that the decoder's motion vector refinement-based bi-prediction inter-inter is disabled on the segments associated with the PH. ph disable dmvr flag equal to 0 specifies that the decoder's motion vector refinement-based bi-prediction inter-inter may or may not be enabled on the segments associated with the PH. When ph_disable_dmvr_flag is not present, the following applies: - If sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 0, the value of ph_disable_dmvr_flag is inferred to be equal to 0. - Conversely, if sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to RQQZ ίη / ΖΖΠΖ / Ε / ΥΙΛΙ 1, the value of ph_disable_dmvr_flag is inferred to be equal to 1. - Otherwise (sps_dmvr_enabled_flag is equal to 0), the value of ph_disable_dmvr_flag is inferred to be equal to 1. The following illustrates another example for deriving the value of ph_disable_dmvr_flag when it is not displayed: If all conditions for deriving the value of ph_disable_dmvr_flag are considered when it is explicitly signaled or implicitly derived: - If sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 0, the value of ph_disable_dmvr_flag is inferred to be equal to 0. - Conversely, if sps_dmvr_enabled_flag is equal to 0 and sps_dmvr_pic_present_flag is equal to 0, the value of ph_disable_dmvr_flag is inferred to be equal to 1. Conversely, if sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 0, the value of ph_disable_dmvr_flag is inferred to be equal to X. (X is explicitly signaled) Conversely, if sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to a and rplinfojnphflag is equal to 1 and num ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0, the value of ph_disable_dmvr_flag is inferred to be equal to X. (X is explicitly signaled) - Conversely (sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] ==0), the value of ph_disable_dmvr_flag is inferred to be equal to 1. Because the syntax element ph_disable_dmvr_flag is explicitly signaled under the third and fourth conditions, these can be removed from the derivation of ph_disable_dmvr_flag when ph_disable_dmvr_flag is not present. When ph_disable_dmvr_flag is not present, the following applies: - If sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 0, the value of ph_disable_dmvr_flag is inferred to be equal to 0. - Conversely, if sps_dmvr_enabled_flag is equal to 0 and sps_dmvr_pic_present_flag is equal to 0, the value of ph_disable_dmvr_flag is inferred to be equal to 1. - Conversely (sps_dmvr_enabled_flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1 and rpl_infojn_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] ==0), the value of ph_disable_dmvr_flag is inferred to be equal to 1. The conditions can be editorially simplified as shown below: When ph_disable_dmvr_flag is not present, the following applies: - If sps dmvr enabled flag is equal to 1 and sps dmvr pie present flag is equal to 0, the value of ph_disable_dmvr_flag is inferred to be equal to 0. - Otherwise (sps_dmvr_enabled_flag is equal to 0 or sps_dmvr_pic_present_flag is equal to 1), the value of ph_disable_dmvr_flag is inferred to be equal to 1. The following illustrates another example of deriving the value of ph_disable_dmvr_flag when it is not displayed: RQQZ ίΠ / ΖΖηΖ / Ε / ΥΙΛΙ When ph_disable_dmvr_flag is not present, the following applies: - If sps_dmvr_pic_present_flag is equal to 0, the value of ph_disable_dmvr_flag is inferred to be equal to 1- sps_dmvr_enabled_flag. - Conversely, if sps_dmvr_pic_present_flag is equal to 1 and rpljnfojn ph flag is equal to 0, the value of ph_disable_dmvr_flag is inferred to be equal to 1- sps_dmvr_enabled_flag. - For example, if sps_dmvr_pic_present_flag is equal to 1 and rpljnfojn_phjlag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0, the value of ph_disable_dmvr_flag is inferred to be equal to 1sps_dmvr_enabled_flag. - Conversely (sps_dmvr_pic_present_flag is equal to 1 and rpljnfojn ph flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] ==0), the value of ph_disable_dmvrjlag is inferred to be equal to 1. In some examples, because the syntax element ph_disable_dmvrjlag is explicitly signaled under the second and third conditions above, these can be removed from the derivation of ph_disable_dmvrjlag when it is not present. In some examples, when ph_disable_dmvrjlag is not present, the following applies: if sps_dmvr_pic_presentjlag is equal to 0, the value of ph_disable_dmvrjlag is inferred to be equal to 1 sps_dmvr enabledjlag; otherwise, the value of ph disable_dmvr flag is inferred to be equal to 1. The following illustrates several examples of conditional signaling of the ph_disable_bdofJlag syntax element: - If (sps_bdof_pic_presentjlag && rpljnfojn_phjlag && numjef_entries[ 0 ][ Rplsldx[ 0 ] ] > 1 && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 1 ) ph_disable_bdofjlag Or if (sps_bdof_pic_presentjlag && (!rpljnfojn_phjlag || (rpljnfojn_phjlag && num_ref_entñes[ 0 ][ Rplsldx[ 0 ] ] > 1 && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 1))) ph_disable_bdofjlag In some examples, an example of the alternative condition check is illustrated below: if (sps_bdof_pic_presentjlag && (!rpljnfojn_phjlag || (rpljnfojn_phjlag && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0)) ) ph_disable_bdofjlag The semantics of ph_disable_bdofjlag are also modified to handle the case when it is not signaled. ph_disable_bdof_flag equal to 1 specifies that inter bi-prediction based on inter bi-directional optical flow prediction is disabled on the segments associated with the PH. ph disable bdof flag equal to 0 specifies that inter bi-prediction based on inter bi-directional optical flow prediction may or may not be enabled on the segments associated with the PH. When ph_disable_bdofjlag is not present, the following applies: - If sps_bdof_enabledjlag is equal to 1 and sps_bdof_pic_presentjlag is equal to 0, the value of ph_disable_bdofjlag is inferred to be equal to 0. RQQZ ίΠ / ΖΖηΖ / Ε / ΥΙΛΙ - Conversely, if sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1, the value of ph_disable_dmvr_flag is inferred to be equal to 1. - Otherwise (sps_bdof_enabled_flag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to 1. The following illustrates an alternative way to derive the value of ph_disable_bdof_flag when it is not displayed: If all conditions for deriving the value of ph_disable_bdof_flag are considered when it is either explicitly signaled or implicitly derived: - If sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to 0. - Conversely, if sps_bdof_enabled_flag is equal to 0 and sps_bdof_pic_present_flag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to 1. Conversely, if sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 and rplinfoinphflag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to X. (X is explicitly signaled) Conversely, if sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0, the value of ph_disable_bdof_flag is inferred to be equal to X. (X is explicitly signaled) - Conversely (sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] ==0), the value of ph_disable_bdof_flag is inferred to be equal to 1. Because the syntax element ph_disable_bdof_flag is explicitly signaled under the third and fourth conditions, these can be removed from the derivation of ph_disable_bdof_flag when ph_disable_bdof_flag is not present: When ph_disable_bdof_flag is not present, the following applies: - If sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to 0. - Conversely, if sps_bdof_enabled_flag is equal to 0 and sps_bdof_pic_present_flag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to 1. - Conversely (sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] ==0), the value of ph_disable_bdof_flag is inferred to be equal to 1. The conditions can be editorially simplified as follows: When the ph disable bdof flag is not present, the following applies: - If sps_bdof_enabled_flag is equal to 1 and sps_bdof_pic_present_flag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to 0. - Otherwise (sps_bdof_enabled_flag is equal to 0 or sps_bdof_pic_present_flag is equal to 1), the value of ph_disable_bdof_flag is inferred to be equal to 1. The following illustrates another alternative way to derive the value of ph_disable_bdof_flag RQQZ ίη / ΖΖΠΖ / Ε / ΥΙΛΙ when not presented: When ph_disable_bdof_flag is not present, the following applies: - If sps_bdof_pic_present_flag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to 1- sps_bdof_enabled_flag. - Conversely, if sps_bdof_pic_present_flag is equal to 1 and rpljnfojn ph flag is equal to 0, the value of ph_disable_bdof_flag is inferred to be equal to 1- sps_bdof_enabled_flag. - Conversely, if sps_bdof_pic_present_flag is equal to 1 and rplinfoinphflag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0, the value of ph_disable_bdof_flag is inferred to be equal to 1sps_bdof_enabled_flag. - Conversely (sps_bdof_pic_present_flag is equal to 1 and rpljnfojn ph flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] ==0), the value of ph_disable_bdofjlag is inferred to be equal to 1. In some examples, because the syntax element ph_disable_bdofjlag is explicitly signaled under the second and third conditions, these can be removed from the derivation of ph_disable_bdofjlag when it is not present. When ph_disable_bdofJlag is not present, the following applies: - If sps_bdof_pic_presentjlag is equal to 0, the value of ph disable_bdofJlag is inferred to be equal to 1- sps_bdof_enabledjlag. - Otherwise, the value of ph_disable_bdof Jlag is inferred to be equal to 1. Furthermore, the signaling conditions for the syntax elements ph_collocated_fromJ0_flag and weightjable() are modified because these two types of syntax elements are only applicable when the associated segments are B-segments. Examples of the signaling for the modified syntax elements are illustrated below. RQQZ ίη / ΖΖΠΖ / Ε / ΥΙΛΙ if( phjemporal_mvp_enabledjlag && (num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] > 1 && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 1))) { ph_collocated_from IO_flag Or if( phjemporal_mvp_enabledjlag && (num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] > 0 && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0))) { ph_collocated_fromJO_flag The semantics of ph collocated from lO flag is also modified to handle the case when it is not signaled. ph_collocated_fromJ0_flag equal to 1 specifies that the placed image used for temporal motion vector prediction is derived from reference image list 0. ph_collocatedJromJ0Jlag equal to 0 specifies that the placed image used for temporal motion vector prediction is derived from reference image list 1. When ph_collocated_from_IO_flag is not present, the following applies: - If num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] is greater than 1, the value of ph_collocated_from_IO_flag is inferred to be 1. - Otherwise (num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] is greater than 1 ), the value of ph_collocated_from_IO_flag is inferred to be 0. RQQ7 ίη / ΖΖΠΖ / Ε / ΥΙΛΙ if( ( pps_weighted_pred_flag | | pps_weighted_bipred_flag ) && wp_info_in_ph_flag flag) pred_weight_table() pred_weight_table() { Descriptor Iuma_log2_weight_denom ue(v) if( ChromaArrayType != 0 ) delta_chroma_log2_weight_denom se(v) if( wp_info_in_ph_flag) num_IO_weights ue(v) for( i = 0; i < NumWeightsLO; i++ ) luma_weight_IO_flag[ i ] u(1) if( ChromaArrayType != 0 ) for( i = 0; i < NumWeightsLO; Í++ ) chroma_weight_IO_flag[ i ] u(1) for( i = 0; i < NumWeightsLO; i++ ) { if( luma_weight_IO_flag[ i ]) { delta_luma_weight_IO[ i ] se(v) luma_offset_IO[ i ] se(v)} if( chroma weight I0 flag[ i ]) for( j = 0; j < 2; j++ ) { delta_chroma_weight_IO[ i ][ j ] se(v) delta_chroma_offset_IO[ i ][ j ] se(v)}} if( pps_weighted_bipred_flag && wpjnfo_in_ph_flag && (!rpl_info_in_ph_flag || (rpl_¡nfo_in_ph_flag && num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] > 0&& num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0))) num_l1_weights ue(v) for( i = 0; i < NumWeightsLI;i++ ) Iuma_weight_l1_flag[ i ] u(1) if( ChromaArrayType != 0 ) for( i = 0; i < NumWeightsLI; i++ ); chroma_weight_l1_flag[ i ] u(1) for( i = 0; i < NumWeightsLI; i++ ) { if( Iuma_weight_l1_flag[ i ]) { delta_luma_weightJ1[ i ] se(v) Iuma_offset_l1[ i ] se(v)} if( chroma_weight_l1_flag[ i ]) for( j = 0; j < 2; j++ ) { delta_chroma_weight_l1[ i ][ j ] se(v) delta_chroma_offset_l1[ i ][ j ] se(v)}}} RQQ7 ίη / ΖΖΠΖ / Ε / ΥΙΛΙ In a similar way, below is an example of the verification of an alternative condition: yes( pps_weighted_bipred_flag && wp_infojn_ph_flag && (!rpljnfo_in_ph_flag || (rpl_info_in_ph_flag && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0))) numJ1_weights The semantics of the syntax elements in pred_weight_table() are also modified to handle the case when they are not reported. numjlweights specifies the number of weights signaled for entries in the reference image list 1 when pps_weighted_bipred_flag and wp_info_in_ph_flag are both equal to 1. The value of numJ1_weights should be in the range of 0 to Min( 15, num_ref_entries[ 1 ][ Rplsldx[ 1 ] ]), inclusive. The NumWeightsLI variable is derived as follows: if( !pps_weighted_bipred_flag) NumWeightsLI = 0 otherwise if (wp_info_in_ph_flag && rpl_info_in_ph_flag && (num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] ==0 || num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] >==0)) NumWeightsLI = 0 otherwise s¡( wp_info_in_ph_flag ) NumWeightsLI = numJ1_weights on the contrary NumWeightsLI = NumRefldxActive[ 1 ] In the semantics of the syntax elements in pred_weight_table(), an alternative way of deriving the value of num_H_weights when it is not presented is illustrated below: num_l1_weights specifies the number of weights signaled for entries in the reference image list 1 when pps_weighted_bipred_flag and wp_info_in_ph_flag are both equal to 1. The value of num_l1_weights should be in the range of 0 to Min(15, num_ref_entries[1][Rplsldx[1]]), inclusive. When it is not present, the value of num_H_weights is inferred to be 0. The NumWeightsLI variable is derived as follows: s¡( !pps_weighted_bipred_flag) NumWeightsLI = 0 otherwise if( wp_info_in_ph_flag ) NumWeightsLI = num_l1_weights on the contrary NumWeightsLI = NumRefldxActive[ 1 ] In the semantics of the syntax elements in pred_weight_table(), another alternative way to derive the value of num_H_weights when it is not presented is illustrated below: if( !pps_weighted_bipred_flag | | ( wp_info_in_ph_flag && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] = = 0)) NumWeightsLI = 0 otherwise s¡( wp_info_in_ph_flag ) NumWeightsLI = num 11 weights otherwise NumWeightsLI = NumRefldxActive[ 1 ] Conceptually, the proposal is to add a signaling condition to check whether the current image has reference images from both reference image lists, `listo` and `listl`, for any syntax elements that are only applicable in B segments to avoid signaling redundant bits. The check condition is not limited to the previously mentioned method for checking the size of both reference image lists (e.g., `listO` / `listl` reference image lists) and can be any other method for indicating whether the current image has reference images from both `listo` and `listl` reference image lists. For example, a flag can be signaled to indicate whether the current image has reference images from both `listo` and `listl`. When syntax elements are not flagged and the reference image list information is flagged in the image header (PH), the values ​​of the syntax elements are derived using information about whether the current image has both ready and listl reference images or only ready or listl reference images. For example, when ph_collocated_from_IO_flag is not flagged, its value is inferred to be the only reference image the current image has. In another example, when sps_bdof_enabled_flag is equal to 1 and sps bdof pie present flag is equal to 1, but ph disable bdof flag is not signaled, this implies that either num_ref_entries[0][Rplsldx[0]] is equal to 0 or num_ref_entries[1][Rplsldx[1]] is equal to 0, according to the signaling condition proposed in ph_disable_bdof_flag. Therefore, under this condition, ph_disable_bdof_flag is not signaled and is inferred to be 1.In current VVC, not only can the resolution of the placed image affect the enabling of TMVP, but also the compensations applied to the image size for scaling ratio calculation can affect it. RQQZ ίη / ZZΖΠZ / E / YΙΛΙ the TMVP enablement. However, in the current VVC, the offsets are not considered in the compliance of the bitstream of ph_temporal_mvp_enabled_flag. In the second mode, it is proposed to add a restriction to the compliance of the bitstream to the current VVC requiring that the value of ph_temporal_mvp_enabled_flag depend on the offsets that are applied to the image size for scaling ratio calculation, as illustrated below. When no reference image in the DPB has the same spatial resolution and the same offsets that are applied to the image size for scaling ratio calculation as the current image, the value of ph_temporal_mvp_enabled_flag should be equal to 0. The above sentences can also be written in another form as follows: when no reference image in the DPB has the associated variable value RprConstraintsActive[ i ][ j ] equal to 0, the value of ph_temporal_mvp_enabled_flag should be equal to 0. In the current VVC specification, there is a bitstream compliance requirement that the image referenced by `slice_collocated_ref_idx` should be the same for all segments of an encoded image. However, when the encoded image has multiple segments and there is no common reference image among all these segments, this bitstream compliance cannot be met. In the third disclosure modality, the bitstream compliance requirement for `ph_temporal_mvp_enabled_flag` is modified to consider whether a common reference image exists among all segments in the current image. Based on this modality, several exemplary modifications to the VVC specification are illustrated below. `ph_temporal_mvp_enabled_flag` specifies whether temporal motion vector predictors can be used for interprediction for segments associated with the PH. If `ph_temporal_mvp_enabled_flag` is 0, the syntax elements of the segments associated with the PH should be restricted so that no temporal motion vector predictors are used in decoding the segments. Otherwise (`ph_temporal_mvp_enabled_flag` is 1), temporal motion vector predictors can be used in decoding the segments associated with the PH. When not present, the value of `ph_temporal_mvp_enabled_flag` is inferred to be 0. When no reference image in the DPB has the same spatial resolution as the current image, the value of `ph_temporal_mvp_enabled_flag` should be 0.When there is no common reference image across all segments associated with PH, the value of ph_temporal_mvp_enabled_flag should be equal to 0. `ph_temporal_mvp_enabled_flag` specifies whether temporal motion vector predictors can be used for interprediction for segments associated with the PH. If `ph_temporal_mvp_enabled_flag` is set to 0, the syntax elements of the segments associated with the PH must be restricted so that no temporal motion vector predictors are used in decoding the segments. Otherwise (`ph_temporal_mvp_enabled_flag` is set to 1), temporal motion vector predictors can be used in decoding the segments associated with the PH. When not present, the value of `ph_temporal_mvp_enabled_flag` is inferred to be 0. When no reference image in RQQZ ίη / ZZΖΠZ / E / YΙΛΙ If the DPB has the same spatial resolution as the current image, the value of ph_temporal_mvp_enabled_flag should be equal to 0. When no common reference image exists in all intersegments associated with the PH, the value of ph_temporal_mvp_enabled_flag should be equal to 0. `ph_temporal_mvp_enabled_flag` specifies whether temporal motion vector predictors can be used for interprediction for segments associated with the PH. If `ph_temporal_mvp_enabled_flag` is 0, the syntax elements of the segments associated with the PH should be restricted so that no temporal motion vector predictors are used in decoding the segments. Otherwise (`ph_temporal_mvp_enabled_flag` is 1), temporal motion vector predictors can be used in decoding the segments associated with the PH. When not present, the value of `ph_temporal_mvp_enabled_flag` is inferred to be 0. When no reference image in the DPB has the same spatial resolution as the current image, the value of `ph_temporal_mvp_enabled_flag` should be 0.When no common reference image exists across all non-intra-segments associated with PH, the value of ph_temporal_mvp_enabled_flag should be equal to 0. In one example, fulfilling the bit stream in slice_collocated_ref_idx is simplified as follows: It is a bitstream compliance requirement that the values ​​of pic_widthjn_luma_samples and pic_heightjn_luma_samples of the reference image referred to by slice_collocated_ref_idx should be equal to the values ​​of picwidthjnjumasamples and pic_height_in_luma_samples, respectively, of the current image, and RprConstraintsActive[ slice_collocated_from_IO_flag ? 0 : 1 ][ slice_collocated_ref_idx ] should be equal to 0. The methods described above can be implemented using an apparatus that includes one or more circuits, which may include application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. The apparatus may use the circuits in combination with the other hardware or software components to execute the methods described above. Each module, sub-module, unit, or sub-unit disclosed above may be implemented at least partially using one or more circuits. In the current VVC specification, compliance with two bitstreams is required for the resolution limitation of the placed image. One is found in `ph_temporal_mvp enabled_flag`, and the other in the bitstream compliance of `slice_collocated_ref_idx`. However, compliance with both bitstreams is redundant in the VVC specification from a functional standpoint because it prohibits the use of a placed image with a different resolution and / or scaling offsets than the current image. To reduce the load on the encoder when checking for bitstream compliance, it is proposed that in the fifth mode, only bitstream compliance be enforced. RQQZ ίη / ZZΖΠZ / E / YΙΛΙ slice collocated ref idx. An example of the revised VVC specification is illustrated below. The changed parts are highlighted. `ph_temporal_mvp_enabled_flag` specifies whether temporal motion vector predictors can be used for interprediction for segments associated with the PH. If `ph_temporal_mvp_enabled_flag` is 0, the syntax elements of the segments associated with the PH should be restricted so that no temporal motion vector predictors are used in decoding the segments. Otherwise (`ph_temporal_mvp_enabled_flag` is 1), temporal motion vector predictors can be used in decoding the segments associated with the PH. When not present, the value of `ph_temporal_mvp_enabled_flag` is inferred to be 0. The other one is raised in compliance with the bit stream in slice_collocated_ref_idx as illustrated below: slice_collocated_ref_idx specifies the reference index of the placed image used for temporal motion vector prediction. It is a requirement of bitstream compliance that the values ​​of pic_width_in_luma_samples and pic_height_in_luma_samples of the reference image referenced by slice_collocated_ref_idx should be equal to the values ​​of pic_width_in_luma_samples and pic_height_in_luma_samples, respectively, of the current image, and RprConstraintsActive[ slice_collocated_from_IO_flag ? 0 : 1 ][ slice_collocated_ref_¡dx ] should be equal to 0. In one example, it is proposed to enforce only the ph_temporal_mvp_enabled_flag bitstream. An example of the revised VVC specification is illustrated below. `ph_temporal_mvp_enabled_flag` specifies whether temporal motion vector predictors can be used for interprediction for segments associated with the PH. If `ph_temporal_mvp_enabled_flag` is 0, the syntax elements of the segments associated with the PH should be restricted so that no temporal motion vector predictors are used in decoding the segments. Otherwise (`ph_temporal_mvp_enabled_flag` is 1), temporal motion vector predictors can be used in decoding the segments associated with the PH. When not present, the value of `ph_temporal_mvp_enabled_flag` is inferred to be 0. When no reference image in the DPB has the same spatial resolution as the current image, the value of `ph_temporal_mvp_enabled_flag` should be 0. The other is raised in compliance with the bit stream in slice_collocated_ref_idx as illustrated below: RQQZ ίη / ZZΖΠZ / E / YΙΛΙ slice_collocated_ref_idx specifies the reference index of the placed image used for temporal motion vector prediction. Figure 5 is a block diagram illustrating an exemplary apparatus for video encoding according to some implementations of this disclosure. The apparatus 500 can be a terminal, such as a mobile phone, tablet computer, digital broadcast terminal, tablet device, or personal digital assistant. As shown in Figure 5, the apparatus 500 may include one or more of the following components: a processing component 502, a memory 504, a power supply component 506, a multimedia component 508, an audio component 510, an input / output (I / O) interface 512, a sensor component 514, and a communication component 516. Processing component 502 generally controls the general operations of device 500, such as operations related to display, a telephone call, data communication, camera operation, and recording. Processing component 502 may include one or more processors 520 to execute instructions to complete all or part of the steps in the preceding method. In addition, processing component 502 may include one or more modules to facilitate interaction between processing component 502 and other components. For example, processing component 502 may include a multimedia module to facilitate interaction between multimedia component 508 and processing component 502. Memory 504 is configured to store various types of data to support the operations of Device 500. Examples of such data include instructions, contact data, directory data, messages, images, videos, and so forth, for any application or method operating on Device 500. Memory 504 can be implemented using any type of volatile or non-volatile storage device, or a combination thereof. Specifically, Memory 504 can be a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), magnetic memory, flash memory, a magnetic disk, or a compact disk. Power supply component 506 supplies power to different components of appliance 500. Power supply component 506 may include a power supply management system, one or more power supplies, and other components associated with the generation, management, and distribution of power for appliance 500. The multimedia component 508 includes a display that provides an output interface between the device 500 and a user. In some examples, the display may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the display includes a touch panel, it can be implemented as a touchscreen that receives an input signal from a user. The touch panel may include one or more touch sensors to detect a tap, a swipe, and a gesture on the panel. RQQZ ίη / ZZΖΠZ / E / YΙΛΙ touch. The touch sensor can detect not only the boundary of a touch or swipe action, but also the duration and pressure of the touch or swipe. In some examples, the multimedia component 508 may include a front-facing and / or rear-facing camera. When the device 500 is in an operating mode, such as image capture or video mode, the front-facing and / or rear-facing camera may receive external multimedia data. The audio component 510 is configured to output and / or input an audio signal. For example, the audio component 510 includes a microphone (MIC). When the device 500 is in an operating mode, such as call mode, recording mode, or speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be stored in memory 504 or sent via communication component 516. In some examples, the audio component 510 also includes a speaker for outputting an audio signal. The I / O interface 512 provides an interface between the processing component 502 and a peripheral interface module. The peripheral interface module can be a keypad, a clickable wheel, a button, or similar. These buttons may include, but are not limited to, a home button, a volume button, a start button, and a lock button.Sensor component 514 includes one or more sensors to provide status assessments for various aspects of device 500. For example, sensor component 514 can detect the power status of device 500 and the relative locations of its components. For example, the components might be a display and a keypad of device 500. Sensor component 514 can also detect a change in the position of device 500 or one of its components, the presence or absence of a user touch on device 500, the orientation or acceleration / deceleration of device 500, and a change in the device 500's temperature. Sensor component 514 can include a proximity sensor configured to detect the presence of a nearby object without physical contact. Additionally, sensor component 514 can include an optical sensor, such as a CMOS or CCD image sensor used in an imaging application.In some examples, the 514 sensor component may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor. The communication component 516 is configured to facilitate wired or wireless communication between the device 500 and other devices. The device 500 can access a wireless network based on a communication standard, such as Wi-Fi, 4G, or a combination thereof. For example, the communication component 516 receives a transmission signal or transmission-related information from an external transmission management system via a transmission channel. Alternatively, the communication component 516 may also include a Near Field Communication (NFC) module to enable short-range communication. For example, the NFC module can be implemented using Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra-Wideband (UWB), Bluetooth (BT), or other technologies. RQQZ ίΠ / ΖΖηΖ / Ε / ΥΙΛΙ In one example, the 500 device can be implemented by one or more Application-Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field-Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements to execute the above method. A non-transient, computer-readable storage medium can be, for example, a Hard Disk Drive (HDD), a Solid State Drive (SSD), Flash memory, a Hybrid Drive or Hybrid Solid State Drive (SSHD), a Read-Only Memory (ROM), a Compact Disc Read-Only Memory (CD-ROM), a magnetic tape, a floppy disk, and so on. Figure 6 is a flowchart that illustrates an exemplary video encoding process according to some implementations of this disclosure. In step 602, the 520 processor determines if a disable flag is present on a PH associated with an image. In some examples, the disable indicator specifies whether a coding tool is disabled in one or more segments associated with the PH. In step 604, the 520 processor infers the value of the disable flag according to one or more enable flags signaled in the image's SPS in response to determining that the disable flag is not present in the PH. In some examples, the 520 processor disables the encoding tool in the decoding of one or more segments in response to determining that the disable flag value is equal to 1 and enables the encoding tool in the decoding of one or more segments in response to determining that the disable flag value is equal to 0. In some examples, the coding tool includes at least one of DMVR-based inter-bi-prediction and BDOF-based inter-bi-prediction. In some instances, the 520 processor skips analyzing the disable flag in response to determining that one or more reference image lists indicate that one or more image-associated segments are not bi-predictive. In some examples, the disable indicator specifies whether DMVR-based inter-bi-prediction is disabled on one or more segments associated with the PH, the 520 processor disables the encoding tool on the decoding of one or more segments by disabling DMVR-based inter-bi-prediction on the decoding of one or more segments, and the 520 processor enables the encoding tool on the decoding of one or more segments by enabling DMVR-based inter-bi-prediction on the decoding of one or more segments. In some examples, the 520 processor infers the value of the disable flag according to one or more enable flags signaled in the image SPS in response to determining that the parsing of the disable flag is skipped by inferring the value of the disable flag as being 0 in response to determining that a first enable flag in the SPS is equal to 1 and a second enable flag in the SPS is equal to 0. In some examples, the first enable indicator in the SPS specifies whether the bi-prediction inter-interference RQQZ ίη / ZZΖΠZ / E / YΙΛΙ based on DMVR is enabled, the first enable indicator being equal to 1 specifies that DMVR-based bi-prediction is enabled, and the first enable indicator being equal to 0 specifies that DMVR-based bi-prediction is disabled. In some examples, the second enable indicator in the SPS specifies whether the disable indicator is present in the PH referring to the SPS; the second enable indicator being equal to 0 specifies that the disable indicator is not present in the PH referring to the SPS; and the second enable indicator being equal to 1 specifies that the disable indicator is present in the PH referring to the SPS. In some examples, the 520 processor infers the value of the disable flag according to one or more enable flags signaled in the image SPS in response to determining that the parsing of the disable flag is skipped by inferring that the value of the disable flag is 1 in response to determining that the first enable flag in the SPS is equal to 1 and the second enable flag in the SPS is equal to 1 and inferring that the value of the disable flag is 1 in response to determining that the first enable flag in the SPS is equal to 0. In some examples, the 520 processor infers the value of the disable flag based on one or more enable flags signaled in the image's SPS in response to determining that parsing the disable flag is skipped, inferring that the disable flag is 1 in response to determining that the first enable flag in the SPS is equal to 0 and the second enable flag in the SPS is equal to 0, and inferring that the value of the disable flag is 1 in response to determining that the first enable flag in the SPS is equal to 1, the second enable flag in the SPS is equal to 1, one or more reference image lists are signaled in the PH, and a number of reference images in a second reference image list is equal to 0. The reference image list(s) include a first reference image list and a second reference image list. In some examples, the 520 processor infers the value of the disable flag according to one or more enable flags signaled in the image SPS in response to determining that the parsing of the disable flag is skipped by inferring that the value of the disable flag is 1 in response to determining that the first enable flag in the SPS is equal to 0 and inferring that the value of the disable flag is 1 in response to determining that the second enable flag in the SPS is equal to 1. In some examples, the 520 processor determines the value of a first enable flag in the SPS as W. The first enable flag in the SPS specifies whether DMVR-based bi-prediction inter-inter ... RQQZ ίη / ZZΖΠZ / E / YΙΛΙ is present in the PH referring to the SPS, the second enable indicator being equal to 0 specifies that the disable indicator is not present in the PH referring to the SPS, and the second enable indicator being equal to 1 specifies that the disable indicator is present in the PH referring to the SPS. In some examples, the 520 processor infers the value of the disable flag according to one or more enable flags signaled in the image SPS in response to determining that the parsing of the disable flag is skipped by inferring that the value of the disable flag is 1 in response to determining that the second enable flag in the SPS is not equal to 0. In some examples, the 520 processor infers that the value of the disable flag is 1 in response to determining that the second enable flag in the SPS is not equal to 0. This occurs when one or more reference image lists are signaled in the PH, and the number of reference images in a second reference image list is equal to 0. The reference image list(s) include a first reference image list and a second reference image list. In some examples, the 520 processor infers the value of the disable flag according to one or more enable flags in the SPS in response to determining that the disable flag is signaled in the PH. In some examples, the 520 processor infers the value of the disable flag according to one or more enable flags in the SPS in response to determining that the disable flag is signaled in the PH through the following: determining a value of a first enable flag in the SPS as W; inferring the value of the disable flag as 1-W in response to determining that a second enable flag in the SPS is equal to 1 and one or more reference image lists are not signaled in the PH; inferring that the value of the disable flag is 1-W in response to determining that the second enable flag in the SPS is equal to 1, the reference image list or lists are signaled in the PH, and a number of reference images in reference image list 1 is greater than 0. In some examples, the 520 processor infers the disable flag value according to one or more enable flags in the SPS in response to determining that the disable flag is signaled in the PH by: inferring that the disable flag value is a disable flag value explicitly signaled in the PH in response to determining that a first enable flag in the SPS is equal to 1, a second enable flag in the SPS is equal to 1, and one or more reference image lists are not signaled in the PH;infer that the value of the disable indicator is the value of the disable indicator explicitly signaled in the PH in response to determining that the first enable indicator in the SPS is equal to 1, the second enable indicator in the SPS is equal to 1, the reference image list(s) are signaled in the PH, and a reference image number in the reference image list 1 is greater than 0.; In some examples, the disable flag specifies whether BDOF-based bi-prediction inter-interference is disabled on the segment or segments associated with the PH. The 520 processor disables the RQQZ ίη / ZZΖΠZ / E / YΙΛΙ encoding tool in the decoding of one or more segments by disabling the inter bi-prediction based on BDOF in the decoding of one or more segments and enables the encoding tool in the decoding of one or more segments by enabling the inter bi-prediction based on BDOF in the decoding of one or more segments. In some examples, the 520 processor infers the value of the disable flag based on one or more enable flags signaled in the image's SPS in response to determining that the analysis of the disable flag is skipped by inferring that the value of the disable flag is 0 in response to determining that a third enable flag in the SPS is equal to 1 and a fourth enable flag in the SPS is equal to 0. The third enable flag in the SPS specifies whether BDOF-based inter-bi-prediction is enabled; the third enable flag being equal to 1 specifies that BDOF-based inter-bi-prediction is enabled, and the third enable flag being equal to 0 specifies that BDOF-based inter-bi-prediction is disabled.The fourth enable indicator in the SPS specifies whether the disable indicator is present in the PH referring to the SPS. The fourth enable indicator being equal to 0 specifies that the disable indicator is not present in the PH referring to the SPS, and the fourth enable indicator being equal to 1 specifies that the disable indicator is present in the PH referring to the SPS. In some examples, the 520 processor infers the value of the disable flag according to one or more enable flags signaled in the image SPS in response to determining that the analysis of the disable flag is skipped by inferring that the value of the disable flag is 1 in response to determining that the third enable flag in the SPS is equal to 1 and the fourth enable flag in the SPS is equal to 1 and inferring that the value of the disable flag is 1 in response to determining that the third enable flag in the SPS is equal to 0. In some examples, the 520 processor infers the value of the disable flag according to one or more enable flags signaled in the image's SPS in response to determining that parsing the disable flag is skipped, inferring that the disable flag is 1 in response to determining that the third enable flag in the SPS is equal to 0 and the fourth enable flag in the SPS is equal to 0, and inferring that the value of the disable flag is 1 in response to determining that the third enable flag in the SPS is equal to 1, the fourth enable flag in the SPS is equal to 1, one or more reference image lists are signaled in the PH, and a number of reference images in a second reference image list is equal to 0. The reference image list(s) include a first reference image list and a second reference image list. In some examples, the 520 processor infers the value of the disable flag according to one or more enable flags signaled in the image SPS in response to determining that the analysis of the disable flag is skipped, inferring that the value of the disable flag is 1 in response to determining that the third enable flag in the SPS is equal to 0, and inferring that the value of the disable flag is 1 in response to determining that the fourth enable flag in the SPS is equal to 1. In some examples, the 520 processor determines the value of a third enable flag in RQQZ ίη / ZZΖΠZ / E / YΙΛΙ the SPS as V and infers the value of the disable indicator according to one or more enable indicators signaled in the SPS of the image inferring that the value of the disable indicator is 1-V in response to determining that a fourth enable indicator in the SPS is equal to 0. In some examples, the 520 processor infers the value of the disable flag according to one or more enable flags signaled in the image SPS in response to determining that the parsing of the disable flag is skipped by inferring that the value of the disable flag is 1 in response to determining that the fourth enable flag in the SPS is not equal to 0. In some examples, the 520 processor infers that the value of the disable flag is 1 in response to determining that the fourth enable flag in the SPS is not equal to 0. This occurs when one or more reference image lists are signaled in the PH, and a number of reference images in a second reference image list is equal to 0. The reference image list(s) include a first reference image list and a second reference image list. In some examples, the 520 processor determines a third enable flag value in the SPS as V and infers the disable flag value according to one or more enable flags in the SPS in response to determining that the disable flag is signaled in the PH through the following: inferring that the disable flag value is 1-V in response to determining that a fourth enable flag in the SPS is equal to 1 and one or more reference image lists are not signaled in the PH; and inferring that the disable flag value is 1-V in response to determining that the fourth enable flag in the SPS is equal to 1, the reference image list or lists are signaled in the PH, and a number of reference images in reference image list 1 is greater than 0. In some examples, the 520 processor infers that the disable flag value is a disable flag value explicitly signaled in the PH in response to determining that a third enable flag in the SPS is equal to 1, a fourth enable flag in the SPS is equal to 1, and one or more reference image lists are not signaled in the PH and infers that the disable flag value is the disable flag value explicitly signaled in the PH in response to determining that the third enable flag in the SPS is equal to 1, the fourth enable flag in the SPS is equal to 1, the reference image list or lists are signaled in the PH, and a number of reference images in reference image list 1 is greater than 0. Figure 7 is a flowchart that illustrates an exemplary video encoding process according to some implementations of this disclosure. In step 702, the 520 processor determines if an indicator is present in a PH associated with an image. In some examples, the indicator specifies whether the image used for TMVP is derived from a reference image list from among a plurality of reference image lists associated with the image. In step 704, the 520 processor infers the indicator value according to a number of RQQZ ίΠ / ZZΖηZ / E / YΙΛΙ reference images in the reference image list in response to determining that the indicator is not present in the PH. In some examples, the 520 processor skips the indicator analysis in response to determining that the plurality of reference image lists indicates that one or more segments associated with the image are not bi-predictive. In some examples, the plurality of reference image lists includes a first reference image list and a second reference image list. In some examples, the indicator being equal to 1 specifies that the image used for TMVP is derived from the first reference image list, and the indicator being equal to 0 specifies that the image used for TMVP is derived from the second reference image list. In some examples, the 520 processor infers the indicator value according to the number of reference images in the reference image list in response to determining that the indicator analysis is skipped, inferring that the indicator value is 1 in response to determining that the number of reference images in the first reference image list is greater than 1, and inferring that the indicator value is 0 in response to determining that the number of reference images in the second reference image list is greater than 1. Figure 8 is a flowchart that illustrates an exemplary video encoding process according to some implementations of this disclosure. In step 802, the 520 processor determines if an indicator is present in a PH associated with an image. In some examples, the indicator specifies a number of signaled weights in a list of reference images according to a first WP indicator in the image's PPS and a second WP indicator in the image's PH, and the indicator is in a WP syntax associated with the image. In step 804, the 520 processor infers the indicator value according to a number of reference images in a reference image list from among a plurality of reference image lists associated with the image in response to determining that the indicator is not present in the PH. In some examples, the 520 processor skips the indicator analysis in response to determining that the plurality of reference image lists indicates that one or more segments associated with the image are not bi-predictive. In some examples, the plurality of reference image lists includes a first reference image list and a second reference image list; the indicator specifies the number of weights signaled in the second reference image list in response to determining that the first WP indicator in the PPS is equal to 1 and the second WP indicator in the PH is equal to 1. In some examples, the 520 processor infers the indicator value according to the number of reference images in the reference image list associated with the image in response to determining that the indicator analysis is skipped, inferring that the indicator value is 0 in response to determining that the first WP indicator in the PPS is equal to 0, the second WP indicator in the PH is equal to 1, and the number of reference images in the second reference image list is equal to RQQZ ίη / ZZΖΠZ / E / YΙΛΙ to 0, inferring that the indicator value is a value of the indicator explicitly signaled in the PH in response to determining that the first WP indicator in the PPS is not equal to 0 and the second WP indicator in the PH is equal to 1, and inferring that the indicator value is a value of NumRefldxActive[ 1 ] in response to determining that the first WP indicator in the PPS is not equal to 0 and the second WP indicator in the PH is not equal to 1. In some examples, the value of NumRefldxActivef i ] - 1 specifies a maximum reference index for a reference image list i, where i equals 0 or 1. For example, the value NumRefldxActive[ 1 ] - 1 specifies a maximum reference index for reference image list 1, i.e., the second reference image list. In some examples, the 520 processor determines the indicator value in response to determining that the indicator is present in the PH by determining the indicator value as 0 in response to determining that the first WP indicator in the PPS is equal to 0, determining that the indicator value is a value of the indicator explicitly signaled in the PH in response to determining that the first WP indicator in the PPS is not equal to 0 and the second WP indicator in the PH is equal to 1, and determining that the indicator value is a NumRefldxActivef 1 value in response to determining that the first WP indicator in the PPS is not equal to 0 and the second WP indicator in the PH is not equal to 1. Figure 9 is a flowchart illustrating an exemplary video encoding process according to some implementations of this disclosure. In step 902, the 520 processor uses an enabled flag to specify whether one or more temporal motion vector predictors are used for Interprediction for one or more segments associated with a PH of an image. In step 904, the 520 processor restricts the enabled indicator value according to a plurality of offsets applied to an image size for scaling ratio calculation. In some examples, the processor sets the enabled flag to 0 in response to determining that there is no common reference image in one or more Inter-segments. The segment or segments include one or more Inter-segments associated with the PH. In some examples, the processor sets the enabled flag to 0 in response to determining that there is no common reference image in one or more Intersegments. In some examples, a video encoding apparatus is provided. The apparatus includes one or more 520 processors; and a 504 memory configured to store instructions executable by one or more processors; wherein the processor, at the time of instruction execution, is configured to execute a method as illustrated in Figure 6. In some examples, a video encoding apparatus is provided. The apparatus includes one or more 520 processors; and a 504 memory configured to store instructions executable by one or more processors; wherein the processor, at the time of instruction execution, is configured to execute a method as illustrated in Figure 7. In some examples, a video encoding apparatus is provided. The apparatus includes one or more 520 processors and a 504 memory configured to store executable instructions. RQQZ ίη / ZZΖΠZ / E / YΙΛΙ by one or more processors; where the processor, at the time of instruction execution, is configured to execute a method as illustrated in Figure 8. In some examples, a video encoding apparatus is provided. The apparatus includes one or more 520 processors; and a 504 memory configured to store instructions executable by one or more processors; wherein the processor, at the time of instruction execution, is configured to execute a method as illustrated in Figure 9. In some other examples, a non-transient, computer-readable storage medium 504 is provided, with instructions stored on it. When the instructions are executed by one or more processors 520, the instructions cause the processor to execute a method as illustrated in Figure 6. In some other examples, a non-transient, computer-readable storage medium 504 is provided, with instructions stored on it. When the instructions are executed by one or more processors 520, the instructions cause the processor to execute a method as illustrated in Figure 7. In some other examples, a non-transient, computer-readable storage medium 504 is provided, with instructions stored on it. When the instructions are executed by one or more processors 520, the instructions cause the processor to execute a method as illustrated in Figure 8. In some other examples, a non-transient, computer-readable storage medium 504 is provided, with instructions stored on it. When the instructions are executed by one or more processors 520, the instructions cause the processor to execute a method as illustrated in Figure 9. The description in this disclosure is for illustrative purposes only and is not intended to be exhaustive or limited to this disclosure. Many modifications, variations, and alternative implementations will be apparent to those skilled in the art who benefit from the teachings presented in the preceding descriptions and associated figures. The examples were chosen and described to explain the principles of the disclosure and to enable other practitioners to understand the disclosure for various implementations and to better utilize the underlying principles and various implementations with modifications as appropriate for the intended use. Therefore, it is understood that the scope of the disclosure is not limited to the specific examples of the disclosed implementations and that modifications and other implementations are intended to be included within the scope of this disclosure.

Claims

CLAIMS 1. A method for video decoding, characterized in that it comprises: determining, through a decoder, whether a disable indicator is present in a picture header (PH) associated with a picture, wherein the disable indicator specifies whether an encoding tool is disabled for one or more segments associated with the PH; and in response to determining that the disable indicator is not present in the PH, inferring, through the decoder, a value of the disable indicator in accordance with one or more enable indicators signaled in sequence parameter sets (SPS) of the picture.

2. The method according to claim 1, further characterized in that it additionally comprises: in response to determining that the value of the disable indicator is equal to 1, disabling, via the decoder, the encoding tool in the decoding of one or more segments; and in response to determining that the value of the disable indicator is equal to 0, enabling, via the decoder, the encoding tool in the decoding of one or more segments.

3. The method according to claim 1, further characterized in that the encoding tool comprises at least one of decoder motion vector refinement-based inter-bi-prediction (DMVR) and bidirectional optical flow-based inter-bi-prediction (BDOF).

4. The method according to claim 3, further characterized in that it additionally comprises: in response to determining from one or more reference image lists that one or more segments associated with the image are not bi-predictive, determining, through the decoder, that the disable indicator is not present in the PH.

5. The method according to claim 4, further characterized in that the disable indicator specifies whether DMVR-based inter-bi-prediction is disabled for one or more segments associated with the PH; wherein disabling the encoding tool in the decoding of one or more segments comprises disabling DMVR-based inter-bi-prediction in the decoding of one or more segments; and wherein disabling the encoding tool in the decoding of one or more segments comprises enabling DMVR-based inter-bi-prediction in the decoding of one or more segments.

6. The method according to claim 5, further characterized in that, in response to determining that the disable indicator is not present in the PH, inferring the value of the disable indicator according to one or more enable indicators signaled in the SPS of the image comprises: in response to determining that a first enable indicator in the SPS is equal to 1 and a second enable indicator in the SPS is equal to 0, inferring that the value of the disable indicator is 0, wherein the first enable indicator in the SPS specifies whether the inter-bi-prediction based on RQQZ ίΠ / ZZΖηZ / E / YΙΛΙ DMVR is enabled, the first enable indicator equal to 1 specifies that the inter-bi-prediction based on DMVR is enabled, and the first enable indicator equal to 0 specifies that the inter-bi-prediction based on DMVR is disabled;and where the second enable indicator in the SPS specifies whether the disable indicator is present in the PH referring to the SPS, the second enable indicator being 0 specifies that the disable indicator is not present in the PH referring to the SPS, and the second enable indicator being 1 specifies that the disable indicator may be present in the PH referring to the SPS.; 7. The method according to claim 6, further characterized in that, in response to determining that the disable indicator is not present in the PH, inferring the value of the disable indicator according to one or more enable indicators signaled in the SPS of the image further comprises: in response to determining that the first enable indicator in the SPS is equal to 1 and the second enable indicator in the SPS is equal to 1, inferring that the value of the disable indicator is 1; and in response to determining that the first enable indicator in the SPS is equal to 0, inferring that the value of the disable indicator is 1.

8. The method according to claim 6, further characterized in that it additionally comprises: in response to determining that one or more reference image lists are signaled in the PH, and a number of the reference images in a second reference image list is equal to 0, determining that the segment or segments associated with the image are not bi-predictive, wherein one or more reference image lists comprise a first reference image list and a second reference image list, wherein in response to determining that the disable indicator is not present in the PH, inferring the value of the disable indicator according to one or more enable indicators signaled in the SPS of the image, further comprising: in response to determining that the first enable indicator in the SPS is equal to 0 and the second enable indicator in the SPS is equal to 0, inferring that the value of the disable indicator is 1;And in response to determining that the first enable indicator in the SPS is equal to 1, and the second enable indicator in the SPS is equal to 1, infer that the value of the disable indicator is 1.; 9. The method according to claim 6, further characterized in that, in response to determining that the disable indicator is not present in the PH, inferring the value of the disable indicator according to one or more enable indicators signaled in the SPS of the image, further comprises: in response to determining that the first enable indicator in the SPS is equal to 0, inferring that the value of the disable indicator is 1; and in response to determining that the second enable indicator in the SPS is equal to 1, inferring that the value of the disable indicator is 1. RQQZ ίη / ZZΖΠZ / E / YΙΛΙ 10. The method according to claim 5, further characterized in that it additionally comprises: determining a value of a first enable indicator in the SPS as W, wherein the first enable indicator in the SPS specifies whether DMVR-based bi-prediction inter is enabled, the first enable indicator being equal to 1 specifies that DMVR-based bi-prediction inter is enabled, and the first enable indicator being equal to 0 specifies that DMVR-based bi-prediction inter is disabled;and wherein in response to determining that the disable indicator analysis is not present in the PH, inferring the value of the disable indicator according to one or more enable indicators signaled in the SPS of the image comprises: in response to determining that a second enable indicator in the SPS is equal to 0, inferring that the value of the disable indicator is 1-W, wherein the second enable indicator in the SPS specifies whether the disable indicator is present in the PH referring to the SPS, the second enable indicator being equal to 0 specifies that the disable indicator is not present in the PH referring to the SPS, and the second enable indicator being equal to 1 specifies that the disable indicator may be present in the PH referring to the SPS.

11. The method according to claim 10, further characterized in that, in response to determining that the disable indicator is not present in the PH, inferring the value of the disable indicator according to one or more enable indicators signaled in the SPS of the image further comprises: in response to determining that the second enable indicator in the SPS is not equal to 0, inferring that the value of the disable indicator is 1.

12. The method according to claim 11, further characterized in that it additionally comprises: in response to determining that one or more reference image lists are signaled in the PH, and a number of reference images in a second reference image list is equal to 0, determining that the segment or segments associated with the image are not bi-predictive, wherein the reference image list or lists comprise a first reference image list and a second reference image list, wherein in response to determining that the second enable indicator in the SPS is not equal to 0, inferring that the value of the disable indicator is 1, further comprising: in response to determining that the second enable indicator in the SPS is equal to 1, inferring that the value of the disable indicator is 1.

13. The method according to claim 3, further characterized in that it additionally comprises: in response to determining that the disable indicator is signaled in the PH, inferring the value of the disable indicator according to the enable indicator(s) in the SPS.

14. The method according to claim 13, further characterized in that, in response to determining that the disable indicator is signaled in the PH, inferring the value of the disable indicator RQQZ ίη / ZZΖΠZ / E / YΙΛΙ in accordance with the enable indicator(s) in the SPS comprises: determining a value of a first enable indicator in the SPS as W, wherein the first enable indicator in the SPS specifies whether DMVR-based bi-prediction inter is enabled, the first enable indicator being equal to 1 specifies that DMVR-based bi-prediction inter is enabled, and the first enable indicator being equal to 0 specifies that DMVR-based bi-prediction inter is disabled; In response to determining that a second enable indicator in the SPS is equal to 1 and one or more reference image lists are not signaled in the PH, infer that the disable indicator value is 1-W;and in response to determining that the second enable indicator in the SPS is equal to 1, the reference image list or lists are signaled in the PH, and a number of reference images in the second reference image list is greater than 0, inferring that the value of the disable indicator is 1-W; wherein the second enable indicator in the SPS specifies whether the disable indicator is present in the PH referring to the SPS, the second enable indicator being equal to 0 specifies that the disable indicator is not present in the PH referring to the SPS, and the second enable indicator being equal to 1 specifies that the disable indicator is present in the PH referring to the SPS.

15. The method according to claim 13, further characterized in that, in response to determining that the disable indicator is signaled in the PH, inferring the value of the disable indicator according to the enable indicator(s) in the SPS comprises: in response to determining that a first enable indicator in the SPS is equal to 1, a second enable indicator in the SPS is equal to 1, and one or more reference image lists are not signaled in the PH, inferring that the value of the disable indicator is a value of the disable indicator explicitly signaled in the PH;and in response to determining that the first enable indicator in the SPS is equal to 1, the second enable indicator in the SPS is equal to 1, the reference image list(s) are signaled in the PH, and the number of reference images in the second reference image list is greater than 0, inferring that the disable indicator value is the value of the disable indicator explicitly signaled in the PH, wherein the first enable indicator in the SPS specifies whether DMVR-based Inter bi-prediction is enabled, the first enable indicator being equal to 1 specifies that DMVR-based Inter bi-prediction is enabled, and the first enable indicator being equal to 0 specifies that DMVR-based Inter bi-prediction is disabled;and where the second enable indicator in the SPS specifies whether the disable indicator is present in the PH referring to the SPS, the second enable indicator being equal to 0 specifies that the disable indicator is not present in the PH referring to the SPS, and the second enable indicator being equal to 1 specifies that the disable indicator is present in the PH referring to the SPS. RQQZ ίη / ZZΖΠZ / E / YΙΛΙ; 16. The method according to claim 4, further characterized in that the disable indicator specifies whether the BDOF-based inter-bi-prediction is disabled for the segment or segments associated with the PH; wherein disabling the encoding tool in the decoding of one or more segments comprises disabling the BDOF-based inter-bi-prediction in the decoding of one or more segments; and wherein enabling the encoding tool in the decoding of one or more segments comprises enabling the BDOF-based inter-bi-prediction in the decoding of one or more segments.

17. The method according to claim 16, further characterized in that, in response to determining that the disable indicator is not present in the PH, inferring the value of the disable indicator according to one or more enable indicators signaled in the SPS of the image comprises: in response to determining that a third enable indicator in the SPS is equal to 1 and a fourth enable indicator in the SPS is equal to 0, inferring that the value of the disable indicator is 0, wherein the third enable indicator in the SPS specifies whether the BDOF-based bi-prediction inter-inter ...and where the fourth enable indicator in the SPS specifies whether the disable indicator is present in the PH referring to the SPS, the fourth enable indicator being equal to 0 specifies that the disable indicator is not present in the PH referring to the SPS, and the fourth enable indicator being equal to 1 specifies that the disable indicator is present in the PH referring to the SPS.; 18. The method according to claim 17, further characterized in that, in response to determining that the disable indicator is not present in the PH, inferring the value of the disable indicator according to the enable indicator(s) signaled in the SPS of the image further comprises: in response to determining that the third enable indicator in the SPS is equal to 1 and the fourth enable indicator in the SPS is equal to 1, inferring that the value of the disable indicator is 1; and in response to determining that the third enable indicator in the SPS is equal to 0, inferring that the value of the disable indicator is 1.

19. The method according to claim 17, further characterized in that it additionally comprises: in response to determining that one or more reference image lists are signaled in the PH, and a number of reference images in a second reference image list is equal to 0, determining that the segment or segments associated with the image are not bi-predictive, wherein the reference image list or lists comprise a first reference image list and a second reference image list, wherein in response to determining that the disable indicator is not present in the PH, inferring the value of the disable indicator according to the enable indicator or indicators signaled in the SPS of the image, further comprises: in response to determining that the third enable indicator in the SPS is equal to 0 and the fourth enable indicator in the SPS is equal to 0,infer the disable indicator as 1; and in response to determining that the third enable indicator in the SPS is equal to 1, and the fourth enable indicator in the SPS is equal to 1, infer that the value of the disable indicator is 1.

20. The method according to claim 17, further characterized in that, in response to determining that the disable indicator is not present in the PH, inferring the value of the disable indicator according to the enable indicator(s) signaled in the SPS of the image further comprises: in response to determining that the third enable indicator in the SPS is equal to 0, inferring that the value of the disable indicator is 1; and in response to determining that the fourth enable indicator in the SPS is equal to 1, inferring that the value of the disable indicator is 1.

21. The method according to claim 16, further characterized in that it additionally comprises: determining a value of a third enable indicator in the SPS as V, wherein the third enable indicator in the SPS specifies whether the BDOF-based inter-bi-prediction is enabled, the third enable indicator being equal to 1 specifies that the BDOF-based inter-bi-prediction is enabled, and the third enable indicator being equal to 0 specifies that the BDOF-based inter-bi-prediction is disabled;and where inferring the value of the disable indicator according to the enable indicator(s) signaled in the SPS of the image comprises: in response to determining that a fourth enable indicator in the SPS is equal to 0, inferring that the value of the disable indicator is 1 -V, where the fourth enable indicator in the SPS specifies whether the disable indicator is present in the PH referring to the SPS, the fourth enable indicator being equal to 0 specifies that the disable indicator is not present in the PH referring to the SPS, and the fourth enable indicator being equal to 1 specifies that the disable indicator is present in the PH referring to the SPS.; 22. The method according to claim 21, further characterized in that, in response to determining that the disable indicator is not present in the PH, inferring the value of the disable indicator according to the enable indicator(s) signaled in the SPS of the image further comprises: in response to determining that the fourth enable indicator in the SPS is not equal to 0, inferring that the value of the disable indicator is 1.

23. The method according to claim 22, further characterized in that it additionally comprises: in response to determining that one or more reference image lists are signaled in the PH, and a number of reference images in a second reference image list is equal to RQQZ ίη / ZZΖΠZ / E / YΙΛΙ 0, determining that the segment or segments associated with the image are not bi-predictive, wherein the reference image list or lists comprise a first reference image list and a second reference image list, in response to determining that the fourth enable indicator in the SPS is not equal to 0, inferring that the value of the disable indicator is 1, further comprising: in response to determining that the fourth enable indicator in the SPS is equal to 1, inferring that the value of the disable indicator is 1.

24. The method according to claim 13, further characterized in that it additionally comprises: determining a value of a third enable indicator in the SPS as V, wherein the third enable indicator in the SPS specifies whether bidirectional optical flow (BDOF)-based inter-bi-prediction is enabled, the third enable indicator being equal to 1 specifies that BDOF-based inter-bi-prediction is enabled, and the third enable indicator being equal to 0 specifies that BDOF-based inter-bi-prediction is disabled;and wherein, in response to determining that the disable indicator is signaled in the PH, inferring the value of the disable indicator according to the enable indicator(s) in the SPS comprises: in response to determining that a fourth enable indicator in the SPS is equal to 1 and the reference image list(s) are not signaled in the PH, inferring that the value of the disable indicator is 1-V; and in response to determining that the fourth enable indicator in the SPS is equal to 1, the reference image list(s) are signaled in the PH, and a number of reference images in the second reference image list is greater than 0, inferring that the value of the disable indicator is 1-V;where the fourth enable indicator in the SPS specifies whether the disable indicator is present in the PH referring to the SPS, the fourth enable indicator being equal to 0 specifies that the disable indicator is not present in the PH referring to the SPS, and the fourth enable indicator being equal to 1 specifies that the disable indicator is present in the PH referring to the SPS.; 25. The method according to claim 13, further characterized in that it additionally comprises: in response to determining that a third enable indicator in the SPS is equal to 1, a fourth enable indicator in the SPS is equal to 1, and one or more reference image lists are not signaled in the PH, inferring that the disable indicator value is a disable indicator value explicitly signaled in the PH;and in response to determining that the third enable indicator in the SPS is equal to 1, the fourth enable indicator in the SPS is equal to 1, the reference image list or lists are signaled in the PH, and a number of reference images in the second reference image list is greater than 0, inferring that the value of the disable indicator is the value of the disable indicator explicitly signaled in the PH, RQQZ ίη / ZZΖΠZ / E / YΙΛΙ where the third enable indicator in the SPS specifies whether bidirectional optical flow (BDOF)-based inter-bi-prediction is enabled, the third enable indicator being equal to 1 specifies that BDOF-based inter-bi-prediction is enabled, and the third enable indicator being equal to 0 specifies that BDOF-based inter-bi-prediction is disabled;and where the fourth enable indicator in the SPS specifies whether the disable indicator is present in the PH referring to the SPS, the fourth enable indicator being equal to 0 specifies that the disable indicator is not present in the PH referring to the SPS, and the fourth enable indicator being equal to 1 specifies that the disable indicator is present in the PH referring to the SPS.; 26. A method for video decoding, characterized in that it comprises: determining, through a decoder, whether an indicator is present in an image header (PH) associated with a current image, wherein the indicator specifies whether an image used for temporal motion vector prediction (TMVP) is derived from a reference image list from among a plurality of reference image lists associated with the current image; and in response to determining that the indicator is not present in the PH, inferring, through the decoder, a value for the indicator such as 1.

27. The method according to claim 26, further characterized in that it additionally comprises: in response to determining from the plurality of reference image lists that one or more segments associated with the current image are not bi-predictive, determining, through the decoder, that the indicator is not present.

28. The method according to claim 27, further characterized in that the plurality of reference image lists comprises a first reference image list and a second reference image list; and the indicator being equal to 1 specifies that the image used for TMVP is derived from the first reference image list, and the indicator being equal to 0 specifies that the image used for TMVP is derived from the second reference image list.

29. A method for video decoding, characterized in that it comprises: determining, through a decoder, whether a cue is present in an image header (PH) associated with an image, wherein the cue specifies a number of signaled weights for inputs in a reference image list in response to a first weighted prediction cue (WP) and a second WP cue being 1, wherein the cue is in a WP syntax associated with the image; and in response to determining that the cue is not present in the PH, inferring, through the decoder, a variable value related to the cue according to a number of reference images in a reference image list from among a plurality of reference image lists associated with the image.

30. The method according to claim 29, further characterized in that it additionally comprises, in response to determining from the plurality of reference image lists that one or more segments associated with the image are not bi-predictive, determining, through the decoder, that the indicator is not present.

31. The method according to claim 29, further characterized in that it additionally comprises: in response to determining that the first WP indicator is equal to 0, and the second WP indicator is equal to 1, determining that the indicator is not present; and in response to determining that the first WP indicator is not equal to 0 and the second WP indicator is not equal to 1, determining that the indicator is not present.

32. The method according to claim 29, further characterized in that the plurality of reference image lists comprises a first reference image list and a second reference image list; and wherein the indicator specifies the number of signaled weights for entries in the second reference image list in response to determining that the first WP indicator is equal to 1 and the second WP indicator is equal to 1.

33. The method according to claim 31, further characterized in that the plurality of reference image lists comprises a first reference image list and a second reference image list; wherein in response to determining that the indicator is not present, inferring the variable value related to the indicator according to the number of reference images in the reference image list associated with the image comprises: in response to determining that the number of reference images in the second reference image list is equal to 0, inferring that the variable value related to the indicator is 0;and in response to determining that the number of reference images in the second reference image list is equal to 1, infer that the variable value related to the indicator is a value of NumRefldxActive[1], where the value of NumRefldxActive[1]-1 specifies a maximum reference index for the second reference image list.

34. The method according to claim 29, further characterized in that it additionally comprises: in response to determining that the indicator is present in the PH, determining the variable value related to the indicator as a value of the indicator explicitly signaled in the PH.

35. A method for video decoding, characterized in that it comprises: obtaining, through a decoder, an enable indicator to specify whether one or more time-motion vector predictors are used for interprediction for one or more segments associated with a picture header (PH) of an image; wherein a value of the enable indicator is restricted according to a plurality of offsets applied to a picture size for scaling ratio calculation.

36. The method according to claim 35, further characterized in that: in response to determining that there is no common reference image for one or more inter-segments, the enabled indicator is set to 0, wherein the segment or segments comprise one or more inter-segments associated with the PH. RQQZ ίη / ZZΖΠZ / E / YΙΛΙ 37. The method according to claim 35, further characterized in that: in response to determining that there is no common reference image for one or more non-intra-segments, the enabled indicator is set to 0, wherein the segment or segments comprise one or more non-intra-segments associated with the PH. RQQZ ίΠ / ZZΖηZ / E / YΙΛΙ 38. A video encoding apparatus, characterized in that it comprises: one or more processors; and a memory; wherein the processor or processors are configured to execute in accordance with any of claims 1 to 25.

39. A video encoding apparatus, characterized in that it comprises: one or more processors; and a memory; wherein the processor or processors are configured to execute in accordance with any of claims 26 to 28.

40. A video encoding apparatus, characterized in that it comprises: one or more processors; and a memory; wherein the processor or processors are configured to execute in accordance with any of claims 29-33.

41. A video encoding apparatus, characterized in that it comprises: one or more processors; and a memory; wherein the processor or processors are configured to execute in accordance with any of claims 35 to 37.

Images