Plasma-processing device and plasma-processing method

Abstract

In order to provide a plasma-processing method capable of suppressing the adhesion of charged foreign matter to a sample in plasma etching processing and thereby reducing the amount of foreign matter, the present invention provides a plasma-processing method comprising: providing a plasma-processing chamber for processing a sample using plasma, a high-frequency power supply for supplying high-frequency power for generating the plasma, an electrostatic adsorption electrode for applying a voltage to the sample and electrically adsorbing and securing the sample in place, and a DC power supply for applying a voltage to the electrostatic adsorption electrode; an ignition step for generating plasma using the high-frequency power supply for the sample placed on the electrostatic adsorption electrode; a plasma discharge step for etching the sample after the ignition step; and a static elimination step for canceling the adsorption fixing by static elimination after the plasma discharge step, wherein, for the sample, during the period from the ignition step to the static elimination step, the voltage applied to the electrostatic adsorption electrode is greater than

Description

[Technical Field]

[0001] This invention relates to semiconductor device manufacturing technology, and in particular to a plasma processing apparatus and plasma processing method suitable for suppressing foreign matter adhesion in plasma etching processes. [Previous Technology]

[0002] In recent years, semiconductor device development, exemplified by roadmaps such as IRDS (International Roadmap for Devices and Systems), has continued to advance towards miniaturization and high integration of circuits. Within this trend, semiconductor manufacturing devices face increasingly higher requirements for both processing precision and mass production capabilities. Suppressing foreign matter adhesion to the sample substrate (wafer) is also a key requirement. With the shrinking pitch of semiconductor devices, small-diameter foreign matter, previously overlooked, has become a significant factor contributing to processing defects. Specifically, it is projected that by 2025, non-electro-active particles with a diameter ≥7nm will become critical particles, making measures to suppress such foreign matter adhesion to the wafer crucial in the future.

[0003] The aforementioned foreign matter problem is particularly important in plasma etching, which is used in the etching process of semiconductor manufacturing samples. In plasma etching, after the wafer is placed on a sample stage inside the processing chamber, electrostatic adsorption is performed to suppress wafer displacement, and then the wafer is exposed to plasma. At this time, by adjusting various processing conditions such as the type of gas introduced into the processing chamber or the high-frequency power applied to the wafer, specific laminated films on the wafer are selectively removed, forming fine circuit patterns on the wafer. When foreign matter adheres to the wafer in the aforementioned plasma process, there is a possibility of fatal defects for semiconductor devices due to broken wires or short circuits, therefore, there is a demand to achieve low foreign matter content to improve yield.

[0004] In view of the above situation, technologies have been proposed to suppress the adhesion of charged foreign matter easily generated in plasma processing equipment to the wafer surface. For example, in Patent Document 1, a method is proposed to suppress the attraction of charged foreign matter to the wafer by adjusting the voltage applied to the wafer from the electrostatic adsorption electrode to a constant value during the electrostatic adsorption of the wafer, so that the surface potential of the wafer is close to ±0V. However, with the aforementioned electrostatic adsorption method, since the floating charge flows into the wafer during the etching process, the wafer becomes negatively charged. After the interruption of plasma discharge, there may be cases where the charged state is not returned to ±0V. Charged foreign matter in the sample chamber may be attracted to the wafer by the aforementioned wafer charge, which may deteriorate the yield. Therefore, it is desirable to eliminate the negative charge on the wafer. During plasma etching, as a method for suppressing the negative charge on the wafer, the method described in Patent Document 2 has been proposed.

[0005] In Patent Document 2, because mobile charges flow into the wafer during plasma processing, the surface potential of the wafer changes to a negative direction. After the aforementioned plasma processing is completed, the surface potential of the wafer tends not to return to the ±0V state before the start of the aforementioned processing. To address this, in the wafer plasma discharge processing step, a technique is proposed that, in a manner that makes the applied voltage to the wafer move a first amount in the negative direction, in a way that is the same as the amount of wafer potential change caused by the inflow of mobile charges, and after the aforementioned plasma discharge processing is completed, the DC voltage that has moved the first amount in the negative direction is moved a second amount in the positive direction, thereby eliminating the charge on the wafer caused by mobile charges. Previous Art Documents Patent Documents

[0006] Patent Document 1: International Publication No. 2009 / 013803; Patent Document 2: Japanese Patent Application Publication No. 2016-213358 [Summary of the Invention]

[0007] (The problem that the invention aims to solve)

[0008] In Patent Document 1, although the applied voltage for electrostatic adsorption of the wafer is changed during the plasma etching process, this control method does not consider the current generated within the wafer due to rapid changes in the applied voltage. During the plasma etching process, due to rapid changes in the current within the wafer, there is a possibility that the plasma generation state is unstable. If the plasma state is unstable, it will lead to abnormal discharge, which may cause foreign matter to be generated. Therefore, it is undesirable to drastically change parameters such as the applied voltage.

[0009] Furthermore, although the technology described in Patent Document 2 can eliminate the charge on the wafer caused by floating charges, the inventors have found through research that the effect of suppressing the adhesion of foreign matter is not sufficient.

[0010] The purpose of this invention is to maintain a stable plasma generation state while suppressing the adhesion of charged foreign matter to the wafer, and to provide a plasma processing apparatus and method that can reduce the adhesion of foreign matter to the wafer. (Means for solving the problem)

[0011] The plasma treatment apparatus of the present invention comprises: a treatment chamber for plasma treatment of a sample using plasma; a high-frequency power supply for supplying high-frequency power for generating the plasma; a sample stage having electrodes on which a voltage is applied to cause the sample to electrostatically attract, and on which the sample is placed; a DC power supply for applying the voltage to the electrodes; and a control device for controlling the DC power supply such that a positive voltage is applied to the electrodes from the ignition of the plasma until the sample is removed from the sample stage. [Effects of the Invention]

[0012] To maintain a stable plasma generation state while suppressing the adsorption of charged foreign objects onto the wafer, a plasma processing apparatus and plasma processing method are provided that can reduce the adhesion of foreign objects to the wafer.

Implementation Method

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, these are merely embodiments and are not intended to limit the scope of the patent application to these embodiments. Embodiment 1

[0015] A first embodiment of the present invention will be described with reference to Figures 1 to 4. Initially, a plasma treatment apparatus for implementing the present invention will be described with reference to Figure 1. Figure 1 is a schematic diagram showing the configuration of the plasma treatment apparatus of the present invention.

[0016] In the plasma processing apparatus used in this embodiment, the semiconductor substrate, i.e. the wafer 1, which becomes the sample, is moved from the wafer transport gate 2 into the processing chamber 3 of the vacuum processing chamber and placed on the sample stage 4 for wafer placement.

[0017] This plasma processing apparatus, as a mechanism for generating plasma, includes: a solenoid coil 5, a high-frequency power supply 6 for generating μ waves, a μ wave oscillation source 7, a resonant section 8, and a gas supply section 9. Within the processing apparatus, a magnetic field is generated by the solenoid coil 5. Furthermore, the μ waves generated by the μ wave oscillation source 7 using high-frequency power from the high-frequency power supply 6 are introduced into the processing chamber 3 via the resonant section 8. The μ waves impart energy to electrons within the magnetic field generated by the solenoid coil 5. These electrons ionize the gas supplied from the gas supply section 9, thereby generating plasma.

[0018] During the plasma processing described above, a cooling gas for temperature control of the wafer 1 is supplied to the back side of the wafer 1. To prevent the wafer 1 from shifting due to the cooling gas, the wafer 1 is adsorbed onto the sample stage 4 by bipolar electrostatic adsorption electrodes 10 and 11 with different polarities. The electrostatic adsorption electrodes 10 and 11 are concentric, with one electrode 10 disposed on the inner side and the other electrode 11 disposed on the outer side.

[0019] The electrostatic adsorption electrodes (hereinafter also referred to as ESC) 10 and 11 are respectively connected to DC power supplies 12 and 13 with independent power sources. The inner electrostatic adsorption electrode 10 is connected to the DC power supply 12, and the outer electrostatic adsorption electrode 11 is connected to the DC power supply 13.

[0020] The electrostatic adsorption electrode and the wafer are insulated from each other. However, if a positive voltage is applied to the electrostatic adsorption electrode, a negative charge is generated on the back side of the wafer near the electrode, and the wafer will be adsorbed onto the electrode by Coulomb force. When a negative voltage is applied, a positive charge is generated on the back side of the wafer.

[0021] When a negative charge is generated on the back side of the wafer, a positive charge is generated on the wafer surface opposite to the back side, and the overall potential of the wafer becomes zero. Conversely, when a positive charge is generated on the back side of the wafer, a negative charge is generated on the wafer surface opposite to the back side.

[0022] Electrostatic adsorption electrodes 10 and 11 are supplied with opposite polarity voltages from DC power supplies. For example, the inner electrostatic adsorption electrode 10 is supplied with a voltage of +800V from DC power supply 12, and the outer electrostatic adsorption electrode 11 is supplied with a voltage of -200V from DC power supply 13.

[0023] During their review, the inventors discovered that if a voltage is applied to the electrostatic adsorption electrode when the sum of the voltages applied to the electrostatic adsorption electrode (in the above case, (+800V) + (-200V) = (+600V). Hereinafter, this voltage is defined as the sum of the applied voltages) is positive, then foreign matter adhesion to the wafer surface can be suppressed. The reason is that a positive charge proportional to +800V is generated on the wafer surface facing the inner electrostatic adsorption electrode 10, and a negative charge proportional to -200V is generated on the wafer surface facing the outer electrostatic adsorption electrode 11. Therefore, on average, a positive charge is generated on the wafer surface, and foreign matter with a higher proportion of positive charges will move away from the wafer surface due to Coulomb forces. The experimental results conducted by the inventors are described below.

[0024] This plasma processing apparatus includes a control device 14 for controlling the output values ​​of the aforementioned DC power supplies 12 and 13. The variable DC voltages 12 and 13 are connected to the control device 14, which controls the output voltage values. Furthermore, the control device 14 is also connected to the high-frequency power supply 6 for μ-wave generation, controlling the power output value from the high-frequency power supply 7 and the timing of output switching.

[0025] Here, the plasma processing apparatus is configured as described above, using bipolar electrostatic adsorption electrodes and employing two different DC power supplies for electrostatic adsorption of the wafer. However, a unipolar electrostatic adsorption electrode with one electrode grounded can also be used. Using a unipolar adsorption electrode simplifies the apparatus configuration and reduces the design complexity and manufacturing cost of the plasma processing apparatus. Alternatively, a multipolar electrostatic adsorption electrode can be used, employing three or more DC power supplies for electrostatic adsorption of the wafer. Using a multipolar electrostatic adsorption electrode allows for localized control of the voltage applied to the wafer, thus adjusting the plasma distribution.

[0026] Figure 2 is a time diagram of the processing of Embodiment 1 of the present invention. The content of the present invention will be explained using the time diagram. In the plasma processing process shown in Figure 2, it is composed of three steps: an ignition step performed between t2-1 and t2-3, a plasma discharge step performed between t2-3 and t2-4, and a de-energization step performed between t2-4 and t2-6. Furthermore, in Figure 2, "μ-wave incident power" is high-frequency power from a high-frequency power source located at the top of the processing chamber, "ESC voltage (+)" is a positive voltage output from DC power source 12, and "ESC voltage (-)" is a negative voltage output from DC power source 13.

[0027] In this embodiment, before the timing t2-1 shown in Figure 2, the wafer 1 is first moved into the processing chamber 3 and placed on the sample stage 4. Then, at the timing t2-1, positive and negative voltages are simultaneously output from DC power supplies 12 and 13 to the electrostatic adsorption electrodes 10 and 11, respectively, so that the wafer 1 is adsorbed onto the sample stage 4.

[0028] Here, the inventors have discovered that if the actual applied voltage to the electrostatic adsorption electrode is +1V or higher, foreign matter can be reduced. From the viewpoint of maintaining the electrostatic adsorption force of the wafer, it is preferable that the potential difference between the electrodes be set to 1000V or higher to stabilize the adsorption of the wafer. In this embodiment, the ESC voltage (+) is set to +800V and the ESC voltage (-) is set to -200V, that is, the actual applied voltage is set to +600V. Next, at the start of the ignition step at t2-2, 1000W of power is supplied from the high-frequency power supply 6, and current flows through the solenoid coil 5, thereby generating plasma in the processing chamber 3. Furthermore, to prevent failure to ignite the plasma, the supplied power is set to be higher than the power used in a typical plasma etching process. Then, at t2-3, the power supplied from the high-frequency power supply is changed to 800W, and the plasma discharge step begins.

[0029] Next, at the start of the de-energization step at t2-4, the power supplied from the high-frequency power source is changed to 450W, and the plasma discharge output is reduced in stages. Then, at t2-5, the voltage supplied from the DC power source to the electrostatic adsorption electrode is changed to 0V, and electrostatic adsorption stops. Finally, by changing the power supplied from the high-frequency power source to 0W at t2-6, the de-energization step ends (this may also be manifested as a de-adsorption step).

[0030] Regarding the aforementioned Example 1, the plasma treatment process of Conventional Example 1, used for comparison of the level of foreign matter reduction effect, will be described here. Figure 3 shows a time diagram of the conventional treatment corresponding to Conventional Example 1. Conventional Example 1 is a plasma treatment process in which the voltage values ​​of ESC voltage (+) and ESC voltage (-) are set to +500V and -500V respectively during the period from t3-1 to t3-6, and the actual applied voltage during electrostatic adsorption is changed to ±0V.

[0031] An evaluation experiment was conducted on the number of foreign matter deposits on the wafer after plasma etching, based on Example 1 and the previous Example 1 described above. In the experiment, the pressure inside the processing chamber 3 was set to 0.5 Pa, and a mixed gas of Ar and O2 was continuously supplied to the chamber from the start of the ignition step until the end of the de-electrolysis step. Furthermore, the flow rate of Ar was set to 100 mL / min, and the flow rate of O2 was set to 30 mL / min. Also, the temperature of the sample stage 4 was set to 50°C, and He was used as the back gas for wafer cooling, maintaining the gas supply to keep the pressure on the back side at 2 kPa.

[0032] In this experiment, the plasma etching process described above was performed more than 30 times under each condition. After totaling the number of foreign matter attachments to the wafer under each condition, the median value of the number of foreign matter attachments under each condition was used for comparison. In addition, in this experiment, the particle size of the foreign matter was set to be 0.025 μm or larger.

[0033] Figure 4 shows the investigation results regarding the reduction effect of foreign matter adhesion to the wafer in Example 1. Furthermore, the vertical axis of Figure 4 represents the converted value of the foreign matter adhesion number when the foreign matter adhesion number of the conventional Example 1 is normalized to 100%. In order to show the correlation between the applied voltage to the wafer and the foreign matter adhesion number, Figure 4 also shows the investigation results for cases where the ESC voltage (+) between t2-1 and t2-5 is set to +600V, the ESC voltage (-) is set to -400V (i.e., the actual applied voltage is +200V), and the ESC voltage (+) is set to +700V, the ESC voltage (-) is set to -300V (i.e., the actual applied voltage is +300V). As the results show, in the plasma processing of Example 1, where the total applied voltage for electrostatic adsorption is maintained at a positive value between t2-1 and t2-5, the foreign matter adhesion number decreases as the actual applied voltage increases. Furthermore, comparing Comparative Example 1 with an applied voltage of +600V, the number of foreign objects was reduced to less than half compared to the previous Example 1. Example 2

[0034] Figure 5 is a time diagram of the processing of Embodiment 2 of the present invention. The second embodiment of the present invention will be described with attention to the differences in configuration compared to Embodiment 1. In Figure 5, during the period t5-3 to t5-4, the total applied voltage to the electrostatic adsorption electrode is changed to 0V, which is a change from +600V used in the aforementioned Embodiment 1. Furthermore, the operating conditions for the period before t5-3 and after t5-4 in Figure 5 are the same as those for the period before t2-3 and after t2-4 in the plasma processing process of the aforementioned Embodiment 1 (Figure 2), therefore, the description is omitted.

[0035] As shown in FIG. 5, in this embodiment, at time t5-3, the voltage value for electrostatic adsorption is changed so that the actual applied voltage from DC power supplies 12 and 13 to the electrostatic adsorption electrodes becomes 0V. Furthermore, in this embodiment, to suppress the decrease in the electrostatic adsorption force of the wafer, the voltage values ​​of ESC voltage (+) and ESC voltage (-) are set to +600V and -600V respectively, maintaining the potential difference between the two electrodes at 1200V. By controlling the applied voltage in this way, the abrupt parameter changes that occur during the processing described in Patent Document 2 can be suppressed, and as a result, the variations in the etching process caused by changes in plasma distribution due to changes in wafer potential can be suppressed. Next, at time t5-4, the total value of the actual applied voltage to the electrostatic adsorption electrodes is changed back to a positive value, thereby suppressing the adhesion of charged foreign matter as described above.

[0036] Furthermore, in this embodiment, the total value of the actual applied voltage to the electrostatic adsorption electrode in the plasma discharge steps t5-3 to t5-4 is set to 0V. However, due to the inflow of floating charges during this period, there is a possibility that the plasma potential of the wafer may shift in the negative direction. In this regard, as a development example from Embodiment 2, it is also possible to set it so that only the aforementioned shift in plasma potential causes the actual applied voltage to the electrostatic adsorption electrode during the aforementioned period to shift to a negative value. FIG6 shows a processing time diagram of the development example of Embodiment 2 of the present invention. Hereinafter, the present development example will be described with attention to the differences in configuration from Embodiment 2.

[0037] In Figure 6, during the period from t6-3 to t6-4, the total value of the actual applied voltage to the electrostatic adsorption electrode is changed to a value of 0V or less, which is more different from the 0V value adopted in Example 2. Moreover, the operating conditions for the period before t6-3 and after t6-4 in Figure 6 are the same as the operating conditions for the period before t5-3 and after t5-4 in the plasma processing process (Figure 5) of Example 2, so the description is omitted.

[0038] As shown in Figure 6, in this development example, at time t6-3, the total value of the applied voltage from DC power supplies 12 and 13 to the electrostatic adsorption electrodes is changed to a value of 0V or less, in a manner equal to the amount of movement of the wafer in the negative direction of the plasma potential during plasma discharge. Furthermore, in order to suppress the decrease in the electrostatic adsorption force of the wafer, the applied voltage is set such that the potential difference between the two electrodes is 1000V or more. Therefore, by changing the applied voltage to the electrostatic adsorption electrodes, the fluctuation of the plasma potential of the wafer can be offset, the decrease in the wafer's adsorption force can be suppressed, and the occurrence of wafer positional displacement can be suppressed.

[0039] Furthermore, in this embodiment, the total value of the actual applied voltage to the electrostatic adsorption electrode during the de-energizing step from t5-4 to t5-6 is set to the same +600V as in Embodiment 1 shown in FIG. 2. However, the actual applied voltage during the period from t5-4 to t5-6 can also be set to the same value as the set value during the period from t5-3 to t5-4. In this case, the abrupt change in adsorption force caused by the change in the actual applied voltage between the plasma discharge step and the de-energizing step can be suppressed, and the occurrence of wafer position shift can be further suppressed.

[0040] An evaluation experiment was conducted on the number of foreign matter deposits on the wafer after plasma etching in Example 2 described above. Furthermore, the comparative conditions used for comparing the level of foreign matter deposits were those of Conventional Example 1. The experimental conditions involved setting the ESC voltage (+) and ESC voltage (-) to +600V and -600V respectively during the period from t3-1 to t3-6, and maintaining the potential difference between the two electrodes at 1200V. Other experimental conditions were the same as those in the evaluation experiment of Example 1 described above, and therefore, their description is omitted.

[0041] Figure 7 shows the investigation results regarding the reduction effect of foreign matter adhesion to the wafer in Example 2. Furthermore, the vertical axis of Figure 7 is the converted value of the foreign matter adhesion number when the foreign matter adhesion number of Conventional Example 1 is normalized to 100%. As the results show, compared to Conventional Example 1, the plasma processing process in Figure 5, which varies the total applied voltage applied to the electrostatic adsorption electrode between t5-3 and t5-4, can reduce the foreign matter number to approximately half. Furthermore, in this embodiment, it is useful to minimize the impact on plasma state changes compared to Example 1. Example 3

[0042] Figure 8 is a time diagram of the processing of Embodiment 3 of the present invention. The third embodiment of the present invention will be described with attention to the differences in configuration compared to Embodiments 1 and 2. In Figure 8, during the period t8-1 to t8-3, the total applied voltage to the electrostatic adsorption electrode is changed to 0V, which is a change from +600V used in the aforementioned Embodiment 2. Furthermore, the operation of each parameter after t8-3 in Figure 8 is the same as the operation of each parameter after t5-3 in the plasma processing process (Figure 5) of the aforementioned Embodiment 2, therefore, the description is omitted.

[0043] In this embodiment, as shown in FIG8, firstly, at time t8-1, the applied voltage is changed such that the applied voltage from DC power supplies 12 and 13 to the electrostatic adsorption electrodes becomes 0V. Furthermore, in this embodiment, to suppress the decrease in the electrostatic adsorption force of the wafer, the voltage values ​​of ESC voltage (+) and ESC voltage (-) are set to +600V and -600V respectively, maintaining the potential difference between the two electrodes at 1200V. Secondly, at the start of the plasma ignition step at t8-2, 1000W of power is supplied from the high-frequency power supply 6, and current flows through the solenoid coil 5, thereby generating plasma in the processing chamber. Next, at the start of the plasma discharge step at t8-3, the power supplied from the high-frequency power supply 6 is changed to 800W, and plasma etching is performed. By setting the supply voltage from DC power supplies 12 and 13 to a constant during the period t8-1 to t8-4, the rapid change in adsorption force due to the change in the applied voltage to the electrostatic adsorption electrode can be suppressed, and the occurrence of wafer position shift can be suppressed.

[0044] An evaluation experiment was conducted on the number of foreign matter deposits on the wafer after plasma etching in Example 3 described above. Furthermore, the comparison conditions used for comparing the level of foreign matter deposits were those of Conventional Example 1. Also, the experimental conditions were the same as those in the evaluation experiment of Example 2 described above, therefore, the description is omitted.

[0045] Figure 9 shows the investigation results regarding the reduction effect of foreign matter adhesion to the wafer in Example 3. Furthermore, the vertical axis of Figure 9 is the converted value of the foreign matter adhesion number when the foreign matter adhesion number of Conventional Example 1 is normalized to 100%. As the results show, by changing the actual applied voltage to the electrostatic adsorption electrode in the plasma processing process of Figure 8 between t8-1 and t8-3, compared with Conventional Example 1, the foreign matter number can be reduced to 60%. Furthermore, in Example 3, compared with Examples 1 and 2, it is superior in minimizing the impact on changes in plasma state and wafer adsorption force. Example 4

[0046] FIG10 is a time diagram of the processing of Embodiment 4 of the present invention. This embodiment will be described with attention to the differences in configuration compared to Embodiments 1-3. In FIG10, during the period t10-1 to t10-2, the timing of the start of the ignition step is changed to precede the electrostatic adsorption of the wafer, which is the opposite of the implementation sequence in Embodiment 1. Furthermore, the operation of each parameter after t10-2 in FIG10 is the same as the operation of each parameter after t2-2 in the plasma processing process (FIG. 2) of Embodiment 1 of the present invention, therefore, the description is omitted.

[0047] As shown in FIG10, in this embodiment, at time t10-1, the power supply from the high-frequency power source at time t2-2 of FIG2 is started, and the power supply is increased to 1000W. Then, at time t10-2, the supply of the applied voltage for electrostatic adsorption implemented at time t2-1 of FIG2 is started, and controlled so that the actual applied voltage from DC power sources 12 and 13 becomes +600V. By changing the timing of wafer adsorption in this plasma ignition step, plasma formation is implemented before the potential change of the wafer, thereby the plasma captures charged foreign objects that fly off from the back of the wafer at the start of the applied voltage supply, which can further suppress the adhesion of foreign objects to the wafer.

[0048] Regarding the aforementioned Example 4, the plasma treatment process of Conventional Example 2, used for comparison of the level of foreign matter reduction effect, will be described here. Figure 11 shows an embodiment for comparison with Example 4, which is a time diagram of the conventional treatment of Conventional Example 2. Conventional Example 2 is a plasma treatment process in which the voltage values ​​of ESC voltage (+) and ESC voltage (-) are set to +600V and -600V respectively during the period from t11-2 to t11-6, and the actual applied voltage to the electrostatic adsorption electrode is changed to 0V.

[0049] For Example 4 and the previous Example 2 described above, an evaluation experiment was conducted on the number of foreign matter deposits on the wafer after plasma etching. Furthermore, the experimental conditions were the same as those for the evaluation experiments in Examples 1-3 described above, therefore, the description is omitted.

[0050] Figure 12 shows the investigation results regarding the reduction effect of foreign matter adhesion to the wafer in Example 4. Furthermore, the vertical axis of Figure 12 is the converted value of the foreign matter adhesion number when the foreign matter adhesion number of Conventional Example 2 is normalized to 100%. As the results show, the plasma processing process of Figure 10, which varies the timing of plasma formation between t10-1 and t10-2, can reduce the number of foreign matter compared to Conventional Example 2 (0V).

[0051] As described in the above embodiments, it can be seen that in the plasma processing of the present invention, by changing the actual voltage applied to the electrostatic adsorption electrode to the positive direction and maintaining the control parameters of the wafer at a constant level in the plasma etching process, the adhesion of foreign matter to the wafer can be greatly reduced.

[0052] Furthermore, in either or only one of the aforementioned ignition step and de-energization step, by changing the applied voltage to the electrostatic adsorption electrode to the positive direction and setting the applied voltage to the electrostatic adsorption electrode in other steps to 0V, it is possible to achieve both suppression of foreign matter adhesion and improvement of wafer adsorption stability.

[0053] Furthermore, by changing the start time of electrostatic adsorption on the wafer from before the ignition step to during the ignition step, the adhesion of foreign matter that flies up due to the rapid potential change of the wafer can be reduced. As a result of the combined effect of these effects, the present invention can prevent foreign matter from adhering to the wafer, thereby improving the yield rate of device manufacturing.

[0054] The present invention is established by means of the movement of the electrostatic adsorption electrode relative to the wafer in the positive direction of the applied voltage and the maintenance of a certain value of the control parameters in the plasma discharge step, which are specified as any one of Figures 2, 5, 6, 8, 10, thereby suppressing the adhesion of foreign matter.

[0055] Furthermore, the present invention is not limited to the embodiments described above, and may include various modifications. For example, the embodiments described above are detailed for ease of understanding of the present invention and are not limited to having all the described components. Also, a part of the configuration of one embodiment may be replaced with the configuration of another embodiment, and the configuration of another embodiment may be added to the configuration of one embodiment. Also, other additions, deletions, and substitutions may be made to a part of the configuration of each embodiment. For example, in embodiments 1 to 4 described above, the ignition step is performed initially, but the present invention is also applicable to plasma processing processes in which the ignition step is removed from each embodiment.

[0056] Furthermore, the aforementioned processing configurations can also be implemented in hardware, for example, through integrated circuit design. Additionally, the aforementioned processing configurations can also be implemented in software by means of a program that is interpreted and executed by a processor. The information such as programs, forms, and files that implement the various functions can be stored in recording devices such as memory, hard drives, SSDs (Solid State Drives), or recording media such as IC cards, SD cards, and DVDs.

[0057] Furthermore, control lines are those deemed necessary in the description, but not all work-in-process require control lines. In fact, almost all components can be considered interconnected. [Simplified Explanation of the Diagram]

[0013] [Fig. 1] is a schematic diagram showing the configuration of the plasma processing apparatus of the present invention. [Fig. 2] is a processing time diagram of Embodiment 1 of the present invention. [Fig. 3] is a processing time diagram of Conventional Example 1. [Fig. 4] is the investigation result regarding the reduction effect of foreign matter adhesion to the wafer in Embodiment 1. [Fig. 5] is a processing time diagram of Embodiment 2 of the present invention. [Fig. 6] is a processing time diagram of a development example of Embodiment 2 of the present invention. [Fig. 7] is the investigation result regarding the reduction effect of foreign matter adhesion to the wafer in Embodiment 2. [Fig. 8] is a processing time diagram of Embodiment 3 of the present invention. [Fig. 9] is the investigation result regarding foreign matter adhesion to the wafer in Embodiment 3. [Fig. 10] is a processing time diagram of Embodiment 4 of the present invention. [Fig. 11] is a processing time diagram of Conventional Example 2. [Fig. 12] is the investigation result regarding the reduction effect of foreign matter adhesion to the wafer in Embodiment 4.

Claims

1. A plasma treatment apparatus, characterized by comprising: a treatment chamber for plasma treatment of a sample using plasma; a high-frequency power supply for supplying high-frequency power to generate the plasma; a sample stage having electrodes on which a voltage is applied to cause the sample to electrostatically attract, and on which the sample is placed; a DC power supply for applying the voltage to the electrodes; and a control device for controlling the DC power supply such that a positive voltage is applied to the electrodes from the ignition of the plasma until the sample is removed from the sample stage.

2. The plasma processing apparatus as described in claim 1, wherein, The aforementioned electrode comprises: a first electrode to which a first voltage is applied to cause the aforementioned sample to be electrostatically adsorbed; and a second electrode to which a second voltage is applied to cause the aforementioned sample to be electrostatically adsorbed, wherein the sum of the aforementioned first voltage and the aforementioned second voltage during the aforementioned plasma treatment is positive.

3. The plasma processing apparatus as described in claim 1, wherein, The aforementioned voltage is approximately the same value from the ignition of the aforementioned plasma to the separation of the aforementioned sample from the aforementioned sample stage.

4. A plasma treatment apparatus, characterized by comprising: a treatment chamber for treating a sample using plasma; a high-frequency power supply for supplying high-frequency power to generate the plasma; a sample stage having electrodes on which a voltage is applied to cause the sample to be electrostatically attracted, and on which the sample is placed; a DC power supply for applying the voltage to the electrodes; and a control device for controlling the DC power supply such that a positive voltage is applied to the electrodes during a treatment period for igniting the plasma or during a treatment period for removing the sample from the sample stage.

5. The plasma processing apparatus as described in claim 4, wherein, During the aforementioned plasma treatment, the aforementioned voltage is below 0V, and the magnitude of the aforementioned voltage during the aforementioned plasma treatment is equal to the shift in plasma potential during the aforementioned plasma treatment.

6. The plasma processing apparatus as described in any one of claims 1 to 5, wherein, The voltage prior to the ignition of the plasma was a positive value.

7. The plasma processing apparatus as described in claim 1, claim 2 or claim 4, wherein, After the aforementioned plasma is ignited, and before the aforementioned plasma treatment begins, the aforementioned voltage is a positive value.

8. A plasma treatment method, wherein a sample placed on a sample stage having electrodes is plasma-treated by means of plasma, the electrodes being subjected to a voltage for electrostatic attraction of the sample, characterized in that: from the ignition of the plasma to the removal of the sample from the sample stage, a step of applying a positive voltage to the electrodes is included.

9. The plasma treatment method as described in claim 8, wherein, The aforementioned electrode comprises: a first electrode to which a first voltage is applied to cause the aforementioned sample to be electrostatically adsorbed; and a second electrode to which a second voltage is applied to cause the aforementioned sample to be electrostatically adsorbed, wherein the sum of the aforementioned first voltage and the aforementioned second voltage during the aforementioned plasma treatment is positive.

10. A plasma treatment method for plasma treating a sample placed on a sample stage equipped with electrodes, wherein a voltage is applied to the electrodes to electrostatically attract the sample, characterized in that: during the process of igniting the plasma or during the process of removing the sample from the sample stage, a step of applying a positive voltage to the electrodes is included.

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