Ferroelectric field-effect transistor and a method for forming the same

Abstract

A ferroelectric field-effect transistor is described in an embodiment. The ferroelectric field-effect transistor comprising: (i) a bottom gate electrode formed on a substrate; (ii) a ferroelectric layer formed on the bottom gate electrode, the ferroelectric layer capable of exhibiting different polarization states in response to an applied electric field provided by a bottom gate voltage at the bottom gate electrode; (iii) a floating gate electrode formed on the ferroelectric layer, the floating gate electrode capable of exhibiting different charge states in response to electric charges injected or removed from the ferroelectric layer and a polarization state of the ferroelectric layer; (iv) an insulating layer formed on the floating gate electrode; (v) a semiconductor layer formed on the insulating layer; and (vi) a source electrode and a drain electrode formed in electrical connection to the semiconductor layer to allow an electric current to pass through the semiconductor layer. The bottom gate electrode is adapted to control the polarization state of the ferroelectric layer and to inject or remove the electric charges from the ferroelectric layer via the bottom gate voltage for changing a charge state of the floating gate electrode to alter a resistance state of the semiconductor layer for use in memory applications A method for forming the ferroelectric field-effect transistor is also described.

Description

[0001] Ferroelectric field-effect transistor and a method for forming the same

[0002] Technical Field

[0003] The present disclosure relates to a ferroelectric field-effect transistor and a method for forming the ferroelectric field-effect transistor.

[0004] Background

[0005] Rapid progress of Internet-of- Things (loT) and artificial intelligence (Al) demand advanced memory technologies with high-density integration as replacements for the von Neumann architecture. Concurrently, complementary metal-oxide-semiconductor (CMOS) technology is approaching its fundamental limit for downscaling. To satisfy the demands of emerging applications, particularly for loT and Al related applications, technologies in relation to CMOS-based memory with new functionalities beyond their conventional utility as data storage are developed.

[0006] Various attempts have been made to improve a functionality of a CMOS-based memory device. For example, a one-transistor one-capacitor ferroelectric randomaccess memory array (1T1C FeRAM) based on ferroelectric hafnium zirconium oxide (HZO) was used to achieve a memory window of about 0.41 V. Other HZO-based ferroelectric field-effect transistors (FeFETs) were also investigated which showed memory windows of about 0.22 V and 1.0 V. In one example, an additional chargetrapping layer was used in a FeFET device architecture to improve charge retention for memory functionality. However, despite all these attempts, the memory windows achieved in these devices were small (e.g. within about 1 V) and there remains reliability concerns due to detrimental charge-trapping effect through channel injection or a reading scheme of these devices.

[0007] It is therefore desirable to provide a ferroelectric field-effect transistor and a method for forming the ferroelectric field-effect transistor which address the aforementioned problems and / or provide a useful alternative. Further, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure. Summary

[0008] Aspects of the present application relate to a ferroelectric field-effect transistor and a method for forming the ferroelectric field-effect transistor.

[0009] In accordance with a first aspect, there is provided a ferroelectric field-effect transistor comprising: a bottom gate electrode formed on a substrate; a ferroelectric layer formed on the bottom gate electrode, the ferroelectric layer capable of exhibiting different polarization states in response to an applied electric field provided by a bottom gate voltage at the bottom gate electrode; a floating gate electrode formed on the ferroelectric layer, the floating gate electrode capable of exhibiting different charge states in response to electric charges injected or removed from the ferroelectric layer and a polarization state of the ferroelectric layer; an insulating layer formed on the floating gate electrode; a semiconductor layer formed on the insulating layer; and a source electrode and a drain electrode formed in electrical connection to the semiconductor layer to allow an electric current to pass through the semiconductor layer, wherein the bottom gate electrode is adapted to control the polarization state of the ferroelectric layer and to inject or remove the electric charges from the ferroelectric layer via the bottom gate voltage for changing a charge state of the floating gate electrode to alter a resistance state of the semiconductor layer for use in memory applications.

[0010] By having the architecture of the aforementioned ferroelectric field-effect transistor (FeFET) which decouples the ferroelectric layer and the insulating layer through the arrangement of the bottom gate electrode and the floating gate electrode, effective areas of the ferroelectric layer and the insulating layer can be tuned. The tunable effective areas of the ferroelectric layer and the insulating layer together with the floating gate electrode are adapted to suppress the fundamental memory window limit and to minimize a depolarization field attributed by a charge mismatch between the ferroelectric layer and the insulating layer. This enables the FeFET of the present disclosure to achieve long retention, small cycle-to-cycle variation, and energy efficient switching as a memory device. Further, the present FeFET architecture can be adapted to provide an improved interface between the semiconductor layer and the insulating layer to mitigate a charge trapping effect at the interface to enhance cycling endurance of the FeFET. With the above improved device characteristics, the aforementioned FeFET architecture can be used in high bit density memory cells and in-memory computing schemes for data storage and computing.

[0011] The bottom gate electrode may be formed asymmetrically with respect to the floating gate electrode and may be formed at one side of the floating gate electrode.

[0012] An area ratio between the insulating layer and the ferroelectric layer may be adapted to tune the bottom gate voltage required for altering the resistance state of the semiconductor layer, and the area ratio may be in the range of 0.1 to 50.

[0013] In accordance with a second aspect, there is provided a method for forming a ferroelectric field-effect transistor. The method comprising: (i) forming a bottom gate electrode on a substrate; (ii) forming a ferroelectric layer on the bottom gate electrode, the ferroelectric layer capable of exhibiting different polarization states in response to an applied electric field provided by a bottom gate voltage at the bottom gate electrode; (Hi) forming a floating gate electrode on the ferroelectric layer, the floating gate electrode capable of exhibiting different charge states in response to electric charges injected or removed from the ferroelectric layer and a polarization state of the ferroelectric layer; (iv) forming an insulating layer on the floating gate electrode; (v) forming a semiconductor layer on the insulating layer; and (vi) forming a source electrode and a drain electrode in electrical connection with the semiconductor layer to allow an electric current to pass through the semiconductor layer, wherein the bottom gate electrode is adapted to control the polarization state of the ferroelectric layer and to inject or remove the electric charges from the ferroelectric layer via the bottom gate voltage for changing a charge state of the floating gate electrode to alter a resistance state of the semiconductor layer for use in memory applications.

[0014] The semiconductor layer may comprise a two-dimensional (2D) semiconductor. Use of a 2D semiconductor as a channel material for the semiconductor layer enables scaling down of a thickness of the semiconductor layer to sub-nanometer scale without sacrificing critical features, e g., carrier mobility, as compared to conventional bulk semiconductors. This allows ultra-scale, high-density, and high-performance memory to be achieved. Further, stackability and crystallinity of 2D semiconductors can be used to achieve heterogeneous integration in a vertical direction without increasing depolarization field and interface trapping as compared to conventional bulk semiconductors. 2D semiconductors also provide better retention characteristics as compared to conventional bulk semiconductors.

[0015] The ferroelectric layer may comprise a polycrystalline hafnium-zirconium oxide.

[0016] A capacitance ratio between the insulating layer and the ferroelectric layer may be in the range of 0.1 to 50.

[0017] Wherein forming the bottom gate electrode on the substrate may include forming the bottom gate asymmetrically with respect to the floating gate electrode and at one side of the floating gate electrode.

[0018] The method may comprise forming the insulating layer and the ferroelectric layer with an area ratio in the range of 0.1 to 50 for tuning the bottom gate voltage required for altering the resistance state of the semiconductor layer.

[0019] The method may comprise annealing the ferroelectric layer after forming the floating gate electrode on the ferroelectric layer.

[0020] It should be appreciated that features relating to one aspect may be applicable to the other aspects. Embodiments provide a ferroelectric field-effect transistor and a method for forming the ferroelectric field-effect transistor. Particularly, by having the architecture of the aforementioned ferroelectric field-effect transistor (FeFET) which decouples the ferroelectric layer and the insulating layer through the arrangement of the bottom gate electrode and the floating gate electrode, effective areas of the ferroelectric layer and the insulating layer can be tuned. The tunable effective areas of the ferroelectric layer and the insulating layer together with the floating gate electrode are adapted to suppress the fundamental memory window limit and to minimize a depolarization field attributed by a charge mismatch between the ferroelectric layer and the insulating layer. This enables the FeFET of the present disclosure to achieve long retention, small cycle-to-cycle variation, and energy efficient switching as a memory device. Further, the present FeFET architecture can be adapted to provide an improved interface between the semiconductor layer and the insulating layer to mitigate a charge trapping effect at the interface to enhance cycling endurance. With the above improved device characteristics, the aforementioned FeFET architecture can be used in high bit density memory cells and in-memory computing schemes for data storage and computing. In embodiments where the semiconductor layer comprises a two-dimensional (2D) semiconductor, use of the 2D semiconductor as a channel material enables scaling down of a thickness of the semiconductor layer to sub-nanometer scale without sacrificing critical features, e g., carrier mobility, as compared to conventional bulk semiconductors. This allows ultra-scale, high-density, and high-performance memory to be achieved. Further, stackability and crystallinity of 2D semiconductors can be used to achieve heterogeneous integration in a vertical direction without increasing depolarization field and interface trapping as compared to conventional bulk semiconductors. 2D semiconductors also provide better retention characteristics as compared to conventional bulk semiconductors.

[0021] Brief description of the drawings

[0022] Embodiments will now be described, by way of example only, with reference to the following drawings, in which:

[0023] Figure 1 is a schematic diagram showing a cross-section of a ferroelectric field-effect transistor in accordance with an embodiment;

[0024] Figure 2 is a flowchart of a method for forming the ferroelectric field-effect transistor of Figure 1 in accordance with an embodiment;

[0025] Figure 3 shows a plot of memory window ratio versus on-off ratio read at a gate voltage of 0 V to benchmark a plurality of ferroelectric field-effect transistors (FeFET) having different architectures in accordance with an embodiment;

[0026] Figure 4 shows a graph of drain current versus gate voltage for the ferroelectric fieldeffect transistor of Figure 1 in accordance with an embodiment;

[0027] Figure 5 shows a graph of memory window versus an area ratio between the insulating layer and the ferroelectric layer using the device architecture of the ferroelectric fieldeffect transistor (FeFET) of Figure 1 in accordance with an embodiment;

[0028] Figure 6 shows a graph of drain current versus pulse width for the ferroelectric fieldeffect transistor of Figure 1 in accordance with an embodiment;

[0029] Figure 7 shows a graph of memory window versus (VstoP-start) of the gate voltage for the ferroelectric field-effect transistor of Figure 1 in accordance with an embodiment; Figure 8 shows an energy band diagram in the z-direction across a material layer stack of the ferroelectric field-effect transistor of Figure 1 in accordance with an embodiment;

[0030] Figure 9 shows a graph of drain current versus retention time for the ferroelectric fieldeffect transistor of Figure 1 in accordance with an embodiment;

[0031] Figure 10 shows a graph of conductance versus pulse number for the ferroelectric field-effect transistor of Figure 1 to illustrate long-term potentiation (LTP) and long-term depression (LTD) of synaptic plasticity in accordance with an embodiment; and

[0032] Figure 11 is a graph of conductance versus cycle number for the ferroelectric fieldeffect transistor of Figure 1 to illustrate reproducibility of the synaptic behavior generated in the ferroelectric field-effect transistor in accordance with an embodiment.

[0033] Detailed description

[0034] Exemplary embodiments relate to a ferroelectric field-effect transistor and a method for forming the ferroelectric field-effect transistor.

[0035] Figure 1 is a schematic diagram showing a cross-section of a ferroelectric field-effect transistor (FeFET) 100 in accordance with an embodiment.

[0036] As shown in Figure 1 , the FeFET 100 comprises a bottom gate electrode 102 formed on a substrate 104. In the present embodiment, the substrate 104 includes a 250 pm thick silicon dioxide (SIC>2) layer 106 formed on a 300 pm thick silicon substrate layer 108. It should be appreciated that other suitable substrate or substrate layers with varying thicknesses or sizes can be used. The bottom gate electrode 102 may include a metal such as titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt) or tungsten (W), and is electrically connected to an external voltage source (not shown) which provides a bottom gate voltage to the bottom gate electrode 102. In the present embodiment, a 30 nm thick tungsten layer is used as the bottom gate electrode 102. The FeFET 100 further comprises a ferroelectric layer 110 formed on the bottom gate electrode 102. The ferroelectric layer 110 is capable of exhibiting different polarization states in response to an applied electric field provided by the bottom gate electrode 102 via an application of the bottom gate voltage. In the present embodiment, the ferroelectric layer 110 comprises a polycrystalline hafnium-zirconium oxide (Hfo 5Zro5O2) layer. The Hfo5Zro5O2 layer is 20 nm thick in the present embodiment although other thicknesses may be used. A floating gate electrode 112 is formed on the ferroelectric layer 110. The floating gate electrode 112 is not electrically connected to any external terminals. The floating gate electrode 112 is capable of exhibiting different charge states in response to electric charges injected or removed from the ferroelectric layer 110 and a polarization state of the ferroelectric layer 110. The floating gate electrode 112 includes a metal which may be the same as or different from the bottom gate electrode 102. The floating gate electrode 112 may include titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt) or tungsten (W). In the present embodiment, a 30 nm thick tungsten layer is used to form the floating gate electrode 112. An insulating layer 114 is formed on the floating gate electrode 112. In the present embodiment, the insulating layer 114 includes a high-k (i.e. a high dielectric constant) dielectric or insulator. This may include hafnium oxide HfC>2, aluminum oxide (AI2O3) and zirconium oxide (ZrO2). In the present embodiment, a 6 nm thick hafnium oxide HfC>2 or aluminum oxide (AI2O3) can be used as the high-k dielectric for the insulating layer 114. A semiconductor layer 116 is formed on the insulating layer 114 which forms a channel of the FeFET 100. In the present embodiment, the semiconductor layer 116 includes a two-dimensional (2D) material layer comprising molybdenum disulfide (M0S2). The semiconductor layer 116 may have a thickness in a range of 3 nm to 10 nm. In the present embodiment, a M0S2 layer of less than 5 nm is used as the semiconductor layer 116. A source electrode 118 and a drain electrode 120 are formed in electrical contact with the semiconductor layer 116 to allow an electric current to pass through the semiconductor layer 116. In the present embodiment, the source electrode 118 is electrically connected to ground 122 and the drain electrode 120 is electrically connected to a voltage supply 124. The source electrode 118 and the drain electrode 120 in the present embodiment include a 20 nm thick nickel (Ni) layer but other materials, for example titanium / gold (Ti / Au), of varying thicknesses can be used. In the present embodiment, the Ni source and drain electrode 118, 120 each has a length (a dimension in the x-direction) of 1 pm. The width (a dimension in the y-direction) may be varied depending on a specific application of the FeFET 100. The x- and z- axes 126 for use in referencing an orientation of the FeFET 100 are also shown in Figure 1. It should be appreciated that an area of the substrate 104 or the various layers of the FeFET 100 can be determined based on a targeted application, performance of the FeFET and / or a device density on the substrate. The bottom gate electrode 102 of the FeFET 100 is adapted to control the polarization state of the ferroelectric layer 110 and to inject or remove the electric charges from the ferroelectric layer 110 via the bottom gate voltage to change a charge state of the floating gate electrode 112. In this way, a resistance state of the semiconductor layer 116 can be altered and this can be used as a parameter for memory applications of the FeFET 100. In the present embodiment, the bottom gate electrode 102 is formed asymmetrically with respect to the floating gate electrode 112 (e.g. asymmetric with respect to a y-z plane) and is formed at one side of the floating gate electrode 112. This is shown, for example, in Figure 1 where the bottom gate electrode 102 is formed at closer proximity to the drain electrode 120 as compared to the source electrode 118, while the floating gate electrode 112 is symmetrically formed and at approximately equidistant to the source electrode 118 and the drain electrode 120.

[0037] Using the architecture of the FeFET 100 as shown in relation to Figure 1 , an effective area ratio between the insulating layer 114 and the ferroelectric layer 110 may be adapted to tune the bottom gate voltage required for altering the resistance state of the semiconductor layer 116. The effective area ratio between the insulating layer 114 and the ferroelectric layer 110 can be approximated to be proportional to a capacitance ratio between the insulating layer 114 and the ferroelectric layer 110 using a parallel plate model and can therefore be used to tune the bottom gate voltage applied for changing a resistance state of the semiconductor layer 116. The area ratio may be in the range of 0.1 to 50.

[0038] Figure 2 is a flowchart of a method 200 for forming the ferroelectric field-effect transistor 100 of Figure 1 in accordance with an embodiment.

[0039] In a step 202, the bottom gate electrode 102 is formed on the substrate 104 comprising the silicon dioxide layer 106 and the silicon substrate layer 108. In the present embodiment, the bottom gate electrode 102 is formed using a conventional lithography process comprising electron beam lithography or photolithography. This may include deposition of a suitable resist layer, exposure and subsequent development of the resist layer to form a pattern of the bottom gate electrode 102 on the substrate 104. A metal layer for forming the bottom gate electrode 102 can then be deposited by evaporation or other deposition technique followed by a lift-off process to form the bottom gate electrode 102. In a step 204, the ferroelectric layer 110 is formed on the bottom gate electrode 102. The ferroelectric layer 110 is adapted to exhibit different polarization states in response to an applied electric field provided using a bottom gate voltage at the bottom gate electrode 102. In the present embodiment, a 20 nm thick polycrystalline hafniumzirconium oxide (HfosZro 5O2) layer was deposited as the ferroelectric layer 110 using atomic layer deposition (ALD).

[0040] In a step 206, the floating gate electrode 112 is formed on the ferroelectric layer 110. The floating gate electrode 112 is adapted to exhibit different charge states in response to electric charges injected or removed from the ferroelectric layer 110 and a polarization state of the ferroelectric layer 110. The floating gate electrode 112 can be formed using metal deposition followed by lithography and etching processes. In the present embodiment, the floating gate electrode 112 is made of a tungsten (W) metal layer of about 30 nm in thickness, which was deposited onto the ferroelectric layer 110 by sputtering at room temperature. A lithography process was applied to pattern the tungsten (W) metal layer using a laser writer, and the floating gate electrode 112 was formed by wet etching the patterned tungsten metal layer using a tungsten etchant to get rid of excessive tungsten metal. Note that the etching time is dependent on the thickness of tungsten layer, and a 20 second etch was used in the present case.

[0041] In an embodiment, the ferroelectric layer 110 is annealed after the floating gate electrode 112 is formed on the ferroelectric layer 110. In the present embodiment where the ferroelectric layer 110 includes a 20 nm thick polycrystalline hafniumzirconium oxide (Hfo.5Zro.5O2) layer, the ferroelectric layer 110 was annealed at a temperature of about 400 °C. The annealing temperature of about 400 °C enables this annealing process to be compatible with back-end-of-line (BEOL) processes and provided an optimal trade-off between thermal budget and ferroelectric properties of the ferroelectric layer 110. In other embodiments, a range of temperature of about 300 °C to 500 °C can be used. The polycrystalline hafnium-zirconium oxide (Hfo5Zro.5O2) layer was annealed for it to exhibit ferroelectric properties. It should be appreciated that an annealing temperature of the ferroelectric layer 110 is therefore dependent on a material used for the ferroelectric layer 110, and in some embodiments, this may not be necessary. In a step 208, the insulating layer 114 is formed on the floating gate electrode 112. The insulating layer 114 includes a high-k oxide which is deposited at a low temperature. In the present embodiment, the insulating layer 114 includes a 6 nm thick AI2O3 or HfC>2 layer, which can be deposited using atomic layer deposition (ALD) at a temperature of about 150 °C.

[0042] In a step 210, the semiconductor layer 116 is formed on the insulating layer 114. In the present embodiment, the semiconductor layer 116 includes a 20 nm thick M0S2 layer which can be formed on the insulating layer 114 by two-dimensional semiconductor transfer.

[0043] In a step 212, the source electrode 118 and the drain electrode 120 are formed in electrical connection with the semiconductor layer 116 to allow an electric current to pass through the semiconductor layer 116. In the present embodiment, a lithography process was used to form the source / drain electrodes 118, 120. First, the source / drain electrodes 118, 120 were patterned using a laser writer or an electron beam lithography. Second, a layer of nickel (Ni) of about 20-nm in thickness was deposited using electron beam evaporation. Third, acetone was used in a lift-off process to get rid of excessive Ni metal to form the source / drain electrodes 118, 120.

[0044] The FeFET 100 of the present disclosure combines a ferroelectric layer, a floating gate electrode, and a 2D semiconductor layer to achieve improved device characteristics for memory applications, such as an extended memory window and a large read on / off ratio (e.g. at a bottom gate voltage of 0 V), as compared to conventional FeFETs having different device architectures. Experimental results obtained using the device architecture of the FeFET 100 of Figure 1 are discussed in relation to Figures 3 to 11 below.

[0045] Figure 3 shows a plot 300 of memory window ratio versus on-off ratio read at a gate voltage of 0 V to benchmark a plurality of ferroelectric field-effect transistors (FeFETs) having different architectures in accordance with an embodiment. The memory window ratio is given by MWexp / MWIdeaiwhere the ideal memory window, MWIdeai, is calculated based on the coercive voltage of the respective ferroelectric layer. The on- off ratio is the ratio between a measured on-state current and a measured off-state current of the respective FeFET. Various ferroelectric layers used in previous attempts have been included in this benchmarking plot 300, these include P(VDF-TrFE), lead zirconium titanate (PZT), PbTiCh (PTO), barium strontium titanate (BST), aluminum scandium nitride (AIScN), CuInPzSe (CIPS), Hf-based ferroelectric and a 20 nm thick Hfo 5Zro 5O2 layer used in the present disclosure. In the present embodiment, a 2D semiconductor M0S2 was used as an example to demonstrate the benefit of the FeFET structure. The data point 302 in relation to the present disclosure as shown in the plot 300, represents a memory window ratio MWexp / MWIdealof about 1.5 with an on-off ratio of about 1 .5 x 106read at a bottom gate voltage of 0 V.

[0046] Figure 4 shows a graph 400 of drain current versus gate voltage for the ferroelectric field-effect transistor (FeFET) 100 of Figure 1 in accordance with an embodiment. The gate voltage was applied at the bottom gate electrode 102. A plot 402 shows 120- cycles of forward and reverse switching of the FeFET 100 with negligible or small cycle-to-cycle variation. This illustrates a stable memory performance in both forward and reverse switching of the FeFET 100. Further, steep slopes as shown in relation to both the forward and reverse switching of the graph 400 also demonstrate achievement of an energy-efficient operation by the FeFET 100 of Figure 1. The insets 404 and 406 show plots of sub-threshold slope (SS) (mV / dec) versus drain current (A / pm) for the forward switching and the reverse switching of the FeFET 100, respectively, to illustrate the efficient switching operation obtained in the present FeFET device architecture.

[0047] Figure 5 shows a graph 500 of memory window versus an area ratio between the insulating layer 114 and the ferroelectric layer 110 using the device architecture of the ferroelectric field-effect transistor (FeFET) 100 of Figure 1 in accordance with an embodiment. Various area ratios between the insulating layer 114 and the ferroelectric layer 110 ( A0X / AFE) together with their corresponding memory windows were measured empirically and these are plotted as data points 502 in the graph 500. A linear fitting 504 of the data points 502 is also shown to show a trend of increasing memory window with increasing A0X / AFE. A wide range of memory window can be obtained by varying the area ratio A0X / AFE. The ideal memory window 506 of 4.8 V is calculated based on the coercive voltage of the 20 nm thick Hfo.5Zro.5O2 layer used in the present case using Equation (1) below: Wideal = 2 X a X Ecx dFE(1) where MWidealis the theoretical memory window, a is a coefficient with a value no larger than 1 , Ecand dFEare the coercive electric field and the thickness of the ferroelectric material, respectively. In the present embodiment, a is assumed to be equal to 1 to simplify calculation.

[0048] As shown in the graph 500, by controlling an area ratio, (Aoy / AFE-), between the insulating layer 114 and the ferroelectric layer 110, the architecture of the FeFET 100 enables tuning of the bottom gate voltage applied to the ferroelectric layer 110 via the bottom gate electrode 102 for the forward and reverse switching to achieve an ultralarge memory window beyond that of the theoretical limit (i.e. MWideal). The graph 500 demonstrates that a memory window of more than 8 V can be obtained with an area ratio (AOX / AFE) of about 6.

[0049] Figure 6 shows a graph 600 of drain current versus pulse width of a pulse voltage Vp applied at the bottom gate electrode 102 of the ferroelectric field-effect transistor (FeFET) 100 of Figure 1 in accordance with an embodiment. Drain current versus pulse width for pulse voltages VP of 5.0 V, 5.5 V, 6.0 V and 7.0 V are shown in plots 602, 604, 606 and 608, respectively. The results of the graph 600 shows that measured drain current increases with increasing pulse width and pulse voltage Vp, highlighting contribution of ferroelectric domain switching with the applied bottom gate voltage and pulse width. This shows that charge injection mechanism is another contributor to achieving the large memory window obtained in the present FeFET structure. The plot 602 shows a small plateau 610 which appeared when the pulse voltage of 5.5 V was applied and gradually disappeared with increasing pulse voltages. This phenomenon may be explained by charge injection through the bottom gate electrode 102.

[0050] Ferroelectric switching strongly depends on an effective electric field in a ferroelectric layer. However, this effective electric field is a synergistic result of an applied electric field and a depolarization field attributed to charge mismatching between the ferroelectric layer 110 and the insulating layer 114. The depolarization field can significantly deteriorate the performance of a FeFET memory. In the FeFET 100 of the present disclosure, the issue related to the depolarization field is mitigated by increasing a potential difference (or the voltage drop) across the ferroelectric layer 110 which is related to the capacitance and area ratios between the ferroelectric layer 110 and the insulating layer 114. This is illustrated using Equations (2) and (3) below:

[0051] VG=VFE +VIL + VFB + 0s (2) where VG, VFE, VIL, VFB, and 0Sare the applied bottom gate voltage, the voltage dropped across the ferroelectric layer 110, the voltage dropped across the insulating layer 114, the flat band voltage, and the surface potential, respectively. Therefore, to increase the voltage dropped across the ferroelectric layer 110, VFE, one can increase the ratio of either the capacitance or the area between the insulating layer 114 and the ferroelectric layer 110. Using the present FeFET architecture, the method of tuning the area ratio can be applied using different semiconductor layer and / or different ferroelectric layer.

[0052] Figure 7 shows a graph 700 of memory window versus (VstoP- Vstart) of the bottom gate voltage of the ferroelectric field-effect transistor (FeFET) 100 of Figure 1 in accordance with an embodiment. In the present embodiment, a 20 nm-thick Hfo5Zro5O2 layer was used as the ferroelectric layer 110. The graph 700 shows measured data points 702 obtained for different (VstoP- Vstart) of the bottom gate voltage at an area ratio AFE'-AIL (i.e. a ratio of the area of the ferroelectric layer to the area of the insulating layer) of about 1 :1.5. A linear fitting 704 of the data points 702 is also shown in the graph 700, with a slope of 0.98. The graph 700 shows efficient voltage transfer to the ferroelectric layer 110 using the present FeFET architecture by controlling an area ratio between the ferroelectric and insulating layers 110, 114.

[0053] Apart from charge mismatching between the ferroelectric layer 110 and the insulating layer 114, an energy band diagram as shown in relation to Figure 8 illustrates another factor that contributes to the large memory window obtained using the FeFET device structure of the present disclosure.

[0054] Figure 8 shows an energy band diagram 800 in the z-direction across a material layer stack of the ferroelectric field-effect transistor (FeFET) 100 of Figure 1 in accordance with an embodiment. The energy band of the bottom gate electrode 102, the ferroelectric layer 110, the floating gate electrode 112, the insulating layer 114 and the semiconductor layer 116 are illustrated by regions 802, 804, 806, 808 and 810 of the energy band diagram 800, respectively.

[0055] As the bottom gate voltage VGis applied, besides inducing ferroelectric switching 812 which causes bending in the energy bands in the various regions / layers, electron carriers are injected by charge injection 814 into trap sites 816 of the ferroelectric layer 110. The trap sites 816 may include grain boundaries and oxygen vacancies present in the ferroelectric layer 110. Together with ferroelectric polarization of the ferroelectric layer 110, this effect due to charge injection enhances electrostatic control of the underlying semiconductor electric field and enhances the memory window of the FeFET.

[0056] Further, the presented FeFET architecture also demonstrates high retention as a result of adopting atomically thin semiconductors (e.g. 2D semiconductors) as the semiconductor layer 116 in the FeFET 100. In the present example, the 2D semiconductor material M0S2 used not only shows excellent transistor performance but also improves retention by mitigating the depolarization field in a metal-ferroelectric- insulator-semiconductor material structure / stack. This is illustrated in relation to Equations (4), (5) and (6) below:

[0057] Cs= ^d2D (6) where Edepis the depolarization field, Pris the remnant polarization of the ferroelectric layer 110, eFEis the permittivity of the ferroelectric layer 110, Cosis the series capacitance of the insulating layer 114 (Cox) and the semiconductor layer 116 (Cs), CFEis the capacitance of the ferroelectric layer 110, e2Dand d2Dare the permittivity and thickness of the semiconductor layer 116 respectively. From the above equations, by decreasing a thickness of the semiconductor layer 116, the depolarization field Edepdecreases, thereby reducing a retention loss of the ferroelectric memory of the FeFET 100. Based on the above, 2D semiconductors are likely better candidates for providing better memory retention as compared to conventional bulk semiconductors in ferroelectric memory devices.

[0058] Figure 9 shows a graph 900 of drain current versus retention time for the ferroelectric field-effect transistor (FeFET) 100 of Figure 1 in accordance with an embodiment. The experimental results as shown in the graph 900 are read at a bottom gate voltage of 0 V at a temperature of 300 K.

[0059] The graph 900 includes data points 902 of drain currents for different retention times at +7 V program voltage and data points 904 of drain currents for different retention times at -7 V erase voltage. The +7 V program voltage and the -7 V erase voltage were applied via the bottom gate electrode 102 and the respective data points 902, 904 were measured when the bottom gate voltage was set to 0 V. A linear extrapolation of the data points 902 and 904 are also shown as fitted lines 912 and 914 respectively. From the graph 900, it can be shown that the FeFET 100 of Figure 1 has a remarkable retention characteristic at a bottom gate voltage of 0 V where the program / erase ratio can be sustained at above five orders for up to 10 years (-0.315 x 108s). The inset 916 shows a pulse width of 1 ms were used for both the +7 V program voltage and the -7 V erase voltage.

[0060] Figure 10 shows a graph 1000 of conductance versus pulse number for the ferroelectric field-effect transistor (FeFET) 100 of Figure 1 to illustrate long-term potentiation (LTP) and long-term depression (LTD) of synaptic plasticity in accordance with an embodiment. The portion 1002 of the graph 1000 shows the conductance of the FeFET 100 versus pulse number at a program voltage of +5.50 V, while the portion 1004 of the graph 1000 shows the conductance of the FeFET 100 versus pulse number at an erase voltage of -5.75 V. Each pulse applied in sequence for each portion 1002, 1004 has a constant voltage amplitude but an increasing pulse width with a fixed time step.

[0061] The portion 1002 shows an almost linear increase of conductance with increasing pulse number while the portion 1004 shows an almost linear decrease of conductance with increasing pulse number. The graph 1000 therefore demonstrates that the FeFET 100 exhibits superior synaptic plasticity, i.e., long-term potentiation (LTP) and long-term depression (LTD) with negligible variation, with a conductance ratio Gmax / Gmin of more than 102. These parameters achieved by the present FeFET architecture are critical to ensure high-efficient in-memory computing.

[0062] Figure 11 is a graph 1100 of conductance versus cycle number for the ferroelectric field-effect transistor (FeFET) 100 of Figure 1 to illustrate reproducibility of the synaptic behaviour generated in the FeFET 100 in accordance with an embodiment. The graph 1100 shows stability and reproducibility of generated synaptic plasticity using the FeFET 100 architecture of Figure 1 with 25,600 applied voltage pulses to the FeFET 100 architecture via the bottom gate electrode 102. Two hundred repetitive LTP-LTD measurements are shown in Figure 11 , where each LTP-LTD cycle comprises a total of 128 pulses. Each LTP or LTD portion of a LTP-LTD cycle (see e.g. Figure 10) includes 64 pulses, where each pulse in sequence has a constant voltage amplitude but an increasing pulse width with a fixed time step. There are therefore 25,600 applied voltage pulses recorded in Figure 11. Figure 11 provides clear indication of good reliability of generated synaptic plasticity as required for implementing in-memory computing.

[0063] In conclusion, a ferroelectric field-effect transistor (FeFET) architecture comprising a two-dimensional (2D) semiconductor material layer is described. By decoupling the ferroelectric layer and the insulating layer through the arrangement of the bottom gate electrode and the floating gate electrode, effective areas of the ferroelectric layer and the insulating layer can be tuned. The tunable effective areas of the ferroelectric layer and the insulating layer together with the floating gate electrode are adapted to suppress the fundamental memory window limit and to minimize a depolarization field attributed by a charge mismatch between the ferroelectric layer and the insulating layer. This enables the FeFET of the present disclosure to achieve long retention, small cycle-to-cycle variation, and energy efficient switching as a memory device. Further, the present FeFET architecture can be adapted to provide an improved interface between the semiconductor layer and the insulating layer to mitigate a charge trapping effect at the interface to enhance cycling endurance. With the ultra-large memory window, mitigated depolarization field, small variation, and long retention, the aforementioned FeFET architecture can be applied to logic-memory colocation devices, high-density memory cell integration and in-memory computing schemes for data storage and computing. The proposed FeFET improves the functionalities of ferroelectric memory used for in-memory computing, where high performance, energyefficient, and high-density integration can be realized with performance and capabilities beyond the traditional silicon technology. The present FeFET architecture can also be used to construct high-performance memory for edge devices of loT and neuromorphic computing chips in Al. Further, the polycrystalline nature of the Hfo 5Zro 5O2 layer used in the present embodiment provides a reservoir of trap sites for charge trapping through bottom gate injection. Together with ferroelectric polarization of the ferroelectric layer 110, this effect due to charge injection enhances electrostatic control of the underlying semiconductor electric field and enhances the memory window of the FeFET.

[0064] Still further, the FeFET architecture of the present disclosure, with the aforementioned use of ferroelectric polarization and charge injection mechanisms, offers a nondestructive reading scheme that is beneficial for improving an operational lifetime of the FeFET.

[0065] Other alternative embodiments of the invention include: (i) use of other ferroelectric layer or layers beside the Hfo.5Zro.5O2 layer used in the exemplary embodiments above; (ii) use of other 2D materials or bulk semiconductors for forming the semiconductor layer 116; (iii) forming the bottom gate electrode symmetrically or in other orientation with respect to the floating gate electrode of the FeFET structure; (iv) a capacitance ratio between the insulating layer and the ferroelectric layer being in the range of 0.1 to 50; (v) an area ratio between the insulating layer and the ferroelectric layer being in the range of 0.1 to 50; (vi) use of other suitable substrate besides the SiO2 on Si substrate used in the present embodiments; and (vii) having various thicknesses for the ferroelectric layer (besides the 20 nm thick HfosZrosCk layer used), the insulating layer and / or the semiconductor layer, taking into consideration voltage drops across these different layers and their effects on switching a resistance state of the semiconductor layer in the FeFET.

[0066] Although only certain embodiments of the present invention have been described in detail, many variations are possible in accordance with the appended claims. For example, features described in relation to one embodiment may be incorporated into one or more other embodiments and vice versa.

Claims

Claims1 . A ferroelectric field-effect transistor comprising: a bottom gate electrode formed on a substrate; a ferroelectric layer formed on the bottom gate electrode, the ferroelectric layer capable of exhibiting different polarization states in response to an applied electric field provided by a bottom gate voltage at the bottom gate electrode; a floating gate electrode formed on the ferroelectric layer, the floating gate electrode capable of exhibiting different charge states in response to electric charges injected or removed from the ferroelectric layer and a polarization state of the ferroelectric layer; an insulating layer formed on the floating gate electrode; a semiconductor layer formed on the insulating layer; and a source electrode and a drain electrode formed in electrical connection to the semiconductor layer to allow an electric current to pass through the semiconductor layer, wherein the bottom gate electrode is adapted to control the polarization state of the ferroelectric layer and to inject or remove the electric charges from the ferroelectric layer via the bottom gate voltage for changing a charge state of the floating gate electrode to alter a resistance state of the semiconductor layer for use in memory applications.

2. The ferroelectric field-effect transistor of claim 1, wherein the semiconductor layer comprises a two-dimensional semiconductor.

3. The ferroelectric field-effect transistor of claim 1 or claim 2, wherein the ferroelectric layer comprises a polycrystalline hafnium-zirconium oxide.

4. The ferroelectric field-effect transistor of any one of the preceding claims, wherein a capacitance ratio between the insulating layer and the ferroelectric layer is in the range of 0.1 to 50.

5. The ferroelectric field-effect transistor of any one of the preceding claims, wherein the bottom gate electrode is formed asymmetrically with respect to the floating gate electrode and at one side of the floating gate electrode.

6. The ferroelectric field-effect transistor of any one of the preceding claims, wherein an area ratio between the insulating layer and the ferroelectric layer can be adapted to tune the bottom gate voltage required for altering the resistance state of the semiconductor layer, and the area ratio is in the range of 0.1 to 50.

7. A method for forming a ferroelectric field-effect transistor, the method comprising: forming a bottom gate electrode on a substrate; forming a ferroelectric layer on the bottom gate electrode, the ferroelectric layer capable of exhibiting different polarization states in response to an applied electric field provided by a bottom gate voltage at the bottom gate electrode; forming a floating gate electrode on the ferroelectric layer, the floating gate electrode capable of exhibiting different charge states in response to electric charges injected or removed from the ferroelectric layer and a polarization state of the ferroelectric layer; forming an insulating layer on the floating gate electrode; forming a semiconductor layer on the insulating layer; and forming a source electrode and a drain electrode in electrical connection with the semiconductor layer to allow an electric current to pass through the semiconductor layer, wherein the bottom gate electrode is adapted to control the polarization state of the ferroelectric layer and to inject or remove the electric charges from the ferroelectric layer via the bottom gate voltage for changing a charge state of the floating gate electrode to alter a resistance state of the semiconductor layer for use in memory applications.

8. The method of claim 7, wherein the semiconductor layer comprises a two- dimensional semiconductor.

9. The method of claim 7 or claim 8, wherein the ferroelectric layer comprises a polycrystalline hafnium-zirconium oxide.

10. The method of any one of claims 7 to 9, wherein a capacitance ratio between the insulating layer and the ferroelectric layer is in the range of 0.1 to 50.

11. The method of any one of claims 7 to 10, wherein forming the bottom gate electrode on the substrate includes forming the bottom gate asymmetrically with respect to the floating gate electrode and at one side of the floating gate electrode.

12. The method of any one of claims 7 to 11, further comprising forming the insulating layer and the ferroelectric layer with an area ratio in the range of 0.1 to 50 for tuning the bottom gate voltage required for altering the resistance state of the semiconductor layer.

13. The method of any one of claims 7 to 12, further comprising annealing the ferroelectric layer after forming the floating gate electrode on the ferroelectric layer.

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