Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: at least one transistor, an insulating layer covering the transistor, and a bit line (30) arranged on the side of the insulating layer away from the transistor. Each transistor comprises a semiconductor pillar (10) extending in a third direction, and the semiconductor pillar (10) comprises a channel region (11), and a first region (12) and a second region (13) respectively arranged on both sides of the channel region (11); the insulating layer is provided with a groove exposing the second region (13); the bit line (30) is arranged in the groove, the bit line (30) is in contact with the second region (13), and the contact surface between the bit line (30) and the second region (13) is perpendicular to the third direction.

Description

Semiconductor device and manufacturing method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 21, 2023, with application number 2023102803899 and invention name “A semiconductor device, its manufacturing method, and electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0003] Traditional vertical gate-all-around dynamic random access memory (DRAM) arrays are manufactured by first forming buried bit lines, then word lines, and finally forming storage nodes on top. This process is complex and difficult to precisely control, resulting in poor device performance.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] An embodiment of the present disclosure provides a semiconductor device, comprising: at least one transistor, an insulating layer covering the transistor, and a bit line arranged on a side of the insulating layer away from the transistor; the transistor comprising: a semiconductor column extending along a third direction, the semiconductor column comprising a channel region and a first region and a second region respectively arranged on both sides of the channel region, the insulating layer having a groove exposing the second region, the bit line being arranged in the groove, the bit line being in contact with the second region, and the contact surface between the bit line and the second region being perpendicular to the third direction.

[0007] In some embodiments, the semiconductor further includes a substrate, the third direction is perpendicular to the substrate, the substrate and the transistor are located on different wafers, and the second region is arranged on a side of the first region facing the substrate.

[0008] In some embodiments, a surface of the bit line away from the semiconductor pillar is parallel to the substrate.

[0009] In some embodiments, the semiconductor device includes a plurality of transistors arrayed along a first direction and a second direction, and a plurality of bit lines extending along the second direction, wherein the second regions of transistors in the same column distributed along the second direction are connected to the same bit line, and the first direction and the second direction intersect.

[0010] In some embodiments, the insulating layer includes an insulating sublayer filled between the bit lines, and the insulating sublayer includes a low-K dielectric.

[0011] In some embodiments, the transistor further includes: a gate electrode, wherein the gate electrode surrounds a sidewall of the channel region, and the gate electrodes of transistors in the same row distributed along the first direction are connected to form a word line.

[0012] In some embodiments, the semiconductor device further includes: a connecting electrode disposed on a side of the word line close to the substrate and extending in a direction perpendicular to the substrate, wherein one connecting electrode is connected to one word line.

[0013] In some embodiments, connecting electrodes connecting adjacent word lines are disposed on opposite sides of the bit line.

[0014] In some embodiments, the semiconductor device further includes: a logic circuit disposed between the substrate and the transistor, wherein an orthographic projection of the logic circuit overlaps with an orthographic projection of the transistor on a plane parallel to the substrate.

[0015] In some embodiments, the substrate includes a central area and a peripheral area surrounding the central area, the transistor is arranged in the central area, and the semiconductor device further includes: a logic circuit arranged in the peripheral area, and on a plane perpendicular to the substrate, the orthographic projection of the logic circuit overlaps with the orthographic projection of the transistor.

[0016] An embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described in any of the above embodiments.

[0017] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes at least one transistor, and the transistor includes a semiconductor pillar. The manufacturing method includes:

[0018] Providing a first wafer, forming a substrate and a semiconductor column of the at least one transistor disposed on the substrate and extending in a direction perpendicular to the substrate, wherein the semiconductor column includes a channel region and a first region and a second region disposed on both sides of the channel region, respectively, wherein the second region is disposed on a side of the channel region away from the substrate;

[0019] forming an insulating layer covering the semiconductor pillar, wherein the insulating layer has a groove exposing the second region, and forming a bit line in contact with the second region in the groove, wherein a contact surface between the bit line and the second region is parallel to the substrate;

[0020] A second wafer is provided, the first wafer is flipped over, a side of the first wafer away from the substrate is bonded to the second wafer, and the substrate is etched away to expose the first region.

[0021] In some embodiments, before forming a bit line in contact with the second region, the method further includes:

[0022] A gate insulating layer surrounding the sidewall of the channel region and a gate electrode surrounding the sidewall of the gate insulating layer are sequentially formed.

[0023] In some embodiments, before bonding the first wafer away from the substrate to the second wafer, the method further includes: forming a logic circuit on the second wafer.

[0024] In some embodiments, before forming the bit line contacting the second region, the method further includes: forming a logic circuit on the first wafer.

[0025] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The purposes and advantages of the present disclosure can be realized and obtained through the structures particularly pointed out in the description and the drawings.

[0026] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation to the technical solution.

[0028] FIG1A is a schematic plan view of a semiconductor device provided by an exemplary embodiment;

[0029] FIG1B is a schematic cross-sectional view taken along the AA′ direction in FIG1A ;

[0030] FIG1C is a schematic diagram of a semiconductor device provided by another exemplary embodiment;

[0031] FIG1D is a schematic diagram of a semiconductor device provided by another exemplary embodiment;

[0032] FIG2 is a perspective view of an exemplary embodiment after forming a bit line isolation trench;

[0033] FIG3 is a perspective schematic diagram of an exemplary embodiment after forming a first insulating layer;

[0034] FIG4 is a perspective view of an exemplary embodiment after word line isolation trenches are formed; FIG.

[0035] FIG5 is a schematic cross-sectional view along the AA′ direction after forming the third edge layer according to an exemplary embodiment;

[0036] FIG6 is a schematic cross-sectional view along the AA′ direction after etching the second insulating layer and the third insulating layer according to an exemplary embodiment;

[0037] FIG7 is a schematic cross-sectional view along the AA′ direction after depositing a gate electrode film according to an exemplary embodiment;

[0038] FIG8 is a schematic cross-sectional view along the AA′ direction after forming a gate insulating layer and a gate electrode according to an exemplary embodiment;

[0039] FIG9 is a schematic cross-sectional view along the AA′ direction after removing the gate electrode and the gate insulating layer located at the edge of the array according to an exemplary embodiment;

[0040] 10A is a schematic cross-sectional view along the AA' direction after forming a fourth insulating layer according to an exemplary embodiment;

[0041] 10B is a schematic cross-sectional view along the AA' direction after forming the fourth insulating layer provided by another exemplary embodiment;

[0042] FIG11A is a top view of an exemplary embodiment after forming a bit line;

[0043] FIG11B is a schematic cross-sectional view along the AA′ direction after forming a bit line according to an exemplary embodiment;

[0044] FIG12A is a top view of an exemplary embodiment after forming a connecting electrode;

[0045] FIG12B is a schematic cross-sectional view along the BB′ direction in FIG12A .

[0046] FIG13 is a top view of a first wafer and a second wafer provided by an exemplary embodiment;

[0047] FIG14 is a schematic cross-sectional view along the AA′ direction after etching a substrate according to an exemplary embodiment;

[0048] FIG15 is a schematic cross-sectional view along the AA′ direction after forming a connection layer according to an exemplary embodiment;

[0049] FIG16 is a schematic cross-sectional view along the AA′ direction after a capacitor is formed, provided by an exemplary embodiment;

[0050] FIG. 17 is a flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0051] Explanation of the accompanying drawings: 1—substrate; 2—first insulating layer; 3—second insulating layer; 4—third insulating layer; 5—fourth insulating layer; 10—semiconductor column; 11—channel region; 12—first region; 13—second region; 14—gate insulating layer; 20—word line; 21—gate electrode; 30—bit line; 40—connecting layer; 41—first plate; 42—second plate; 51—first insulating sublayer; 52—second insulating sublayer; 60—connecting electrode; 70—dielectric layer; 81—first bonding pad; 82—second bonding pad; 100—first wafer; 101—central region; 102—peripheral region; 200—second wafer; 210—logic circuit; 301—bonding pad. DETAILED DESCRIPTION

[0052] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0053] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs.

[0054] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0055] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0056] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0057] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0058] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0059] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 81°, and thus also includes the angle of greater than 85° and less than 95°.

[0060] The phrase "the orthographic projection of B is within the range of the orthographic projection of A" in the present disclosure means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0061] In one technical solution, bit lines are formed by trenching the bottom of a semiconductor pillar and filling it with conductive material. This process is complex, resulting in poor bit line uniformity and prone to voids within the bit lines, causing different and high resistances between bit lines. Furthermore, it is difficult to form a reliable ohmic contact between the bit lines and the drain terminal, resulting in high contact resistance. The bit lines are isolated by deep trenches, which are easily filled with insulating material to form voids, leading to leakage between the bit lines.

[0062] In the disclosed embodiments, the bit lines are fabricated by trenching the tops of the semiconductor pillars, which reduces process complexity, improves bit line uniformity, avoids voids, and reduces bit line resistance. This facilitates reliable ohmic contact between the bit lines and the semiconductor pillars, reducing contact resistance. Furthermore, the size and shape of different bit lines in the same memory array are more easily controlled, ensuring consistent size and shape, thereby stabilizing bit line resistance. The insulating layer between the bit lines is less likely to form voids, thus preventing leakage.

[0063] Figure 1A is a schematic plan view of a semiconductor device provided by an embodiment of the present disclosure, and Figure 1B is a schematic cross-sectional view taken along the AA' direction in Figure 1A . As shown in Figures 1A and 1B , an embodiment of the present disclosure provides a semiconductor device that may include: at least one transistor; a fourth insulating layer 5 covering the transistor; and a bit line 30 disposed on a side of the fourth insulating layer 5 away from the transistor. The transistor may include: a semiconductor pillar 10 extending along a third direction Z; the semiconductor pillar 10 may include a channel region 11 and first and second regions 12 and 13 disposed on either side of the channel region 11, respectively; the fourth insulating layer 5 includes a recess exposing the second region 13; the bit line 30 is disposed within the recess and contacts the second region 13, with the contact surface between the bit line 30 and the second region 13 being perpendicular to the third direction Z. The channel region 11 may be substantially distinguished from the first and second regions 12 and 13 by the location of a gate electrode, or may be substantially distinguished by the different levels of conductivity between the first and second regions 12 and 13 and the channel region 11.

[0064] In the solution provided by this embodiment, the contact surface between the bit line 30 and the second region 13 is parallel to the substrate. The bit line 30 is prepared by digging a groove in the insulating layer at the top of the semiconductor column and then filling it. That is, the bit line 30 is prepared at the top of the semiconductor column, which reduces the process difficulty, improves the uniformity of the bit line, is less likely to produce voids, and reduces the bit line resistance.

[0065] The first region 12 and the second region 13 may be regions doped with impurities in the semiconductor pillar 10. In one embodiment, the conductivity type of the first region 12 and the second region 13 may be n-type or p-type. The first region 12 may be a source region, and the second region 13 may be a drain region, or the first region 12 may be a drain region, and the second region 13 may be a source region.

[0066] In an exemplary embodiment, the semiconductor pillar 10 extending in a direction perpendicular to the substrate 1 can be understood as extending only in a direction perpendicular to the substrate 1 as a whole, and the morphology of the sidewall of the semiconductor pillar 10 is not limited.

[0067] In an exemplary embodiment, the transistor may further include a gate electrode 21 , and the gate electrode 21 may surround a sidewall of the channel region 11 .

[0068] In an exemplary embodiment, the transistor may further include a gate insulating layer 14 surrounding a sidewall of the semiconductor pillar 10 . The gate insulating layer 14 is located between the gate electrode 21 and the semiconductor pillar 10 to insulate the gate electrode 21 from the semiconductor pillar 10 .

[0069] In an exemplary embodiment, the semiconductor device may further include a substrate, wherein the third direction Z is perpendicular to the substrate, and the second region 13 is disposed on the side of the first region 11 facing the substrate. The substrate and the transistor may be located on different wafers, i.e., the transistor is located on one wafer, which is bonded to another wafer, and the substrate of the other wafer serves as the substrate of the semiconductor device. As shown in Figures 1C and 1D, the transistor is located on a first wafer 100, which is disposed on a second wafer 200, and the substrate of the second wafer 200 (not shown in Figures 1C and 1D) or the second wafer 200 serves as the substrate of the semiconductor device.

[0070] In an exemplary embodiment, the surface of the bit line 30 away from the semiconductor pillar 10 may be parallel to the substrate. In this embodiment, both the upper and lower surfaces of the bit line 30 are parallel to the substrate, and the bit line resistance is stable.

[0071] In an exemplary embodiment, the cross-section of the bit line 30 in a direction parallel to the substrate may have substantially the same size and shape at different locations.

[0072] In an exemplary embodiment, the cross-section of the channel region 11 in a direction parallel to the substrate may have substantially the same size and shape at different locations.

[0073] In an exemplary embodiment, the cross-section of the first region 12 in a direction parallel to the substrate may have substantially the same size and shape at different locations.

[0074] In an exemplary embodiment, the size and shape of the cross section of the second region 13 in a direction parallel to the substrate at different positions may be substantially the same.

[0075] In one exemplary embodiment, the semiconductor device may include a memory array, which may include a plurality of vertical channel transistors arranged in an array along a first direction X and a second direction Y, a plurality of word lines 20 extending along the first direction X, and a plurality of bit lines 30 extending along the second direction Y. The gate electrodes 21 of transistors arranged in the same row along the first direction X are connected to form a word line 20, and the second regions 13 of transistors arranged in the same column along the second direction Y are connected to the same bit line 30. The first direction X and the second direction Y may intersect. In one exemplary embodiment, the first direction X and the second direction Y may be perpendicular.

[0076] In an exemplary embodiment, the first direction X may be parallel to the substrate, and the second direction Y may be parallel to the substrate.

[0077] In one exemplary embodiment, as shown in FIG10B , the fourth insulating layer 5 may include a second insulating sublayer 52 filled between the bit lines 30. The second insulating sublayer 52 may include a low-K dielectric. Compared to a solution in which trenches are formed at the bottom of the semiconductor pillars 10 and then filled with the trenches to form the bit lines (typically, the bit lines are isolated by silicon dioxide), the bit lines can be isolated using a low-K dielectric, thereby improving circuit delay. However, the disclosed embodiments are not limited thereto, and non-low-K dielectrics may be used to isolate the bit lines.

[0078] In an exemplary embodiment, the semiconductor device may further include an isolation structure filled between the transistors, and the isolation structure may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0079] In one exemplary embodiment, as shown in FIG12B , the semiconductor device may further include a connecting electrode 60 disposed on a side of the word line 20 close to the substrate and extending perpendicular to the substrate, with each connecting electrode 60 connected to one word line 20. FIG12B is a schematic diagram during the fabrication process. The actual semiconductor device will be flipped over later. At this point, the connecting electrode 60, like the bit line 30, is flipped downward, i.e., close to the substrate.

[0080] In one exemplary embodiment, as shown in FIG12A , the connection electrodes 60 connecting adjacent word lines 20 can be disposed on opposite sides of the bit line 30. Some connection electrodes 60 are distributed on one side of the bit line 30, while others are distributed on the other side of the bit line 30. Furthermore, the connection electrodes 60 connecting adjacent word lines 20 are disposed on different sides to prevent the connection electrodes 60 from being too densely packed and interfering with each other.

[0081] In one exemplary embodiment, as shown in FIG1C , the semiconductor device may further include a logic circuit 210 disposed between the substrate and the transistor, wherein the orthographic projection of the logic circuit 210 overlaps with the orthographic projection of the transistor on a plane parallel to the substrate. In this embodiment, the logic circuit 210 is disposed below the transistor. The logic circuit 210 and the transistor may be disposed on separate wafers, achieving a stacked configuration. Compared to a solution in which the logic circuit 210 and the transistor are disposed flatly on the same wafer, this can reduce the area occupied by the semiconductor device and improve integration.

[0082] In an exemplary embodiment, as shown in FIG1D , the substrate may include a central region 101 and a peripheral region 102 surrounding the central region 101. The transistor may be disposed in the central region 101. The semiconductor device may further include a logic circuit (not shown in FIG1D ) disposed in the peripheral region 102. On a plane perpendicular to the substrate, the orthographic projection of the logic circuit overlaps with the orthographic projection of the transistor. In this embodiment, the logic circuit and the transistor may be fabricated on the same wafer.

[0083] In an exemplary embodiment, the semiconductor device may further include: a data storage element.

[0084] In an exemplary embodiment, the data storage element is a capacitor, forming a 1T1C storage structure. However, the present disclosure is not limited thereto and can be combined with other transistors to form a 2T0C storage structure, etc.

[0085] In an exemplary embodiment, as shown in FIG16 , the capacitor may include a first plate 41 and a second plate 42 , and a dielectric layer 70 disposed between the first plate 41 and the second plate 42 . The first plate 41 is connected to the first region 12 .

[0086] The semiconductor device structures shown in FIG. 1A and FIG. 1B are merely examples, and the embodiments of the present disclosure are not limited thereto, and other structures may be used.

[0087] The technical solution of this embodiment is further explained below through the preparation process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology. The "photolithography process" mentioned in this embodiment includes coating of film layers, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, "thin film" refers to a thin film made by depositing or coating a certain material on a substrate.

[0088] In an exemplary embodiment, a process for manufacturing the semiconductor device may include:

[0089] 101) A first wafer is provided, and a plurality of bit line isolation trenches T1 extending along a second direction Y are formed on a substrate 1, as shown in FIG2 , which is a perspective schematic diagram after the bit line isolation trenches T1 are formed. The bit line isolation trenches T1 may be spaced apart along the first direction X.

[0090] In an exemplary embodiment, the substrate 1 may be a semiconductor substrate; for example, it may include at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0091] 102) Depositing a first insulating film on the substrate 1 to form a first insulating layer 2, wherein the first insulating layer 2 fills the bit line isolation trench T1, as shown in FIG3 , which is a three-dimensional schematic diagram after the first insulating layer 2 is formed.

[0092] In an exemplary embodiment, the first insulating film includes, but is not limited to, silicon oxide (SiOx), silicon nitride (SiN), and the like.

[0093] After the first insulating layer 2 is formed, ion implantation (Implant), ie, doping, may be performed according to the requirements of the first region 12 , the channel region 11 , and the second region 13 of the semiconductor device.

[0094] 103) A plurality of word line isolation trenches T2 extending along the first direction X are formed. The word line isolation trenches T2 may be spaced apart along the second direction Y, as shown in FIG. 4 .

[0095] At this time, a plurality of semiconductor pillars 10 are formed on the substrate 1 through the bit line isolation trench T1 and the word line isolation trench T2 .

[0096] The word line isolation trench T2 and the bit line isolation trench T1 may have the same depth along a direction perpendicular to the substrate 1 .

[0097] 104) depositing a second insulating film to form a second insulating layer 3; and depositing a third insulating film to form a third insulating layer 4, wherein the second insulating layer 3 covers the semiconductor pillar 10, as shown in FIG5, which is a schematic cross-sectional view along the AA' direction after forming the third edge layer 4.

[0098] In an exemplary embodiment, the second insulating film and the third insulating film may be deposited by ALD.

[0099] In an exemplary embodiment, the second insulating film and the third insulating film may be low-K dielectric layers, i.e., dielectric layers with a dielectric constant K less than 3.9. For example, they may be any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC).

[0100] In one exemplary embodiment, the second insulating film may be silicon oxide.

[0101] In one exemplary embodiment, the third insulating film may be silicon nitride.

[0102] In an exemplary embodiment, a second insulating film with a thickness of 3 nm to 8 nm may be deposited, and then polished so that the thickness of the second insulating layer 3 at the top of the semiconductor pillar 10 is less than or equal to 2 nm.

[0103] 105) Etch the second insulating layer 3 to expose the channel region 11 and the second region 13, and etch the third insulating layer 4 to expose the second region 13, as shown in FIG6 , which is a schematic cross-sectional view along the AA′ direction after etching the second insulating layer 3 and the third insulating layer 4.

[0104] 106) depositing a gate insulating film 140 and a gate electrode film 210;

[0105] The gate insulating film 140 is located between the gate electrode film 210 and the semiconductor pillar 10 to insulate the gate electrode film 210 from the semiconductor pillar 10 , as shown in FIG7 , which is a schematic cross-sectional view along the AA′ direction after the gate electrode film 210 is deposited.

[0106] In an exemplary embodiment, the gate insulating film 140 may be a High-K dielectric material, including but not limited to at least one of the following: a single-layer structure or a multi-layer structure of at least one of silicon oxide, aluminum oxide, silicon nitride, hafnium oxide, and silicon oxynitride.

[0107] In an exemplary embodiment, the gate electrode film 210 may be formed of or include a conductive material, and the conductive material may be, for example, one of a doped semiconductor material, a conductive metal nitride, a metal material, and a metal-semiconductor compound.

[0108] 107) forming a gate insulating layer 14 and a gate electrode 21;

[0109] Forming the gate insulating layer 14 and the gate electrode 21 may include etching the gate insulating film 140 and the gate electrode film 210 to expose the second region 13, thereby forming the gate insulating layer 14 and the gate electrode 21, as shown in FIG8 , which is a schematic cross-sectional view taken along the AA′ direction after forming the gate insulating layer 14 and the gate electrode 21. The gate electrodes 21 of transistors in the same row are connected to form a word line 20.

[0110] 108) removing the gate electrode 21 and the gate insulating layer 14 located at the edge of the array;

[0111] The removal of the gate electrode 21 and the gate insulating layer 14 located at the edge of the array may include: removing the gate electrode 21 and the gate insulating layer 14 located on the side of the third insulating layer 4 at the outermost edge away from the semiconductor column 10 by photolithography, as shown in Figure 9, which is a cross-sectional schematic diagram along the AA' direction after removing the gate electrode 21 and the gate insulating layer 14 located at the edge of the array.

[0112] 109) forming a fourth insulating layer 5;

[0113] The forming of the fourth insulating layer 5 may include: coating a fourth insulating film on the substrate 1 on which the aforementioned pattern is formed to form the fourth insulating layer 5, as shown in Figures 10A and 10B, Figure 10A is a schematic cross-sectional view along the AA' direction after the fourth insulating layer 5 is formed provided in one embodiment, and Figure 10B is a schematic cross-sectional view along the AA' direction after the fourth insulating layer 5 is formed provided in another embodiment.

[0114] In an exemplary embodiment, the fourth insulating layer 5 may be formed by depositing a fourth insulating film by spin coating a spin oxide dielectric (SOD) and then annealing the film.

[0115] In an exemplary embodiment, the fourth insulating film may include silicon oxide, such as SiO 2 .

[0116] In another exemplary embodiment, the fourth insulating layer 5 may include a first insulating sublayer 51 and a second insulating sublayer 52. The first insulating sublayer 51 is disposed on a side of the second insulating sublayer 52 closer to the substrate 1. The first insulating sublayer 51 may be formed by SOD, and the second insulating sublayer 52 may be formed by ALD deposition. The first insulating sublayer 51 fills the gaps between the semiconductor pillars 10, and the second insulating sublayer 52 covers the first insulating sublayer 51 and the semiconductor pillars 10.

[0117] In one exemplary embodiment, the first insulating sublayer 51 may include silicon oxide, such as SiO2. The second insulating sublayer 52 may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9. For example, it may be one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or silicon carbide (SiC). Using a low-K dielectric layer to isolate the bit lines 30 provides a lower dielectric constant for the isolation layer between the bit lines compared to a solution where the bit lines are formed in bottom trenches, thereby improving circuit delay.

[0118] 110) forming a bit line 30;

[0119] The forming of the bit line 30 may include: etching the fourth insulating layer 5 to form a groove exposing the semiconductor pillar 10, referred to herein as a bit line groove, the bit line groove may extend along the second direction Y, the bit line groove exposing the second region 13; the bit line groove exposes the surface of the second region 13 away from the substrate 1, that is, the surface of the top of the semiconductor pillar 10.

[0120] A first conductive film is deposited in the bitline trench to form a bitline 30 extending along a second direction Y, as shown in Figures 11A and 11B . Figure 11A is a top view of the bitline 30 after formation, and Figure 11B is a schematic cross-sectional view taken along the AA' direction after formation of the bitline 30. In Figure 11A , the wider bonding region near the edge of the bitline 30 may be a bonding pad 301. The bitline 30 may subsequently be connected to other devices, such as a logic circuit, via the bonding pad 301.

[0121] Depositing a first conductive film in the bit line groove to form the bit line 30 may include:

[0122] A cobalt film is deposited, a first rapid thermal annealing (RTA) is performed, the cobalt film is wet-etched, and a second RTA is performed to deposit a seed layer comprising tantalum (Ta) or tantalum nitride (TaN) and copper (Cu). A copper (Cu) film is formed on the seed layer by electrochemical plating (ECP). The copper film is then polished, for example, by CMP, to form bit lines 30. The material of the first conductive film is not limited thereto and may include other conductive materials, such as tungsten. In the scheme of forming bit lines by etching trenches at the bottom, copper cannot be used as the bit lines due to the inconvenience of etching copper. Therefore, the scheme provided in this embodiment can significantly reduce resistance when using copper to form the bit lines.

[0123] 11A , a plurality of bit lines 30 may be formed. The number of bit lines 30 may be related to the number of columns of semiconductor pillars 10 , and one bit line 30 may correspond to one column of semiconductor pillars 10 .

[0124] In some embodiments, each of the bit lines 30 may be connected to a column of semiconductor pillars 10 .

[0125] 111) forming a connecting electrode 60;

[0126] The forming of the connection electrode 60 may include:

[0127] forming a first through hole exposing the word line 20;

[0128] A second conductive film is deposited in the first through hole to form a connecting electrode 60. As shown in Figures 12A and 12B, Figure 12A is a top view after forming the connecting electrode 60, and Figure 12B is a cross-sectional view along the BB' direction in Figure 12A.

[0129] The first through holes may correspond to the word lines 20 one by one, with each first through hole exposing one word line 20 . The connecting electrodes 60 may correspond to the word lines 20 one by one, with each connecting electrode 60 connected to one word line 20 .

[0130] In an exemplary embodiment, the connecting electrode 60 can be arranged in a boundary area (i.e., an area surrounding the memory array), and the connecting electrode 60 can be divided into two groups, which are respectively arranged on opposite sides, and the connecting electrodes 60 connected to adjacent word lines 20 are respectively arranged on different sides of the bit line 30. Taking four word lines as an example, the connecting electrode 60 connected to the first word line is arranged on the first side of the bit line 30, the connecting electrode 60 connected to the second word line is arranged on the second side of the bit line 30, the connecting electrode 60 connected to the third word line is arranged on the first side of the bit line 30, and the connecting electrode 60 connected to the fourth word line is arranged on the second side of the bit line 30, and so on. This is only an example, and the position of the connecting electrode 60 can be changed.

[0131] In an exemplary embodiment, depositing the second conductive film may include:

[0132] A seed layer comprising tantalum (Ta) or tantalum nitride (TaN) and copper (Cu) is deposited, a copper (Cu) film is formed on the seed layer by ECP, and the copper film is then polished, for example, by CMP. The second conductive film formed here is only an example and may comprise other conductive materials.

[0133] Through the above manufacturing process, a memory array including a plurality of transistors distributed in an array, a plurality of word lines 20 , and a plurality of bit lines 30 is formed on the first wafer.

[0134] 112) A second wafer is provided, and a logic circuit is formed on the second wafer. The first wafer including the memory array is flipped and bonded to the second wafer including the logic circuit, wherein the first wafer including the memory array is located above and the second wafer including the logic circuit is located below. The first wafer is bonded to the second wafer on the side away from the substrate 1. The second bonding pads 82 on the second wafer including the logic circuit are mirror-symmetrical with the first bonding pads 81 on the first wafer including the memory array. The first bonding pads 81 on the first wafer including the memory array include bonding pads for the bit lines 30 and connecting electrodes 60, as shown in FIG13. FIG13 (a) on the left side is a top view of the first wafer (before flipping), and FIG13 (b) on the right side is a top view of the second wafer. It can be seen that the second bonding pads 82 on the second wafer are mirror-symmetrical with the first bonding pads 81 on the first wafer. During bonding, the mirror-symmetrical first bonding pads 81 and second bonding pads 82 contact each other to achieve electrical connection. The bonding pad layout shown in FIG13 is only an example, and the electrical connection between the logic circuit and the memory array can be performed in other ways.

[0135] In an exemplary embodiment, the logic circuit may include, but is not limited to, a sense amplifier, a decoder, a voltage converter, and the like.

[0136] 113) The substrate 1 is etched away to expose the semiconductor column 10, and the height of the semiconductor column 10 is made smaller than the height of the first insulating layer 2, as shown in FIG14 . FIG14 is a schematic cross-sectional view along the AA' direction after etching the substrate 1, and FIG14 only shows the first wafer, and does not show the second wafer.

[0137] In an exemplary embodiment, the substrate 1 may be etched to a thickness of 1 μm to 2 μm by CMP, and then tetramethylammonium hydroxide (TMAH) may be used to perform more precise etching control on the substrate 1 and the semiconductor pillar 10 .

[0138] In an exemplary embodiment, a height difference d between the semiconductor pillar 10 and the first insulating layer 2 is, for example, 50 angstroms to 1000 angstroms.

[0139] 114) forming a connecting layer 40;

[0140] The forming of the connecting layer 40 may include: depositing a polysilicon thin film on the first wafer forming the aforementioned structure and then grinding it flat to form the connecting layer 40, as shown in Figure 15. Figure 15 is a schematic cross-sectional view along the AA' direction after the connecting layer 40 is formed, and Figure 15 only shows the first wafer, and does not show the second wafer.

[0141] In an exemplary embodiment, the polysilicon film may be highly phosphorus-doped polysilicon. The connection layer 40 may reduce the contact resistance between the first electrode plate formed subsequently and the first region 12 .

[0142] 115) forming a capacitor;

[0143] The forming of capacitance may include:

[0144] Depositing a first conductive material on the first wafer forming the aforementioned structure, and patterning to form a first electrode plate 41 disposed on the surface of the connecting layer 40;

[0145] Depositing a dielectric material on the first wafer forming the aforementioned structure to form a dielectric layer 70;

[0146] A second conductor material is deposited on the first wafer forming the aforementioned structure to form a second electrode 42, as shown in FIG16 , wherein FIG16 is a schematic cross-sectional view along the AA' direction after the capacitor is formed, and FIG16 only shows the first wafer, and does not show the second wafer.

[0147] In an exemplary embodiment, the first conductor material or the second conductor material may include or include at least one of a metal material (e.g., titanium, tantalum, tungsten, copper, and aluminum), a conductive metal nitride (e.g., titanium nitride and tantalum nitride), and a doped semiconductor material (e.g., doped silicon and doped germanium).

[0148] In an exemplary embodiment, the dielectric material includes, for example, a zirconium oxide (ZrO 2 ) / aluminum oxide (Al 2 O 3 ) / zirconium oxide (ZrO 2 ) stacked structure, hafnium oxide, or strontium titanate.

[0149] In an exemplary embodiment, the dielectric layer 70 of the capacitor connected to the transistor in the memory array may be connected to form an integrated structure.

[0150] In an exemplary embodiment, the second plates 42 of the capacitors connected to the transistors in the memory array may be connected to form an integrated structure, which may be, for example, a full-surface electrode.

[0151] In an exemplary embodiment, the first electrode plate 41 may be U-shaped along a cross section perpendicular to the substrate. The first electrode plate 41 may be cylindrical with one open end, and the second electrode plate 42 may fill an inner space of the cylindrical shape.

[0152] 116) depositing a fifth insulating film to form a sixth insulating layer covering the capacitor;

[0153] forming an extraction electrode penetrating the sixth insulating layer and the first wafer; the extraction electrode is connected to the logic circuit, the extraction electrode can be connected to an external circuit, and a signal can be subsequently loaded to the logic circuit through the extraction electrode;

[0154] A bonding bump (bumping pad) connected to the extraction electrode is formed to complete the preparation of the semiconductor device.

[0155] In one exemplary embodiment, the extraction electrode can be formed using through silicon via (TSV) technology. For example, a second via is formed that penetrates the sixth insulating layer and the first wafer and exposes the logic circuit. A seed layer comprising tantalum (Ta) or tantalum nitride (TaN) and copper (Cu) is deposited in the second via. A copper (Cu) film is formed on the seed layer by electrochemical processing (ECP). The copper film is then polished, for example, by carbon mechanical polishing (CMP), to form the extraction electrode.

[0156] In the above embodiments, the logic circuit and the memory array are distributed in different wafers. In other embodiments, the logic circuit and the memory array may be distributed in the same wafer. This will be explained below with examples.

[0157] In an exemplary embodiment, a process for manufacturing the semiconductor device may include:

[0158] Steps 201) to 209) are the same as steps 101) to 109), providing a first wafer, and forming transistors distributed in an array on the first wafer, that is, forming a memory array. The transistors may include a semiconductor pillar 10 extending in a direction perpendicular to the substrate 1, a gate electrode 21 surrounding the semiconductor pillar 10, and a gate insulating layer 14 disposed between the gate 21 and the semiconductor pillar 10. The semiconductor pillar 10 includes a channel region 11 and a first region 12 and a second region 13 disposed on either side of the channel region, respectively. The second region 13 is disposed on a side of the channel region 11 away from the substrate 1. In this embodiment, the substrate 1 includes a central region and a peripheral region surrounding the central region. The memory array is prepared in the central region, and the peripheral region can be protected using photoresist.

[0159] 210) forming a logic circuit in the peripheral area;

[0160] When preparing the logic circuit, photoresist can be used to protect the memory array.

[0161] In an exemplary embodiment, the logic circuit may include, but is not limited to, a sense amplifier, a decoder, a voltage converter, and the like.

[0162] 211) forming a bit line 30.

[0163] The formation of the bit line 30 may refer to step 110 , wherein the fourth insulating layer 5 is etched to form a groove exposing the semiconductor pillar 10 , namely a bit line groove; and a first conductive film is deposited in the bit line groove to form the bit line 30 .

[0164] 212) forming a connecting electrode 60;

[0165] The connection electrode 60 may be formed by referring to step 111 , wherein a through hole is formed to expose the word line 20 ; and a second conductive film is deposited in the through hole to form the connection electrode 60 .

[0166] 213) Realize the interconnection between logic circuits and storage arrays;

[0167] 214) Flip the first wafer including the memory array and the logic circuit and bond it to the blank second wafer, with the side of the first wafer away from the substrate 1 bonded to the second wafer, with the second wafer located at the bottom and the first wafer located at the top.

[0168] 215) to 217) are the same as 113) to 115) and are not described in detail. That is, a capacitor connected to the transistor is formed.

[0169] 218) depositing a fifth insulating film to form a sixth insulating layer covering the capacitor;

[0170] A lead-out electrode is formed that penetrates the sixth insulating layer; the lead-out electrode is connected to the logic circuit, the lead-out electrode can be connected to an external circuit, and a signal can be subsequently loaded to the logic circuit through the lead-out electrode.

[0171] A bonding bump connected to the lead-out electrode is formed to complete the preparation of the semiconductor device.

[0172] In an exemplary embodiment, the extraction electrode can be formed using TSV technology. For example, a through-hole is formed through the sixth insulating layer and exposes the logic circuit, a seed layer including tantalum (Ta) or tantalum nitride (TaN) and copper (Cu) is deposited in the through-hole, a copper (Cu) film is formed on the seed layer by ECP, and the copper film is then polished, for example, by CMP, to form the extraction electrode.

[0173] In the above embodiment, 1T1C is used as an example for description, but the embodiments of the present disclosure are not limited thereto. The transistor can be combined with other devices, for example, forming a 2T0C storage structure with another transistor, and so on.

[0174] In the above embodiment, instead of digging trenches at the bottom of the semiconductor pillar to form the bit lines, the bit lines are formed at the top of the semiconductor pillar and then flipped over. This greatly reduces the process difficulty, and the formed bit lines are highly uniform, less likely to form voids, and more stable in contact resistance. Compared with the solution of forming bit lines in bottom trenches, the solution provided by the embodiment of the present disclosure is less likely to produce voids in the insulating layer filled between the bit lines, which can avoid leakage between the bit lines. In addition, the size and shape of the bit lines are easier to control, which can facilitate control so that the size and shape of different bit lines in the same storage array are consistent, thereby reducing the resistance difference between different bit lines.

[0175] The present disclosure also provides an electronic device comprising the semiconductor device of the aforementioned embodiment. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power bank. The storage device may include, but is not limited to, computer memory.

[0176] FIG17 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown in FIG17 , an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes at least one transistor, wherein the transistor includes a semiconductor pillar, and the manufacturing method includes:

[0177] Step 1701, providing a first wafer, forming a substrate and a semiconductor column of the at least one transistor disposed on the substrate and extending in a direction perpendicular to the substrate, wherein the semiconductor column includes a channel region and a first region and a second region disposed on either side of the channel region, wherein the second region is disposed on a side of the channel region away from the substrate;

[0178] Step 1702: forming an insulating layer covering the semiconductor pillar, wherein the insulating layer has a groove exposing the second region, and forming a bit line in contact with the second region in the groove, wherein a contact surface between the bit line and the second region is parallel to the substrate;

[0179] Step 1703: provide a second wafer, flip the first wafer, bond the first wafer away from the substrate to the second wafer, and etch away the substrate to expose the first region.

[0180] The semiconductor device manufacturing method provided in this embodiment reduces process difficulty by fabricating bit lines on top of semiconductor pillars, improves bit line uniformity, avoids voids, and reduces bit line resistance. It also facilitates reliable ohmic contact between the bit lines and the semiconductor pillars, reducing contact resistance. Furthermore, the size and shape of different bit lines are more easily controlled, ensuring consistent size and shape, thereby stabilizing bit line resistance. The insulating layer between the bit lines is less likely to form voids, thus preventing leakage.

[0181] In an exemplary embodiment, before forming a bit line in contact with the second region, the method may further include:

[0182] A gate insulating layer surrounding the sidewall of the channel region and a gate electrode surrounding the sidewall of the gate insulating layer are sequentially formed.

[0183] In an exemplary embodiment, before bonding the side of the first wafer away from the substrate to the second wafer, the method further includes: forming a logic circuit on the second wafer.

[0184] In an exemplary embodiment, before forming the bit line contacting the second region, the method further includes: forming a logic circuit on the first wafer.

[0185] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A semiconductor device, comprising: at least one transistor, an insulating layer covering the transistor, and a bit line disposed on a side of the insulating layer away from the transistor; The transistor includes: a semiconductor column extending along a third direction, the semiconductor column including a channel region and a first region and a second region respectively arranged on both sides of the channel region; the insulating layer is provided with a groove exposing the second region, the bit line is arranged in the groove, the bit line is in contact with the second region, and the contact surface between the bit line and the second region is perpendicular to the third direction.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes a substrate, the third direction is perpendicular to the substrate, the substrate and the transistor are located on different wafers, and the second region is arranged on a side of the first region facing the substrate.

3. The semiconductor device according to claim 2, wherein: A surface of the bit line away from the semiconductor pillar is parallel to the substrate.

4. The semiconductor device according to claim 2, wherein: The semiconductor device includes a plurality of transistors arrayed along a first direction and a second direction, and a plurality of bit lines extending along the second direction, wherein the second regions of transistors in the same column distributed along the second direction are connected to the same bit line, and the first direction and the second direction intersect.

5. The semiconductor device according to claim 4, wherein: The insulating layer includes an insulating sublayer filled between the bit lines, and the insulating sublayer includes a low-K dielectric.

6. The semiconductor device according to claim 4, wherein: The transistor further includes: a gate electrode, the gate electrode surrounds the side wall of the channel region, and the gate electrodes of transistors in the same row distributed along the first direction are connected to form a word line.

7. The semiconductor device according to claim 6, wherein: The semiconductor device further comprises: a connecting electrode arranged on a side of the word line close to the substrate and extending in a direction perpendicular to the substrate, wherein one connecting electrode is connected to one word line.

8. The semiconductor device according to claim 7, wherein: The connection electrodes for connecting adjacent word lines are arranged on opposite sides of the bit line.

9. The semiconductor device according to any one of claims 2 to 8, wherein: The semiconductor device further includes: a logic circuit disposed between the substrate and the transistor, wherein an orthographic projection of the logic circuit overlaps with an orthographic projection of the transistor on a plane parallel to the substrate.

10. The semiconductor device according to any one of claims 2 to 8, wherein: The substrate includes a central area and a peripheral area surrounding the central area, the transistor is arranged in the central area, and the semiconductor device also includes: a logic circuit arranged in the peripheral area, and on a plane perpendicular to the substrate, the orthographic projection of the logic circuit overlaps with the orthographic projection of the transistor.

11. An electronic device comprising the semiconductor device according to any one of claims 1 to 10.

12. A method for manufacturing a semiconductor device, the semiconductor device comprising at least one transistor, the transistor comprising a semiconductor column, the manufacturing method comprising: Providing a first wafer, forming a substrate and a semiconductor column of the at least one transistor disposed on the substrate and extending in a direction perpendicular to the substrate, the semiconductor column comprising a channel region and a first region and a second region disposed on both sides of the channel region, respectively, wherein the second region is disposed on a side of the channel region away from the substrate; forming an insulating layer covering the semiconductor column, wherein the insulating layer is provided with a groove exposing the second region, and a bit line contacting the second region is formed in the groove, wherein a contact surface between the bit line and the second region is parallel to the substrate; A second wafer is provided, the first wafer is turned over, a side of the first wafer away from the substrate is bonded to the second wafer, and the substrate is removed by etching to expose the first region.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: Before forming a bit line contacting the second region, the method further includes: A gate insulating layer surrounding the sidewall of the channel region and a gate electrode surrounding the sidewall of the gate insulating layer are sequentially formed.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: Before bonding the first wafer with the second wafer at a side away from the substrate, the method further includes: forming a logic circuit on the second wafer.

15. The method for manufacturing a semiconductor device according to claim 12, wherein: Before forming the bit line contacting the second region, the method further includes: forming a logic circuit on the first wafer.

Images