Magnetoresistive memory unit, preparation method, array circuit, and binary neural network chip

Abstract

A magnetoresistive memory unit, a preparation method, an array circuit, and a binary neural network chip. The magnetoresistive memory unit comprises a heavy metal layer configured to input a write current; a first magnetic tunnel junction, arranged on one side of a bottom surface of the heavy metal layer, a first preset included angle being formed between the easy axis of the first magnetic tunnel junction and an input direction of the write current; and a second magnetic tunnel junction, arranged on the other side of the bottom surface of the heavy metal layer, a second preset included angle being formed between the easy axis of the second magnetic tunnel junction and the input direction of the write current. The first magnetic tunnel junction and the second magnetic tunnel junction are configured to input a read current.

Description

Magnetoresistive memory unit, preparation method, array circuit and binary neural network chip Technical Field

[0001] The present disclosure relates to the technical field of magnetoresistive memory, and more specifically, to a magnetoresistive memory unit, a method for preparing a magnetoresistive memory unit, an array circuit based on the magnetoresistive memory unit, and a binary neural network chip. Background Art

[0002] Convolutional Neural Networks (CNNs) have been widely used in a variety of fields, including image recognition, speech recognition, and natural language processing, demonstrating excellent performance. However, the large number of vector-matrix multiplication and addition operations, resulting in significant storage and computational overhead, has limited the hardware implementation of large-scale CNNs. Consequently, binary neural networks (BNNs) have garnered increasing attention in recent years.

[0003] Binary neural networks simplify computational tasks by binarizing the synaptic weights and neuron outputs of convolutional neural networks (CNNs), replacing high-precision multiplication and addition operations with dot products. While reducing storage and computational resource overhead, they achieve comparable accuracy to convolutional neural networks on various large-scale datasets. Hardware neural networks based on traditional von Neumann architectures are hindered by memory and power consumption bottlenecks, hindering large-scale integration and application. To overcome the von Neumann bottleneck, in-memory computing (IMC) has emerged as a new computing paradigm. In recent years, the development of in-memory computing platforms based on new non-volatile memories has ushered in a new era of development for hardware neural networks. Among various new non-volatile memories, SOT-MRAM (Spin-Orbit Torque Magnetic Random Access Memory) has become an ideal platform for in-memory computing and hardware neural network implementation due to its high read and write speeds, unlimited erase and write cycles, high data retention, low write power consumption, and compatibility with CMOS (Complementary Metal Oxide Semiconductor) processes.

[0004] However, SOT-MRAM currently has the following problems:

[0005] (1) Small tunneling magnetoresistance (TMR);

[0006] (2) Type x and type z SOT-MRAM require an external magnetic field to assist in electrically controlled magnetization reversal.

[0007] The low tunnel magnetoresistance limits the read performance of SOT-MRAM, resulting in a higher error rate, while the external magnetic field is not conducive to large-scale integration.

[0008] Summary of the Invention

[0009] In view of this, embodiments of the present disclosure provide a magnetoresistive memory unit, a method for preparing a magnetoresistive memory unit, an array circuit based on the magnetoresistive memory unit, and a binary neural network chip.

[0010] One aspect of an embodiment of the present disclosure provides a magnetoresistive memory cell, comprising:

[0011] a heavy metal layer configured to input a write current;

[0012] A first magnetic tunnel junction is provided on one side of the bottom surface of the heavy metal layer, wherein the easy axis of the first magnetic tunnel junction forms a first preset angle with the input direction of the write current;

[0013] A second magnetic tunnel junction is provided on the other side of the bottom surface of the heavy metal layer, wherein the easy axis of the second magnetic tunnel junction forms a second preset angle with the input direction of the write current;

[0014] The first magnetic tunnel junction and the second magnetic tunnel junction are configured to input a read current.

[0015] According to an embodiment of the present disclosure, the first preset angle is complementary to the second preset angle, and the first preset angle is in a range of 10° to 60°.

[0016] According to an embodiment of the present disclosure, any one of the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0017] bottom electrode;

[0018] a pinning layer disposed on a top surface of the bottom electrode, wherein the pinning layer is configured to fix the magnetization direction of the ferromagnetic reference layer;

[0019] The ferromagnetic reference layer is arranged on the top surface of the pinned layer;

[0020] a barrier layer, disposed on top of the ferromagnetic reference layer;

[0021] a ferromagnetic free layer, disposed on top of the barrier layer;

[0022] According to an embodiment of the present disclosure, the pinning layer includes:

[0023] an antiferromagnetic layer or a synthetic ferrimagnetic layer or a synthetic antiferromagnetic layer, disposed on the top surface of the bottom electrode;

[0024] A space layer is arranged on the top surface of the above-mentioned antiferromagnetic layer or synthetic ferrimagnetic layer or synthetic antiferromagnetic layer, wherein the above-mentioned space layer is constructed to couple the magnetization directions of the above-mentioned ferromagnetic reference layer and the above-mentioned antiferromagnetic layer or synthetic ferrimagnetic layer or synthetic antiferromagnetic layer.

[0025] Another aspect of the present disclosure provides a method for preparing a magnetoresistive memory cell, comprising:

[0026] Performing patterning on the initial thin film behind the hard mask to obtain a patterned thin film, wherein the initial thin film is used to generate a first magnetic tunnel junction and a second magnetic tunnel junction;

[0027] Etching the patterned thin film to obtain an initial memory cell, wherein the initial memory cell includes the first magnetic tunnel junction and the second magnetic tunnel junction, and the first magnetic tunnel junction and the second magnetic tunnel junction form a first preset angle and a second preset angle with the initial thin film, respectively;

[0028] growing a heavy metal layer on the top surface of the initial memory cell;

[0029] A top electrode and a bottom electrode are grown on the top surface of the heavy metal layer and the bottom surface of the initial memory unit respectively, so as to obtain the magnetoresistive memory unit.

[0030] According to an embodiment of the present disclosure, the initial thin film is generated by forming a pinned layer, a ferromagnetic reference layer, a barrier layer, and a ferromagnetic free layer;

[0031] According to an embodiment of the present disclosure, etching the patterned thin film to obtain an initial memory cell includes:

[0032] Performing a first etching on the patterned thin film to the insulating substrate to obtain an effective device area;

[0033] The effective device region is etched a second time, etching to the bottom electrode to obtain a magnetic tunnel junction, wherein the magnetic tunnel junction includes a first magnetic tunnel junction and a second magnetic tunnel junction, and the initial memory cell includes the magnetic tunnel junction.

[0034] According to an embodiment of the present disclosure, etching the patterned thin film to obtain an initial memory cell further includes:

[0035] growing an insulating protective layer on the effective device region to obtain an insulating magnetic tunnel junction;

[0036] polishing the insulated magnetic tunnel junction to obtain a polished magnetic tunnel junction;

[0037] Performing hard mask patterning on the polished magnetic tunnel junction to obtain a patterned magnetic tunnel junction, and performing a second etching on the patterned magnetic tunnel junction to obtain a transitional memory cell;

[0038] growing an insulating protective layer on the transitional memory cell to obtain an insulating memory cell;

[0039] The insulated memory cell is polished to obtain the initial memory cell.

[0040] Another aspect of the present disclosure provides an array circuit based on a magnetoresistive memory cell, comprising:

[0041] a plurality of line groups arranged vertically and spaced apart, each line group including a write word line, a first read word line and a second read word line spaced apart by a preset distance, and a source line;

[0042] a plurality of bit line groups arranged horizontally at intervals, wherein the bit line groups include write control bit lines and read control bit lines arranged horizontally from top to bottom, the write control bit lines and read control bit lines in one bit line group, the first read word line and the second read word line in each line group forming a placement area;

[0043] A plurality of magnetoresistive memory cells, one magnetoresistive memory cell being disposed in each of the placement regions;

[0044] The connection method of the magnetoresistive memory unit, the line group corresponding to the placement area, and the bit line includes:

[0045] One end of the heavy metal layer is connected to the write control bit line and the write word line respectively through the first transistor, and the other end is connected to the source line;

[0046] The first magnetic tunnel junction is connected to the first read word line and the read control bit line through the second transistor, and the second magnetic tunnel junction is connected to the second read word line and the read control bit line through the third transistor.

[0047] According to an embodiment of the present disclosure, the source and drain of the first transistor are connected to the heavy metal layer and the write word line respectively, and the gate of the first transistor is connected to the write control bit line;

[0048] The source and drain of the second transistor are connected to the first magnetic tunnel junction and the first read word line respectively, and the gate of the second transistor is connected to the read control bit line;

[0049] A source and a drain of the third transistor are connected to the second magnetic tunnel junction and the second read word line respectively, and a gate of the third transistor is connected to the read control bit line.

[0050] Another aspect of the embodiments of the present disclosure provides a binary neural network chip, comprising: a decoding unit, a cache unit, an instruction storage unit, a storage and calculation unit, a data processing unit, and a clock unit;

[0051] Among them, the above-mentioned storage and computing unit includes a synaptic array constructed by an array circuit, the above-mentioned array circuit includes multiple columns of magnetoresistive memory unit groups, each column of the above-mentioned magnetoresistive memory unit group includes multiple magnetoresistive memory units, and each column of the above-mentioned magnetoresistive memory unit group is constructed to store the synaptic weight of a neuron.

[0052] According to an embodiment of the present disclosure, for each column of the magnetoresistive memory cell group, when a read current of the first magnetic tunnel junction of the magnetoresistive memory cell is greater than a read current of the magnetoresistive memory cell, a synaptic weight of the magnetoresistive memory cell is determined to be a positive target value;

[0053] determining a negative target value for the synaptic weight of the magnetoresistive memory cell when a read current of the first magnetic tunnel junction of the magnetoresistive memory cell is less than a read current of the magnetoresistive memory cell;

[0054] When the sum of the synaptic weights of the plurality of magnetoresistive memory units is a positive number, the neuron outputs a first value;

[0055] When the sum of the synaptic weights of the plurality of magnetoresistive memory units is a negative number, the neuron outputs a second value.

[0056] The magnetoresistive memory unit, preparation method, array circuit, and binary neural network chip disclosed in the present invention have the following effects:

[0057] (1) In the magnetoresistive storage unit, since the first magnetic tunnel junction and the second magnetic tunnel junction are arranged on the lower side of the metal layer and are deflected by the first preset angle and the second preset angle respectively, ultrafast magnetization reversal can be achieved without the assistance of an external magnetic field, which is conducive to large-scale integration.

[0058] (2) The magnetoresistive memory cell adopts a 1HM2SOT-MTJ (one heavy metal layer, two spin-orbit moment magnetic tunnel junctions) structure. The resistance states of the first and second magnetic tunnel junctions are always opposite after reversal, forming a complementary structure to store one bit. When reading information, it can be read through a self-reference mechanism, improving the read margin, thereby enhancing read reliability and reducing read latency. In addition, it does not require an external magnetic field to achieve reversal during operation.

[0059] (3) The magnetoresistive memory cell uses a pinned layer as the bottom pinning structure, which is beneficial to the subsequent regulation of the heavy metal layer and the heavy metal layer\ferromagnetic free layer interface, thereby optimizing the read performance.

[0060] (4) Magnetoresistive memory cells can realize a 1R1W (one read, one write) dual-port storage array based on 3T2SOT-MTJ (three transistors, two spin-orbit moment magnetic tunnel junctions), which can read and write in blocks simultaneously, greatly improving the read and write efficiency and increasing the parallelism of storage cells.

[0061] (5) The storage and calculation unit of the binary neural network chip can read the entire column when reading, and realize the summation of synaptic weights at the same time. The output of the storage and calculation unit can be directly used as the output of the binary neuron, which greatly improves the parallelism of the binary neural network. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0063] FIG1 schematically shows a schematic structural diagram of a magnetoresistive memory unit according to an embodiment of the present disclosure;

[0064] FIG2 schematically shows a relationship diagram between a first preset angle and a second preset angle according to an embodiment of the present disclosure;

[0065] FIG3 schematically shows a schematic diagram of a process for preparing a magnetoresistive memory cell according to an embodiment of the present disclosure;

[0066] FIG4 schematically shows a structural diagram of an array circuit according to an embodiment of the present disclosure;

[0067] FIG5 schematically shows a structural diagram of a 3T2SOT-MTJ unit structure according to an embodiment of the present disclosure;

[0068] FIG6 schematically shows a simulation result diagram of an array circuit according to an embodiment of the present disclosure;

[0069] FIG7 schematically shows a structural diagram of a binary neural network chip according to an embodiment of the present disclosure; and

[0070] FIG8 schematically shows a corresponding relationship between the storage state of a magnetoresistive memory unit and a synaptic weight according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0072] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0073] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0074] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. Additionally, if a layer / element is "on top of" another layer / element in one orientation, it can be "under" the other layer / element when the orientation is reversed.

[0075] When expressions such as "at least one of A, B and C, etc." are used, they should generally be interpreted in accordance with the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0076] Embodiments of the present disclosure provide a magnetoresistive memory cell, a method for fabricating a magnetoresistive memory cell, an array circuit based on the magnetoresistive memory cell, and a binary neural network chip. The magnetoresistive memory cell includes a heavy metal layer configured to input a write current; a first magnetic tunnel junction disposed on one side of a bottom surface of the heavy metal layer, wherein the easy axis of the first magnetic tunnel junction forms a first preset angle with the input direction of the write current; and a second magnetic tunnel junction disposed on the other side of the bottom surface of the heavy metal layer, wherein the easy axis of the second magnetic tunnel junction forms a second preset angle with the input direction of the write current. The first and second magnetic tunnel junctions are configured to input a read current.

[0077] Fig. 1 schematically shows a schematic diagram of the structure of a magnetoresistive memory unit according to an embodiment of the present disclosure. Fig. 2 schematically shows a schematic diagram of the relationship between a first preset angle and a second preset angle according to an embodiment of the present disclosure.

[0078] As shown in Figure 1, the magnetoresistive memory cell includes:

[0079] a heavy metal layer configured to input a write current;

[0080] A first magnetic tunnel junction is provided on one side of the bottom surface of the heavy metal layer, wherein the easy axis of the first magnetic tunnel junction forms a first preset angle with the input direction of the write current;

[0081] a second magnetic tunnel junction, disposed on the other side of the bottom surface of the heavy metal layer, wherein the easy axis of the second magnetic tunnel junction forms a second preset angle with the input direction of the write current;

[0082] The first magnetic tunnel junction and the second magnetic tunnel junction are configured to input a read current.

[0083] According to an embodiment of the present disclosure, the preset angle is the angle between the projection of the easy axis on the plane of the heavy metal layer and the input direction of the write current. The first preset angle and the second preset angle are deflected in opposite directions relative to the direction of the write current and are equal in magnitude.

[0084] In one possible implementation, the cross-sections of the first and second magnetic tunnel junctions are both elliptical. It should be noted that the elliptical shape in this embodiment is optimally a strict ellipse; however, due to process limitations, the elliptical shape may also refer to a generally elliptical shape. The first and second magnetic tunnel junctions can be elliptical cylinders as a whole. With this shape, the easy axis of the ferromagnetic layer of a magnetic tunnel junction will be aligned with the major axis of the ellipse due to shape anisotropy.

[0085] In a possible implementation, as shown in FIG2 , the first preset angle and the second preset angle The magnitudes of the first and second magnetic tunnel junctions should be equal to ensure the same write characteristics. Furthermore, the first and second preset angles can be determined to range from 10° to 60°, ensuring a suitable threshold current. When only current passes through, the magnetic tunnel junction can flip.

[0086] It should be noted that the cross-section of the magnetic tunnel junction can be not only an ellipse as in the above example, but can also be other shapes, such as a rectangle.

[0087] According to the embodiments of the present disclosure, in the magnetoresistive storage unit, since the first magnetic tunnel junction and the second magnetic tunnel junction are arranged on the lower side of the metal layer and are deflected by the first preset angle and the second preset angle respectively, ultrafast magnetization reversal without the assistance of an external magnetic field can be achieved, which is conducive to large-scale integration.

[0088] According to an embodiment of the present disclosure, either the first magnetic tunnel junction or the second magnetic tunnel junction (MTJ) includes:

[0089] bottom electrode;

[0090] a pinning layer disposed on a top surface of the bottom electrode, wherein the pinning layer is configured to fix a magnetization direction of the ferromagnetic reference layer;

[0091] The ferromagnetic reference layer is arranged on the top surface of the pinned layer;

[0092] a barrier layer, disposed on a top surface of the ferromagnetic reference layer;

[0093] a ferromagnetic free layer, disposed on a top surface of the barrier layer;

[0094] According to an embodiment of the present disclosure, the pinning layer includes:

[0095] an antiferromagnetic layer or a synthetic ferrimagnetic layer or a synthetic antiferromagnetic layer, disposed on the top surface of the bottom electrode;

[0096] A space layer is arranged on the top surface of the antiferromagnetic layer or the synthetic ferrimagnetic layer or the synthetic antiferromagnetic layer, wherein the space layer is configured to couple the magnetization directions of the ferromagnetic reference layer and the antiferromagnetic layer or the synthetic ferrimagnetic layer or the synthetic antiferromagnetic layer.

[0097] According to an embodiment of the present disclosure, the magnetization directions of the ferromagnetic reference layers in the first magnetic tunnel junction and the second magnetic tunnel junction are the same along the write current direction.

[0098] According to an embodiment of the present disclosure, the pinned layer is a stacked multilayer structure and can be antiferromagnetic, synthetic antiferromagnetic, synthetic ferrimagnetic, etc. The ferromagnetic reference layer and the ferromagnetic free layer can be one of cobalt (Co), cobalt boride (CoB), iron boride (FeB), cobalt iron boron (CoFeB), Permalloy (NiFe), van der Waals two-dimensional materials, topological materials, etc., or a combination thereof. The barrier layer can be magnesium oxide (MgO), aluminum oxide (Al2O3), etc. The heavy metal (SOC) layer can be composed of a heavy metal material. For example, any one of platinum (Pt), tantalum (Ta), and tungsten (W) or an alloy thereof can be used.

[0099] According to the embodiments of the present disclosure, since the first and second magnetic tunnel junctions are in an antisymmetric state, when a write current passes through the heavy metal layer, the magnetization directions of the ferromagnetic free layers in the first and second magnetic tunnel junctions are always opposite, which can make the resistance states of the two magnetic tunnel junctions always opposite and complementary. In this way, after passing write currents in different directions, the first and second magnetic tunnel junctions can be made to exhibit a high-resistance state or a low-resistance state, respectively. When a read current is passed through the first and second magnetic tunnel junctions, the stored resistance state can be obtained by comparing the read current magnitudes of the two magnetic tunnel junctions. During the entire read and write process, the write current can achieve ultrafast magnetization reversal at the sub-nanosecond level without the need for external magnetic field assistance.

[0100] According to the embodiments of the present disclosure, the magnetoresistive memory cell adopts a pinning layer as a bottom pinning structure, which is beneficial to the subsequent regulation of the heavy metal layer and the heavy metal layer / ferromagnetic free layer interface, thereby optimizing the read performance.

[0101] According to an embodiment of the present disclosure, when performing a write operation on a magnetoresistive memory cell, the process is as follows:

[0102] A write current is passed through the heavy metal layer in a first direction, causing the magnetoresistive memory cell to assume a first storage state; the first storage state is: the first magnetic tunnel junction is in a high resistance state, and the second magnetic tunnel junction is in a low resistance state. For example, when the magnetization directions of the ferromagnetic reference layers of the first and second magnetic tunnel junctions are both in the +x direction (i.e., the magnetization component of the ferromagnetic reference layer along the x-axis is positive), and the first direction is the +x direction, the magnetization direction of the first magnetic tunnel junction is in the -x direction, and the magnetization direction of the second magnetic tunnel junction is in the +x direction. At this time, in the first magnetic tunnel junction, the magnetization directions of the ferromagnetic free layer and the ferromagnetic reference layer are antiparallel, and the first magnetic tunnel junction is in a high resistance state; in the second magnetic tunnel junction, the magnetization directions of the ferromagnetic free layer and the ferromagnetic reference layer are parallel, and the second magnetic tunnel junction is in a low resistance state.

[0103] Alternatively, a write current is passed through the heavy metal layer along a second direction to make the magnetoresistive memory unit present in a second storage state; the second storage state is: the first magnetic tunnel junction is in a low resistance state, and the second magnetic tunnel junction is in a high resistance state; wherein the first direction and the second direction are opposite.

[0104] For example, when the ferromagnetic reference layers of the first and second magnetic tunnel junctions are both oriented in the +x direction, and the first direction is the -x direction, the magnetization direction of the first magnetic tunnel junction is in the +x direction, and the magnetization direction of the second magnetic tunnel junction is in the -x direction. In this case, in the first magnetic tunnel junction, the magnetization directions of the ferromagnetic free layer and the ferromagnetic reference layer are parallel, and the first magnetic tunnel junction is in a low-resistance state. In the second magnetic tunnel junction, the magnetization directions of the ferromagnetic free layer and the ferromagnetic reference layer are antiparallel, and the second magnetic tunnel junction is in a high-resistance state.

[0105] According to an embodiment of the present disclosure, a 3T2SOT-MTJ cell structure is prepared by multiple transistors and magnetoresistive memory cells. The multiple transistors enable the read operation circuit and the write operation circuit of the magnetoresistive memory cell to be independently controlled. Based on this characteristic, a 1R1W (one read and one write) dual-port storage array can be realized, which can greatly improve the read and write efficiency and increase the parallelism of the magnetoresistive memory cells.

[0106] FIG3 schematically shows a schematic diagram of a preparation process of a magnetoresistive memory unit according to an embodiment of the present disclosure.

[0107] As shown in FIG3 , the method for preparing a magnetoresistive memory cell includes:

[0108] Performing patterning on the initial thin film behind the hard mask to obtain a patterned thin film, wherein the initial thin film is used to generate a first magnetic tunnel junction and a second magnetic tunnel junction;

[0109] Etching the patterned thin film to obtain an initial memory cell, wherein the initial memory cell includes the first magnetic tunnel junction and the second magnetic tunnel junction, and the first magnetic tunnel junction and the second magnetic tunnel junction form a first preset angle and a second preset angle with the initial thin film, respectively;

[0110] growing a heavy metal layer on a top surface of the initial memory cell;

[0111] A top electrode and a bottom electrode are grown on the top surface of the heavy metal layer and the bottom surface of the initial memory cell respectively to obtain the magnetoresistive memory cell.

[0112] According to an embodiment of the present disclosure, the initial thin film is generated by stacking a pinned layer, a ferromagnetic reference layer, a barrier layer, and a ferromagnetic free layer in sequence;

[0113] According to an embodiment of the present disclosure, as shown in FIG3 , etching the patterned thin film to obtain an initial memory cell includes:

[0114] Performing a first etching on the patterned thin film, etching down to the insulating substrate, to obtain an effective device area;

[0115] The effective device region is etched a second time, etching to the bottom electrode to obtain a magnetic tunnel junction, the magnetic tunnel junction including a first magnetic tunnel junction and a second magnetic tunnel junction, and the initial memory cell includes the magnetic tunnel junction.

[0116] According to an embodiment of the present disclosure, as shown in FIG3 , etching the patterned thin film to obtain an initial memory cell further includes:

[0117] growing an insulating protective layer on the effective device region to obtain an insulating magnetic tunnel junction;

[0118] polishing the insulated magnetic tunnel junction to obtain a polished magnetic tunnel junction;

[0119] Performing hard mask patterning on the polished magnetic tunnel junction to obtain a patterned magnetic tunnel junction, and performing a second etching on the patterned magnetic tunnel junction to obtain a transitional memory cell;

[0120] growing an insulating protective layer on the transitional memory cell to obtain an insulating memory cell;

[0121] The insulated memory cell is polished to obtain the initial memory cell.

[0122] Figure 4 schematically shows a schematic structural diagram of an array circuit according to an embodiment of the present disclosure. Figure 5 schematically shows a schematic structural diagram of a 3T2SOT-MTJ unit structure according to an embodiment of the present disclosure.

[0123] As shown in FIG4 , the array circuit based on the magnetoresistive memory cell includes:

[0124] A plurality of line groups arranged vertically and spaced apart, each line group including a write word line WBLn, a first read word line RBLn and a second read word line / RBLn spaced apart by a predetermined distance, and a source line SLn;

[0125] a plurality of bit line groups arranged horizontally at intervals, wherein the bit line groups include write control bit lines WWLn and read control bit lines RWLn arranged horizontally from top to bottom, the write control bit lines and read control bit lines in one bit line group, and the first read word lines and the second read word lines in each line group forming a placement area;

[0126] a plurality of magnetoresistive memory cells, one magnetoresistive memory cell being arranged in each of the placement areas;

[0127] The connection method of the magnetoresistive memory unit, the line group corresponding to the placement area, and the bit line includes:

[0128] One end of the heavy metal layer is connected to the write control bit line and the write word line respectively through a first transistor, and the other end is connected to the source line;

[0129] The first magnetic tunnel junction is connected to the first read word line and the read control bit line respectively through the second transistor, and the second magnetic tunnel junction is connected to the second read word line and the read control bit line respectively through the third transistor.

[0130] According to an embodiment of the present disclosure, the source and drain of the first transistor are connected to the heavy metal layer and the write word line respectively, and the gate of the first transistor is connected to the write control bit line;

[0131] The source and drain of the second transistor are connected to the first magnetic tunnel junction and the first read word line respectively, and the gate of the second transistor is connected to the read control bit line;

[0132] A source and a drain of the third transistor are connected to the second magnetic tunnel junction and the second read word line respectively, and a gate of the third transistor is connected to the read control bit line.

[0133] According to an embodiment of the present disclosure, an array circuit is constructed based on multiple 3T2SOT-MTJ cell structures as shown in Figure 5. The 3T2SOT-MTJ cell structure includes a first transistor T1, a second transistor T2, a third transistor T3, and a magnetoresistive memory cell. The first transistor T1 is connected to the first end of the heavy metal layer in the lateral direction, and the second end of the heavy metal layer in the lateral direction serves as an input end or an output end. The second transistor T2 is connected to the side of the first magnetic tunnel junction away from the heavy metal layer, and the third transistor T3 is connected to the side of the second magnetic tunnel junction away from the heavy metal layer. The drains of the second transistor T2 and the third transistor T3 are also connected to the first read word line RBL and the second read word line / RBL, respectively, and the word lines are used to provide read current.

[0134] The gates of the second and third transistors T2 and T3 are connected to a read control bit line RWL. The read control bit line provides a signal that controls the on / off switching of the second and third transistors T2 and T3. The drain of the first transistor T1 is connected to a write word line WBL. The gate of the first transistor T1 is connected to a write control bit line WWL. The write control bit line provides a signal that controls the on / off switching of the first transistor T1. The second end of the heavy metal layer can function as an input or output by connecting to a source line SL.

[0135] According to the embodiments of the present disclosure, the magnetoresistive memory unit can realize a 1R1W (one read and one write) dual-port storage array based on 3T2SOT-MTJ (3 transistors, 2 spin-orbit moment magnetic tunnel junctions), which can read and write in blocks simultaneously, greatly improving the read and write efficiency and increasing the parallelism of the storage unit.

[0136] FIG6 schematically shows a simulation result diagram of an array circuit according to an embodiment of the present disclosure.

[0137] According to an embodiment of the present disclosure, the array circuit constructed as shown in Figure 4 can implement a write operation on the first row and first column (1, 1) 3T2SOT-MTJ cell structure and a read operation on the nth row and second column (n, 2) 3T2SOT-MTJ cell structure within the same clock cycle, with simulation results shown in Figure 6. As can be seen from Figures 4 and 6, the circuits for the read and write operations of the magnetoresistive memory cell can be independently controlled through the first transistor T1, the second transistor T2, and the third transistor T3. Based on this characteristic, a 1R1W (one read, one write) dual-port memory array can be implemented, which can greatly improve read and write efficiency and increase the parallelism of the magnetoresistive memory cells.

[0138] Table 1

[0139] According to the embodiment of the present disclosure, as shown in the operation table in Table 1: when writing, the level of the write control bit line can be pulled high and the level of the read control bit line can be pulled low, so that the second transistor T2 and the third transistor T1 are turned off and the first transistor T1 is turned on. Then, according to the information to be written (0 / 1), the level of the write word line is pulled up to V write (0), the source line level is set to 0 (V write ), a current path is formed between the drain and source of the first transistor T1, flowing through the heavy metal layer. The heavy metal layer converts the current along the x-axis into a spin current with spin polarization along the y-axis through the spin Hall effect or the Rashaba-Edelstein effect. This spin current is injected into the ferromagnetic free layer along the z-axis, generating a spin-orbit moment that flips the magnetization of the ferromagnetic free layer, enabling data writing. The writing process is completed in a single step, with high efficiency and speed.

[0140] According to the embodiments of the present disclosure, when performing a read operation on a magnetoresistive memory cell, the write control bit line can be controlled to be pulled low and the read control bit line to be pulled high, turning on the second transistor T2 and the third transistor T3 and turning off the first transistor T1. Simultaneously, the source line is connected to a low level. This creates a current path through the first magnetic tunnel junction between the first read word line and the source line, and a current path through the second magnetic tunnel junction between the second read word line and the source line. The currents on the first and second read word lines can be fed into a current-mode sense amplifier for comparison and reading the storage state of the memory cell.

[0141] FIG7 schematically shows a structural diagram of a binary neural network chip according to an embodiment of the present disclosure.

[0142] As shown in Figure 7, the binary neural network chip includes: a decoding unit, a cache unit, an instruction storage unit, a storage and calculation unit, a data processing unit and a clock unit;

[0143] The storage and computing unit includes a synaptic array constructed by an array circuit, the array circuit includes multiple columns of magnetoresistive memory cell groups, each column of the magnetoresistive memory cell group includes multiple magnetoresistive memory cells, and each column of the magnetoresistive memory cell group is constructed to store the synaptic weight of a neuron.

[0144] According to an embodiment of the present disclosure, Figure 7 illustrates a binary neural network chip based on a 3T2SOT-MTJ memory-computation unit (MMU) with a magnetoresistive memory cell. This chip can be used for speech recognition. The synaptic array in the 3T2SOT-MTJ memory-computation unit enables synaptic weight storage, updates, and bit-by-bit operations. The output of each column of sense amplifiers serves as the output of the neurons in that layer and is fed into the next layer.

[0145] FIG8 schematically shows a corresponding relationship between the storage state of a magnetoresistive memory unit and a synaptic weight according to an embodiment of the present disclosure.

[0146] According to an embodiment of the present disclosure, for each column of the magnetoresistive memory cell group, when a read current of the first magnetic tunnel junction of the magnetoresistive memory cell is greater than a read current of the magnetoresistive memory cell, determining a target positive value for the synaptic weight of the magnetoresistive memory cell;

[0147] determining a negative target value for the synaptic weight of the magnetoresistive memory cell when a read current of the first magnetic tunnel junction of the magnetoresistive memory cell is less than a read current of the magnetoresistive memory cell;

[0148] When the sum of the synaptic weights of the plurality of magnetoresistive memory units is a positive number, the neuron outputs a first value;

[0149] When the sum of the synaptic weights of the plurality of magnetoresistive memory cells is a negative number, the neuron outputs a second value.

[0150] According to an embodiment of the present disclosure, the target value can be specifically set according to actual needs, for example, it can be 1.

[0151] According to the embodiments of the present disclosure, the storage and computing unit of the binary neural network chip can read the entire column during reading, and realize the summation of synaptic weights while reading. The output of the storage and computing unit can be directly used as the output of the binary neuron, which greatly improves the parallelism of the binary neural network.

[0152] According to an embodiment of the present disclosure, FIG8 shows the correspondence between the storage state and the synaptic weight of the magnetoresistive memory cell, and the following algorithm definition can be performed: When the input signal is 0, the second transistor and the third transistor are cut off, and no current flows through the magnetic tunnel junction. At this time, no matter how the resistance of the first magnetic tunnel junction and the second magnetic tunnel junction are configured, the current on the bit line is 0. When the input signal is 1, the second transistor and the third transistor are turned on. When the first magnetic tunnel junction is low resistance and the second magnetic tunnel junction is high resistance, the synaptic weight is 1, corresponding to the read current IBL>IBL_bar. When the first magnetic tunnel junction is high resistance and the second magnetic tunnel junction is low resistance, the synaptic weight is "-1", corresponding to the read current IBL <IBL_bar。

[0153] In an alternative embodiment, other definitions can be made. For example, when IBL > IBL_bar, the synaptic weight corresponds to "-1", and when IBL < IBL_bar, the synaptic weight corresponds to "1", without limitation. When reading, multiple read control lines are activated simultaneously for column - wide reading. In the array structure, each column of magnetoresistive memory cells shares a source line and a sense amplifier. When performing a read operation, reading is done on a column - by - column basis. The read current on the first read word line or the second read word line is mainly generated by the read current of the magnetoresistive memory cells in the low - resistance state. Therefore, the difference between the current IBL_bar of the first read word line and the current / IBL_bar of the second read word line reflects the difference in the number of magnetoresistive memory cells in the low - resistance state in the two columns of word lines. That is, it corresponds to the sum of the synaptic weights of the magnetoresistive memory cells on one column. For each neuron, the output of the sense amplifier can be directly used as the output of a binary neuron. It can be defined that when the sum of the weights is positive, the output is "1", and when it is negative, the output is "0".

[0154] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A magnetoresistive memory cell, comprising: a heavy metal layer configured to input a write current; A first magnetic tunnel junction is provided on one side of the bottom surface of the heavy metal layer, wherein the easy axis of the first magnetic tunnel junction forms a first preset angle with the input direction of the write current; a second magnetic tunnel junction, disposed on the other side of the bottom surface of the heavy metal layer, wherein the easy axis of the second magnetic tunnel junction forms a second preset angle with the input direction of the write current; The first magnetic tunnel junction and the second magnetic tunnel junction are configured to input a read current.

2. The magnetoresistive memory cell according to claim 1, wherein The first preset angle is complementary to the second preset angle, and the first preset angle ranges from 10° to 60°.

3. The magnetoresistive memory cell according to claim 1 , wherein: Any one of the first magnetic tunnel junction and the second magnetic tunnel junction includes: bottom electrode; a pinning layer disposed on a top surface of the bottom electrode, wherein the pinning layer is configured to fix a magnetization direction of the ferromagnetic reference layer; The ferromagnetic reference layer is arranged on the top surface of the pinned layer; a barrier layer, disposed on a top surface of the ferromagnetic reference layer; a ferromagnetic free layer, disposed on a top surface of the barrier layer; Wherein, the pinning layer includes: an antiferromagnetic layer or a synthetic ferrimagnetic layer or a synthetic antiferromagnetic layer, disposed on the top surface of the bottom electrode; A space layer is arranged on the top surface of the antiferromagnetic layer or the synthetic ferrimagnetic layer or the synthetic antiferromagnetic layer, wherein the space layer is configured to couple the magnetization directions of the ferromagnetic reference layer and the antiferromagnetic layer or the synthetic ferrimagnetic layer or the synthetic antiferromagnetic layer.

4. A method for preparing a magnetoresistive memory cell, comprising: Performing patterning on the initial thin film behind the hard mask to obtain a patterned thin film, wherein the initial thin film is used to generate a first magnetic tunnel junction and a second magnetic tunnel junction; Etching the patterned thin film to obtain an initial memory cell, wherein the initial memory cell includes the first magnetic tunnel junction and the second magnetic tunnel junction, and the first magnetic tunnel junction and the second magnetic tunnel junction form a first preset angle and a second preset angle with the initial thin film, respectively; growing a heavy metal layer on a top surface of the initial memory cell; A top electrode and a bottom electrode are grown on the top surface of the heavy metal layer and the bottom surface of the initial memory cell respectively to obtain the magnetoresistive memory cell.

5. The preparation method according to claim 4, wherein The initial film is generated based on a pinned layer, a ferromagnetic reference layer, a barrier layer and a ferromagnetic free layer; The etching of the patterned thin film to obtain an initial memory cell includes: Performing a first etching on the patterned thin film, etching down to the insulating substrate, to obtain an effective device area; The effective device region is etched a second time, etching to the bottom electrode to obtain a magnetic tunnel junction, wherein the magnetic tunnel junction includes a first magnetic tunnel junction and a second magnetic tunnel junction, and the initial memory cell includes the magnetic tunnel junction.

6. The preparation method according to claim 5, wherein The etching of the patterned thin film to obtain an initial memory cell further includes: growing an insulating protective layer on the effective device region to obtain an insulating magnetic tunnel junction; polishing the insulated magnetic tunnel junction to obtain a polished magnetic tunnel junction; Performing hard mask patterning on the polished magnetic tunnel junction to obtain a patterned magnetic tunnel junction, and performing a second etching on the patterned magnetic tunnel junction to obtain a transitional memory cell; growing an insulating protective layer on the transitional memory cell to obtain an insulating memory cell; The insulated memory cell is polished to obtain the initial memory cell.

7. An array circuit based on a magnetoresistive memory cell, comprising: a plurality of line groups arranged vertically and spaced apart, each line group including a write word line, a first read word line and a second read word line spaced apart by a preset distance, and a source line; a plurality of bit line groups arranged horizontally and spaced apart, wherein the bit line groups include write control bit lines and read control bit lines arranged horizontally from top to bottom, and the write control bit lines and read control bit lines in one bit line group, and the first read word line and the second read word line in each line group form a placement area; A plurality of magnetoresistive memory cells according to any one of claims 1 to 3 or a plurality of magnetoresistive memory cells prepared by the preparation method according to any one of claims 4 to 6, wherein one magnetoresistive memory cell is provided in each placement area; The connection method of the magnetoresistive memory unit, the line group corresponding to the placement area, and the bit line includes: One end of the heavy metal layer is connected to the write control bit line and the write word line respectively through a first transistor, and the other end is connected to the source line; The first magnetic tunnel junction is connected to the first read word line and the read control bit line respectively through the second transistor, and the second magnetic tunnel junction is connected to the second read word line and the read control bit line respectively through the third transistor.

8. The array circuit according to claim 7, wherein: The source and drain of the first transistor are connected to the heavy metal layer and the write word line respectively, and the gate of the first transistor is connected to the write control bit line; The source and drain of the second transistor are connected to the first magnetic tunnel junction and the first read word line respectively, and the gate of the second transistor is connected to the read control bit line; A source and a drain of the third transistor are connected to the second magnetic tunnel junction and the second read word line respectively, and a gate of the third transistor is connected to the read control bit line.

9. A binary neural network chip, comprising: Decoding unit, cache unit, instruction storage unit, storage and calculation unit, data processing unit and clock unit; Wherein, the storage and computing unit includes a synaptic array constructed by the array circuit described in claim 7 or 8, and the array circuit includes multiple columns of magnetoresistive memory cell groups, each column of the magnetoresistive memory cell group includes multiple magnetoresistive memory cells, and each column of the magnetoresistive memory cell group is constructed to store the synaptic weight of a neuron.

10. The binary neural network chip according to claim 9, wherein: For each column of the magnetoresistive memory cell group, when a read current of a first magnetic tunnel junction of the magnetoresistive memory cell is greater than a read current of the magnetoresistive memory cell, determining a target positive value for the synaptic weight of the magnetoresistive memory cell; determining a negative target value for the synaptic weight of the magnetoresistive memory cell when a read current of the first magnetic tunnel junction of the magnetoresistive memory cell is less than a read current of the magnetoresistive memory cell; When the sum of the synaptic weights of the plurality of magnetoresistive memory units is a positive number, the neuron outputs a first value; When the sum of the synaptic weights of the plurality of magnetoresistive memory cells is a negative number, the neuron outputs a second value.

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