Display substrate and display apparatus

Abstract

Provided are a display substrate and a display apparatus. The display substrate comprises: a substrate (10), and a drive structure layer, which is disposed on the substrate (10), wherein the substrate comprises a display area (100) and a non-display area (200). The drive structure layer comprises: a plurality of pixel circuits, which are located in the display area (100), and a gate drive circuit and an electrostatic release circuit (ER), which are located in the non-display area (200), wherein the gate drive circuit is configured to provide a drive signal to each pixel circuit, the gate drive circuit comprises a plurality of drive circuits, and the plurality of drive circuits and the electrostatic release circuit (ER) are arranged in a direction close to the display area (100); and the electrostatic release circuit (ER) is disposed between two adjacent drive circuits and is electrically connected to at least one signal line of any one of the two adjacent drive circuits.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate, comprising: a base and a driving structure layer disposed on the base, wherein the base includes a display area and a non-display area, the driving structure layer including: a plurality of pixel circuits located in the display area, and a gate driving circuit and an electrostatic discharge circuit located in the non-display area, the gate driving circuit being configured to provide a driving signal to the pixel circuit, the gate driving circuit including a plurality of driving circuits, the plurality of driving circuits and the electrostatic discharge circuit being arranged in a direction close to the display area;

[0006] The electrostatic discharge circuit is arranged between two adjacent driving circuits and is electrically connected to at least one signal line of any one of the two adjacent driving circuits.

[0007] In an exemplary embodiment, the electrostatic discharge circuit includes at least: a first discharge transistor and a second discharge transistor;

[0008] The gate electrode and the second electrode of the first release transistor are connected to the first signal terminal, and the first electrode of the first release transistor is connected to the second signal terminal;

[0009] The gate electrode and the first electrode of the second release transistor are connected to the third signal terminal, and the second electrode of the second release transistor is connected to the first signal terminal.

[0010] In an exemplary embodiment, the plurality of driving circuits include: a light emitting driving circuit and a scanning driving circuit, wherein the scanning driving circuit is located on a side of the light emitting driving circuit close to the display area;

[0011] The driving structure layer further includes: a light-emitting initial signal line, a first light-emitting clock signal line, a second light-emitting clock signal line, a first light-emitting power line, a second light-emitting power line, a scanning initial signal line, a first scanning clock signal line, a second scanning clock signal line, a first scanning power line, and a second scanning power line located in the non-display area; any one of the light-emitting initial signal line, the first light-emitting clock signal line, the second light-emitting clock signal line, the first light-emitting power line, and the second light-emitting power line, the scanning initial signal line, the first scanning clock signal line, the second scanning clock signal line, the first scanning power line, and the second scanning power line extends along the first direction;

[0012] The light driving circuit is electrically connected to the light initial signal line, the first light clock signal line, the second light clock signal line, the first light power line and the second light power line respectively; the scan driving circuit is electrically connected to the scan initial signal line, the second scan clock signal line, the first scan clock signal line, the first scan power line and the second scan power line respectively;

[0013] The light-emitting initial signal line, the first light-emitting clock signal line, the second light-emitting clock signal line, the first light-emitting power line, the second light-emitting power line, the first scanning power line, the first scanning clock signal line, the second scanning clock signal line, the scanning initial signal line and the second scanning power line are arranged in sequence along the direction close to the display area.

[0014] In an exemplary embodiment, an orthographic projection of the electrostatic discharge circuit on the substrate partially overlaps the first scanning power line and the second light emitting power line, and at least a portion of the electrostatic discharge circuit is located between the second light emitting power line and the first scanning power line.

[0015] In an exemplary embodiment, the driving structure layer further includes: a light emitting output signal line and a scan output signal line located in the non-display area, and a light emitting signal line and a scan signal line at least partially located in the display area; any one of the scan output signal line, the light emitting signal line, and the scan signal line at least partially extending along a second direction, and the first direction intersects the second direction; and the pixel circuit is connected to the light emitting signal line and the scan signal line, respectively.

[0016] The light-emitting driving circuit includes: a plurality of cascaded light-emitting shift registers; the scanning driving circuit includes: a plurality of cascaded scanning shift registers;

[0017] The light emitting output signal line is electrically connected to the light emitting shift register and at least one light emitting signal line respectively;

[0018] The scan output signal lines are electrically connected to the scan shift register and the scan signal lines respectively.

[0019] In an exemplary embodiment, the first signal terminal of the electrostatic discharge circuit is electrically connected to the light output signal line, the second signal terminal of the electrostatic discharge circuit is electrically connected to the second light power line, and the third signal terminal of the electrostatic discharge circuit is electrically connected to the first scan power line.

[0020] In an exemplary embodiment, a distance between the second light emitting power line and the first scanning power line is approximately 8 micrometers to 15 micrometers.

[0021] In an exemplary embodiment, the light-emitting shift register includes a plurality of light-emitting transistors and a plurality of light-emitting capacitors, the scanning shift register includes a plurality of scanning transistors and a plurality of scanning capacitors, the light-emitting capacitors and the scanning capacitors each include a first electrode plate and a second electrode plate, the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence, the first scanning clock signal line includes: a first sub-clock signal line and a second sub-clock signal line electrically connected to each other, and the second scanning clock signal line includes: a third sub-clock signal line and a fourth sub-clock signal line electrically connected to each other;

[0022] The semiconductor layer includes at least: an active layer of a plurality of light emitting transistors, an active layer of a plurality of scanning transistors, an active layer of a first release transistor, and an active layer of a second release transistor;

[0023] The first conductive layer at least includes: a light emitting signal line, a scanning signal line, gate electrodes of a plurality of light emitting transistors, first plates of a plurality of light emitting capacitors, gate electrodes of a plurality of scanning transistors, first plates of a plurality of scanning capacitors, a gate electrode of a first release transistor, and a gate electrode of a second release transistor;

[0024] The second conductive layer at least includes: a plurality of second plates of light-emitting capacitors, a plurality of second plates of scan capacitors, a scan output signal line and a light-emitting output signal line;

[0025] The third conductive layer at least includes: a light-emitting initial signal line, a first light-emitting clock signal line, a second light-emitting clock signal line, a first light-emitting power line, a second light-emitting power line, a scan initial signal line, a first sub-clock signal line of the first scan clock signal line, a third sub-clock signal line of the second scan clock signal line, a first scan power line and a second scan power line, first electrodes and second electrodes of a plurality of light-emitting transistors, first electrodes and second electrodes of a plurality of scan transistors, first electrodes and second electrodes of a first release transistor, and first electrodes and second electrodes of a second release transistor;

[0026] The fourth conductive layer includes at least a second sub-clock signal line of the first scanning clock signal line and a fourth sub-clock signal line of the second scanning clock signal line.

[0027] In an exemplary embodiment, the first and second electrodes of a plurality of light-emitting transistors are located between the first light-emitting power line and the second light-emitting power line, the first and second electrodes of the first release transistor to the first and second electrodes of the second release transistor are located between the second light-emitting power line and the first scanning power line, the first and second electrodes of some scanning transistors are located between the scanning initial signal line and the second scanning power line, and the first and second electrodes of another portion of the scanning transistors can be located on the side of the second scanning power line close to the display area.

[0028] In an exemplary embodiment, at least one of the light emitting output signal lines includes: an output connection portion and at least one output line, the output connection portion extends along a first direction, and the at least one output line is arranged along the first direction;

[0029] The output connection parts are electrically connected to the light emitting shift register and at least one output line respectively. The output lines correspond to the light emitting signal lines connected to the light emitting output signal lines one by one and are electrically connected to the corresponding light emitting signal lines.

[0030] In an exemplary embodiment, the output line includes: an output main body portion extending at least partially along the second direction and an output connection portion extending along the first direction, the output main body portion being electrically connected to the output connection portion;

[0031] The second electrode of the first release transistor and the second electrode of the second release transistor are an integrated structure, and the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the output connection portion on the substrate. The integrated structure of the second electrode of the first release transistor and the second electrode of the second release transistor is electrically connected to the output connection portion.

[0032] In an exemplary embodiment, the active layer of the first release transistor and the active layer of the second release transistor are an integral structure and extend along the second direction;

[0033] An orthographic projection of the output connection portion on the substrate does not overlap with an orthographic projection of an integrated structure of the active layer of the first release transistor and the active layer of the second release transistor on the substrate.

[0034] In an exemplary embodiment, the active layer of the first release transistor and the active layer of the second release transistor are an integrated structure and include: an active body portion and an active connection portion, the active body portion and the active connection portion are electrically connected, and the active body portion and the active connection portion are arranged along a first direction;

[0035] The active main portion extends along the second direction, and the active connecting portion at least partially extends along the first direction;

[0036] The active connection portion is in a broken line shape.

[0037] In an exemplary embodiment, the output line at least partially extends along the second direction; the second electrode of the first release transistor and the second electrode of the second release transistor are an integrated structure;

[0038] An orthographic projection of the active connection portion on the substrate at least partially overlaps with an orthographic projection of the second electrode of the first release transistor and the second electrode of the second release transistor and the output line on the substrate, and is electrically connected to the second electrode of the first release transistor and the second electrode of the second release transistor and the output line, respectively.

[0039] In an exemplary embodiment, the width of the active connection portion is smaller than the width of the active body portion.

[0040] In an exemplary embodiment, the scan shift register includes: a first scan capacitor, a second plate of the first scan capacitor is electrically connected to the first scan power line, and the second plate of the first scan capacitor extends along the second direction;

[0041] The orthographic projection of the second electrode plate of the first scan capacitor on the substrate at least partially overlaps with the orthographic projections of the first scan power line, the second scan power line, the first scan clock signal line, the second scan clock signal line and the scan initial signal line on the substrate.

[0042] In an exemplary embodiment, the display area includes: a first display area and a second display area located on at least one side of the first display area; the display substrate further includes: a light-emitting device and an anode connection line located in the display area, and a pixel circuit is electrically connected to the light-emitting device; the pixel circuit includes: a first pixel circuit and a second pixel circuit located in the second display area; the light-emitting device includes: a first light-emitting device located in the first display area and a second light-emitting device located in the second display area; the first pixel circuit is electrically connected to the first light-emitting device, and the second pixel circuit is electrically connected to the second light-emitting device;

[0043] An orthographic projection of the first pixel circuit on the substrate at least partially overlaps with an orthographic projection of the first light-emitting device connected to the first pixel circuit on the substrate;

[0044] The anode connection line is electrically connected to the second light emitting device and the second pixel circuit connected to the second light emitting device.

[0045] In an exemplary embodiment, the driving structure layer further includes: a first power line, a data signal line, and a data connection line at least partially located in the display area; the first power line and the data signal line at least partially extend along the first direction, and the data connection line at least partially extends along the second direction;

[0046] The driving structure layer further includes: a fourth conductive layer and a fifth conductive layer sequentially stacked on the third conductive layer;

[0047] The third conductive layer at least includes: a data connection line;

[0048] The fourth conductive layer at least includes: a first power line and a data signal line;

[0049] The fifth conductive layer at least includes: an anode connection line;

[0050] The fifth conductive layer is a transparent conductive layer.

[0051] In an exemplary embodiment, the driving structure layer further includes: a flat layer located between the third conductive layer and the fourth conductive layer, the flat layer being provided with a groove;

[0052] The orthographic projection of the electrostatic discharge circuit on the substrate at least partially overlaps with the orthographic projection of the groove on the substrate.

[0053] In an exemplary embodiment, the driving structure layer further includes: at least one initial power supply line located in the non-display area and at least one initial signal line located at least partially in the display area; the initial power supply line is located on a side of the scan driving circuit close to the display area, the initial power supply line at least partially extends along the first direction, and the initial signal line at least partially extends along the second direction; the initial power supply line includes a first sub-initial power supply line and a second sub-initial power supply line electrically connected to each other;

[0054] At least one initial signal line corresponds to at least one initial power supply line one by one, and the initial signal line is electrically connected to the pixel circuit and the corresponding initial power supply line respectively;

[0055] The second conductive layer at least includes: an initial signal line;

[0056] The third conductive layer includes at least: a first sub-initial power supply line of the initial power supply line;

[0057] The fourth conductive layer includes at least a second sub-initial power supply line of the initial power supply line.

[0058] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate and a photosensitive sensor, wherein the photosensitive sensor is located inside the display substrate.

[0059] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0060] Summary of the Figures

[0061] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0062] FIG1 is a schematic structural diagram of a display substrate;

[0063] FIG2 is another schematic diagram showing a substrate;

[0064] FIG3A is a schematic diagram of an equivalent circuit of a pixel circuit;

[0065] FIG3B is an operating timing diagram of the pixel circuit provided in FIG3A ;

[0066] FIG4 is a schematic structural diagram of a display substrate;

[0067] FIG5A is a partial schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0068] FIG5B is a cross-sectional view of the display substrate provided in FIG5A along line AA;

[0069] FIG6A is another partial schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0070] FIG6B is a cross-sectional view of the display substrate provided in FIG6A along the AA direction;

[0071] FIG7A is a schematic structural diagram of a pixel circuit;

[0072] FIG7B is a schematic structural diagram of another pixel circuit;

[0073] FIG7C is a schematic structural diagram of yet another pixel circuit;

[0074] FIG8 is an equivalent circuit diagram of an electrostatic discharge circuit;

[0075] FIG9A is an equivalent circuit diagram of a scan shift register;

[0076] FIG9B is a timing diagram of the scan shift register provided in FIG9A ;

[0077] FIG10A is an equivalent circuit diagram of a light-emitting shift register;

[0078] FIG10B is a timing diagram of the light-emitting shift register provided in FIG10A ;

[0079] FIG11 is a schematic structural diagram of the semiconductor layer and the second conductive layer in FIG5A;

[0080] FIG12 is a schematic structural diagram of the semiconductor layer and the second conductive layer in FIG6A;

[0081] FIG13 is another schematic structural diagram of a display substrate;

[0082] FIG14 is a schematic diagram of FIG5A after the semiconductor layer pattern is formed;

[0083] FIG15 is a schematic diagram of FIG6A after the semiconductor layer pattern is formed;

[0084] FIG16 is a schematic diagram of the first conductive layer pattern of FIG5A and FIG6A;

[0085] FIG17 is a schematic diagram of FIG5A after forming a first conductive layer pattern;

[0086] FIG18 is a schematic diagram of FIG6A after forming a first conductive layer pattern;

[0087] FIG19 is a schematic diagram of FIG6A after forming a second insulating layer pattern;

[0088] FIG20 is a schematic diagram of the second conductive layer pattern of FIG5A;

[0089] FIG21 is a schematic diagram of FIG5A after forming a second conductive layer pattern;

[0090] FIG22 is a schematic diagram of the second conductive layer pattern of FIG6A ;

[0091] FIG23 is a schematic diagram of FIG6A after forming a second conductive layer pattern;

[0092] FIG24 is a schematic diagram of FIG5A after forming a third insulating layer pattern;

[0093] FIG25 is a schematic diagram of FIG6A after forming a third insulating layer pattern;

[0094] FIG26 is a schematic diagram of the third conductive layer pattern of FIG5A and FIG6A;

[0095] FIG27 is a schematic diagram of FIG5A after forming a third conductive layer pattern;

[0096] FIG28 is a schematic diagram of FIG6A after forming a third conductive layer pattern;

[0097] FIG29 is a schematic diagram of FIG5A after a planar layer pattern is formed;

[0098] FIG30 is a schematic diagram of FIG6A after a flat layer pattern is formed;

[0099] FIG31 is a schematic diagram of the fourth conductive layer pattern of FIG5A and FIG6A;

[0100] FIG32 is a schematic diagram of FIG5A after forming a fourth conductive layer pattern;

[0101] FIG33 is a schematic diagram of FIG6A after forming a fourth conductive layer pattern;

[0102] FIG34 is a schematic diagram of FIG7B after the semiconductor layer pattern is formed;

[0103] FIG35 is a schematic diagram of FIG7C after the semiconductor layer pattern is formed;

[0104] FIG36 is a schematic diagram of the first conductive layer pattern of FIG7B ;

[0105] FIG37 is a schematic diagram of FIG7B after forming a first conductive layer pattern;

[0106] FIG38 is a schematic diagram of the first conductive layer pattern of FIG7C ;

[0107] FIG39 is a schematic diagram of FIG7C after the first conductive layer pattern is formed;

[0108] FIG40 is a schematic diagram of the second conductive layer pattern of FIG7B ;

[0109] FIG41 is a schematic diagram of FIG7B after forming a second conductive layer pattern;

[0110] FIG42 is a schematic diagram of the second conductive layer pattern of FIG7C ;

[0111] FIG43 is a schematic diagram of FIG7C after forming a second conductive layer pattern;

[0112] FIG44 is a schematic diagram of FIG7B after forming a third insulating layer pattern;

[0113] FIG45 is a schematic diagram of FIG7C after forming a third insulating layer pattern;

[0114] FIG46 is a schematic diagram of the third conductive layer pattern of FIG7B ;

[0115] FIG47 is a schematic diagram of FIG7B after forming a third conductive layer pattern;

[0116] FIG48 is a schematic diagram of the third conductive layer pattern of 7C;

[0117] FIG49 is a schematic diagram of FIG7C after forming a third conductive layer pattern;

[0118] FIG50 is a schematic diagram of FIG7B after forming a fourth insulating layer pattern;

[0119] FIG51 is a schematic diagram of FIG7C after forming a fourth insulating layer pattern;

[0120] FIG52 is a schematic diagram of the fourth conductive layer pattern of FIG7B ;

[0121] FIG53 is a schematic diagram of FIG7B after forming a fourth conductive layer pattern;

[0122] FIG54 is a schematic diagram of the fourth conductive layer pattern of FIG7C ;

[0123] FIG. 55 is a schematic diagram illustrating forming a fourth conductive layer pattern in FIG. 7C .

[0124] Details

[0125] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings below. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0126] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0127] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0128] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0129] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0130] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0131] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0132] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0133] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0134] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0135] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0136] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0137] Display substrates offer advantages such as high resolution, high response speed, high brightness, and high aperture ratio, and have broad application prospects. A driver circuit is provided within the display substrate to drive the pixel circuits to emit light, thereby achieving display. The display substrate is generally shaped like a rounded rectangle, with the four corners of the rounded rectangle being called the rounded corners. The driver circuits are placed within the rounded corners according to the arc of the rounded corners, resulting in some blank areas between the driver circuits. Excessive blank areas can cause uneven etching, affecting the stability of the driver circuit's output signal transmission and, consequently, the display effect.

[0138] Figure 1 is a schematic diagram of the structure of a display substrate, and Figure 2 is another schematic diagram of the display substrate. As shown in Figures 1 and 2, the display substrate may include: a display area 100 and a non-display area 200. Among them, the display area 100 of the display substrate may include: a first display area A1 and a second display area A2 located on at least one side of the first display area A1. In some examples, the first display area A1 is a light-transmitting display area, and the first display area A1 can also be referred to as an under-screen camera (UDC, Under Display Camera) area. The second display area A2 is a non-light-transmitting display area, and the second display area A2 can also be referred to as a normal display area. For example, the orthographic projection of hardware such as a light-sensitive sensor (such as a camera, an infrared sensor) on the display substrate can be located in the first display area A1 of the display substrate.

[0139] In an exemplary embodiment, as shown in FIG1 , the first display area A1 may be circular, and the size of the orthographic projection of the light sensor on the display substrate may be smaller than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the light sensor on the display substrate may be smaller than or equal to the size of the inscribed circle of the first display area.

[0140] In an exemplary embodiment, as shown in FIG1 , the first display area A1 may be located at the top center of the display area 100. The second display area A2 may surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 may be located at another location, such as the upper left corner or the upper right corner of the display area 100.

[0141] In some exemplary embodiments, as shown in FIG1 , the display area may be rectangular, such as a rounded rectangle. The first display area A1 may be circular or elliptical. However, this embodiment is not limited thereto. For example, the first display area may be rectangular, pentagonal, hexagonal, or other shapes. The display substrate provided by the present disclosure can achieve large-angle bending on all four sides, improving module alignment wrinkle issues and increasing product yield.

[0142] In an exemplary embodiment, as shown in FIG1 and FIG2 , a display area may include pixel units arranged in an array, at least one pixel unit including at least three sub-pixels P, and at least one sub-pixel including a pixel circuit and a light-emitting device. The pixel circuit within the same sub-pixel is electrically connected to the light-emitting device and is configured to drive the light-emitting device to emit light.

[0143] In an exemplary embodiment, a pixel unit may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in the present disclosure.

[0144] In an exemplary embodiment, the shape of the sub-pixels in the pixel unit can be rectangular, diamond, pentagonal, or hexagonal. When the pixel unit includes three sub-pixels, the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular pattern. When the pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, or square pattern. This disclosure is not limited hereto.

[0145] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED), wherein the OLED may include a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked together.

[0146] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0147] In an exemplary embodiment, as shown in FIG. 1 , the non-display area 200 may include a binding area located on one side of the display area 100 and a bezel area located on the other side of the display area 100 .

[0148] In an exemplary embodiment, the binding area may include a lead area, a bending area, and a composite circuit area arranged in sequence along a direction away from the display area, the lead area is connected to the display area 100, the bending area is connected to the lead area, and the composite circuit area is connected to the bending area.

[0149] In an exemplary embodiment, a plurality of lead lines may be provided in the lead area, one end of a portion of the plurality of lead lines being connected to a plurality of data fan-out lines in the display area 100, one end of another portion of the plurality of lead lines being connected to a plurality of data lines in the display area 100, and the other ends of the plurality of lead lines crossing the bending area to connect to the integrated circuit in the composite circuit area, so that the integrated circuit applies data signals to the data lines through the lead lines and the data fan-out lines.

[0150] In an exemplary embodiment, the bending region can be bent at a curvature to reverse the surface of the composite circuit region. That is, the surface of the composite circuit region facing upward can be transformed to face downward by bending the bending region. In an exemplary embodiment, when the bending region is bent, the composite circuit region can overlap with the display area 100.

[0151] In an exemplary embodiment, the composite circuit area may include an anti-static area, a driver chip area, and a binding pin area. The integrated circuit (IC) may be bound and connected to the driver chip area, and the flexible printed circuit (FPC) may be bound and connected to the binding pin area.

[0152] In an exemplary embodiment, the integrated circuit can generate the drive signals required to drive the sub-pixels and can provide the drive signals to the sub-pixels in the display area 100. For example, the drive signals can be data signals that drive the brightness of the sub-pixels. In an exemplary embodiment, the integrated circuit can be bonded to the driver chip area using an anisotropic conductive film or other means. In an exemplary embodiment, the bonding pin area can be provided with pads including a plurality of pins (PINs), and the flexible circuit board can be bonded to the pads.

[0153] In an exemplary embodiment, as shown in FIG2 , a display substrate may include a timing controller, a data driving circuit, a gate driving circuit, and a pixel array. The timing controller is connected to the data driving circuit and the gate driving circuit, respectively. The data driving circuit is connected to data signal lines Data, respectively. The gate driving circuit is connected to gate lines. The gate lines may include one or more of emission signal lines EM and scan signal lines Gate. The pixel circuits are connected to the gate lines and the data signal lines, respectively.

[0154] In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver circuit to the data driver circuit, clock signals, start signals, etc. suitable for the specifications of the gate driver circuit to the gate driver circuit, and clock signals, emission stop signals, etc. suitable for the specifications of the light driver circuit to the light driver circuit. The data driver circuit may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines. For example, the data driver circuit may sample grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines on a pixel row basis.

[0155] In an exemplary embodiment, the gate drive circuit can generate a scan signal to be provided to the gate line by receiving a clock signal, a start signal, etc. from a timing controller. For example, the gate drive circuit can sequentially provide a signal having an on-level pulse to the gate line. For example, the gate drive circuit can be configured in the form of a shift register and can sequentially transmit the start signal provided in the form of an on-level pulse to the next stage circuit under the control of the clock signal to generate the scan signal.

[0156] In example embodiments, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.

[0157] In an exemplary embodiment, FIG3A is a schematic diagram of an equivalent circuit of a pixel circuit. As shown in FIG3A , the pixel circuit may include seven transistors (first transistor M1 to seventh transistor M7), one capacitor C, and eight signal lines (data signal line Data, scan signal line Gate, reset signal line Reset, emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, high-level power line VDD, and low-level power line VSS).

[0158] In an exemplary embodiment, as shown in FIG3A , a first plate of capacitor C is connected to a high-level power supply line VDD, and a second plate of capacitor C is connected to a first node N1. A gate electrode of first transistor M1 is connected to reset signal line Reset, a first electrode of first transistor M1 is connected to a first initialization signal line INIT1, and a second electrode of first transistor M1 is connected to first node N1. A gate electrode of second transistor M2 is connected to scan signal line Gate, a first electrode of second transistor M2 is connected to first node N1, and a second electrode of second transistor M2 is connected to second node N2. A gate electrode of third transistor M3 is connected to first node N1, a first electrode of third transistor M3 is connected to second node N2, and a second electrode of third transistor M3 is connected to third node N3. A gate electrode of fourth transistor M4 is connected to scan signal line Gate, a first electrode of fourth transistor M4 is connected to data signal line Data, and a second electrode of fourth transistor M4 is connected to second node N2. The gate electrode of the fifth transistor M5 is connected to the light emitting signal line EM, the first electrode of the fifth transistor M5 is connected to the high-level power line VDD, and the second electrode of the fifth transistor M5 is connected to the second node N2. The gate electrode of the sixth transistor M6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light emitting device L. The gate electrode of the seventh transistor M7 is connected to the reset signal line Reset or the scan signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and the second electrode of the light emitting device is connected to the low-level power line VSS. FIG3A is described using the gate electrode of the seventh transistor M7 and the reset signal line Reset as an example.

[0159] In an exemplary embodiment, the first transistor M1 may be referred to as a node reset transistor, and when the reset signal line Reset inputs an active level signal, the first transistor M1 transmits an initialization voltage to the first node N1 to initialize the charge amount of the first node N1.

[0160] In an exemplary embodiment, the second transistor M2 may be referred to as a compensation transistor, and when the control signal line SL inputs an active level signal, the second transistor M2 transmits a signal of the second node N2 to the first node N1 to compensate for the signal of the first node N1 .

[0161] In an exemplary embodiment, the third transistor M3 may be referred to as a driving transistor, and the third transistor M3 determines a driving current flowing between the high-level power line VDD and the low-level power line VSS according to a potential difference between the gate electrode and the first electrode.

[0162] In an exemplary embodiment, the fourth transistor M4 may be referred to as a write transistor or the like, and when the scan signal line Gate inputs an active level signal, the fourth transistor M4 inputs a data voltage of the data signal line Data to the third node N3 .

[0163] In an exemplary embodiment, the fifth transistor M5 and the sixth transistor M6 may be referred to as light emitting transistors. When the light emitting signal line EM inputs an active level signal, the fifth transistor M5 and the sixth transistor M6 form a driving current path between the high-level power line VDD and the low-level power line VSS to enable the light emitting device to emit light.

[0164] In an exemplary embodiment, the seventh transistor M7 can be called an anode reset transistor. When the reset signal line Reset or the scan signal line Gate inputs an active level signal, the seventh transistor M7 transmits an initialization voltage to the first electrode of the light emitting device L to initialize the charge amount of the first electrode of the light emitting device L.

[0165] In an exemplary embodiment, the signal of the high-level power line VDD is a continuously provided high-level signal, and the signal of the low-level power line VSS is a low-level signal.

[0166] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0167] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor M1 to the seventh transistor M7 may include P-type transistors and N-type transistors.

[0168] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0169] In an exemplary embodiment, when the display substrate is an LTPO display substrate, the first transistor T1 and the second transistor T2 may be N-type transistors, and the remaining transistors may be P-type transistors. When the display substrate is an LTPS display substrate, the first transistor M1 to the seventh transistor M7 may be P-type transistors.

[0170] FIG3B is an operating timing diagram of the pixel circuit provided in FIG3A. FIG3B is illustrated by taking the example of the transistors in FIG3A as P-type transistors. The following describes an exemplary embodiment of the present disclosure using the operating process of the pixel circuit illustrated in FIG3B. In an exemplary embodiment, the operating process of the pixel circuit may include:

[0171] The first phase A1, known as the reset phase, is characterized by high-level signals on the scanning signal line Gate and the emission signal line EM, while the reset signal line Reset is low. The reset signal line Reset is high, turning on the first transistor M1. The signal on the first initialization signal line INIT1 is supplied to the first node N1, initializing the capacitor C and clearing the existing data voltage in the capacitor C. The seventh transistor M7 is turned on, and the initialization voltage on the second initialization signal line INIT2 is supplied to the first electrode of the light-emitting device L, initializing (resetting) the first electrode of the light-emitting device L and clearing the pre-stored voltage therein, completing initialization. The signals on the scanning signal line Gate and the emission signal line EM are high, turning off the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6. During this phase, the light-emitting device L does not emit light.

[0172] In the second phase A2, known as the data writing phase or threshold compensation phase, the scan signal line Gate is a low-level signal, the signals on the luminescence signal line EM and the reset signal line Reset are high-level signals, and the data signal line Data outputs a data voltage. During this phase, since the first node N1 is a low-level signal, the third transistor M3 is turned on. The scan signal line Gate is a low-level signal, turning on the second transistor T2 and the fourth transistor M4. The second and fourth transistors M2 and M4 are turned on, causing the data voltage output by the data signal line Data to be supplied to the first node N1 via the second node N, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage at the first node N1 reaches Vd - |Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor M3. This ensures that the light-emitting device L does not emit light. The reset signal line Reset is a high-level signal, turning off the first transistor M1. The signal of the light emitting signal line EM is a high level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off.

[0173] In the third phase A3, referred to as the light-emitting phase, the signals on the scanning signal line Gate and the reset signal line Reset are high-level signals, and the signal on the light-emitting signal line EM is low-level. The signal on the light-emitting signal line EM is low-level, and the fifth transistor M5 and the sixth transistor M6 are turned on. The power supply voltage output from the high-level power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, thereby driving the light-emitting device L to emit light.

[0174] During the pixel circuit driving process, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is: I=K*(Vgs-Vth)2=K*[(Vdd-Vd+|Vth|)-Vth]2=K*[(Vdd-Vd]2

[0175] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0176] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0177] In example embodiments, the display substrate may be an LTPO display substrate or an LTPS display substrate.

[0178] In an exemplary embodiment, the gate driving circuits in the display substrate may be two, three, or more types, depending on the structure of the display substrate, which is not limited in the present disclosure.

[0179] Some metal conductive layers in FDC display products include multiple isolated block structures, which makes the metal conductive layer's ability to conduct static electricity poor. The inability to release static electricity will cause some transistors to burn, thereby affecting the display effect and reducing the reliability of the display substrate.

[0180] FIG4 is a schematic diagram of the structure of a display substrate, FIG5A is a partial schematic diagram of the display substrate provided by an embodiment of the present disclosure, FIG5B is a cross-sectional view of FIG5A along the AA direction, FIG6A is another partial schematic diagram of the display substrate provided by an embodiment of the present disclosure, and FIG6B is a cross-sectional view of FIG6A along the AA direction. As shown in FIG4, FIG5A, FIG5B, FIG6A and FIG6B, the display substrate provided by an embodiment of the present disclosure may include: a substrate 10 and a driving structure layer arranged on the substrate 10, the substrate includes a display area 100 and a non-display area 200, the driving structure layer includes: a plurality of pixel circuits located in the display area and a gate driving circuit and an electrostatic discharge circuit ER located in the non-display area, the gate driving circuit is configured to provide a driving signal to the pixel circuit, and the gate driving circuit includes a plurality of driving circuits. The plurality of driving circuits and the electrostatic discharge circuit are arranged in a direction close to the display area, and the electrostatic discharge circuit ER is arranged between two adjacent driving circuits and is electrically connected to at least one signal line of any one of the two adjacent driving circuits.

[0181] In an exemplary embodiment, the display substrate may further include: a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate; and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the substrate. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited in this disclosure.

[0182] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The driving structure layer of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel circuit, and the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel circuit through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0183] In an exemplary embodiment, the touch structure layer may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer 43 covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include multiple bridging electrodes, the second touch metal layer may include multiple first touch electrodes and second touch electrodes, and the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.

[0184] The present disclosure discloses an electrostatic discharge circuit which is arranged between adjacent driving circuits and electrically connected to the adjacent driving circuits to release static electricity in the gate driving circuit, thereby improving the static electricity conduction capability of the display substrate, and enhancing the display effect and the reliability of the display substrate.

[0185] In an exemplary embodiment, when the display substrate is an LTPO display substrate, the multiple drive circuits may include: a light-emitting drive circuit, a control drive circuit, and a scan drive circuit, arranged sequentially near the display area. The control drive circuit is connected to the N-type transistors in the pixel circuit, and the scan drive circuit is connected to the P-type transistors in the pixel circuit. Exemplarily, the electrostatic discharge circuit may be located between the light-emitting drive circuit and the control drive circuit and electrically connected to at least one signal line of either the light-emitting drive circuit or the control drive circuit. Alternatively, the electrostatic discharge circuit may be located between the control drive circuit and the scan drive circuit and electrically connected to at least one signal line of either the control drive circuit or the scan drive circuit.

[0186] In an exemplary embodiment, as shown in FIG. 4 , when the display substrate is an LTPS display substrate, the plurality of driving circuits may include a light emitting driving circuit and a scanning driving circuit. The scanning driving circuit is located on a side of the light emitting driving circuit close to the display area 100 .

[0187] In an exemplary embodiment, as shown in Figures 5A and 6A, the driving structure layer may further include: a light-emitting initial signal line ESTV, a first light-emitting clock signal line ECK1, a second light-emitting clock signal line ECK2, a first light-emitting power line EVGH, a second light-emitting power line EVGL, a scanning initial signal line GSTV, a first scanning clock signal line GCK1, a second scanning clock signal line GCK2, a first scanning power line GVGH, and a second scanning power line GVGL located in a non-display area.

[0188] In an exemplary embodiment, as shown in Figures 5A and 6A, any one of the light-emitting initial signal line ESTV, the first light-emitting clock signal line ECK1, the second light-emitting clock signal line ECK2, the first light-emitting power line EVGH, the second light-emitting power line EVGL, the scan initial signal line GSTV, the first scan clock signal line GCK1, the second scan clock signal line GCK2, the first scan power line GVGH, and the second scan power line GVGL extends along the first direction D1.

[0189] In an exemplary embodiment, as shown in FIG5A and FIG6A, the light emitting driving circuit may be electrically connected to the light emitting start signal line ESTV, the first light emitting clock signal line ECK1, the second light emitting clock signal line ECK2, the first light emitting power line EVGH, and the second light emitting power line EVGL, respectively.

[0190] In exemplary embodiments, as shown in FIG. 5A and FIG. 6A , the scan driving circuit may be electrically connected to the scan start signal line GSTV, the second scan clock signal line GCK2 , the first scan clock signal line GCK1 , the first scan power line GVGH, and the second scan power line GVGL, respectively.

[0191] In an exemplary embodiment, as shown in FIG. 5A and FIG. 6A , at least one of the first scan clock signal line GCK1 and the second scan clock signal line GCK2 may have a double-layer structure.

[0192] 5A and 6A , the first scan clock signal line may include a first sub-clock signal line and a second sub-clock signal line electrically connected to each other. The first sub-clock signal line and the second sub-clock signal line may be provided in different layers.

[0193] 5A and 6A , the second scan clock signal line may include a third sub-clock signal line and a fourth sub-clock signal line electrically connected to each other. The third sub-clock signal line and the fourth sub-clock signal line may be provided in different layers.

[0194] In an exemplary embodiment, as shown in Figures 5A and 6A, the light-emitting initial signal line ESTV, the first light-emitting clock signal line ECK1, the second light-emitting clock signal line ECK2, the first light-emitting power line EVGH, the second light-emitting power line EVGL, the first scan power line GVGH, the first scan clock signal line GCK1, the second scan clock signal line GCK2, the scan initial signal line GSTV and the second scan power line GVGL are arranged in sequence in a direction close to the display area.

[0195] In an exemplary embodiment, signals of the first light emitting power line EVGH and the first scanning power line GVGH are high level signals, and signals of the second light emitting power line EVGL and the second scanning power line GVGL are low level signals.

[0196] In an exemplary embodiment, as shown in Figures 5A and 6A, the orthographic projection of the electrostatic discharge circuit ER on the substrate partially overlaps with the first scanning power line GVGH and the second light emitting power line EVGL, and at least part of the electrostatic discharge circuit is located between the second light emitting power line EVGL and the first scanning power line GVGH.

[0197] In an exemplary embodiment, Figure 7A is a schematic diagram of the structure of a pixel circuit, Figure 7B is another schematic diagram of the structure of a pixel circuit, and Figure 7C is yet another schematic diagram of the structure of a pixel circuit. As shown in Figures 5A, 6A, and 7A-7C, the driving structure layer may further include: emission output signal lines EOL and scan output signal lines GOL located in the non-display area, and emission signal lines EM and scan signal lines Gate located at least partially in the display area. Each of the scan output signal lines GOL, the emission signal lines EM, and the scan signal lines Gate extends at least partially along a second direction D2, with the first direction D1 intersecting the second direction D2.

[0198] In an exemplary embodiment, the pixel circuits are connected to the emission signal line EM and the scanning signal line Gate, respectively.

[0199] In an exemplary embodiment, as shown in FIG. 5A and FIG. 6A , the light emitting driving circuit may include: a plurality of cascaded light emitting shift registers EM-GOA, and the scan driving circuit may include: a plurality of cascaded scan shift registers Gate-GOA.

[0200] In an exemplary embodiment, the light output signal line EOL is electrically connected to the light shift register EM-GOA and at least one light signal line. Figures 5A and 6A illustrate the light output signal line and two light signal lines as examples.

[0201] In an exemplary embodiment, the scan output signal line GOL is electrically connected to the scan shift register Gate-GOA and the scan signal line, respectively.

[0202] Figure 8 is an equivalent circuit diagram of an electrostatic discharge circuit. As shown in Figure 8 , in an exemplary embodiment, the electrostatic discharge circuit may include at least a first discharge transistor R1 and a second discharge transistor R2. The gate electrode and second electrode of the first discharge transistor R1 are connected to the first signal terminal S1, and the first electrode of the first discharge transistor R1 is connected to the second signal terminal S2. The gate electrode and first electrode of the second discharge transistor R2 are connected to the third signal terminal S3, and the second electrode of the second discharge transistor R2 is connected to the first signal terminal S1.

[0203] In an exemplary embodiment, the signal at the second signal terminal S2 may be a low-level signal, and the signal at the third signal terminal S3 may be a high-level signal.

[0204] In an exemplary embodiment, the first release transistor R1 and the second release transistor R2 can be P-type transistors or N-type transistors. Using the same type of transistors in the electrostatic discharge circuit can simplify the process flow, reduce the difficulty of display panel manufacturing, and improve product yield. In some possible implementations, the first release transistor R1 and the second release transistor R2 can include P-type transistors and N-type transistors.

[0205] In an exemplary embodiment, the first release transistor R1 and the second release transistor R2 may employ low-temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low-temperature polysilicon thin film transistors and oxide thin film transistors.

[0206] In an exemplary embodiment, the electrostatic discharge circuit operates as follows: when the voltage of the signal at the first signal terminal S1 is too high (e.g., higher than the voltage of the signal at the third signal terminal S3), the second release transistor R2 is turned on. At this point, the voltage of the signal at the first signal terminal S1 approaches the voltage of the signal at the third signal terminal S3, preventing it from being too high. Similarly, when the voltage of the signal at the first signal terminal S1 is too low (e.g., lower than the voltage of the signal at the second signal terminal S2), the first release transistor R1 is turned on. At this point, the voltage of the signal at the first signal terminal S1 approaches the voltage of the signal at the second signal terminal S2, preventing it from being too low.

[0207] In an exemplary embodiment, the first signal terminal of the electrostatic discharge circuit can be electrically connected to the light output signal line EOL, the second signal terminal of the electrostatic discharge circuit can be electrically connected to the second light power line EVGL, and the third signal terminal of the electrostatic discharge circuit can be electrically connected to the first scan power line GVGH.

[0208] In an exemplary embodiment, the distance between the second light emitting power line EVGL and the first scan power line GVGH is approximately 8 to 15 micrometers. For example, the distance between the second light emitting power line EVGL and the first scan power line GVGH may be 10 micrometers.

[0209] In an exemplary embodiment, the pixel circuit includes: a plurality of transistors and capacitors, a light-emitting shift register includes a plurality of light-emitting transistors and a plurality of light-emitting capacitors, a scanning shift register includes a plurality of scanning transistors and a plurality of scanning capacitors, the light-emitting capacitors and the scanning capacitors each include a first electrode plate and a second electrode plate, and the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence;

[0210] In an exemplary embodiment, the semiconductor layer may include at least active layers of a plurality of transistors, active layers of a plurality of light emitting transistors, active layers of a plurality of scan transistors, active layers of a first release transistor, and active layers of a second release transistor.

[0211] In an exemplary embodiment, the first conductive layer may include at least: a light-emitting signal line, a scanning signal line, gate electrodes of multiple transistors, gate electrodes of multiple light-emitting transistors, a first plate of a capacitor, a first plate of multiple light-emitting capacitors, gate electrodes of multiple scanning transistors, first plates of multiple scanning capacitors, a gate electrode of a first release transistor, and a gate electrode of a second release transistor.

[0212] In an exemplary embodiment, the second conductive layer may include at least a second plate of a capacitor, second plates of a plurality of light emitting capacitors, second plates of a plurality of scan capacitors, a scan output signal line, and a light emitting output signal line.

[0213] In an exemplary embodiment, the third conductive layer may include at least: a light-emitting initial signal line, a first light-emitting clock signal line, a second light-emitting clock signal line, a first light-emitting power line, a second light-emitting power line, a scan initial signal line, a first sub-clock signal line of the first scan clock signal line, a third sub-clock signal line of the second scan clock signal line, a first scan power line, a second scan power line, the first and second electrodes of multiple transistors, the first and second electrodes of multiple light-emitting transistors, the first and second electrodes of multiple scan transistors, the first and second electrodes of the first release transistor, and the first and second electrodes of the second release transistor.

[0214] In an exemplary embodiment, the fourth conductive layer may include at least a second sub-clock signal line of the first scan clock signal line and a fourth sub-clock signal line of the second scan clock signal line.

[0215] In an exemplary embodiment, as shown in Figures 5A and 6A, the first and second electrodes of a plurality of light-emitting transistors are located between the first light-emitting power line EVGH and the second light-emitting power line EVGL, the first and second electrodes of the first release transistor to the first and second electrodes of the second release transistor are located between the second light-emitting power line EVGL and the first scanning power line GVGH, the first and second electrodes of some scanning transistors are located between the scanning initial signal line GSTV and the second scanning power line GVGL, and the first and second electrodes of another part of the scanning transistors can be located on the side of the second scanning power line GVGL close to the display area.

[0216] In an exemplary embodiment, the scanning shift register may be an 8T2C circuit structure, and the light emitting shift register may be a 10T3C or 12T3C circuit structure, which is not limited in the present disclosure.

[0217] In an exemplary embodiment, FIG9A is an equivalent circuit diagram of a scan shift register. As shown in FIG9A , the scan shift register may include: first to eighth scan transistors GT1 to GT8, a first scan capacitor GC1, and a second scan capacitor GC2.

[0218] In an exemplary embodiment, as shown in FIG9A , a gate electrode of the first scanning transistor GT1 is electrically connected to the first clock signal terminal CK1, a first electrode of the first scanning transistor GT1 is electrically connected to the input terminal GIN, and a second electrode of the first scanning transistor GT1 is electrically connected to the first node N1; a gate electrode of the second scanning transistor GT2 is electrically connected to the first node N1, a first electrode of the second scanning transistor GT2 is electrically connected to the first clock signal terminal CK1, and a second electrode of the second scanning transistor GT2 is electrically connected to the second node N2; a gate electrode of the third scanning transistor GT3 is electrically connected to the first clock signal terminal CK1, a first electrode of the third scanning transistor GT3 is electrically connected to the second power supply terminal VGL, and a second electrode of the third scanning transistor GT3 is electrically connected to the second node N2; a gate electrode of the fourth scanning transistor GT4 is electrically connected to the second node N2, a first electrode of the fourth scanning transistor GT4 is electrically connected to the first power supply terminal VGH, and a second electrode of the fourth scanning transistor GT4 is electrically connected to the output terminal GOUT; a gate electrode of the fifth scanning transistor GT5 is electrically connected to the third node N3, a first electrode of the fifth scanning transistor GT5 is electrically connected to the The second clock signal terminal CK2 is electrically connected, and the second electrode of the fifth scanning transistor GT5 is electrically connected to the output terminal GOUT; the gate electrode of the sixth scanning transistor GT6 is electrically connected to the second node N2, the first electrode of the sixth scanning transistor GT6 is electrically connected to the first power supply terminal VGH, and the second electrode of the sixth scanning transistor GT6 is electrically connected to the first electrode of the seventh scanning transistor GT7; the gate electrode of the seventh scanning transistor GT7 is electrically connected to the second clock signal terminal CK2, and the second electrode of the seventh scanning transistor GT7 is electrically connected to the first node N1; the gate electrode of the eighth scanning transistor GT8 is electrically connected to the second power supply terminal VGL, the first electrode of the eighth scanning transistor GT8 is electrically connected to the first node N1, and the second electrode of the eighth scanning transistor GT8 is electrically connected to the third node N3; the first plate GC11 of the first scanning capacitor GC1 is electrically connected to the second node N2, and the second plate GC12 of the first scanning capacitor GC1 is electrically connected to the first power supply terminal VGH; the first plate GC21 of the second scanning capacitor GC2 is electrically connected to the third node N3, and the second plate GC22 of the second scanning capacitor GC2 is electrically connected to the output terminal GOUT.

[0219] In an exemplary embodiment, the first to eighth scanning transistors GT1 to GT8 may be P-type transistors or may be N-type transistors.

[0220] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high level signal, and the second power supply terminal VGL continuously provides a low level signal.

[0221] FIG9B is a timing diagram of the scan shift register provided in FIG9A . FIG9B takes the first scan transistor GT1 to the eighth scan transistor GT8 as an example of P-type transistors. As shown in FIG9B , the operation process of the scan shift register provided by an exemplary embodiment includes the following stages:

[0222] During input phase B1, the signals at the first clock signal terminal CK1 and the input terminal GIN are low-level signals, while the signal at the second clock signal terminal CK2 is high-level. Since the signal at the first clock signal terminal CK1 is low-level, the first scan transistor GT1 is turned on, and the signal at the input terminal GIN is transmitted to the first node N1 via the first scan transistor GT1. Since the signal at the eighth scan transistor GT8 receives the low-level signal from the second power supply terminal VGL, the eighth scan transistor GT8 is turned on. The level at the third node N3 can be adjusted by turning on the fifth scan transistor GT5, and the signal at the second clock signal terminal CK2 is transmitted to the output terminal GOUT via the fifth scan transistor GT5. That is, during input phase B1, the signal at the second clock signal terminal CK2 is high-level at the output terminal GOUT. Furthermore, since the signal at the first clock signal terminal CK1 is low-level, the third scan transistor GT3 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the second node N2 via the third scan transistor GT3. At this time, the fourth scan transistor GT4 and the sixth scan transistor GT6 are both turned on. Since the signal at the second clock signal terminal CK2 is high-level, the seventh scan transistor GT7 is turned off.

[0223] During output phase B2, the signal at the first clock signal terminal CK1 is high, the signal at the second clock signal terminal CK2 is low, and the signal at the input terminal GIN is high. The fifth scanning transistor GT5 is turned on, and the signal at the second clock signal terminal CK2 is transmitted through the fifth scanning transistor GT5 as the signal at the output terminal GOUT. During output phase B2, the signal at the terminal of the second scanning capacitor GC2 connected to the output terminal GOUT becomes the signal at the second power supply terminal VGL. Due to the bootstrap effect of the second scanning capacitor GC2, the eighth scanning transistor GT8 is turned off, allowing the fifth scanning transistor GT5 to be turned on more effectively, and the signal at the output terminal GOUT is low. Furthermore, the signal at the first clock signal terminal CK1 is high, turning off both the first scanning transistor GT1 and the third scanning transistor GT3. The second scanning transistor GT2 is turned on, and the high-level signal at the first clock signal terminal CK1 is transmitted to the second node N2 via the second scanning transistor GT2. Consequently, the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are both turned off. Because the signal at the second clock signal terminal CK2 is low, the seventh scanning transistor GT7 is turned on.

[0224] During the buffering phase B3, the signals at both the first clock signal terminal CK1 and the second clock signal terminal CK2 are high-level signals, the signal at the input terminal GIN is high-level, the fifth scanning transistor GT5 is turned on, and the second clock signal terminal CK2 is output via the fifth scanning transistor GT5. The signal at the first clock signal terminal CK1 is high-level, turning off the first scanning transistor GT1 and the third scanning transistor GT3. The eighth scanning transistor GT8 is turned on, and the second scanning transistor GT2 is turned on. The high-level signal at the first clock signal terminal CK1 is transmitted to the second node N2 via the second scanning transistor GT2. Consequently, the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are both turned off. Since the signal at the second clock signal terminal CK2 is high-level, the seventh scanning transistor GT7 is turned off.

[0225] In the first sub-phase B41 of the stable phase B4, the signal at the first clock signal terminal CK1 is a low-level signal, while the signals at the second clock signal terminal CK2 and the input terminal GIN are high-level signals. Since the signal at the first clock signal terminal CK1 is a low-level signal, the first scan transistor GT1 is turned on, and the signal at the input terminal GIN is transmitted to the first node N1 via the first scan transistor GT1. The second scan transistor GT2 is turned off. Since the eighth scan transistor GT8 is turned on, the fifth scan transistor GT5 is turned off. Since the signal at the first clock signal terminal CK1 is a low-level signal, the third scan transistor GT3 is turned on, and the fourth and sixth scan transistors GT4 and GT6 are both turned on. The high-level signal at the first power supply terminal VGH is transmitted to the output terminal GOUT via the fourth scan transistor GT4. Therefore, the signal at the output terminal GOUT is a high-level signal.

[0226] In the second sub-phase B42 of the stable phase B4, the signal at the first clock signal terminal CK1 is a high-level signal, the signal at the second clock signal terminal CK2 is a low-level signal, and the signal at the input terminal GIN is a high-level signal. The fifth scanning transistor GT5 and the second scanning transistor GT2 are both turned off. The signal at the first clock signal terminal CK1 is a high-level signal, so the first scanning transistor GT1 and the third scanning transistor GT3 are both turned off. Due to the holding effect of the first scanning capacitor GC1, the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are both turned on. The high-level signal is transmitted to the output terminal GOUT via the fourth scanning transistor GT4, that is, the signal at the output terminal GOUT is a high-level signal.

[0227] In the second sub-stage B42, since the signal at the second clock signal terminal CK2 is a low-level signal, the seventh scanning transistor GT7 is turned on, so that the high-level signal is transmitted to the third node N3 and the first node N1 via the sixth scanning transistor GT6 and the seventh scanning transistor GT7, so that the signals at the third node N3 and the first node N1 remain high-level signals.

[0228] In the third sub-phase B43, the signals at the first clock signal terminal CK1 and the second clock signal CK2 are both high-level signals, and the signal at the input terminal GIN is also high-level. The fifth scanning transistor GT5 and the second scanning transistor GT2 are turned off. The signal at the first clock signal terminal CK1 is high-level, so the first scanning transistor GT1 and the third scanning transistor GT3 are both turned off, and the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are both turned on. The high-level signal is transmitted to the output terminal GOUT via the fourth scanning transistor GT4, that is, the signal at the output terminal GOUT is also high-level.

[0229] FIG10A is an equivalent circuit diagram of a light emitting shift register. As shown in FIG10A , the light emitting shift register may include: first to tenth light emitting transistors ET1 to ET10 and first to third light emitting capacitors EC1 to EC3.

[0230] In an exemplary embodiment, as shown in FIG10A , a gate electrode of the first light-emitting transistor ET1 is electrically connected to the first clock signal terminal CK1, a first electrode of the first light-emitting transistor ET1 is electrically connected to the input terminal EIN, and a second electrode of the first light-emitting transistor ET1 is electrically connected to the first node N1; a gate electrode of the second light-emitting transistor ET2 is electrically connected to the first node N1, a first electrode of the second light-emitting transistor ET2 is electrically connected to the first clock signal terminal CK1, and a second electrode of the second light-emitting transistor ET2 is electrically connected to the second node N2; a gate electrode of the third light-emitting transistor ET3 is electrically connected to the first clock signal terminal CK1, and a first electrode of the third light-emitting transistor ET3 is electrically connected to the second power supply terminal VGL , a second electrode of the third light emitting transistor ET3 is electrically connected to the second node N2; a gate electrode of the fourth light emitting transistor ET4 is electrically connected to the second clock signal terminal CK2, a first electrode of the fourth light emitting transistor ET4 is electrically connected to the first node N1, and a second electrode of the fourth light emitting transistor ET4 is electrically connected to a first electrode of the fifth light emitting transistor ET5; a gate electrode of the fifth light emitting transistor ET5 is electrically connected to the second node N2, and a second electrode of the fifth light emitting transistor ET5 is electrically connected to the first power supply terminal VGH; a first electrode of the sixth light emitting transistor ET6 is electrically connected to the second clock signal terminal CK2, and a second electrode of the sixth light emitting transistor ET6 is electrically connected to the third node N3; a gate electrode of the seventh light emitting transistor ET7 is electrically connected to the second node N2, and a second electrode of the fifth light emitting transistor ET5 is electrically connected to the first power supply terminal VGH; The electrode of the seventh light emitting transistor ET7 is electrically connected to the second clock signal terminal CK2, the first electrode of the seventh light emitting transistor ET7 is electrically connected to the third node N3, the second electrode of the seventh light emitting transistor ET7 is electrically connected to the gate electrode of the ninth light emitting transistor ET9; the gate electrode of the eighth light emitting transistor ET8 is electrically connected to the first node N1, the first electrode of the eighth light emitting transistor ET8 is electrically connected to the first power supply terminal VGH, the second electrode of the eighth light emitting transistor ET8 is electrically connected to the gate electrode of the ninth light emitting transistor ET9; the first electrode of the ninth light emitting transistor ET9 is electrically connected to the first power supply terminal VGH, the second electrode of the ninth light emitting transistor ET9 is electrically connected to the output terminal EOUT; the first electrode of the tenth light emitting transistor ET10 is electrically connected to the second The power supply terminal VGL is electrically connected, and the second electrode of the tenth light-emitting transistor ET10 is electrically connected to the output terminal EOUT; the first plate of the first light-emitting capacitor EC1 is electrically connected to the gate electrode of the sixth light-emitting transistor ET6, and the second plate of the first light-emitting capacitor EC1 is electrically connected to the third node N3; the first plate EC21 of the second light-emitting capacitor EC2 is electrically connected to the gate electrode of the ninth light-emitting transistor ET9, and the second plate EC22 of the second light-emitting capacitor EC2 is electrically connected to the first power supply terminal VGH; the first plate E31 of the third light-emitting capacitor EC3 is electrically connected to the gate electrode of the tenth light-emitting transistor ET10, and the second plate EC32 of the third light-emitting capacitor EC3 is electrically connected to the second power supply terminal VGL.

[0231] In an exemplary embodiment, the first to tenth light emitting transistors ET1 to ET10 may be P-type transistors or may be N-type transistors.

[0232] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high level signal, and the second power supply terminal VGL continuously provides a low level signal.

[0233] FIG10B is a timing diagram of the light emitting shift register provided in FIG10A. FIG10B takes the first light emitting transistor ET1 to the tenth light emitting transistor ET10 as P-type transistors as an example. An exemplary embodiment of the light emitting shift register provided by the working process may include the following stages:

[0234] In the first phase C1, the signal at the first clock signal terminal CK1 is at a low level, turning on the first and third light-emitting transistors ET1 and ET3. The turned-on first light-emitting transistor ET1 transmits the high-level signal at the input terminal EIN to the first node N1, causing the signal at the first node N1 to become high. Consequently, the second, eighth, and tenth light-emitting transistors ET2, ET8, and ET10 are turned off. Furthermore, the turned-on third light-emitting transistor ET3 transmits the low-level signal at the second power supply terminal VGL to the second node N2, causing the signal at the second node N2 to become low. Consequently, the fifth and sixth light-emitting transistors ET5 and ET6 are turned on. Because the signal at the second clock signal terminal CK2 is at a high level, the seventh light-emitting transistor ET7 is turned off. Furthermore, due to the storage function of the third light-emitting capacitor EC3, the ninth light-emitting transistor ET9 is turned off. In the first phase C1, because the ninth and tenth light-emitting transistors ET9 and ET10 are both turned off, the signal at the output terminal EOUT remains at its previous low level.

[0235] In the second phase C2, the signal at the second clock signal terminal CK2 is at a low level, turning on the fourth and seventh light-emitting transistors ET4 and ET7. Since the signal at the first clock signal terminal CK1 is at a high level, the first and third light-emitting transistors ET1 and ET3 are turned off. Due to the storage function of the first light-emitting capacitor EC1, the second node N2 can continue to maintain the low level from the previous phase, turning on the fifth and sixth light-emitting transistors ET5 and ET6. The high-level signal from the first power supply terminal VGH is transmitted to the first node N1 through the turned-on fifth and fourth light-emitting transistors ET5 and ET4. The level of the first node N1 continues to remain at the high level from the previous phase, turning off the second, eighth, and tenth light-emitting transistors ET2, ET8, and ET10. Furthermore, the low-level signal from the second clock signal terminal CK2 is transmitted to the gate electrode of the ninth light-emitting transistor ET9 through the turned-on sixth and seventh light-emitting transistors ET6 and ET7. This turns on the ninth light-emitting transistor ET9, which then outputs the high-level signal from the first power supply terminal VGH, resulting in a high signal at the output terminal EOUT.

[0236] In the third phase C3, the signal at the first clock signal terminal CK1 is at a low level, turning on the first and third light-emitting transistors ET1 and ET3. The signal at the second clock signal terminal CK2 is at a high level, turning off the fourth and seventh light-emitting transistors ET4 and ET7. Due to the storage function of the third light-emitting capacitor EC3, the ninth light-emitting transistor ET9 remains on. The turned-on ninth light-emitting transistor ET9 outputs the high-level signal from the first power supply terminal VGH, and the signal at the output terminal EOUT remains high.

[0237] In the fourth phase C4, the signal at the first clock signal terminal CK1 is high, turning off the first and third light-emitting transistors ET1 and ET3. The signal at the second clock signal terminal CK2 is low, turning on the fourth and seventh light-emitting transistors ET4 and ET7. Due to the storage function of the second light-emitting capacitor EC2, the voltage level at the first node N1 remains high, as in the previous phase. The second, eighth, and tenth light-emitting transistors ET2, ET8, and ET10 are turned off. Due to the storage function of the first light-emitting capacitor EC1, the second node N2 continues to maintain the low voltage level from the previous phase, turning on the fifth and sixth light-emitting transistors ET5 and ET6. Furthermore, the low voltage level at the second clock signal terminal CK2 is transmitted to the gate electrode of the ninth light-emitting transistor ET9 via the turned-on sixth and seventh light-emitting transistors ET6 and ET7. Consequently, the ninth light-emitting transistor ET9 turns on and outputs the high voltage level from the first power supply terminal VGH. The signal at the output terminal EOUT remains high.

[0238] In the fifth phase C5, the signal at the first clock signal terminal CK1 is at a low level, turning on the first and third light-emitting transistors ET1 and ET3. The signal at the second clock signal terminal CK2 is at a high level, turning off the fourth and seventh light-emitting transistors ET4 and ET7. The turned-on first light-emitting transistor ET1 transmits the high-level signal at the input terminal EIN to the first node N1, causing the signal at the first node N1 to become low. This turns on the second, eighth, and tenth light-emitting transistors ET2 and ET8, respectively. The turned-on second light-emitting transistor ET2 transmits the low-level signal at the first clock signal terminal CK1 to the second node N2, pulling down the level at the second node N2. This causes the second node N2 to maintain the low level from the previous phase, turning on the fifth and sixth light-emitting transistors ET5 and ET6. Furthermore, the turned-on eighth light-emitting transistor ET8 transmits the high-level signal at the first power supply terminal VGH to the gate electrode of the ninth light-emitting transistor ET9, turning off the ninth light-emitting transistor ET9. The turned-on tenth light-emitting transistor ET10 outputs the low-level signal at the second power supply terminal VGL, causing the signal at the output terminal EOUT to become low.

[0239] In an exemplary embodiment, Figure 11 is a schematic diagram of the structure of the semiconductor layer and the second conductive layer in the display substrate shown in Figure 5A, and Figure 12 is a schematic diagram of the structure of the semiconductor layer and the second conductive layer in the display substrate shown in Figure 6A. As shown in Figures 11 and 12, at least one light-emitting output signal line includes an output connection portion COL and at least one output line OL. The output connection portion COL extends along a first direction D1, and the at least one output line OL is arranged along the first direction D1.

[0240] The output connection portion COL is electrically connected to the light emitting shift register and at least one output line OL. The output line OL corresponds to the light emitting signal line connected to the light emitting output signal line one by one and is electrically connected to the corresponding light emitting signal line.

[0241] In an exemplary embodiment, as shown in FIG11 , in the display substrate provided in FIG5A , the output line OL includes an output main portion OLA extending at least partially along the second direction D2 and an output connection portion OLB extending along the first direction D1 , and the output main portion OLA is electrically connected to the output connection portion OLB.

[0242] In an exemplary embodiment, as shown in FIG5A , the second electrode of the first release transistor and the second electrode of the second release transistor are an integral structure, and their orthographic projections on the substrate at least partially overlap with the orthographic projections of the output connection portion on the substrate, and the integral structure of the second electrode of the first release transistor and the second electrode of the second release transistor is electrically connected to the output connection portion.

[0243] In an exemplary embodiment, as shown in FIG11 , the active layer RT11 of the first release transistor and the active layer RT21 of the second release transistor in the display substrate provided in FIG5A are integrally formed and extend along a second direction D2. The orthographic projection of the output connection portion OLB on the substrate does not overlap with the orthographic projection of the integral structure of the active layer RT11 of the first release transistor and the active layer RT21 of the second release transistor on the substrate.

[0244] In an exemplary embodiment, as shown in FIG12 , the active layer RT11 of the first release transistor and the active layer RT21 of the second release transistor in the display substrate provided in FIG6A are an integrated structure and include: an active main body portion R1 and an active connection portion R2, the active main body portion R1 and the active connection portion R2 are electrically connected, and the active main body portion R1 and the active connection portion R2 are arranged along a first direction D1.

[0245] In an exemplary embodiment, as shown in FIG. 12 , the active body portion R1 extends along the second direction D2 , and the active connection portion R2 at least partially extends along the first direction D1 .

[0246] In an exemplary embodiment, as shown in FIG12 , the active connection portion R2 has a zigzag shape. The zigzag shape of the active connection portion R2 can increase resistance, thereby increasing static electricity consumption, preventing the gate drive circuit from being burned, and improving the display effect and reliability of the display substrate.

[0247] In an exemplary embodiment, as shown in FIG12 , the output line OL extends at least partially along the second direction D2; the second electrode of the first release transistor and the second electrode of the second release transistor are an integral structure. The orthographic projection of the active connection portion R2 on the substrate at least partially overlaps with the integral structure of the second electrode of the first release transistor and the second electrode of the second release transistor, and the orthographic projection of the output line OL on the substrate, and is electrically connected to the integral structure of the second electrode of the first release transistor and the second electrode of the second release transistor, and the output line OL, respectively.

[0248] In an exemplary embodiment, as shown in FIG. 12 , the width of the active connection portion R2 is smaller than the width of the active body portion R1 .

[0249] In an exemplary embodiment, as shown in FIG11 and FIG12 , the scan shift register includes a first scan capacitor, a second plate GC12 of the first scan capacitor is electrically connected to the first scan power line, and the second plate GC21 of the first scan capacitor extends along the second direction D2.

[0250] In an exemplary embodiment, as shown in Figures 5A, 6A, 11 and 12, the orthographic projection of the second plate GC21 of the first scan capacitor on the substrate at least partially overlaps with the orthographic projections of the first scan power line GVGH, the second scan power line GVGL, the first scan clock signal line GCK1, the second scan clock signal line GCK2 and the scan initial signal line GSTV on the substrate.

[0251] In an exemplary embodiment, Figure 13 is another schematic diagram of the structure of a display substrate. As shown in Figure 13, the display area may include a first display area A1 and a second display area A2 located at least to one side of the first display area A1. The display substrate also includes a light-emitting device located in the display area 100 and an anode connection line AL. The pixel circuit is electrically connected to the light-emitting device. The pixel circuit includes a first pixel circuit 11 and a second pixel circuit 12 located in the second display area A2. The light-emitting device includes a first light-emitting device 21 located in the first display area A1 and a second light-emitting device 22 located in the second display area. The first pixel circuit 11 is electrically connected to the first light-emitting device 21, and the second pixel circuit is electrically connected to the second light-emitting device 22.

[0252] As shown in FIG. 13 , the orthographic projection of the first pixel circuit 11 on the substrate at least partially overlaps with the orthographic projection of the first light-emitting device 21 connected to the first pixel circuit 11 on the substrate.

[0253] As shown in FIG. 13 , the anode connection line AL is electrically connected to the second light emitting device 22 and the second pixel circuit 12 connected to the second light emitting device 22 .

[0254] In example embodiments, the anode connection line AL may be a transparent conductive line.

[0255] 7A to 7C , the driving structure layer may further include a first power line VDD and a data signal line Data at least partially located in the display area. The first power line VDD and the data signal line Data at least partially extend along the first direction D1.

[0256] In an exemplary embodiment, the data signal lines Data connected to the columns of pixel circuits located at the left and right sides of the first display area extend along the first direction D1.

[0257] In an exemplary embodiment, as shown in FIG. 7B , the driving structure layer may further include a data link line DL located in the display area, wherein the data link line DL at least partially extends along the second direction D2 .

[0258] In an exemplary embodiment, to ensure the display quality of the first display area, the data signal lines connecting the columns of pixel circuits located on the upper and lower sides of the first display area are arranged around the perimeter of the first display area. Specifically, the data signal lines connecting the columns of pixel circuits located on the upper and lower sides of the first display area are arranged in a zigzag pattern. The data signal lines connecting the columns of pixel circuits located on the upper and lower sides of the first display area include: a plurality of data main lines spaced apart along a first direction, and a plurality of data connection lines spaced apart along a second direction. Adjacent data main lines are connected by the data connection lines, and adjacent data connection lines are connected by the data main lines. To prevent crosstalk between data signals, the data main lines and the data connection lines are arranged on different layers.

[0259] In the display substrate, some pixel circuits include data connection lines, while others do not. FIG7B illustrates the structure of a pixel circuit including data connection lines, while FIG7A and FIG7C illustrate the structure of a pixel circuit not including data connection lines.

[0260] In an exemplary embodiment, the driving structure layer further includes: a fourth conductive layer and a fifth conductive layer sequentially stacked on the third conductive layer.

[0261] In an exemplary embodiment, the third conductive layer includes at least a data connection line.

[0262] In an exemplary embodiment, the fourth conductive layer includes at least a first power line and a data signal line.

[0263] In an exemplary embodiment, the fifth conductive layer includes at least an anode connection line.

[0264] In an exemplary embodiment, as shown in Figures 5A, 6A, and 7A to 7C, the drive structure layer may further include: at least one initial power supply line located in the non-display area and at least one initial signal line located at least partially in the display area; the initial power supply line is located on a side of the scan drive circuit close to the display area, the initial power supply line extending at least partially along a first direction D1, and the initial signal line extending at least partially along a second direction D2. Figures 5 and 6 illustrate an example including two initial power supply lines, such as a first initial power supply line INITL1 and a second initial power supply line INITL2. Figures 7A and 7B illustrate an example including two initial signal lines, a first initial signal line INIT1 and a second initial signal line INIT2.

[0265] In an exemplary embodiment, the initial signal lines correspond to the initial power supply lines one by one, and the initial signal lines are electrically connected to the pixel circuits and the corresponding initial power supply lines, respectively.

[0266] In an exemplary embodiment, the initial power supply line may have a double-layer structure and may include a first sub-initial power supply line and a second sub-initial power supply line electrically connected to each other.

[0267] In an exemplary embodiment, the second conductive layer includes at least an initial signal line.

[0268] In an exemplary embodiment, the third conductive layer includes at least: a first sub-initial power supply line of the initial power supply line;

[0269] In an exemplary embodiment, the fourth conductive layer includes at least a second sub-initial power supply line of the initial power supply line.

[0270] In an exemplary embodiment, as shown in Figures 5B and 6B, the driving structure layer may further include: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a planarizing layer 15, a fifth insulating layer 16, and a sixth insulating layer 17. The first insulating layer 11 is located between the semiconductor layer and the first conductive layer, the second insulating layer 12 is located between the first conductive layer and the second conductive layer, the third insulating layer 13 is located between the second conductive layer and the third conductive layer, the fourth insulating layer 14 and the planarizing layer 15 are located between the third conductive layer and the fourth conductive layer, the fifth insulating layer 16 is located between the fourth conductive layer and the fifth conductive layer, and the sixth insulating layer 17 is located on a side of the fifth conductive layer away from the substrate.

[0271] 5A and 6A , the planar layer is provided with a groove X. The depth of the groove X may be less than or equal to the thickness of the planar layer, which is not limited in the present disclosure.

[0272] In an exemplary embodiment, the orthographic projection of the electrostatic discharge circuit ER on the substrate at least partially overlaps the orthographic projection of the groove X on the substrate. By disposing the electrostatic discharge circuit at the groove position of the flat layer, the present disclosure can achieve a narrow frame without increasing the area occupied by the display frame.

[0273] In an exemplary embodiment, the length of the groove X along the second direction is less than or equal to the distance between the second light emitting power line EVGL and the first scan power line GVGH.

[0274] In an exemplary embodiment, the driving structure layer may further include: a second power connection line and a second power line, wherein the second power line and the second power connection line are electrically connected to each other, and the second power line is electrically connected to the cathode of the light emitting device.

[0275] In an exemplary embodiment, the second power connection line may be located in the third conductive layer, and the second power line may be located in the fourth conductive layer.

[0276] In an exemplary embodiment, an orthographic projection of the second power connection line on the substrate and an orthographic projection of the second power line on the substrate at least partially overlap.The second power line is connected to the second power connection line through a via hole between the fourth insulating layer and the planar layer.

[0277] In an exemplary embodiment, the second power connection line may be linear in shape extending along the second direction D2 and may be located on a side of the light emitting start signal line away from the first light emitting clock signal line.

[0278] In an exemplary embodiment, the shape of the second power line can be a linear shape extending along the second direction D2, and its orthographic projection on the substrate also at least partially overlaps with the orthographic projections of the light-emitting initial signal line, the first light-emitting clock signal line, the second light-emitting clock signal line, and the first light-emitting power line on the substrate.

[0279] In an exemplary embodiment, a plurality of via holes are provided on the second power line.

[0280] In an exemplary embodiment, a distance between an orthographic projection of the second power line on the substrate and an orthographic projection of the second light emitting power line on the substrate is smaller than a distance between the first light emitting power line and the second light emitting power line.

[0281] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. Figures 14 to 33 are illustrated by taking the structures provided in Figures 5A and 6A and located in the non-display area as an example, and Figures 34 to 55 are illustrated by taking the pixel circuits provided in Figures 7B and 7C and located in the display area as an example.

[0282] (1) Forming a semiconductor layer pattern on a substrate, including: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern. As shown in Figures 14, 15, 34, and 35, Figure 14 is a schematic diagram of Figure 5A after the semiconductor layer pattern is formed, Figure 15 is a schematic diagram of Figure 6A after the semiconductor layer pattern is formed, Figure 34 is a schematic diagram of Figure 7B after the semiconductor layer pattern is formed, and Figure 35 is a schematic diagram of Figure 7C after the semiconductor layer pattern is formed.

[0283] In an exemplary embodiment, as shown in Figures 14, 15, 34 and 35, the semiconductor layer pattern may include: an active layer ET11 of the first light-emitting transistor to an active layer ET101 of the tenth light-emitting transistor located in the light-emitting shift register, an active layer RT11 of the first release transistor to an active layer RT21 of the second release transistor located in the electrostatic discharge circuit, an active layer GT11 of the first scanning transistor to an active layer GT81 of the eighth scanning transistor located in the scanning shift register, and an active layer M11 of the first transistor to an active layer M71 of the seventh transistor located in the pixel circuit.

[0284] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0285] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0286] 14 and 15 , the active layers ET41 and ET51 of the fourth and fifth light emitting transistors are connected as one body. The active layers ET91 and ET101 of the ninth and tenth light emitting transistors are connected as one body.

[0287] In an exemplary embodiment, as shown in Figures 14 and 15, in the second direction D2, the active layers ET11 of the first to eighth light-emitting transistors ET81 are located on the side of the active layer ET91 of the ninth light-emitting transistor (also the active layer ET101 of the tenth light-emitting transistor) away from the display area. The active layer ET71 of the seventh light-emitting transistor is located on the side of the active layer ET81 of the eighth light-emitting transistor away from the display area. The active layers ET11 of the first light-emitting transistor and ET41 of the fourth light-emitting transistor (also the active layer ET51 of the fifth light-emitting transistor) are located on the side of the active layer ET21 of the second light-emitting transistor away from the display area. The active layers ET31 of the third light-emitting transistor and ET61 of the sixth light-emitting transistor are located on the side of the active layer ET21 of the second light-emitting transistor close to the active layer ET91 of the ninth light-emitting transistor (also the active layer ET101 of the tenth light-emitting transistor). In the first direction D1, the active layer ET51 of the fifth light-emitting transistor of the current level light-emitting shift register is located on the side of the active layer ET41 of the fourth light-emitting transistor close to the next level light-emitting shift register, and the active layer ET11 of the first light-emitting transistor to the active layer ET61 of the sixth light-emitting transistor of the current level shift register are located on the side of the active layer ET81 of the eighth light-emitting transistor close to the previous level light-emitting shift register.

[0288] In an exemplary embodiment, as shown in Figures 14 and 15, the active layers ET11 to ET71 of the first to seventh light-emitting transistors, the active layers ET91 of the ninth light-emitting transistor, and the active layer ET101 of the tenth light-emitting transistor may have a strip shape extending along the first direction D1. The active layer ET81 of the eighth light-emitting transistor may have a strip shape extending along the second direction D2.

[0289] In an exemplary embodiment, the active layer of each light emitting transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region ET41-1 of the active layer ET41 of the fourth light emitting transistor may also serve as the second region ET51-2 of the active layer ET51 of the fifth light emitting transistor, the first region ET11-1 and the second region ET11-2 of the active layer ET11 of the first light emitting transistor, the first region ET21-1 and the second region ET21-2 of the active layer ET21 of the second light emitting transistor, the first region ET31-1 and the second region ET31-2 of the active layer ET31 of the third light emitting transistor, the second region ET41-2 of the active layer ET41 of the fourth light emitting transistor, and the fifth light emitting transistor. The first region ET51-1 of the active layer ET51, the first region ET61-1 and the second region ET61-2 of the active layer ET61 of the sixth light-emitting transistor, the first region ET71-1 and the second region ET71-2 of the active layer ET71 of the seventh light-emitting transistor, the first region ET81-1 and the second region ET81-2 of the active layer ET81 of the eighth light-emitting transistor, the first region ET91-1 and the second region ET91-2 of the active layer ET91 of the ninth light-emitting transistor, and the first region ET101-1 and the second region ET101-2 of the active layer ET101 of the tenth light-emitting transistor can be set separately.

[0290] In an exemplary embodiment, as shown in Figures 14 and 15, the active layer RT11 of the first release transistor and the active layer RT21 of the second release transistor are connected to each other as an integral structure. The active layer RT11 of the first release transistor and the active layer RT21 of the second release transistor are located on the side of the active layer ET91 of the ninth light-emitting transistor (also the active layer ET101 of the tenth light-emitting transistor) closer to the display area.

[0291] In an exemplary embodiment, as shown in FIG. 14 and FIG. 15 , in the second direction D2 , the active layer RT21 of the second release transistor is located on a side of the active layer RT11 of the first release transistor close to the display area.

[0292] In an exemplary embodiment, as shown in FIG. 14 , the active layer RT11 of the first release transistor (also the active layer RT21 of the second release transistor) in the display substrate provided in FIG. 3B may be shaped like a strip extending along the second direction D2 .

[0293] In an exemplary embodiment, as shown in FIG15 , the active layer RT11 of the first release transistor (also the active layer RT21 of the second release transistor) in the display substrate shown in FIG3C may include an active body portion R1 and an active connection portion R2. The active body portion R1 and the active connection portion R2 are interconnected and integrally structured and arranged along a first direction D1.

[0294] In an exemplary embodiment, as shown in FIG. 15 , the active body portion R1 may be in the shape of a bar extending along the second direction D2 , and the active connection portion R2 may be in the shape of a zigzag extending at least partially along the first direction D1 .

[0295] In an exemplary embodiment, as shown in FIG. 15 , the width of the active connection portion R2 may be smaller than the width of the active body portion R1 .

[0296] In an exemplary embodiment, the active layer of each release transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region RT11-2 of the active layer RT11 of the first release transistor may also serve as the second region RT21-2 of the active layer RT21 of the second release transistor. The first region RT11-1 of the active layer RT11 of the first release transistor and the first region RT21-1 of the active layer RT21 of the second release transistor may be provided separately.

[0297] In an exemplary embodiment, as shown in FIG. 15 , the second region RT11 - 2 of the active layer RT11 of the first release transistor (the second region RT21 - 2 of the active layer RT21 of the second release transistor) includes a middle section of an active body portion and an active connection portion R2 .

[0298] In the exemplary embodiment, as shown in Figures 14 and 15, the active layer GT11 of the first scan transistor, the active layer GT61 of the sixth scan transistor, and the active layer GT71 of the seventh scan transistor are connected to each other as an integral structure. The active layer GT21 of the second scan transistor and the active layer GT31 of the third scan transistor are connected to each other as an integral structure. The active layer GT41 of the fourth scan transistor and the active layer GT51 of the fifth scan transistor are connected to each other as an integral structure.

[0299] In an exemplary embodiment, as shown in Figures 14 and 15, in the second direction D2, the active layers GT11 to GT31 of the first to third scan transistors and the active layers GT51 to GT81 of the fifth to eighth scan transistors are located on the side of the active layer GT41 of the fourth scan transistor (also the active layer GT51 of the fifth transistor) away from the display area, and on the side of the active layer RT11 of the first release transistor (also the active layer RT21 of the second release transistor) closer to the display area. The active layer GT21 of the second scan transistor (also the active layer GT31 of the third scan transistor) is located between the active layer GT11 of the first scan transistor (the active layer GT61 of the sixth scan transistor and the active layer GT71 of the seventh scan transistor) and the active layer GT81 of the eighth scan transistor. The active layer GT11 of the first scan transistor (the active layer GT61 of the sixth scan transistor and the active layer GT71 of the seventh scan transistor) is located on the side of the active layer GT21 of the second scan transistor (also the active layer GT31 of the third scan transistor) close to the active layer RT11 of the first release transistor (also the active layer RT21 of the second release transistor). The active layer GT81 of the eighth scan transistor is located on the side of the active layer GT21 of the second scan transistor (also the active layer GT31 of the third scan transistor) close to the active layer GT41 of the fourth scan transistor (also the active layer GT51 of the fifth transistor). In the first direction D1, the active layer GT41 of the fourth scan transistor of the current stage scan shift register is located on the side of the active layer GT51 of the fifth transistor close to the scan shift register of the next stage.

[0300] In an exemplary embodiment, as shown in FIG14 and FIG15 , the active layer GT11 of the first scan transistor, the active layer GT41 of the fourth scan transistor, the active layer GT51 of the fifth transistor, the active layer GT61 of the sixth scan transistor, the active layer GT71 of the seventh scan transistor, and the active layer GT81 of the eighth scan transistor may be shaped like a line extending along the first direction D1. The active layer GT21 of the second scan transistor may be shaped like a line extending along the second direction D2. The active layer GT31 of the third scan transistor may be shaped like a horizontally inverted "7."

[0301] In an exemplary embodiment, the active layer of each scan transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region GT11-2 of the active layer GT11 of the first scan transistor may serve as the second region GT71-2 of the active layer GT71 of the seventh scan transistor, the second region GT21-2 of the active layer GT21 of the second scan transistor may serve as the second region GT31-2 of the active layer GT31 of the third scan transistor, and the second region GT41-2 of the active layer GT41 of the fourth scan transistor may serve as the second region GT51-2 of the active layer GT51 of the fifth scan transistor. The second region GT61-2 of the active layer GT61 of the sixth scan transistor may serve as the second region GT71-1 of the active layer GT71 of the seventh scan transistor.

[0302] In an exemplary embodiment, as shown in FIG. 34 and FIG. 35 , the active layer M11 of the first transistor to the active layer M71 of the seventh transistor in the same sub-pixel are an integral structure connected to each other.

[0303] In an exemplary embodiment, as shown in Figures 34 and 35, in the second direction D2, the active layer M21 of the second transistor and the active layer M61 of the sixth transistor can be located on the same side of the active layer M31 of the third transistor in the present sub-pixel, the active layer M41 of the fourth transistor and the active layer M51 of the fifth transistor can be located on the same side of the active layer M31 of the third transistor in the present sub-pixel, and the active layer M21 of the second transistor and the active layer M41 of the fourth transistor can be located on different sides of the active layer M31 of the third transistor of the present sub-pixel. In the first direction D1, the active layer M11 of the first transistor, the active layer M21 of the second transistor, and the active layer M41 of the fourth transistor in the current row of sub-pixels can be located on the side of the active layer M31 of the third transistor in the current sub-pixel away from the sub-pixels in the previous row, and the active layer M51 of the fifth transistor, the active layer M61 of the sixth transistor, and the active layer M71 of the seventh transistor in the current sub-pixel can be located on the side of the active layer M31 of the third transistor in the current sub-pixel close to the sub-pixels in the previous row.

[0304] In an exemplary embodiment, as shown in Figures 34 and 35, the active layer M11 of the first transistor may have an "n" shape, the active layer M51 of the fifth transistor and the active layer M61 of the sixth transistor may have an "L" shape, the active layer M31 of the third transistor may have an "Ω" shape, and the active layer M41 of the fourth transistor and the active layer M71 of the seventh transistor may have an "I" shape.

[0305] In an exemplary embodiment, as shown in FIG. 34 , the active layer M21 of the second transistor may have a zigzag shape including two bends.

[0306] In an exemplary embodiment, as shown in FIG. 35 , the active layer M21 of the second transistor may be shaped like an “L”.

[0307] In an exemplary embodiment, as shown in FIG34 and FIG35, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region M11-2 of the active layer M11 of the first transistor may serve as the first region M21-1 of the active layer M21 of the second transistor, the first region M31-1 of the active layer M31 of the third transistor may serve as the second region M41-2 of the active layer M41 of the fourth transistor and the second region M51-2 of the active layer M51 of the fifth transistor, and the second region M31-2 of the active layer M31 of the third transistor may serve as the active layer M21 of the second transistor. The second region M21-2 and the first region M61-1 of the active layer M61 of the sixth transistor, the second region M61-2 of the active layer M61 of the sixth transistor can serve as the second region M71-2 of the active layer M71 of the seventh transistor, the first region M11-1 of the active layer of the first transistor, the first region M41-1 of the active layer M41 of the fourth transistor, the first region M51-1 of the active layer M51 of the fifth transistor and the first region M71-1 of the active layer M71 of the seventh transistor can be set separately.

[0308] (2) forming a first conductive layer pattern, comprising: depositing a first insulating film and a first conductive film on a substrate having the aforementioned pattern formed thereon, patterning the first insulating film and the first conductive film through a patterning process to form a first insulating layer pattern and a first conductive layer pattern disposed on the first insulating layer pattern, as shown in Figures 16 to 18 and Figures 36 to 39, Figure 16 is a schematic diagram of the first conductive layer pattern of Figures 5A and 6A, Figure 17 is a schematic diagram of Figure 5A after the first conductive layer pattern is formed, Figure 18 is a schematic diagram of the display substrate provided in Figure 6A after the first conductive layer pattern is formed, Figure 36 is a schematic diagram of the first conductive layer pattern of Figure 7B, Figure 37 is a schematic diagram of Figure 7B after the first conductive layer pattern is formed, Figure 38 is a schematic diagram of the first conductive layer pattern of Figure 7C, and Figure 39 is a schematic diagram of Figure 7C after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0309] In an exemplary embodiment, as shown in Figures 16 to 18 and Figures 36 to 39, the first conductive layer pattern may at least include: the gate electrode ET12 of the first light-emitting transistor to the gate electrode ET102 of the tenth light-emitting transistor located in the light-emitting shift register and the first plate EC11 of the first light-emitting capacitor to the first plate EC31 of the third light-emitting capacitor, the gate electrode RT12 of the first release transistor and the gate electrode RT22 of the second release transistor located in the electrostatic release circuit, the gate electrode GT12 of the first scanning transistor to the gate electrode GT82 of the scanning light-emitting transistor located in the scanning shift register and the first plate GC11 of the first scanning capacitor and the first plate GC21 of the second scanning capacitor, the first signal connection line L1 and the second signal connection line L2, the reset signal line Reset, the scanning signal line Gate, the light-emitting signal line EM, the gate electrode M11 of the first transistor to the gate electrode M71 of the seventh transistor and the first plate C1 of the capacitor.

[0310] In an exemplary embodiment, as shown in Figures 16 to 18, the gate electrode ET12 of the first light-emitting transistor and the gate electrode ET32 of the third light-emitting transistor are interconnected as an integrated structure. The gate electrode ET22 of the second light-emitting transistor, the gate electrode ET82 of the eighth light-emitting transistor, the gate electrode ET102 of the tenth light-emitting transistor, and the first electrode plate EC31 of the third light-emitting capacitor are interconnected as an integrated structure. The gate electrode ET52 of the fifth light-emitting transistor, the gate electrode ET62 of the sixth light-emitting transistor, and the first electrode plate EC11 of the first light-emitting capacitor are interconnected as an integrated structure. The gate electrode ET2 of the ninth light-emitting transistor and the first electrode plate EC21 of the second light-emitting capacitor are interconnected as an integrated structure. The gate electrode ET42 of the fourth light-emitting transistor and the gate electrode ET72 of the seventh light-emitting transistor can be provided separately.

[0311] In an exemplary embodiment, as shown in Figures 16 to 18 , in the second direction D2, the first plate EC31 of the third light-emitting capacitor is located on the side of the first plate EC11 of the first light-emitting capacitor close to the display area, the gate electrode ET22 of the second light-emitting transistor is located on the side of the first plate EC31 of the third light-emitting capacitor away from the display area, the gate electrode ET102 of the tenth light-emitting transistor is located on the side of the first plate EC31 of the third light-emitting capacitor close to the display area, the gate electrode ET92 of the ninth light-emitting transistor is located on the side of the first plate EC21 of the second light-emitting capacitor close to the display area, the gate electrode ET52 of the fifth light-emitting transistor is located on the side of the first plate EC11 of the first light-emitting capacitor away from the display area, and the gate electrode ET62 of the sixth light-emitting transistor is located on the side of the first plate EC11 of the first light-emitting capacitor close to the display area. In the first direction D1, the gate electrode ET82 of the eighth light-emitting transistor of the current-stage light-emitting shift register is located on the side of the first plate EC31 of the third light-emitting capacitor close to the next-stage light-emitting shift register. The first plate EC11 of the first light emitting capacitor and the first plate EC31 of the third light emitting capacitor of the current stage shift light emitting shift register are located on the side of the first plate EC21 of the second light emitting capacitor close to the previous stage light emitting shift register.

[0312] In an exemplary embodiment, as shown in Figures 16 to 18, the gate electrode ET12 of the first light-emitting transistor, the gate electrode ET42 of the fourth light-emitting transistor, the gate electrode ET52 of the fifth light-emitting transistor, the gate electrode ET62 of the sixth light-emitting transistor, and the gate electrode ET72 of the seventh light-emitting transistor may be shaped like a strip extending at least partially along the second direction D2.

[0313] In an exemplary embodiment, as shown in Figures 16 to 18, the shape of the gate electrode ET22 of the second light-emitting transistor can be rectangular, and an opening is provided on the gate electrode ET22 of the second light-emitting transistor. The shape of the opening can be rectangular and can be located in the middle of the gate electrode ET22 of the second light-emitting transistor, so that the gate electrode ET22 of the second light-emitting transistor forms a ring structure.

[0314] In an exemplary embodiment, as shown in FIG. 16 to FIG. 18 , the gate electrode ET32 of the third light emitting transistor may have an inverted “T” shape.

[0315] In an exemplary embodiment, as shown in FIG. 16 to FIG. 18 , the gate electrode ET82 of the eighth light emitting transistor may be in the shape of a bar extending at least partially along the first direction D1 , or may be in the shape of a broken line.

[0316] In an exemplary embodiment, as shown in Figures 16 to 18, the shape of the gate electrode ET92 of the ninth light-emitting transistor may include a first connecting segment extending along the first direction D1 and a plurality of first branch segments extending along the second direction D2, the first connecting segment is connected to the first plate of the second capacitor, and the first branch segments are located on a side of the first connecting segment close to the display area. The gate electrode ET92 of the ninth light-emitting transistor may be shaped like a comb, with the first connecting segment serving as the back of the comb and the first branch segments serving as the teeth of the comb.

[0317] In an exemplary embodiment, as shown in Figures 16 to 18, the shape of the gate electrode ET102 of the tenth light-emitting transistor may include a plurality of second branch segments extending along the second direction D2, and the plurality of second branch segments and the first electrode EC31 of the third light-emitting capacitor may be in a comb-like structure, with the first electrode of the third light-emitting capacitor serving as a comb back and the plurality of second branch segments serving as comb teeth.

[0318] In an exemplary embodiment, as shown in FIG. 16 to FIG. 18 , the first electrode plate EC11 of the first light emitting capacitor may be in the shape of a strip extending at least partially along the first direction D1 , and may be provided with a protrusion on a side away from the display area.

[0319] In an exemplary embodiment, as shown in FIG. 16 to FIG. 18 , the first electrode plate EC21 of the second light emitting capacitor may be in the shape of a strip extending along the second direction D2 .

[0320] In an exemplary embodiment, as shown in FIG. 16 to FIG. 18 , the first electrode plate EC31 of the third light emitting capacitor may be in the shape of a strip extending along the first direction D1 .

[0321] In an exemplary embodiment, as shown in Figures 16 to 18, the gate electrode ET12 of the first light-emitting transistor is arranged across the channel region of the active layer of the first light-emitting transistor, the gate electrode ET22 of the second light-emitting transistor is arranged across the channel region of the active layer of the second light-emitting transistor, the gate electrode ET32 of the third light-emitting transistor is arranged across the channel region of the active layer of the third light-emitting transistor, the gate electrode ET42 of the fourth light-emitting transistor is arranged across the channel region of the active layer of the fourth light-emitting transistor, the two first branch segments ET55 of the gate electrode ET52 of the fifth light-emitting transistor are arranged across the channel region of the active layer of the fifth light-emitting transistor, and the gate electrode ET62 of the sixth light-emitting transistor is arranged across the channel region of the active layer of the fifth light-emitting transistor. The gate electrode ET62 is arranged across the channel region of the active layer of the first light-emitting transistor, the gate electrode ET72 of the seventh light-emitting transistor is arranged across the channel region of the active layer of the seventh light-emitting transistor, the gate electrode ET82 of the eighth light-emitting transistor is arranged across the channel region of the active layer of the eighth light-emitting transistor, multiple first branch segments of the gate electrode ET92 of the ninth light-emitting transistor are arranged across the channel region of the active layer of the ninth light-emitting transistor, and the gate electrode ET102 of the tenth light-emitting transistor is arranged across the channel region of the active layer of the tenth light-emitting transistor. That is, the extension direction of the gate electrode of at least one light-emitting transistor is perpendicular to the extension direction of the channel region of the active layer.

[0322] In an exemplary embodiment, as shown in FIG. 16 to FIG. 18 , since the gate electrode ET22 of the second light emitting transistor has a ring structure, the second light emitting transistor has a double-gate structure.

[0323] In exemplary embodiments, as shown in FIGS. 16 to 18 , the gate electrode RT12 of the first release transistor and the gate electrode RT22 of the second release transistor may be shaped like a bar extending in the first direction D1 .

[0324] In an exemplary embodiment, as shown in Figures 16 to 18, the gate electrode RT12 of the first release transistor is arranged across the channel region of the active layer of the first transistor, and the gate electrode RT22 of the second release transistor is arranged across the channel region of the active layer of the second transistor, that is, the extension direction of the gate electrode of at least one release transistor is perpendicular to the extension direction of the active layer.

[0325] In an exemplary embodiment, as shown in Figures 16 to 18, the gate electrode GT12 of the first scan transistor and the gate electrode GT32 of the third scan transistor are connected to each other as an integral structure. The gate electrode GT42 of the fourth scan transistor, the gate electrode GT62 of the sixth scan transistor, and the first plate GC31 of the first scan capacitor are connected to each other as an integral structure. The gate electrode GT52 of the fifth scan transistor and the first plate EC21 of the second scan capacitor are connected to each other as an integral structure. The gate electrode GT22 of the second scan transistor, the gate electrode GT72 of the seventh scan transistor, and the gate electrode GT82 of the eighth scan transistor can be provided separately.

[0326] In an exemplary embodiment, as shown in Figures 16 to 18, in the second direction D2, the first plate GC11 of the first scanning capacitor is located on a side of the first plate GC21 of the second scanning capacitor away from the display area, the gate electrode GT52 of the fifth scanning transistor is located on a side of the first plate EC21 of the second scanning capacitor away from the display area, the gate electrode GT42 of the fourth scanning transistor is located on a side of the first plate GC31 of the first scanning capacitor close to the display area, and the gate electrode GT62 of the sixth scanning transistor is located on a side of the first plate GC31 of the first scanning capacitor away from the display area.

[0327] In an exemplary embodiment, as shown in FIG. 16 to FIG. 18 , the shape of the gate electrode GT12 of the first scan transistor may include a second connecting segment and two third branch segments, the third branch segments being located on a side of the second connecting segment away from the display area, and the second connecting end being connected to the gate electrode GT32 of the third scan transistor. The two branch segments may have different lengths.

[0328] In exemplary embodiments, as shown in FIG. 16 to FIG. 18 , the shape of the gate electrode GT22 of the second scan transistor may include a gate body portion extending in the second direction D2 and a gate connection portion extending in the first direction D1 .

[0329] In an exemplary embodiment, as shown in Figures 16 to 18, the gate electrode GT32 of the third scanning transistor, the gate electrode GT42 of the fourth scanning transistor, the gate electrode GT62 of the sixth scanning transistor, the gate electrode GT72 of the seventh scanning transistor, and the gate electrode GT82 of the eighth scanning transistor may be shaped like a strip extending at least partially along the second direction D2.

[0330] In an exemplary embodiment, as shown in Figures 16 to 18, the shape of the gate electrode GT52 of the fifth scanning transistor may include a plurality of fourth branch segments extending along the second direction D2, and the shape of the gate electrode GT52 of the fifth scanning transistor may be a comb, with the first plate GC21 of the second scanning capacitor serving as the comb back and the plurality of fourth branch segments serving as the comb teeth.

[0331] In an exemplary embodiment, as shown in FIG. 16 to FIG. 18 , the first plate GC11 of the first scan capacitor may be shaped like a strip extending at least partially along the second direction D2 .

[0332] In an exemplary embodiment, as shown in FIG. 16 to FIG. 18 , the first electrode plate ECG1 of the second scanning capacitor may be shaped like a strip extending along the first direction D1 .

[0333] In an exemplary embodiment, as shown in Figures 16 to 18, the two third branch segments of the gate electrode GT12 of the first scan transistor are arranged across the channel region of the active layer of the first scan transistor, the gate connection portion of the gate electrode GT22 of the second scan transistor is arranged across the channel region of the active layer of the second scan transistor, the gate electrode GT32 of the third scan transistor is arranged across the channel region of the active layer of the third scan transistor, the gate electrode GT42 of the fourth scan transistor is arranged across the channel region of the active layer of the fourth scan transistor, the two first branch segments GT55 of the gate electrode GT52 of the fifth scan transistor are arranged across the channel region of the active layer of the fifth scan transistor, the gate electrode GT62 of the sixth scan transistor is arranged across the channel region of the active layer of the first scan transistor, the gate electrode GT72 of the seventh scan transistor is arranged across the channel region of the active layer of the seventh scan transistor, and the gate electrode GT82 of the eighth scan transistor is arranged across the channel region of the active layer of the eighth scan transistor. That is, the extension direction of the gate electrode of at least one scan transistor is perpendicular to the extension direction of the channel region of the active layer.

[0334] In an exemplary embodiment, as shown in FIG. 16 to FIG. 18 , the two third branch segments of the gate electrode GT12 of the first scan transistor are arranged across the channel region of the active layer of the first scan transistor, and the first scan transistor has a dual-gate structure.

[0335] In exemplary embodiments, as shown in FIG. 16 and FIG. 17 , the first signal connection line L1 and the second signal connection line L2 may at least partially extend in the second direction D2 .

[0336] In an exemplary embodiment, as shown in Figures 36 to 39 , the first plate C1 of the capacitor may be rectangular, with chamfered corners. The orthographic projection of the first plate C1 of the capacitor on the substrate at least partially overlaps the orthographic projection of the active layer of the third transistor on the substrate. In an exemplary embodiment, the first plate C1 of the capacitor may also serve as the gate electrode M32 of the third transistor.

[0337] In exemplary embodiments, as shown in Figures 36 to 39 , the reset signal line Reset may be in the shape of a line with a main portion extending along the second direction D2. The reset signal line Reset connected to the sub-pixels in the current row may be located on a side of the first electrode C1 of the current sub-pixel that is closer to the sub-pixels in the previous row. The region where the reset signal line Reset overlaps with the active layer of the first transistor serves as the gate electrode MT12 of the first transistor in the dual-gate structure.

[0338] In an exemplary embodiment, as shown in Figures 36 to 39, the shape of the scanning signal line Gate can be a line shape with a main portion extending along the second direction D2, the scanning signal line Gate connected to the sub-pixels of this row can be located on the side of the reset signal line Reset connected to the sub-pixels close to the first electrode C1, and the area where the scanning signal line Gate overlaps with the active layer of the second transistor of the sub-pixel serves as the gate electrode MT22 of the second transistor of the dual-gate structure, and the area where the scanning signal line Gate overlaps with the active layer of the fourth transistor serves as the gate electrode MT42 of the fourth transistor.

[0339] In an exemplary embodiment, as shown in Figures 36 to 39 , the scan signal line Gate includes a signal main portion 21 and a signal connection portion 22. One end of the signal connection portion 22 is electrically connected to the signal main portion 21. The signal main portion 21 extends along the second direction D2, and the signal connection portion 22 extends along the first direction D1.

[0340] In an exemplary embodiment, as shown in FIG. 36 and FIG. 37 , the signal connection portion 22 is located on a side of the signal main portion 21 close to the first plate of the capacitor.

[0341] In an exemplary embodiment, as shown in FIG. 38 and FIG. 39 , the signal connection portion 22 is located on a side of the signal main portion 21 away from the first plate of the capacitor.

[0342] In an exemplary embodiment, the shape of the light-emitting signal line EM can be a line shape in which the main part extends along the second direction D2. The light-emitting signal line EM can be located on the side of the first plate C1 of the capacitor of this sub-pixel close to the next row of sub-pixels. The area where the light-emitting signal line EM overlaps with the active layer of the fifth transistor of this sub-pixel serves as the gate electrode MT52 of the fifth transistor, and the area where the light-emitting signal line EM overlaps with the active layer of the sixth transistor of this sub-pixel serves as the gate electrode MT62 of the sixth transistor.

[0343] In an exemplary embodiment, the reset signal line Reset, the scanning signal line Gate, and the light-emitting signal line EM can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0344] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductorized using the first conductive layer as a shield, and the semiconductor layer in the area blocked by the first conductive layer forms the channel region of the first to tenth light-emitting transistors, the channel region of the first to second release transistors, and the channel region of the first to eighth scan transistors, and the semiconductor layer in the area not blocked by the first conductive layer is conductorized, that is, the first and second areas of the active layers of the first to tenth light-emitting transistors, the first and second areas of the active layers of the first to second release transistors, and the first and second areas of the active layers of the first to eighth scan transistors are all conductorized. In an exemplary embodiment, as shown in Figures 16 and 17, the first area of ​​the active layer of the fourth light-emitting transistor (which is also the second area of ​​the active layer of the fifth light-emitting transistor) is multiplexed as the first electrode of the fourth light-emitting transistor (which is also the second area of ​​the active layer of the fifth light-emitting transistor), the second area of ​​the active layer of the sixth scan transistor (which is also the first area of ​​the active layer of the seventh scan transistor) is multiplexed as the second electrode of the sixth scan transistor (which is also the first area of ​​the active layer of the seventh scan transistor), the second area of ​​the active layer of the second transistor (which is also the second area of ​​the active layer of the third transistor and the first area of ​​the active layer of the sixth transistor) is multiplexed as the second electrode of the second transistor (which is also the second area of ​​the active layer of the third transistor and the first area of ​​the active layer of the sixth transistor), and the first area of ​​the active layer of the third transistor (which is also the second area of ​​the active layer of the fourth transistor and the second area of ​​the active layer of the fifth transistor) is multiplexed as the first electrode of the third transistor (which is also the second electrode of the fourth transistor and the second electrode of the fifth transistor).

[0345] (3) Forming a second insulating layer pattern, including: In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film using a patterning process to form a second insulating layer covering the first conductive layer, and providing a via hole on the second insulating layer, as shown in FIG19 , which is a schematic diagram of the display substrate provided in FIG6A after the second insulating layer pattern is formed.

[0346] In an exemplary embodiment, the vias include at least a via V0 located in at least the electrostatic discharge circuit. The orthographic projection of the via V0 on the substrate is located within the orthographic projection of the active connection portion on the substrate, exposing the surface of the active connection portion. The via V0 is configured to connect a subsequently formed light-emitting output signal line to the active connection portion through the via.

[0347] In an exemplary embodiment, a second insulating layer is also formed in FIG. 5A , FIG. 7B , and FIG. 7C , but no via hole is provided on the second insulating layer.

[0348] (4) forming a second conductive layer pattern, comprising: depositing a second conductive film on the substrate having the aforementioned pattern, patterning the second conductive film through a patterning process to form a second conductive layer pattern located on the second insulating layer pattern, as shown in Figures 20 to 23 and Figures 40 to 43, Figure 20 is a schematic diagram of the second conductive layer pattern of Figure 5A, Figure 21 is a schematic diagram of Figure 5A after the second conductive layer pattern is formed, Figure 22 is a schematic diagram of the second conductive layer of Figure 6A, Figure 23 is a schematic diagram of Figure 6A after the second conductive layer pattern is formed, Figure 40 is a schematic diagram of the second conductive layer pattern of Figure 7B, Figure 41 is a schematic diagram of Figure 7B after the second conductive layer pattern is formed, Figure 42 is a schematic diagram of the second conductive layer pattern of Figure 7C, and Figure 43 is a schematic diagram of Figure 7C after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0349] In an exemplary embodiment, as shown in Figures 20 to 23 and Figures 40 to 43, the second conductive layer pattern may include at least: the second plate EC12 of the first light-emitting capacitor to the second plate EC32 of the third light-emitting capacitor located in the light-emitting shift register, the first plate GC12 of the first scan capacitor and the second plate GC22 of the second scan capacitor located in the scan shift register, the second plate C2 of the capacitor located in the pixel circuit, the scan signal output line GOL, the light-emitting signal output line EOL, the third signal connection line L3, the first initial signal line INIT1 and the second initial signal line INIT2.

[0350] In exemplary embodiments, as shown in FIG. 42 and FIG. 43 , the second conductive layer pattern may further include a shielding electrode SL.

[0351] In an exemplary embodiment, as shown in Figures 20 to 23, the orthographic projection of the second plate EC12 of the first light-emitting capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the first light-emitting capacitor on the substrate. The orthographic projection of the second plate EC22 of the second light-emitting capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the second light-emitting capacitor on the substrate. The orthographic projection of the second plate EC32 of the third light-emitting capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the third light-emitting capacitor on the substrate.

[0352] In an exemplary embodiment, as shown in FIG. 20 to FIG. 23 , the scan output signal line GOL and the second plate GC22 of the second scan capacitor are connected as an integral structure and are located on a side of the second plate GC22 of the second scan capacitor close to the display area.

[0353] In an exemplary embodiment, as shown in Figures 20 to 23, the orthographic projection of the second plate GC12 of the first scanning capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the first scanning capacitor on the substrate. The orthographic projection of the second plate GC22 of the second scanning capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the second scanning capacitor on the substrate.

[0354] In an exemplary embodiment, as shown in FIG. 20 to FIG. 23 , the scan output signal line GOL at least partially extends along the second direction D2 .

[0355] In an exemplary embodiment, as shown in FIG. 20 to FIG. 23 , the third signal connection line L3 has a bar shape extending along the second direction D2 .

[0356] In an exemplary embodiment, as shown in Figures 20 to 23, the light emitting output signal line may include an output connection portion COL connected to at least one output line OL. The plurality of output lines OL are arranged along a first direction D1. At least one output line OL is located on a side of the output connection portion COL close to the display area.

[0357] In an exemplary embodiment, as shown in FIG. 20 to FIG. 23 , the output connection portion COL extends in the first direction D1 , and the output line OL at least partially extends in the second direction D2 .

[0358] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the output line OL in FIG. 5A includes an output main body portion OLA and an output connection portion OLB, and the output main body portion OLA and the output connection portion OLB are an integral structure connected to each other.

[0359] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the output body portion OLA extends in the second direction D2 , and the output connection portion OLB extends in the first direction D1 .

[0360] In an exemplary embodiment, as shown in FIG. 22 and FIG. 23 , the orthographic projection of the output line OL in FIG. 6A on the substrate at least partially overlaps with the orthographic projection of the active connection portion on the substrate and is connected to the active connection portion through a via.

[0361] In an exemplary embodiment, as shown in FIG. 40 to FIG. 43 , the second plates C2 of the capacitors of adjacent sub-pixels located in the same row are electrically connected.

[0362] In an exemplary embodiment, as shown in Figures 40 and 41 , the second plate C2 of the capacitor includes a capacitor body 50, a first capacitor connecting portion 51, a second capacitor connecting portion 52, and a third capacitor connecting portion 53. In the second direction D2, the first capacitor connecting portion 51 and the second capacitor connecting portion 52 are located on either side of the capacitor body 50, respectively. In the first direction D1, the third capacitor connecting portion 53 is located on a side of the capacitor body 50 closer to the first initial signal line.

[0363] In an exemplary embodiment, as shown in Figures 40 and 41, the outline of the capacitor body 50 can be rectangular, and the corners of the rectangle can be chamfered, and the positive projection of the capacitor body 50 on the substrate at least partially overlaps with the positive projection of the first plate of the capacitor on the substrate. An opening K is provided on the capacitor body 50. The shape of the opening K can be any shape and can be located in the middle of the capacitor body 50 so that the capacitor body 50 forms a ring structure. The opening K exposes the third insulating layer covering the first plate, and the positive projection of the first plate on the substrate includes the positive projection of the opening K on the substrate. In an exemplary embodiment, the opening K is configured to expose the first plate of the capacitor so that the second pole of the subsequently formed first transistor (also the first pole of the second transistor) is connected to the first plate of the capacitor.

[0364] In an exemplary embodiment, as shown in Figures 40 and 41, the first capacitor connection portion of the present sub-pixel is electrically connected to the second capacitor connection portion of one of the adjacent sub-pixels located in the same row, and the second capacitor connection portion of the present sub-pixel is electrically connected to the first capacitor connection portion of another adjacent sub-pixel located in the same row.

[0365] In an exemplary embodiment, as shown in FIG. 40 and FIG. 41 , an orthographic projection of the third capacitor connecting portion on the substrate at least partially overlaps an orthographic projection of the capacitance of the second transistor on the substrate.

[0366] In an exemplary embodiment, as shown in Figures 40 and 41, the first initial signal line INIT1 may be located on a side of the second plate C2 of the capacitor of the current sub-pixel that is closer to the sub-pixels in the previous row. The orthographic projection of the first initial signal line INIT1 on the substrate is located between the orthographic projections of the reset signal line and the orthographic projections of the scan signal line on the substrate.

[0367] In an exemplary embodiment, as shown in Figures 40 and 41, the first initial signal line INIT1 includes: an initial signal main body 41, a first initial connection block 42, and a second initial connection block 43. The first initial connection block 42 and the second initial connection block 43 are respectively electrically connected to the initial signal main body 41. The first initial connection block 42 is located on a side of the initial signal main body 41 away from the second electrode plate of the capacitor, and the second initial connection block 43 is located on a side of the initial signal main body 41 close to the second electrode plate C2 of the capacitor. The shape of the initial signal main body 41 can be a line shape extending along the second direction D2. The first initial connection block 42 and the second initial connection block 43 can be equivalent to shielding electrodes, which are configured to effectively shield the impact of data voltage jumps on key nodes in the pixel circuit, prevent the data voltage jumps from affecting the potential of key nodes of the pixel driving circuit, and improve the display effect.

[0368] In an exemplary embodiment, as shown in Figures 40 and 41, the second initial signal line INIT2 may be in the shape of a line extending along the second direction D2. The second initial signal line INIT2 connected to the sub-pixels in the current row may be located on a side of the second plate of the capacitor of the current sub-pixel that is closer to the sub-pixels in the next row. The orthographic projection of the second initial signal line INIT2 connected to the sub-pixels in the current row on the substrate is located between the orthographic projection of the light emitting signal line connected to the sub-pixels in the current row on the substrate and between the orthographic projection of the reset signal line connected to the sub-pixels in the next row on the substrate.

[0369] In an exemplary embodiment, as shown in Figures 42 and 43 , the second plate C2 of the capacitor includes a capacitor body 50, a first capacitor connecting portion 51, and a second capacitor connecting portion 52. In the second direction D2, the first capacitor connecting portion 51 and the second capacitor connecting portion 52 are respectively located on either side of the capacitor body 50.

[0370] In an exemplary embodiment, as shown in Figures 42 and 43, the outline of the capacitor body 50 can be rectangular, and the corners of the rectangle can be chamfered, and the positive projection of the capacitor body 50 on the substrate at least partially overlaps with the positive projection of the first plate of the capacitor on the substrate. An opening K is provided on the capacitor body 50, and the shape of the opening K can be any shape and can be located in the middle of the capacitor body 50 so that the capacitor body 50 forms a ring structure. The opening K exposes the third insulating layer covering the first plate, and the positive projection of the first plate on the substrate includes the positive projection of the opening K on the substrate. In an exemplary embodiment, the opening K is configured to expose the first plate of the capacitor so that the second pole of the first transistor formed subsequently (also the first pole of the second transistor) is connected to the first plate of the capacitor.

[0371] In an exemplary embodiment, as shown in Figures 42 and 43, the first capacitor connection portion of the present sub-pixel is electrically connected to the second capacitor connection portion of one of the adjacent sub-pixels located in the same row, and the second capacitor connection portion of the present sub-pixel is electrically connected to the first capacitor connection portion of another adjacent sub-pixel located in the same row.

[0372] In an exemplary embodiment, as shown in FIG42 and FIG43 , the first initial signal line INIT1 may be in the shape of a line extending along the second direction D2. The first initial signal line INIT1 may be located on a side of the second plate C2 of the capacitor of the current sub-pixel that is closer to the sub-pixels in the previous row. The orthogonal projection of the first initial signal line INIT1 on the substrate is located on a side of the orthogonal projection of the reset signal line on the substrate that is away from the orthogonal projection of the scan signal line on the substrate.

[0373] In an exemplary embodiment, as shown in Figures 42 and 43, the shielding electrode SL may be shaped like an "n". The shielding electrode SL is located between the first initial signal line INT1 and the second plate C2 of the capacitor. The orthographic projection of the shielding electrode SL on the substrate at least partially overlaps with the orthographic projections of the active layer of the first transistor and the active layer of the second transistor on the substrate, and is located between the orthographic projections of the reset signal line and the orthographic projections of the scan signal line on the substrate. The shielding electrode is configured to effectively shield the impact of data voltage jumps on key nodes in the pixel circuit, prevent the data voltage jumps from affecting the potentials of key nodes in the pixel driving circuit, and improve the display effect.

[0374] In an exemplary embodiment, as shown in FIG42 and FIG43 , the second initial signal line INIT2 may be shaped as a line extending along the second direction D2. The second initial signal line INIT2 connected to the sub-pixels in the current row may be located on the second plate C2 of the capacitor near the sub-pixels in the next row. The orthographic projection of the second initial signal line INIT2 connected to the sub-pixels in the current row on the substrate is located between the orthographic projection of the scanning signal line connected to the sub-pixels in the current row on the substrate and the orthographic projection of the first initial signal line connected to the sub-pixels in the next row on the substrate.

[0375] (5) forming a third insulating layer pattern, comprising: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, and patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned structure, wherein the third insulating layer is provided with a plurality of via patterns, as shown in FIG. 24 , FIG. 25 , FIG. 44 and FIG. 45 , FIG. 24 is a schematic diagram of FIG. 5A after the third insulating layer pattern is formed, FIG. 25 is a schematic diagram of FIG. 6A after the third insulating layer pattern is formed, FIG. 44 is a schematic diagram of FIG. 7B after the third insulating layer pattern is formed, and FIG. 45 is a schematic diagram of FIG. 7C after the third insulating layer pattern is formed.

[0376] In an exemplary embodiment, as shown in FIG. 24 , the plurality of via hole patterns in FIG. 5A may include at least a first via hole V1 to a fifty-seventh via hole V57 .

[0377] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the active layer of the first light-emitting transistor, and the first via hole V1 is configured to connect the first electrode of the subsequently formed first light-emitting transistor to the first region of the active layer of the first light-emitting transistor through the via hole.

[0378] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the active layer of the first light-emitting transistor, and the second via hole V2 is configured to connect the second electrode of the subsequently formed first light-emitting transistor (also the second electrode of the fourth light-emitting transistor) to the second region of the active layer of the first light-emitting transistor through the via hole.

[0379] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the second light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the active layer of the second light-emitting transistor, and the third via hole V3 is configured to connect the first electrode of the subsequently formed second light-emitting transistor to the first region of the active layer of the second light-emitting transistor through the via hole.

[0380] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the second light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the active layer of the second light-emitting transistor, and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed second light-emitting transistor (which is also the second electrode of the third light-emitting transistor) to the second region of the active layer of the second light-emitting transistor through the via hole.

[0381] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the third light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first region of the active layer of the third light-emitting transistor, and the fifth via hole V5 is configured to connect the first electrode of the subsequently formed third light-emitting transistor (which is also the first electrode of the tenth light-emitting transistor) to the first region of the active layer of the third light-emitting transistor through the via hole.

[0382] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the third light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the second region of the active layer of the third light-emitting transistor, and the sixth via hole V6 is configured to connect the second electrode of the subsequently formed second light-emitting transistor (which is also the second electrode of the third light-emitting transistor) to the second region of the active layer of the third light-emitting transistor through the via hole.

[0383] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the fourth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the second region of the active layer of the fourth light-emitting transistor, and the seventh via hole V7 is configured to connect the second electrode of the subsequently formed first light-emitting transistor (which is also the second electrode of the fourth light-emitting transistor) to the second region of the active layer of the fourth light-emitting transistor through the via hole.

[0384] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the fifth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region of the active layer of the fifth light-emitting transistor, and the eighth via hole V8 is configured to connect the first electrode of the subsequently formed fifth light-emitting transistor to the first region of the active layer of the fifth light-emitting transistor through the via hole.

[0385] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the sixth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the first region of the active layer of the sixth light-emitting transistor, and the ninth via hole V9 is configured to connect the first electrode of the subsequently formed sixth light-emitting transistor to the first region of the active layer of the sixth light-emitting transistor through the via hole.

[0386] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the sixth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the tenth via hole V10 are etched away, exposing the surface of the second region of the active layer of the sixth light-emitting transistor, and the tenth via hole V10 is configured to connect the second electrode of the subsequently formed sixth light-emitting transistor (which is also the first electrode of the seventh light-emitting transistor) to the second region of the active layer of the sixth light-emitting transistor through the via hole.

[0387] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the seventh light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first region of the active layer of the seventh light-emitting transistor, and the eleventh via hole V11 is configured to connect the second electrode of the subsequently formed sixth light-emitting transistor (which is also the first electrode of the seventh light-emitting transistor) to the first region of the active layer of the seventh light-emitting transistor through the via hole.

[0388] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the seventh light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the active layer of the seventh light-emitting transistor, and the twelfth via hole V12 is configured to connect the second electrode of the subsequently formed seventh light-emitting transistor (which is also the second electrode of the eighth light-emitting transistor) to the second region of the active layer of the seventh light-emitting transistor through the via hole.

[0389] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the eighth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the thirteenth via hole V13 are etched away, exposing the surface of the first region of the active layer of the eighth light-emitting transistor, and the thirteenth via hole V13 is configured to connect the first electrode of the subsequently formed eighth light-emitting transistor (which is also the first electrode of the ninth light-emitting transistor) to the first region of the active layer of the eighth light-emitting transistor through the via hole.

[0390] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eighth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the second region of the active layer of the eighth light-emitting transistor, and the fourteenth via hole V14 is configured to connect the second electrode of the subsequently formed seventh light-emitting transistor (which is also the second electrode of the eighth light-emitting transistor) to the second region of the active layer of the eighth light-emitting transistor through the via hole.

[0391] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the ninth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the first region of the active layer of the ninth light-emitting transistor, and the fifteenth via hole V15 is configured to connect the first electrode of the subsequently formed eighth light-emitting transistor (which is also the first electrode of the ninth light-emitting transistor) to the first region of the active layer of the ninth light-emitting transistor through the via hole.

[0392] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the ninth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the sixteenth via hole V16 are etched away to expose the surface of the second region of the active layer of the ninth light-emitting transistor, and the sixteenth via hole V16 is configured to connect the second electrode of the subsequently formed ninth light-emitting transistor to the second region of the active layer of the ninth light-emitting transistor through the via hole.

[0393] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the tenth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the first region of the active layer of the tenth light-emitting transistor, and the seventeenth via hole V17 is configured to connect the first electrode of the subsequently formed tenth light-emitting transistor to the first region of the active layer of the tenth light-emitting transistor through the via hole.

[0394] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the tenth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the second region of the active layer of the tenth light-emitting transistor, and the eighteenth via hole V18 is configured to connect the second electrode of the subsequently formed tenth light-emitting transistor to the second region of the active layer of the tenth light-emitting transistor through the via hole.

[0395] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the gate electrode of the first light-emitting transistor (also the gate electrode of the third light-emitting transistor) on the substrate, the second insulating layer in the nineteenth via hole V19 is etched away to expose the surface of the gate electrode of the first light-emitting transistor (also the gate electrode of the third light-emitting transistor), and the nineteenth via hole V19 is configured to connect the first electrode of the subsequently formed second light-emitting transistor and one of the first light-emitting clock signal line and the second light-emitting clock signal line to the gate electrode of the first light-emitting transistor (also the gate electrode of the third light-emitting transistor) through the via hole.

[0396] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth light-emitting transistor on the substrate, the second insulating layer in the twentieth via hole V20 is etched away to expose the surface of the gate electrode of the fourth light-emitting transistor, and the twentieth via hole V20 is configured to connect the other of the subsequently formed first light-emitting clock signal line and the second light-emitting clock signal line to the gate electrode of the fourth light-emitting transistor through the via hole.

[0397] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the gate electrode of the fifth light-emitting transistor (which is also the gate electrode of the sixth light-emitting transistor and the first plate of the first light-emitting capacitor) on the substrate, and the second insulating layer in the twenty-first via hole V21 is etched away to expose the surface of the gate electrode of the fifth light-emitting transistor (which is also the gate electrode of the sixth light-emitting transistor and the first plate of the first light-emitting capacitor). The twenty-first via hole V21 is configured to connect the second electrode of the subsequently formed second light-emitting transistor (which is also the second electrode of the third light-emitting transistor) to the gate electrode of the fifth light-emitting transistor (which is also the gate electrode of the sixth light-emitting transistor and the first plate of the first light-emitting capacitor) through the via hole.

[0398] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the gate electrode of the seventh light-emitting transistor on the substrate, the second insulating layer in the twenty-second via hole V22 is etched away to expose the surface of the gate electrode of the seventh light-emitting transistor, and the twenty-second via hole V22 is configured to connect the other of the subsequently formed first light-emitting clock signal line and the second light-emitting clock signal line to the gate electrode of the seventh light-emitting transistor through the via hole.

[0399] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the gate electrode of the ninth light-emitting transistor (also the first plate of the second light-emitting capacitor) on the substrate, and the second insulating layer in the twenty-third via hole V23 is etched away to expose the surface of the gate electrode of the ninth light-emitting transistor (also the first plate of the second light-emitting capacitor). The twenty-third via hole V23 is configured to connect the second electrode of the subsequently formed seventh light-emitting transistor (also the second electrode of the eighth light-emitting transistor) to the gate electrode of the ninth light-emitting transistor (also the first plate of the second light-emitting capacitor) through the via hole.

[0400] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the second electrode plate of the first light-emitting capacitor on the substrate, exposing the surface of the second electrode plate of the first light-emitting capacitor, and the twenty-fourth via V24 is configured to connect the second electrode of the subsequently formed sixth light-emitting transistor (which is also the first electrode of the seventh light-emitting transistor) to the second electrode plate of the first light-emitting capacitor through the via.

[0401] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the second electrode plate of the second light-emitting capacitor on the substrate, exposing the surface of the second electrode plate of the second light-emitting capacitor, and the twenty-fifth via hole V25 is configured to connect the first electrode of the subsequently formed eighth light-emitting transistor (which is also the first electrode of the ninth light-emitting transistor) to the second electrode plate of the second light-emitting capacitor through the via hole.

[0402] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the twenty-sixth via hole V26 on the substrate is located within the range of the orthographic projection of the second electrode plate of the third light-emitting capacitor on the substrate, exposing the surface of the second electrode plate of the third light-emitting capacitor. The twenty-sixth via hole V26 is configured to connect the first electrode of the subsequently formed sixth light-emitting transistor to the second electrode plate of the third light-emitting capacitor through the via hole.

[0403] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthographic projection of the output main body portion of the output line on the substrate, exposing the surface of the output main body portion of the output line, and the twenty-seventh via hole V27 is configured to connect a subsequently formed second connecting line to the output main body portion of the output line through the via hole.

[0404] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the twenty-eighth via V28 on the substrate is located within the range of the orthographic projection of the output connection portion of the output line on the substrate, exposing the surface of the output connection portion of the output line, and the twenty-eighth via V28 is configured to connect the second electrode of the subsequently formed first release transistor (also the second electrode of the second release transistor) to the output connection portion of the output line through the via.

[0405] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the twenty-ninth via hole V29 on the substrate is located within the range of the orthographic projection of the output connection line on the substrate, exposing the surface of the output connection line, and the twenty-ninth via hole V29 is configured to connect the second electrode of the subsequently formed ninth light-emitting transistor and the second electrode of the tenth light-emitting transistor to the output connection line through the via hole.

[0406] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the 30th via hole V30 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first release transistor on the substrate, the first insulating layer and the second insulating layer in the 30th via hole V30 are etched away to expose the surface of the first region of the active layer of the first release transistor, and the 30th via hole V30 is configured to connect the first electrode (also the second light-emitting power line) of the subsequently formed first release transistor to the first region of the active layer of the first release transistor through the via hole.

[0407] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first release transistor (also the second region of the active layer of the second release transistor) on the substrate, the first insulating layer and the second insulating layer within the thirty-first via V31 are etched away to expose the surface of the second region of the active layer of the first release transistor (also the second region of the active layer of the second release transistor), and the thirty-first via V31 is configured to connect the second electrode of the subsequently formed first release transistor (also the second electrode of the second release transistor) to the second region of the active layer of the first release transistor (also the second region of the active layer of the second release transistor) through the via.

[0408] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the second release transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-second via V32 are etched away to expose the surface of the first region of the active layer of the second release transistor, and the thirty-second via V32 is configured to connect the first electrode of the subsequently formed second release transistor to the first region of the active layer of the second release transistor through the via.

[0409] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the gate electrode of the first release transistor on the substrate, the second insulating layer in the thirty-third via V33 is etched away to expose the surface of the gate electrode of the first release transistor, and the thirty-third via V33 is configured to connect the second electrode of the subsequently formed first release transistor (also the second electrode of the second release transistor) to the gate electrode of the first release transistor through the via.

[0410] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the gate electrode of the first release transistor on the substrate, the second insulating layer in the thirty-fourth via V34 is etched away, exposing the surface of the gate electrode of the first release transistor, and the thirty-fourth via V34 is configured to connect the first electrode (also the first scanning power line) of the subsequently formed second release transistor to the gate electrode of the second release transistor through the via.

[0411] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first scanning transistor on the substrate, the first insulating layer and the second insulating layer within the thirty-fifth via V35 are etched away to expose the surface of the first region of the active layer of the first scanning transistor, and the thirty-fifth via V35 is configured to connect the first electrode of the subsequently formed first scanning transistor to the first region of the active layer of the first scanning transistor through the via.

[0412] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the first scan transistor (also the second area of ​​the active layer of the seventh scan transistor) on the substrate, the first insulating layer and the second insulating layer within the thirty-sixth via V36 are etched away to expose the surface of the second area of ​​the active layer of the first scan transistor (also the second area of ​​the active layer of the seventh scan transistor), and the thirty-sixth via V36 is configured to connect the second electrode of the subsequently formed first scan transistor (also the second electrode of the seventh scan transistor) to the second area of ​​the active layer of the first scan transistor (also the second area of ​​the active layer of the seventh scan transistor) through the via.

[0413] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the thirty-seventh via V37 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the second scan transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-seventh via V37 are etched away to expose the surface of the first area of ​​the active layer of the second scan transistor, and the thirty-seventh via V37 is configured to connect the first electrode of the subsequently formed second scan transistor to the first area of ​​the active layer of the second scan transistor through the via.

[0414] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the thirty-eighth via V38 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the second scanning transistor (also the second area of ​​the active layer of the third scanning transistor) on the substrate, the first insulating layer and the second insulating layer in the thirty-eighth via V38 are etched away to expose the surface of the second area of ​​the active layer of the second scanning transistor (also the second area of ​​the active layer of the third scanning transistor), and the thirty-eighth via V38 is configured to connect the second electrode of the subsequently formed second scanning transistor (also the second electrode of the third scanning transistor) to the second area of ​​the active layer of the second scanning transistor (also the second area of ​​the active layer of the third scanning transistor) through the via.

[0415] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the thirty-ninth via V39 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the third scanning transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-ninth via V39 are etched away to expose the surface of the first area of ​​the active layer of the third scanning transistor, and the thirty-ninth via V39 is configured to connect the first electrode of the subsequently formed third scanning transistor (which is also the second scanning power line) to the first area of ​​the active layer of the third scanning transistor through the via.

[0416] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the 40th via V40 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fourth scan transistor on the substrate, the first insulating layer and the second insulating layer in the 40th via V40 are etched away to expose the surface of the first area of ​​the active layer of the fourth scan transistor, and the 40th via V40 is configured to connect the first electrode of the subsequently formed fourth scan transistor to the first area of ​​the active layer of the fourth scan transistor through the via.

[0417] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the forty-first via V41 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the fourth scan transistor (the second area of ​​the active layer of the fifth scan transistor) on the substrate, the first insulating layer and the second insulating layer in the forty-first via V41 are etched away to expose the surface of the second area of ​​the active layer of the fourth scan transistor (the second area of ​​the active layer of the fifth scan transistor), and the forty-first via V41 is configured to connect the second electrode of the subsequently formed fourth scan transistor (also the second electrode of the fifth scan transistor) to the second area of ​​the active layer of the fourth scan transistor (the second area of ​​the active layer of the fifth scan transistor) through the via.

[0418] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the forty-second via V42 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fifth scan transistor on the substrate, the first insulating layer and the second insulating layer in the forty-second via V42 are etched away to expose the surface of the first area of ​​the active layer of the fifth scan transistor, and the forty-second via V42 is configured to connect the first electrode of the subsequently formed fifth scan transistor to the first area of ​​the active layer of the fifth scan transistor through the via.

[0419] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the forty-third via V43 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the sixth scan transistor on the substrate, the first insulating layer and the second insulating layer in the forty-third via V43 are etched away to expose the surface of the first region of the active layer of the sixth scan transistor, and the forty-third via V43 is configured to connect the first electrode of the subsequently formed sixth scan transistor to the first region of the active layer of the sixth scan transistor through the via.

[0420] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the forty-fourth via V44 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the eighth scan transistor on the substrate, the first insulating layer and the second insulating layer within the forty-fourth via V44 are etched away to expose the surface of the first region of the active layer of the eighth scan transistor, and the forty-fourth via V44 is configured to connect the first electrode of the subsequently formed eighth scan transistor to the first region of the active layer of the eighth scan transistor through the via.

[0421] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the forty-fifth via V45 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eighth scan transistor on the substrate, the first insulating layer and the second insulating layer within the forty-fifth via V45 are etched away to expose the surface of the second region of the active layer of the eighth scan transistor, and the forty-fifth via V45 is configured to connect the second electrode of the subsequently formed eighth scan transistor to the second region of the active layer of the eighth scan transistor through the via.

[0422] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the forty-sixth via V46 on the substrate is located within the range of the orthographic projection of the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor) on the substrate, the second insulating layer in the forty-sixth via V46 is etched away to expose the surface of the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor), and the forty-sixth via V46 is configured to connect the first pole of the subsequently formed second scanning transistor and one of the first scanning clock signal line and the second scanning clock signal line to the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor) through the via.

[0423] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the forty-seventh via V47 on the substrate is located within the range of the orthographic projection of the gate electrode of the second scanning transistor on the substrate, the second insulating layer in the forty-seventh via V47 is etched away to expose the surface of the gate electrode of the fourth scanning transistor, and the forty-seventh via V47 is configured to connect the second electrode of the first scanning transistor (also the second electrode of the seventh scanning transistor) and the first electrode of the eighth scanning transistor to be formed subsequently to the gate electrode of the second scanning transistor through the via.

[0424] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the forty-eighth via V48 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth scanning transistor (which is also the gate electrode of the sixth scanning transistor and the first plate of the first scanning capacitor) on the substrate, and the second insulating layer in the forty-eighth via V48 is etched away to expose the surface of the gate electrode of the fourth scanning transistor (which is also the gate electrode of the sixth scanning transistor and the first plate of the first scanning capacitor), and the forty-eighth via V48 is configured to connect the second electrode of the subsequently formed second scanning transistor (which is also the second electrode of the third scanning transistor) to the gate electrode of the fourth scanning transistor (which is also the gate electrode of the sixth scanning transistor and the first plate of the first scanning capacitor) through the via.

[0425] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the forty-ninth via V49 on the substrate is located within the range of the orthographic projection of the gate electrode of the fifth scanning transistor (also the first plate of the second scanning capacitor) on the substrate, the second insulating layer in the forty-ninth via V49 is etched away to expose the surface of the gate electrode of the fifth scanning transistor (also the first plate of the second scanning capacitor), and the forty-ninth via V49 is configured to connect the second electrode of the subsequently formed eighth scanning transistor to the gate electrode of the fifth scanning transistor (also the first plate of the second scanning capacitor) through the via.

[0426] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the fiftieth via V50 on the substrate is located within the range of the orthographic projection of the gate electrode of the seventh scanning transistor on the substrate, the second insulating layer in the fiftieth via V50 is etched away to expose the surface of the gate electrode of the seventh scanning transistor, and the fiftieth via V50 is configured to connect the first electrode of the subsequently formed fifth light-emitting transistor and the other of the first scanning clock signal line and the second scanning clock signal line to the gate electrode of the seventh scanning transistor through the via.

[0427] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the fifty-first via V51 on the substrate is located within the range of the orthographic projection of the gate electrode of the eighth scan transistor on the substrate, the second insulating layer in the fifty-first via V51 is etched away to expose the surface of the gate electrode of the eighth scan transistor, and the fifty-first via V51 is configured to connect a subsequently formed second scan power line to the gate electrode of the eighth scan transistor through the via.

[0428] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the fifty-second via V52 on the substrate is located within the range of the orthographic projection of the second plate of the first scanning capacitor on the substrate, exposing the surface of the second plate of the first scanning capacitor, and the fifty-second via V52 is configured to connect the first electrode of the subsequently formed fourth scanning transistor and the first electrode of the sixth scanning transistor to the second plate of the first scanning capacitor through the via.

[0429] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the fifty-third via V53 on the substrate is located within the range of the orthographic projection of the second plate of the second scanning capacitor on the substrate, exposing the surface of the second plate of the second scanning capacitor, and the fifty-third via V53 is configured to connect the second electrode of the subsequently formed fourth scanning transistor (which is also the second electrode of the fifth scanning transistor) to the second plate of the second scanning capacitor through the via.

[0430] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the fifty-fourth via V54 on the substrate is located within the range of the orthographic projection of the third signal connection line on the substrate, exposing the surface of the third signal connection line, and the fifty-fourth via V54 is configured to connect the second electrode of the first scanning transistor of the subsequently formed scanning shift register at this level and the second electrode of the fourth scanning transistor of the previous level scanning shift register (which is also the second electrode of the fifth scanning transistor) to the third signal connection line through the via.

[0431] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the fifty-fifth via V55 on the substrate is located within the range of the orthographic projection of the scan output signal line on the substrate, exposing the surface of the scan output signal line, and the fifty-fifth via V55 is configured to connect the subsequently formed first connecting line to the scan output signal line through the via.

[0432] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the fifty-sixth via V56 on the substrate is located within the range of the orthographic projection of the first signal connection line on the substrate, the second insulating layer in the fifty-sixth via V56 is etched away to expose the surface of the first signal connection line, and the fifty-sixth via V56 is configured to connect the subsequently formed first initial power supply line to the first signal connection line through the via.

[0433] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the fifty-seventh via V57 on the substrate is located within the range of the orthographic projection of the second signal connection line on the substrate, the second insulating layer in the fifty-seventh via V57 is etched away to expose the surface of the second signal connection line, and the fifty-seventh via V57 is configured to connect the subsequently formed second initial power supply line to the second signal connection line through the via.

[0434] In an exemplary embodiment, as shown in FIG. 25 , the plurality of via hole patterns of the display substrate provided in FIG. 6A may include at least first to fifty-sixth via holes V1 to V56 .

[0435] In an exemplary embodiment, the first to twenty-sixth via holes V1 to V26 in FIG. 6A are the same as the first to twenty-sixth via holes V1 to V26 in the display substrate provided in FIG. 5A , and are not described again herein.

[0436] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthographic projection of the output line on the substrate, exposing the surface of the output line, and the twenty-seventh via hole V27 is configured to connect a subsequently formed second connecting line to the output line through the via hole.

[0437] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the twenty-eighth via hole V28 on the substrate is located within the range of the orthographic projection of the output connection line on the substrate, exposing the surface of the output connection line, and the twenty-eighth via hole V28 is configured to connect the second electrode of the subsequently formed ninth light-emitting transistor and the second electrode of the tenth light-emitting transistor to the output connection line through the via hole.

[0438] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the twenty-ninth via V29 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the first release transistor on the substrate, the first insulating layer and the second insulating layer in the twenty-ninth via V29 are etched away to expose the surface of the first area of ​​the active layer of the first release transistor, and the twenty-ninth via V29 is configured to connect the first electrode (also the second light-emitting power line) of the subsequently formed first release transistor to the first area of ​​the active layer of the first release transistor through the via.

[0439] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the 30th via V30 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first release transistor (also the second region of the active layer of the second release transistor) on the substrate, the first insulating layer and the second insulating layer in the 30th via V30 are etched away to expose the surface of the second region of the active layer of the first release transistor (also the second region of the active layer of the second release transistor), and the 30th via V30 is configured to connect the second electrode of the subsequently formed first release transistor (also the second region of the active layer of the second release transistor) to the second region of the active layer of the first release transistor (also the second region of the active layer of the second release transistor) through the via.

[0440] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the second release transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-first via V312 are etched away to expose the surface of the first region of the active layer of the second release transistor, and the thirty-first via V31 is configured to connect the first electrode of the subsequently formed second release transistor to the first region of the active layer of the second release transistor through the via.

[0441] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the gate electrode of the first release transistor on the substrate, the second insulating layer in the thirty-second via V32 is etched away to expose the surface of the gate electrode of the first release transistor, and the thirty-second via V32 is configured to connect the second pole of the subsequently formed first release transistor (which is also the second region of the active layer of the second release transistor) to the gate electrode of the first release transistor through the via.

[0442] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the gate electrode of the first release transistor on the substrate, the second insulating layer in the thirty-third via V33 is etched away, exposing the surface of the gate electrode of the first release transistor, and the thirty-third via V33 is configured to connect the first electrode (also the first scanning power line) of the subsequently formed second release transistor to the gate electrode of the second release transistor through the via.

[0443] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first scanning transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-fourth via V34 are etched away to expose the surface of the first region of the active layer of the first scanning transistor, and the thirty-fifth via V35 is configured to connect the first electrode of the subsequently formed first scanning transistor to the first region of the active layer of the first scanning transistor through the via.

[0444] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the first scan transistor (also the second area of ​​the active layer of the seventh scan transistor) on the substrate, the first insulating layer and the second insulating layer within the thirty-fifth via V35 are etched away to expose the surface of the second area of ​​the active layer of the first scan transistor (also the second area of ​​the active layer of the seventh scan transistor), and the thirty-fifth via V35 is configured to connect the second electrode of the subsequently formed first scan transistor (also the second electrode of the seventh scan transistor) to the second area of ​​the active layer of the first scan transistor (also the second area of ​​the active layer of the seventh scan transistor) through the via.

[0445] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the second scan transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-sixth via V36 are etched away to expose the surface of the first area of ​​the active layer of the second scan transistor, and the thirty-sixth via V36 is configured to connect the first electrode of the subsequently formed second scan transistor to the first area of ​​the active layer of the second scan transistor through the via.

[0446] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the thirty-seventh via V37 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the second scan transistor (also the second region of the active layer of the third scan transistor) on the substrate, the first insulating layer and the second insulating layer within the thirty-seventh via V37 are etched away to expose the surface of the second region of the active layer of the second scan transistor (also the second region of the active layer of the third scan transistor), and the thirty-seventh via V37 is configured to connect the second electrode of the subsequently formed second scan transistor (also the second electrode of the third scan transistor) to the second region of the active layer of the second scan transistor (also the second region of the active layer of the third scan transistor) through the via.

[0447] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the thirty-eighth via V38 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the third scanning transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-eighth via V38 are etched away to expose the surface of the first area of ​​the active layer of the third scanning transistor, and the thirty-eighth via V38 is configured to connect the first electrode (also the second scanning power line) of the subsequently formed third scanning transistor to the first area of ​​the active layer of the third scanning transistor through the via.

[0448] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the thirty-ninth via V39 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fourth scan transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-ninth via V39 are etched away to expose the surface of the first area of ​​the active layer of the fourth scan transistor, and the thirty-ninth via V39 is configured to connect the first electrode of the subsequently formed fourth scan transistor to the first area of ​​the active layer of the fourth scan transistor through the via.

[0449] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the 40th via V40 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the fourth scan transistor (the second area of ​​the active layer of the fifth scan transistor) on the substrate, the first insulating layer and the second insulating layer in the 40th via V40 are etched away to expose the surface of the second area of ​​the active layer of the fourth scan transistor (the second area of ​​the active layer of the fifth scan transistor), and the 40th via V40 is configured to connect the second electrode of the subsequently formed fourth scan transistor (also the second electrode of the fifth scan transistor) to the second area of ​​the active layer of the fourth scan transistor (the second area of ​​the active layer of the fifth scan transistor) through the via.

[0450] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the forty-first via V41 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the fifth scan transistor on the substrate, the first insulating layer and the second insulating layer within the forty-first via V41 are etched away to expose the surface of the first region of the active layer of the fifth scan transistor, and the forty-first via V41 is configured to connect the first electrode of the subsequently formed fifth scan transistor to the first region of the active layer of the fifth scan transistor through the via.

[0451] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the forty-second via V42 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the sixth scan transistor on the substrate, the first insulating layer and the second insulating layer within the forty-second via V42 are etched away to expose the surface of the first region of the active layer of the sixth scan transistor, and the forty-second via V423 is configured to connect the first electrode of the subsequently formed sixth scan transistor to the first region of the active layer of the sixth scan transistor through the via.

[0452] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the forty-third via V43 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the eighth scan transistor on the substrate, the first insulating layer and the second insulating layer in the forty-third via V43 are etched away to expose the surface of the first region of the active layer of the eighth scan transistor, and the forty-third via V43 is configured to connect the first electrode of the subsequently formed eighth scan transistor to the first region of the active layer of the eighth scan transistor through the via.

[0453] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the forty-fourth via V44 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eighth scan transistor on the substrate, the first insulating layer and the second insulating layer within the forty-fourth via V44 are etched away to expose the surface of the second region of the active layer of the eighth scan transistor, and the forty-fourth via V44 is configured to connect the second electrode of the subsequently formed eighth scan transistor to the second region of the active layer of the eighth scan transistor through the via.

[0454] In an exemplary embodiment, as shown in Figure 25, the orthographic projection of the forty-fifth via V45 on the substrate is located within the range of the orthographic projection of the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor) on the substrate, the second insulating layer in the forty-fifth via V45 is etched away to expose the surface of the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor), and the forty-fifth via V45 is configured to connect the first electrode of the subsequently formed second scanning transistor and one of the first scanning clock signal line and the second scanning clock signal line to the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor) through the via.

[0455] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the forty-sixth via V46 on the substrate is located within the range of the orthographic projection of the gate electrode of the second scanning transistor on the substrate, the second insulating layer in the forty-sixth via V46 is etched away to expose the surface of the gate electrode of the fourth scanning transistor, and the forty-sixth via V46 is configured to connect the second electrode of the first scanning transistor (also the second electrode of the seventh scanning transistor) and the first electrode of the eighth scanning transistor to be formed subsequently to the gate electrode of the second scanning transistor through the via.

[0456] In an exemplary embodiment, as shown in Figure 25, the orthographic projection of the forty-seventh via V47 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth scan transistor (which is also the gate electrode of the sixth scan transistor and the first plate of the first scan capacitor) on the substrate, and the second insulating layer in the forty-seventh via V47 is etched away to expose the surface of the gate electrode of the fourth scan transistor (which is also the gate electrode of the sixth scan transistor and the first plate of the first scan capacitor). The forty-seventh via V47 is configured to connect the second electrode of the subsequently formed second scan transistor (which is also the second electrode of the third scan transistor) to the gate electrode of the fourth scan transistor (which is also the gate electrode of the sixth scan transistor and the first plate of the first scan capacitor) through the via.

[0457] In an exemplary embodiment, as shown in Figure 25, the orthographic projection of the forty-eighth via V48 on the substrate is located within the range of the orthographic projection of the gate electrode of the fifth scanning transistor (also the first plate of the second scanning capacitor) on the substrate, the second insulating layer in the forty-eighth via V48 is etched away to expose the surface of the gate electrode of the fifth scanning transistor (also the first plate of the second scanning capacitor), and the forty-eighth via V48 is configured to connect the second electrode of the subsequently formed eighth scanning transistor to the gate electrode of the fifth scanning transistor (also the first plate of the second scanning capacitor) through the via.

[0458] In an exemplary embodiment, as shown in Figure 25, the orthographic projection of the forty-ninth via V49 on the substrate is located within the range of the orthographic projection of the gate electrode of the seventh scanning transistor on the substrate, the second insulating layer in the forty-ninth via V49 is etched away to expose the surface of the gate electrode of the seventh scanning transistor, and the forty-ninth via V49 is configured to connect the first electrode of the subsequently formed fifth light-emitting transistor and the other of the first scanning clock signal line and the second scanning clock signal line to the gate electrode of the seventh scanning transistor through the via.

[0459] In an exemplary embodiment, as shown in Figure 25, the orthographic projection of the fiftieth via V50 on the substrate is located within the range of the orthographic projection of the gate electrode of the eighth scan transistor on the substrate, the second insulating layer in the fiftieth via V50 is etched away to expose the surface of the gate electrode of the eighth scan transistor, and the fiftieth via V50 is configured to connect a subsequently formed second scan power line to the gate electrode of the eighth scan transistor through the via.

[0460] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the fifty-first via V51 on the substrate is located within the range of the orthographic projection of the second plate of the first scanning capacitor on the substrate, exposing the surface of the second plate of the first scanning capacitor, and the fifty-first via V51 is configured to connect the first electrode of the subsequently formed fourth scanning transistor and the first electrode of the sixth scanning transistor to the second plate of the first scanning capacitor through the via.

[0461] In an exemplary embodiment, as shown in FIG25 , the orthographic projection of the fifty-second via V52 on the substrate is located within the range of the orthographic projection of the second plate of the second scanning capacitor on the substrate, exposing the surface of the second plate of the second scanning capacitor, and the fifty-second via V52 is configured to connect the second electrode of the subsequently formed fourth scanning transistor (which is also the second electrode of the fifth scanning transistor) to the second plate of the second scanning capacitor through the via.

[0462] In an exemplary embodiment, as shown in Figure 25, the orthographic projection of the fifty-third via V53 on the substrate is located within the range of the orthographic projection of the third signal connection line on the substrate, exposing the surface of the third signal connection line, and the fifty-third via V53 is configured to connect the second electrode of the first scanning transistor of the subsequently formed scanning shift register at this level and the second electrode of the fourth scanning transistor of the previous level scanning shift register (which is also the second electrode of the fifth scanning transistor) to the third signal connection line through the via.

[0463] In an exemplary embodiment, as shown in Figure 25, the orthographic projection of the fifty-fourth via V54 on the substrate is located within the range of the orthographic projection of the scan output signal line on the substrate, exposing the surface of the scan output signal line, and the fifty-fourth via V54 is configured to connect the subsequently formed first connecting line to the scan output signal line through the via.

[0464] In an exemplary embodiment, as shown in Figure 25, the orthographic projection of the fifty-fifth via V55 on the substrate is located within the range of the orthographic projection of the first signal connection line on the substrate, the second insulating layer in the fifty-fifth via V55 is etched away to expose the surface of the first signal connection line, and the fifty-fifth via V55 is configured to connect the subsequently formed first initial power supply line to the first signal connection line through the via.

[0465] In an exemplary embodiment, as shown in Figure 25, the orthographic projection of the fifty-sixth via V56 on the substrate is located within the range of the orthographic projection of the second signal connection line on the substrate, the second insulating layer in the fifty-sixth via V56 is etched away to expose the surface of the second signal connection line, and the fifty-sixth via V56 is configured to connect the subsequently formed second initial power supply line to the second signal connection line through the via.

[0466] In an exemplary embodiment, as shown in FIG. 44 and FIG. 45 , the plurality of via hole patterns in FIG. 7B and FIG. 7C may include at least a fifty-eighth via hole V58 to a sixty-seventh via hole V67 .

[0467] In an exemplary embodiment, as shown in Figures 44 and 45, the orthographic projection of the fifty-eighth via V58 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first transistor on the substrate, the first insulating layer and the second insulating layer in the fifty-eighth via V58 are etched away to expose the surface of the first region of the active layer of the first transistor, and the fifty-eighth via V58 is configured to connect the first electrode of the subsequently formed first transistor to the first region of the active layer of the first transistor through the via.

[0468] In an exemplary embodiment, as shown in Figures 44 and 45, the orthographic projection of the fifty-ninth via V59 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the first transistor (also the first area of ​​the active layer of the second transistor) on the substrate, the first insulating layer and the second insulating layer in the fifty-ninth via V59 are etched away to expose the surface of the second area of ​​the active layer of the first transistor (also the first area of ​​the active layer of the second transistor), and the fifty-ninth via V59 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the second area of ​​the active layer of the first transistor (also the first area of ​​the active layer of the second transistor) through the via.

[0469] In an exemplary embodiment, as shown in Figures 44 and 45, the orthographic projection of the sixtieth via V60 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the sixtieth via V60 are etched away to expose the surface of the first region of the active layer of the fourth transistor, and the sixtieth via V60 is configured to connect the first electrode of the subsequently formed fourth transistor to the first region of the active layer of the fourth transistor through the via.

[0470] In an exemplary embodiment, as shown in Figures 44 and 45, the orthographic projection of the sixty-first via hole V61 on the substrate is located within the orthographic projection of the first region of the active layer of the fifth transistor on the substrate. The first and second insulating layers within the sixty-first via hole V61 are etched away, exposing the surface of the second region of the active layer of the fifth transistor. The sixty-first via hole V61 in Figure 44 is configured to connect the first electrode of a subsequently formed fifth transistor to the first region of the active layer of the fifth transistor through this via hole. The sixty-first via hole V61 in Figure 45 is configured to connect the first sub-power line formed subsequently to the first region of the active layer of the fifth transistor through this via hole.

[0471] In an exemplary embodiment, as shown in Figures 44 and 45, the orthographic projection of the sixty-second via V62 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the sixth transistor (the second region of the active layer of the seventh transistor) on the substrate, the first insulating layer and the second insulating layer within the sixty-second via V62 are etched away to expose the surface of the second region of the active layer of the sixth transistor (the second region of the active layer of the seventh transistor), and the sixty-second via V62 is configured to connect the second electrode of the subsequently formed sixth transistor (also the second electrode of the seventh transistor) to the second region of the active layer of the sixth transistor (the second region of the active layer of the seventh transistor) through the via.

[0472] In an exemplary embodiment, as shown in Figures 44 and 45, the orthographic projection of the sixty-third via hole V63 on the substrate is located within the orthographic projection of the first region of the active layer of the seventh transistor on the substrate. The first insulating layer and the second insulating layer within the sixty-third via hole V63 are etched away, exposing the surface of the first region of the active layer of the seventh transistor. The sixty-third via hole V63 in Figure 44 is configured to connect the first electrode of a subsequently formed seventh transistor to the first region of the active layer of the seventh transistor through this via hole. The sixty-third via hole V63 in Figure 45 is configured to connect the first electrode of a subsequently formed seventh transistor or the fourth signal connection line to the first region of the active layer of the seventh transistor through this via hole.

[0473] In an exemplary embodiment, as shown in FIG44 , the orthographic projection of the sixty-fourth via V64 on the substrate is located within the range of the orthographic projection of the gate electrode of the third transistor (also the first plate of the capacitor) on the substrate, the second insulating layer in the sixty-fourth via V64 is etched away to expose the surface of the gate electrode of the third transistor (also the first plate of the capacitor), and the sixty-fourth via V64 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the gate electrode of the third transistor (also the first plate of the capacitor) through the via.

[0474] In an exemplary embodiment, as shown in FIG44 , the orthographic projection of the sixty-fifth via V65 on the substrate is located within the range of the orthographic projection of the first initial signal line on the substrate, exposing the first initial signal line, and the sixty-fifth via V65 is configured to connect the first electrode of the subsequently formed first transistor to the first initial signal line through the via.

[0475] In an exemplary embodiment, as shown in Figures 44 and 45 , the orthographic projection of the sixty-sixth via V66 on the substrate is located within the orthographic projection of the second plate of the capacitor on the substrate, exposing the surface of the second plate of the capacitor. The sixty-sixth via V66 in Figure 44 is configured to connect the first electrode of the subsequently formed fifth transistor to the second plate of the capacitor through this via. The sixty-sixth via V66 in Figure 45 is configured to connect the subsequently formed first sub-power line to the second plate of the capacitor through this via.

[0476] In an exemplary embodiment, as shown in FIG44 , the orthographic projection of the sixty-seventh via V67 on the substrate is located within the range of the orthographic projection of the second initial signal line on the substrate, exposing the surface of the second initial signal line, and the sixty-seventh via V67 is configured to connect the first electrode of the subsequently formed seventh transistor to the second initial signal line through the via.

[0477] (6) forming a third conductive layer pattern, comprising: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film through a patterning process to form a third conductive layer pattern, as shown in Figures 26 to 28 and Figures 46 to 49, wherein Figure 26 is a schematic diagram of the third conductive layer pattern of Figures 5A and 6A, Figure 27 is a schematic diagram of Figure 5A after the third conductive layer pattern is formed, Figure 28 is a schematic diagram of Figure 6A after the third conductive layer pattern is formed, Figure 46 is a schematic diagram of the third conductive layer pattern of Figure 7B, Figure 47 is a schematic diagram of Figure 7B after the third conductive layer pattern is formed, Figure 48 is a schematic diagram of the third conductive layer pattern of Figure 7C, and Figure 49 is a schematic diagram of Figure 7C after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0478] In an exemplary embodiment, as shown in Figures 26 to 28 and Figures 46 to 49, the third conductive layer pattern may at least include: a light-emitting initial signal line ESTV, a first light-emitting clock signal line ECK1, a second light-emitting clock signal line ECK2, a first light-emitting power line EVGH, a second light-emitting power line EVGL, a scan initial signal line GSTV, a first sub-clock signal line GCK1A of the first scan clock signal line, a third sub-clock signal line GCK2A of the second scan clock signal line, a first scan power line GVGH, a second scan power line GVGL, a first sub-initial power line INITL1A of the first initial power supply line, a first sub-initial power supply line INITL2A of the second initial power supply line, first to fourth connecting lines CL1 to CL4, first and second electrodes of multiple light-emitting transistors, first and second electrodes of multiple release transistors, and first and second electrodes of multiple scan transistors, a first electrode MT13 and a second electrode MT14 of the first transistor, a first electrode MT23 of the second transistor, a first electrode MT43 of the fourth transistor, a first electrode MT53 of the fifth transistor, a second electrode MT64 of the sixth transistor, and a first electrode MT73 and a second electrode MT74 of the seventh transistor.

[0479] In an exemplary embodiment, as shown in FIG. 46 and FIG. 47 , the third conductive layer pattern further includes at least a data link line DL.

[0480] In an exemplary embodiment, as shown in FIG. 48 and FIG. 49 , the third conductive layer pattern further includes at least a first lower sub-power source VDDA and an electrode connection line CL.

[0481] In an exemplary embodiment, as shown in Figure 26, the first light-emitting clock signal line ECK1 can be located on the side of the light-emitting initial signal line ESTV close to the display area, the second light-emitting clock signal line ECK2 can be located on the side of the first light-emitting clock signal line ECK1 close to the display area, the first light-emitting power line EVGH can be located on the side of the second light-emitting clock signal line ECK2 close to the display area, the second light-emitting power line EVGL is located on the side of the first light-emitting power line EVGH close to the display area, the first scan power line GVGH is located on the side of the second light-emitting power line EVGL close to the display area, the first sub-clock signal line GCK1A of the first scan clock signal line is located on the side of the first scan power line GVGH close to the display area, the third sub-clock signal line GCK2A of the second scan clock signal line is located on the side of the first scan clock signal line GCK1 close to the display area, the scan initial signal line GSTV is located on the side of the second scan clock signal line GCK2 close to the display area, and the second scan power line GVGL is located on the side of the scan initial signal line GSTV close to the display area.

[0482] In an exemplary embodiment, any one of the light-emitting initial signal line ESTV, the first light-emitting clock signal line ECK1, the second light-emitting clock signal line ECK2, the first light-emitting power line EVGH, the second light-emitting power line EVGL, the scan initial signal line GSTV, the first sub-clock signal line GCK1A of the first scan clock signal line, the third sub-clock signal line GCK2A of the second scan clock signal line, the first scan power line GVGH, the second scan power line GVGL, the first sub-initial power line INITL1A of the first initial power line, and the first sub-initial power line INITL2A of the second initial power line extends at least partially along the first direction D1 and is in a line shape.

[0483] In an exemplary embodiment, as shown in FIG26 , the first electrode ET13 and the second electrode ET14 of the first light-emitting transistor through the first electrode ET103 and the second electrode ET104 of the tenth light-emitting transistor may be located between the first light-emitting power line EVGH and the second light-emitting power line EVGL. The first electrode RT11 and the second electrode RT14 of the first release transistor through the first electrode RT21 and the second electrode RT24 of the second release transistor may be located between the second light-emitting power line EVGL and the first scan power line GVGH. The first electrode GT13 and the second electrode GT14 of the first scan transistor through the first electrode GT33 and the second electrode of the third scan transistor, as well as the first electrode GT63 of the sixth scan transistor and the second electrode GT74 of the seventh scan transistor may be located between the scan initial signal line GSTV and the second scan power line GVGL. The first electrode GT43 and the first electrode GT44 of the fourth scan transistor through the first electrode GT53 and the first electrode GT54 of the fifth scan transistor, and the first electrode GT83 and the second electrode GT84 of the eighth scan transistor may be located between the second scan power line GVGL and the first initial power supply line INITL1.

[0484] In an exemplary embodiment, an orthographic projection of the second plate of the second scan capacitor on the substrate at least partially overlaps with an orthographic projection of the second scan power line, the first scan clock signal line, the second scan clock signal line, the scan initial signal line, and the first scan power line on the substrate.

[0485] 26 , the first and second initial power supply lines INITL1 and INITL2 are located on a side of the second scan power line GVGL closer to the display area.

[0486] 26 to 28 , the first electrode ET13 of the first light emitting transistor may be in the shape of a bar extending along the first direction D1 and pass through the first region of the active layer of the first light emitting transistor through the first via hole.

[0487] In an exemplary embodiment, as shown in Figures 26 to 28, the second electrode ET14 of the first light-emitting transistor and the second electrode ET44 of the fourth light-emitting transistor are connected to each other as an integral structure and can be shaped like a strip extending along the first direction D1. The second electrode ET14 of the first light-emitting transistor (also the second electrode ET44 of the fourth light-emitting transistor) is connected to the second region of the active layer of the first light-emitting transistor through a second via hole, and is connected to the second region of the active layer of the fourth light-emitting transistor through a seventh via hole.

[0488] In an exemplary embodiment, as shown in Figures 26 to 28, the shape of the first electrode ET23 of the second light-emitting transistor can be a strip extending along the first direction D1, and the first electrode ET23 of the second light-emitting transistor is connected to the first region of the active layer of the second light-emitting transistor through a third via hole, and is connected to the gate electrode of the first light-emitting transistor (which is also the gate electrode of the third light-emitting transistor) through a nineteenth via hole.

[0489] In an exemplary embodiment, as shown in Figures 26 to 28, the second electrode ET24 of the second light-emitting transistor and the second electrode ET34 of the third light-emitting transistor are interconnected and integrally formed, and extend at least partially along the first direction D1, and may be in a zigzag shape. The second electrode ET24 of the second light-emitting transistor (also the second electrode ET34 of the third light-emitting transistor) is connected to the second region of the active layer of the second light-emitting transistor via a fourth via hole, connected to the second region of the active layer of the third light-emitting transistor via a sixth via hole, and connected to the gate electrode of the fifth light-emitting transistor (also the gate electrode of the sixth light-emitting transistor and the first plate of the first light-emitting capacitor) via a twenty-first via hole.

[0490] In an exemplary embodiment, as shown in Figures 26 to 28, the first electrode ET33 of the third light-emitting transistor, the first electrode ET103 of the tenth light-emitting transistor, and the second light-emitting power line EVGL are connected to each other as an integral structure. The first electrode ET33 of the third light-emitting transistor can be in the shape of a strip extending along the second direction D2, and the first electrode ET103 of the tenth light-emitting transistor can be in the shape of an "n" with an opening facing the second light-emitting power line EVGL. The first electrode ET33 of the third light-emitting transistor (also the first electrode ET103 of the tenth light-emitting transistor) is connected to the first region of the active layer of the third light-emitting transistor via a fifth via hole, and is connected to the first region of the active layer of the tenth light-emitting transistor via a seventeenth via hole.

[0491] In an exemplary embodiment, as shown in Figures 26 to 28, the first electrode ET53 of the fifth light-emitting transistor and the first light-emitting power line EVGH are connected to each other as an integral structure. The first electrode ET53 of the fifth light-emitting transistor can be in a block shape. The fifth light-emitting transistor ET53 is connected to the first region of the active layer of the fifth light-emitting transistor through an eighth via hole.

[0492] In an exemplary embodiment, as shown in Figures 26 to 28, the first electrode ET63 of the sixth light-emitting transistor can be in a block shape. The first electrode ET63 of the sixth light-emitting transistor is connected to the first region of the active layer of the sixth light-emitting transistor through a ninth via hole, and is connected to the second plate of the third light-emitting capacitor through a twenty-sixth via hole.

[0493] In an exemplary embodiment, as shown in Figures 26 to 28, the second electrode ET64 of the sixth light-emitting transistor and the first electrode ET73 of the seventh light-emitting transistor are interconnected as an integral structure. The second electrode ET64 of the sixth light-emitting transistor (also the first electrode ET73 of the seventh light-emitting transistor) extends at least partially along the first direction D1. The second electrode ET64 of the sixth light-emitting transistor (also the first electrode ET73 of the seventh light-emitting transistor) is connected to the second region of the active layer of the sixth light-emitting transistor via a tenth via, connected to the first region of the active layer of the seventh light-emitting transistor via an eleventh via, and connected to the second plate of the first light-emitting capacitor via a twenty-fourth via.

[0494] In an exemplary embodiment, as shown in Figures 26 to 28, the second electrode ET74 of the seventh light-emitting transistor and the second electrode ET84 of the eighth light-emitting transistor are interconnected as an integral structure. The second electrode ET74 of the seventh light-emitting transistor (also the second electrode ET84 of the eighth light-emitting transistor) can be shaped like a horizontally flipped "7." The second electrode ET74 of the seventh light-emitting transistor (also the second electrode ET84 of the eighth light-emitting transistor) is connected to the second region of the active layer of the seventh light-emitting transistor via a twelfth via hole, connected to the second region of the active layer of the eighth light-emitting transistor via a fourteenth via hole, and connected to the gate electrode of the ninth light-emitting transistor (also the first plate of the second light-emitting capacitor) via a twenty-third via hole.

[0495] In an exemplary embodiment, as shown in Figures 26 to 28, the first electrode ET83 of the eighth light-emitting transistor, the first electrode ET93 of the ninth light-emitting transistor, and the first light-emitting power line EVGH are interconnected as an integrated structure. The first electrode ET83 of the eighth light-emitting transistor can be in a block shape, and the first electrode ET93 of the ninth light-emitting transistor can be in a comb shape. The first electrode ET83 of the eighth light-emitting transistor (also the first electrode ET93 of the ninth light-emitting transistor) is connected to the first region of the active layer of the eighth light-emitting transistor via a thirteenth via hole, connected to the first region of the active layer of the ninth light-emitting transistor via a fifteenth via hole, and connected to the second plate of the second light-emitting capacitor via a twenty-fifth via hole.

[0496] In an exemplary embodiment, as shown in Figures 26 to 28, the second electrode ET94 of the ninth light-emitting transistor can be shaped like a comb, with the teeth of the second electrode ET94 of the ninth light-emitting transistor positioned interlaced with the teeth of the first electrode ET93 of the ninth light-emitting transistor. The second electrode ET94 of the ninth light-emitting transistor is connected to the second region of the active layer of the ninth light-emitting transistor via a sixteenth via. As shown in Figure 27, the second electrode ET94 of the ninth light-emitting transistor in Figure 5A is connected to the output connection line via a twenty-ninth via. As shown in Figure 28, the second electrode ET94 of the ninth light-emitting transistor in Figure 6A is connected to the output connection line via a twenty-eighth via.

[0497] In an exemplary embodiment, as shown in Figures 26 to 28 , the second electrode ET104 of the tenth light-emitting transistor may be shaped like an "n" with an opening facing away from the second light-emitting power line EVGL. The second electrode ET104 of the tenth light-emitting transistor is connected to the second region of the active layer of the tenth light-emitting transistor via an eighteenth via. As shown in Figure 27 , the second electrode ET104 of the tenth light-emitting transistor in Figure 5A is connected to the output connection line via a twenty-ninth via. As shown in Figure 28 , the second electrode ET104 of the tenth light-emitting transistor in Figure 6A is connected to the output connection line via a twenty-eighth via.

[0498] In an exemplary embodiment, as shown in FIG. 26 to FIG. 28 , one of the first and second light emitting clock signal lines ECK1 and ECK2 is connected to the gate electrode of the first light emitting transistor (also the gate electrode of the third light emitting transistor) through a nineteenth via hole.

[0499] In an exemplary embodiment, as shown in FIG26 to FIG28, the other of the first light emitting clock signal line ECK1 and the second light emitting clock signal line ECK2 is connected to the gate electrode of the fourth light emitting transistor through the twentieth via hole and is connected to the gate electrode of the seventh light emitting transistor through the twenty-second via hole.

[0500] In an exemplary embodiment, as shown in Figures 26 to 28, the second connection line CL2 may be in a block shape. As shown in Figure 27, the second connection line in Figure 5A is connected to the output main body portion of the output line through the twenty-seventh via hole.

[0501] In an exemplary embodiment, as shown in Figures 26 to 28, the area where the second light-emitting power line EVGL overlaps with the first region of the active layer of the first release transistor can be reused as the first electrode of the first release transistor. As shown in Figure 27, the first electrode of the first release transistor in Figure 5A is connected to the first region of the active layer of the first release transistor through the 30th via hole, and the first electrode of the first release transistor in Figure 6A is connected to the first region of the active layer of the first release transistor through the 29th via hole.

[0502] In an exemplary embodiment, as shown in Figures 26 to 28 , the second electrode ET14 of the first release transistor and the second electrode ET24 of the second release transistor are interconnected and integrally formed, and may be in the shape of a horizontally inverted "L." As shown in Figure 27 , the orthographic projection of the second electrode ET14 of the first release transistor (also the second electrode of the second release transistor) on the substrate in Figure 5A at least partially overlaps with the orthographic projection of the output connection portion on the substrate. The orthographic projection of the second electrode ET14 of the first release transistor (also the second electrode of the second release transistor) on the substrate in Figure 5A does not overlap with the orthographic projection of the output line on the substrate.

[0503] In an exemplary embodiment, as shown in FIG27 , the second electrode ET14 of the first release transistor (also the second electrode of the second release transistor) in FIG5A is connected to the output connection portion of the output line via the twenty-eighth via, connected to the second region of the active layer of the first release transistor (also the second region of the active layer of the second release transistor) via the thirty-first via, and connected to the gate electrode of the first release transistor via the thirty-third via. As shown in FIG28 , the second electrode ET14 of the first release transistor (also the second electrode of the second release transistor) in FIG6A is connected to the second region of the active layer of the first release transistor (also the second region of the active layer of the second release transistor) via the thirtieth via, and connected to the gate electrode of the first release transistor via the thirty-second via.

[0504] In an exemplary embodiment, as shown in Figures 26 to 28 , the second electrode ET21 of the second release transistor and the first scan power line GVGH are connected to each other as an integral structure, and the shape may be a horizontally inverted "L" shape. As shown in Figure 27 , the second electrode ET21 of the second release transistor in Figure 5A is connected to the first region of the active layer of the second release transistor via the 32nd via hole, and is connected to the gate electrode of the second release transistor via the 34th via hole. As shown in Figure 28 , the second electrode ET21 of the second release transistor in Figure 6A is connected to the first region of the active layer of the second release transistor via the 31st via hole, and is connected to the gate electrode of the second release transistor via the 33rd via hole.

[0505] In an exemplary embodiment, as shown in Figures 26 to 28, the first electrode GT13 of the first scan transistor may be in the shape of a strip extending along the second direction D2. As shown in Figure 27, the first electrode GT13 of the first scan transistor in Figure 5A is connected to the first region of the active layer of the first scan transistor via the 35th via hole and to the third signal connection line via the 54th via hole. As shown in Figure 28, the first electrode GT13 of the first scan transistor in Figure 6A is connected to the first region of the active layer of the first scan transistor via the 34th via hole and to the third signal connection line via the 53rd via hole.

[0506] In an exemplary embodiment, as shown in Figures 26 to 28, the second electrode GT14 of the first scan transistor and the second electrode GT74 of the seventh scan transistor are interconnected and integrally formed, and may be in the shape of a strip extending along the second direction D2. As shown in Figure 27, the second electrode GT14 of the first scan transistor (also the second electrode GT74 of the seventh scan transistor) in Figure 5A is connected to the second region of the active layer of the first scan transistor (also the second region of the active layer of the seventh scan transistor) via the 36th via hole, and is connected to the gate electrode of the second scan transistor via the 47th via hole. As shown in Figure 28, the second electrode GT14 of the first scan transistor (also the second electrode GT74 of the seventh scan transistor) in Figure 6A is connected to the second region of the active layer of the first scan transistor (also the second region of the active layer of the seventh scan transistor) via the 35th via hole, and is connected to the gate electrode of the second scan transistor via the 46th via hole.

[0507] In an exemplary embodiment, as shown in Figures 26 to 28, the first electrode GT23 of the second scan transistor may be shaped like a strip extending along the first direction D1. As shown in Figure 27, the first electrode GT23 of the second scan transistor in the display substrate provided in Figure 5A is connected to the first region of the active layer of the second scan transistor via the 37th via hole, and is connected to the gate electrode of the first scan transistor (also the gate electrode of the third scan transistor) via the 46th via hole. As shown in Figure 28, the first electrode GT23 of the second scan transistor in Figure 6A is connected to the first region of the active layer of the second scan transistor via the 36th via hole, and is connected to the gate electrode of the first scan transistor (also the gate electrode of the third scan transistor) via the 45th via hole.

[0508] In an exemplary embodiment, as shown in Figures 26 to 28, the second electrode GT24 of the second scan transistor and the second electrode GT34 of the third scan transistor are interconnected and integrally formed, and may be in the shape of a strip extending along the second direction D2. As shown in Figure 27, the second electrode GT24 of the second scan transistor (also the second electrode GT34 of the third scan transistor) in the display substrate provided in Figure 5A is connected to the second region of the active layer of the second scan transistor (also the second region of the active layer of the third scan transistor) via the 38th via hole, and is connected to the gate electrode of the fourth scan transistor (also the gate electrode of the sixth scan transistor and the first plate of the first scan capacitor) via the 48th via hole. As shown in Figure 28, the second electrode GT24 of the second scan transistor (also the second electrode GT34 of the third scan transistor) in Figure 6A is connected to the second region of the active layer of the second scan transistor (also the second region of the active layer of the third scan transistor) via the 37th via hole, and is connected to the gate electrode of the fourth scan transistor (also the gate electrode of the sixth scan transistor and the first plate of the first scan capacitor) via the 47th via hole.

[0509] In an exemplary embodiment, as shown in Figures 26 to 28, the region where the second scan power line GVGL overlaps with the first region of the active layer of the third scan transistor is reused as the first electrode GT33 of the third scan transistor. As shown in Figure 27, the first electrode GT33 of the third scan transistor in Figure 5A is connected to the first region of the active layer of the third scan transistor through the thirty-ninth via hole.

[0510] In an exemplary embodiment, as shown in Figures 26 to 28, the first electrode GT43 of the fourth scan transistor may be in the shape of a strip extending along the second direction D2. As shown in Figure 27, the first electrode GT43 of the fourth scan transistor in the display substrate provided in Figure 5A is connected to the first region of the active layer of the fourth scan transistor via the 40th via hole, and is connected to the second plate of the first scan capacitor via the 52nd via hole. As shown in Figure 28, the first electrode GT23 of the second scan transistor in Figure 6A is connected to the first region of the active layer of the fourth scan transistor via the 39th via hole, and is connected to the second plate of the first scan capacitor via the 51st via hole.

[0511] In an exemplary embodiment, as shown in Figures 26 to 28, the second electrode GT44 of the fourth scan transistor and the second electrode GT54 of the fifth scan transistor are interconnected and integrally formed, and may be shaped like an "M" with an opening facing the second scan power line GVGH. As shown in Figure 27, the second electrode GT44 of the fourth scan transistor (also the second electrode GT54 of the fifth scan transistor) in Figure 5A is connected to the second region of the active layer of the fourth scan transistor (the second region of the active layer of the fifth scan transistor) via the 41st via, and is connected to the second plate of the second scan capacitor via the 53rd via. As shown in Figure 28, the second electrode GT44 of the fourth scan transistor (also the second electrode GT54 of the fifth scan transistor) in Figure 6A is connected to the second region of the active layer of the fourth scan transistor (the second region of the active layer of the fifth scan transistor) via the 40th via, and is connected to the second plate of the second scan capacitor via the 52nd via.

[0512] In an exemplary embodiment, as shown in Figures 26 to 28, the first electrode GT53 of the fifth scan transistor may be shaped like an "F." As shown in Figure 27, the first electrode GT53 of the fifth scan transistor in Figure 5A is connected to the first region of the active layer of the fifth scan transistor via the 42nd via hole, and is connected to the gate electrode of the seventh scan transistor via the 50th via hole. As shown in Figure 28, the first electrode GT53 of the fifth scan transistor in Figure 6A is connected to the first region of the active layer of the fifth scan transistor via the 41st via hole, and is connected to the gate electrode of the seventh scan transistor via the 49th via hole.

[0513] In an exemplary embodiment, as shown in Figures 26 to 28, the first electrode GT63 of the sixth scan transistor may be in the shape of a strip extending along the second direction D2. As shown in Figure 27, the first electrode GT63 of the sixth scan transistor in Figure 5A is connected to the first region of the active layer of the sixth scan transistor via the 43rd via hole, and is connected to the second plate of the second scan capacitor via the 52nd via hole. As shown in Figure 28, the first electrode GT63 of the sixth scan transistor in Figure 6A is connected to the first region of the active layer of the sixth scan transistor via the 42nd via hole, and is connected to the second plate of the second scan capacitor via the 51st via hole.

[0514] In an exemplary embodiment, as shown in Figures 26 to 28, the first electrode GT83 of the eighth scan transistor can be in a block shape. As shown in Figure 27, the first electrode GT83 of the eighth scan transistor in Figure 5A is connected to the first region of the active layer of the eighth scan transistor via the 44th via hole, and is connected to the gate electrode of the fifth scan transistor (also the second plate of the second scan capacitor) via the 49th via hole. As shown in Figure 28, the first electrode GT63 of the sixth scan transistor in Figure 6A is connected to the first region of the active layer of the eighth scan transistor via the 43rd via hole, and is connected to the gate electrode of the fifth scan transistor (also the second plate of the second scan capacitor) via the 48th via hole.

[0515] In an exemplary embodiment, as shown in Figures 26 to 28, the second electrode GT84 of the eighth scan transistor can be in a block shape. As shown in Figure 27, the second electrode GT84 of the eighth scan transistor in Figure 5A is connected to the second region of the active layer of the eighth scan transistor via the 45th via hole, and is connected to the gate electrode of the second scan transistor via the 47th via hole. As shown in Figure 28, the second electrode GT84 of the eighth scan transistor in Figure 6A is connected to the second region of the active layer of the eighth scan transistor via the 44th via hole, and is connected to the gate electrode of the second scan transistor via the 46th via hole.

[0516] In an exemplary embodiment, as shown in FIG27 , one of the first sub-clock signal line GCK1A of the first scan clock signal line and the third sub-clock signal line GCK2A of the second scan clock signal line in FIG5A is connected to the gate electrode of the first scan transistor (also the gate electrode of the third scan transistor) through a 46th via hole. As shown in FIG28 , one of the first sub-clock signal line GCK1A of the first scan clock signal line and the third sub-clock signal line GCK2A of the second scan clock signal line in FIG6A is connected to the gate electrode of the first scan transistor (also the gate electrode of the third scan transistor) through a 45th via hole.

[0517] In an exemplary embodiment, as shown in FIG27 , the other of the first sub-clock signal line GCK1A of the first scan clock signal line and the third sub-clock signal line GCK2A of the second scan clock signal line in FIG5A is connected to the gate electrode of the seventh scan transistor through the 50th via hole. As shown in FIG28 , the other of the first sub-clock signal line GCK1A of the first scan clock signal line and the third sub-clock signal line GCK2A of the second scan clock signal line in FIG6A is connected to the gate electrode of the seventh scan transistor through the 49th via hole.

[0518] In an exemplary embodiment, as shown in Figure 27, the second scan power line GVGH in Figure 5A is connected to the gate electrode of the eighth scan transistor through the 51st via hole. As shown in Figure 28, the second scan power line GVGH in Figure 6A is connected to the gate electrode of the eighth scan transistor through the 50th via hole.

[0519] In an exemplary embodiment, as shown in Fig. 27, the first connection line CL1 in Fig. 5A is connected to the scan output signal line through the fifty-fifth via hole. As shown in Fig. 28, the first connection line CL1 in Fig. 6A is connected to the scan output signal line through the fifty-fourth via hole.

[0520] In an exemplary embodiment, as shown in FIG27 , the first sub initial power supply line INITL1A and the fourth connection line CL4 of the first initial power supply line in FIG5A are connected to the first signal connection line through the fifty-sixth via hole. As shown in FIG28 , the first sub initial power supply line INITL1A and the fourth connection line CL4 of the first initial power supply line in FIG6A are connected to the first signal connection line through the fifty-fifth via hole.

[0521] In an exemplary embodiment, as shown in FIG27 , the first sub-initial power supply line INITL2A and the third connection line CL3 of the second initial power supply line in FIG5A are connected to the second signal connection line through the fifty-seventh via hole. As shown in FIG28 , the first sub-initial power supply line INITL2A and the third connection line CL3 of the second initial power supply line in FIG6A are connected to the second signal connection line through the fifty-sixth via hole.

[0522] In an exemplary embodiment, as shown in Figures 46 and 47, the first electrode MT13 of the first transistor is shaped like a strip extending along the second direction D2. As shown in Figures 48 and 49, the first electrode MT13 of the first transistor is shaped like a strip extending along the first direction D1. As shown in Figures 46 to 49, the first electrode MT13 of the first transistor is electrically connected to the first region of the active layer of the first transistor through the fifty-eighth via hole and is electrically connected to the first initial signal line through the sixty-fifth via hole.

[0523] In the exemplary embodiment, as shown in Figures 46 to 49, the second electrode MT14 of the first transistor and the first electrode MT23 of the second transistor are integrally structured and are shaped like a strip extending along the first direction D1. The second electrode MT14 of the first transistor (also the first electrode MT23 of the second transistor) is electrically connected to the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor) through a fifty-ninth via hole, and is electrically connected to the gate electrode of the third transistor (also the first plate of the capacitor) through a sixty-fourth via hole.

[0524] 46 to 49 , the first electrode MT43 of the fourth transistor is in a block shape and is electrically connected to the first region of the active layer of the fourth transistor through a sixtieth via hole.

[0525] In an exemplary embodiment, as shown in Figures 46 and 47, the first electrode M53 of the fifth transistor extends at least partially along the first direction D1. The first electrode M53 of the fifth transistor is electrically connected to the first region of the active layer of the fifth transistor through a sixty-first via hole, and is electrically connected to the second plate of the capacitor through a sixty-sixth via hole.

[0526] In the exemplary embodiment, as shown in Figures 46 to 49, the second electrode MT64 of the sixth transistor and the first electrode MT74 of the seventh transistor are integrally formed and have a block shape. The second electrode MT64 of the sixth transistor (also the first electrode MT74 of the seventh transistor) is electrically connected to the second region of the active layer of the sixth transistor (the second region of the active layer of the seventh transistor) through the sixty-second via.

[0527] In an exemplary embodiment, as shown in Figures 46 to 49, the first electrode MT73 of the seventh transistor is shaped like a strip extending along the first direction D1. The first electrode MT73 of the seventh transistor is electrically connected to the first region of the active layer of the seventh transistor through a sixty-third via hole and is electrically connected to the second initial signal line through a sixty-seventh via hole.

[0528] In exemplary embodiments, as shown in FIG. 46 and FIG. 49 , the data link line DL extends at least partially along the second direction D2 and may be located between the second electrode MT64 of the sixth transistor (also the first electrode MT74 of the seventh transistor) and the first electrode MT73 of the seventh transistor.

[0529] In an exemplary embodiment, as shown in Figures 48 and 49, the first sub-power line VDDA is shaped like a line extending at least partially along the first direction D1. The overlapping region of the first sub-power line VDDA and the first region of the active layer of the fifth transistor serves as the first electrode MT53 of the fifth transistor. The first sub-power line VDDA is electrically connected to the first region of the active layer of the fifth transistor through a sixty-first via and to the second plate of the capacitor through a sixty-sixth via.

[0530] In an exemplary embodiment, as shown in Figures 48 and 49, an electrode connection line CL is electrically connected to the first electrodes MT73 of the seventh transistors of adjacent sub-pixels located in the same column. The first electrodes MT73 of the seventh transistors of adjacent sub-pixels in at least one column of sub-pixels are spaced apart, and the first electrodes MT73 of the seventh transistors of adjacent sub-pixels in at least one column of sub-pixels are electrically connected via the electrode connection line CL. Specifically, the first electrodes MT73 of the seventh transistors of adjacent sub-pixels in the jth column of sub-pixels are spaced apart, and the first electrodes MT73 of the seventh transistors of adjacent sub-pixels in the j+1th column of sub-pixels are electrically connected via the electrode connection line CL. The arrangement of the electrode connection line CL can form a mesh structure with the multiple second initial signal lines, ensuring that the signals of the second initial signal lines in each sub-pixel are consistent, thereby ensuring the display effect of the display substrate.

[0531] In an exemplary embodiment, as shown in Figures 48 and 49, when the first electrodes MT73 of the seventh transistors in adjacent sub-pixels located in the same column of sub-pixels are spaced apart, a virtual straight line extending along the first direction D1 and passing through the first electrode MT73 of the seventh transistor passes through the second electrode MT64 of the sixth transistor (also the first electrode MT74 of the seventh transistor). When the first electrodes MT73 of the seventh transistors in adjacent sub-pixels located in the same column of sub-pixels are connected to each other, the orthographic projection of the electrode connection line CL on the substrate does not overlap with the orthographic projection of the second electrode MT64 of the sixth transistor (also the first electrode MT74 of the seventh transistor) on the substrate.

[0532] (7) forming a fourth insulating layer pattern, comprising: depositing a fourth insulating film on a substrate having the aforementioned pattern, coating a first flat film, and patterning the fourth insulating film and the first flat film through a patterning process to form a fourth insulating layer covering the aforementioned structure and a flat layer pattern arranged on the fourth insulating layer, wherein the flat layer is provided with grooves and a plurality of via patterns, as shown in Figures 29, 30, 50 and 51, wherein Figure 29 is a schematic diagram of Figure 5A after the flat layer pattern is formed, Figure 30 is a schematic diagram of Figure 6A after the flat layer pattern is formed, Figure 50 is a schematic diagram of Figure 7B after the flat layer pattern is formed, and Figure 51 is a schematic diagram of Figure 7C after the flat layer pattern is formed.

[0533] In an exemplary embodiment, as shown in Figures 29, 30, 50 and 51, the plurality of vias of the planar layer pattern may include at least: a seventy-first via V71, a seventy-second via V72, a seventy-third via V73, a seventy-fourth via V74, a seventy-fifth via V75, a seventy-sixth via V76, a seventy-seventh via V77, a seventy-eighth via V78 and sixty-eighth via V68 to seventieth via V70.

[0534] In an exemplary embodiment, as shown in Figures 29 and 30, the orthographic projection of the seventy-first via V71 on the substrate is located within the range of the orthographic projection of the first sub-clock signal line of the first scan clock signal line on the substrate, the fourth insulating layer in the seventy-first via V71 is etched away to expose the first sub-clock signal line of the first scan clock signal line, and the seventy-first via V71 is configured to connect the subsequently formed second sub-clock signal line of the first scan clock signal line to the first sub-clock signal line of the first scan clock signal line through the via.

[0535] In an exemplary embodiment, as shown in Figures 29 and 30, the orthographic projection of the seventy-second via V72 on the substrate is located within the range of the orthographic projection of the third sub-clock signal line of the second scan clock signal line on the substrate, the fourth insulating layer in the seventy-second via V72 is etched away to expose the third sub-clock signal line of the second scan clock signal line, and the seventy-second via V72 is configured to connect the subsequently formed fourth sub-clock signal line of the second scan clock signal line to the third sub-clock signal line of the second scan clock signal line through the via.

[0536] In an exemplary embodiment, as shown in Figures 29 and 30, the orthographic projection of the seventy-third via V73 on the substrate is located within the range of the orthographic projection of the first sub-initial power supply line of the first initial power supply line on the substrate, the fourth insulating layer in the seventy-third via V73 is etched away to expose the first sub-initial power supply line of the first initial power supply line, and the seventy-third via V73 is configured to connect the second sub-initial power supply line of the first initial power supply line formed subsequently to the first sub-initial power supply line of the first initial power supply line through the via.

[0537] In an exemplary embodiment, as shown in Figures 29 and 30, the orthographic projection of the seventy-fourth via V74 on the substrate is located within the range of the orthographic projection of the first sub-initial power supply line of the second initial power supply line on the substrate, exposing the first sub-initial power supply line of the second initial power supply line, and the seventy-fourth via V74 is configured to connect the second sub-initial power supply line of the second initial power supply line formed subsequently to the first sub-initial power supply line of the second initial power supply line through the via.

[0538] In an exemplary embodiment, as shown in Figures 29 and 30, the orthographic projection of the seventy-fifth via V75 on the substrate is located within the range of the orthographic projection of the first connecting line on the substrate, the fourth insulating layer in the seventy-fifth via V75 is etched away to expose the first connecting line, and the seventy-fifth via V75 is configured to connect the subsequently formed fifth connecting line to the first connecting line through the via.

[0539] In an exemplary embodiment, as shown in Figures 29 and 30, the orthographic projection of the seventy-sixth via V76 on the substrate is located within the range of the orthographic projection of the second connecting line on the substrate, the fourth insulating layer in the seventy-sixth via V76 is etched away to expose the second connecting line, and the seventy-sixth via V76 is configured to connect the subsequently formed sixth connecting line to the second connecting line through the via.

[0540] In an exemplary embodiment, as shown in Figures 29 and 30, the orthographic projection of the seventy-seventh via V77 on the substrate is located within the range of the orthographic projection of the third connecting line on the substrate, the fourth insulating layer in the seventy-seventh via V77 is etched away to expose the first connecting line, and the seventy-seventh via V77 is configured to connect the subsequently formed seventh connecting line to the third connecting line through the via.

[0541] In an exemplary embodiment, as shown in Figures 29 and 30, the orthographic projection of the seventy-eighth via V78 on the substrate is located within the range of the orthographic projection of the fourth connecting line on the substrate, the fourth insulating layer in the seventy-eighth via V78 is etched away to expose the fourth connecting line, and the seventy-eighth via V78 is configured to connect the subsequently formed eighth connecting line to the fourth connecting line through the via.

[0542] In an exemplary embodiment, as shown in Figures 50 and 51, the orthographic projection of the sixty-eighth via V68 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, exposing the first electrode of the fourth transistor, and the sixty-eighth via V68 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor through the via.

[0543] In an exemplary embodiment, as shown in FIG50 , the orthographic projection of the sixty-ninth via V69 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, exposing the first electrode of the fifth transistor, and the sixty-ninth via V69 is configured to connect a subsequently formed first power line to the first electrode of the fifth transistor through the via.

[0544] In an exemplary embodiment, as shown in FIG51 , the orthographic projection of the sixty-ninth via V69 on the substrate is located within the range of the orthographic projection of the first sub-power line on the substrate, exposing the first sub-power line, and the sixty-ninth via V69 is configured to connect the subsequently formed second sub-power line to the first sub-power line through the via.

[0545] In an exemplary embodiment, as shown in Figures 50 and 51, the orthographic projection of the seventieth via V70 on the substrate is located within the range of the orthographic projection of the second pole of the sixth transistor (also the second pole of the seventh transistor) on the substrate, exposing the second pole of the sixth transistor (also the second pole of the seventh transistor), and the seventieth via V70 is configured to connect the subsequently formed anode connecting electrode to the second pole of the sixth transistor (also the second pole of the seventh transistor) through the via.

[0546] In an exemplary embodiment, a fourth insulating layer is provided in FIG. 5A and FIG. 6A , but the fourth insulating layer provided in FIG. 5A and FIG. 6A does not have a via hole.

[0547] (8) forming a fourth conductive layer pattern, comprising: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern, as shown in FIG31, FIG32, FIG33, and FIG52 to FIG55, FIG31 is a schematic diagram of the fourth conductive layer pattern of FIG5A and FIG6A, FIG32 is a schematic diagram of FIG5A after the fourth conductive layer pattern is formed, FIG33 is a schematic diagram of FIG6A after the fourth conductive layer pattern is formed, FIG52 is a schematic diagram of the fourth conductive layer pattern of FIG7B, FIG53 is a schematic diagram of FIG7B after the fourth conductive layer pattern is formed, FIG54 is a schematic diagram of FIG7C after the fourth conductive layer pattern is formed, and FIG55 is a schematic diagram of FIG7C after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0548] In an exemplary embodiment, as shown in Figures 31 to 33, the fourth conductive layer pattern may include at least: a second sub-clock signal line GCK1B of the first scan clock signal line, a fourth sub-clock signal line GCK2B of the second scan clock signal line, a second sub-initial power supply line INITL1B of the first initial power supply line, a second sub-initial power supply line INITL2B of the second initial power supply line, a fifth connecting line CL5, a sixth connecting line CL6, a seventh connecting line CL7 and an eighth connecting line CL8.

[0549] In an exemplary embodiment, the second sub-clock signal line GCK1B of the first scan clock signal line is shaped like a line in the first direction D1 and is connected to the first sub-clock signal line of the first scan clock signal line through the 71st via hole.

[0550] In an exemplary embodiment, an orthographic projection of the second sub-clock signal line GCK1B of the first scan clock signal line on the substrate at least partially overlaps with an orthographic projection of the first sub-clock signal line of the first scan clock signal line on the substrate.

[0551] In an exemplary embodiment, the fourth sub-clock signal line GCK2B of the second scan clock signal line is shaped like a line in the first direction D1 and passes through the 72nd via hole and the third sub-clock signal line of the second scan clock signal line.

[0552] In an exemplary embodiment, an orthographic projection of the fourth sub-clock signal line GCK2B of the second scan clock signal line on the substrate at least partially overlaps with an orthographic projection of the third sub-clock signal line of the second scan clock signal line on the substrate.

[0553] In an exemplary embodiment, the second sub-initial power line of the first initial power line is linear in the first direction D1 and is connected to the first sub-initial power line of the first initial power line through the seventy-third via hole.

[0554] In an exemplary embodiment, an orthographic projection of the second sub-initial power supply line of the first initial power supply line on the substrate at least partially overlaps with an orthographic projection of the first sub-initial power supply line of the first initial power supply line on the substrate.

[0555] In an exemplary embodiment, the second sub-initial power line of the second initial power line is linear in the first direction D1 and is connected to the first sub-initial power line of the second initial power line through the seventy-fourth via hole.

[0556] In an exemplary embodiment, an orthographic projection of the second sub-initial power supply line of the second initial power supply line on the substrate at least partially overlaps with an orthographic projection of the first sub-initial power supply line of the second initial power supply line on the substrate.

[0557] In an exemplary embodiment, the fifth connection line CL5 may have a block shape. The fifth connection line CL5 is connected to the first connection line through the seventy-fifth via hole.

[0558] In an exemplary embodiment, the sixth connection line CL6 may have a block shape. The sixth connection line CL6 is connected to the second connection line through the seventy-sixth via hole.

[0559] In an exemplary embodiment, the seventh connection line CL7 may have a block shape and is connected to the third connection line through the seventy-seventh via hole.

[0560] In an exemplary embodiment, the eighth connection line CL8 may have a block shape. The eighth connection line CL8 is connected to the fourth connection line through the seventy-eighth via hole.

[0561] In exemplary embodiments, as shown in FIG. 52 to FIG. 55 , the fourth conductive layer pattern may include at least a data signal line Data, an anode connection electrode VL, and a flat portion BL.

[0562] In exemplary embodiments, as shown in FIG. 52 and FIG. 53 , the fourth conductive layer pattern may further include a first power line VDD.

[0563] 54 and 55 , the fourth conductive layer pattern may further include a second sub power line VDDB. The second sub power line VDDB and the first sub power line constitute a first power line.

[0564] 52 to 55 , the data signal line Data extends along the first direction D1 and is electrically connected to the first electrode of the fourth transistor through the sixty-eighth via hole.

[0565] 52 to 55 , the anode connection electrode VL extends in the first direction D1 and is electrically connected to the second electrode of the sixth transistor (also the first electrode of the seventh transistor) through the seventieth via hole.

[0566] 52 and 53 , the flat portion BL is integrally formed with the first power line VDD, and an orthographic projection of the flat portion BL on the substrate at least partially overlaps an orthographic projection of the anode of the light emitting device on the substrate.

[0567] 54 and 55 , the flat portion BL is integral with the second sub power line VDDB, and an orthographic projection of the flat portion BL on the substrate at least partially overlaps with an orthographic projection of the anode of the light emitting device on the substrate.

[0568] 52 and 53 , the first power line VDD extends in the first direction D1 and is electrically connected to the first electrode of the fifth transistor through the sixty-ninth via hole.

[0569] 52 and 53 , the second sub power line VDD extends in the first direction D1. The second sub power line VDD is electrically connected to the first sub power line through the sixty-ninth via hole.

[0570] (9) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the planar layer may include: depositing a fifth insulating film and a fifth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fifth conductive film using a patterning process to form a fifth insulating layer and a fifth conductive layer disposed on the fifth insulating layer, and depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the fifth conductive layer pattern.

[0571] In exemplary embodiments, the fifth conductive layer may include an anode connection line.

[0572] At this point, the drive structure layer is completed on the substrate. In a plane parallel to the display substrate, the drive structure layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a planar layer, a fourth conductive layer, a fifth insulating layer, a fifth conductive layer, and a sixth insulating layer, which are sequentially arranged on the substrate.

[0573] In an exemplary embodiment, the semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide comprising indium and tin, an oxide comprising tungsten and indium, an oxide comprising tungsten, indium and zinc, an oxide comprising titanium and indium, an oxide comprising titanium, indium and tin, an oxide comprising indium and zinc, an oxide comprising silicon, indium and tin, or an oxide comprising indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer. The active layer thin film may be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide oxide technology, silicon technology, and organic technology.

[0574] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0575] In exemplary embodiments, the fifth conductive layer may employ an indium tin oxide (ITO) or indium zinc oxide (IZO) material.

[0576] In exemplary embodiments, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may be formed of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer and the second insulating layer may be referred to as a gate insulating (GI) layer, and the third insulating layer may be referred to as an interlayer insulating (ILD) layer.

[0577] In an exemplary embodiment, the planar ...

Claims

1. A display substrate, comprising: A substrate and a driving structure layer arranged on the substrate, wherein the substrate includes a display area and a non-display area, and the driving structure layer includes: a plurality of pixel circuits located in the display area and a gate driving circuit and an electrostatic discharge circuit located in the non-display area, wherein the gate driving circuit includes a plurality of driving circuits, and the plurality of driving circuits and the electrostatic discharge circuit are arranged in a direction close to the display area; The electrostatic discharge circuit is arranged between two adjacent driving circuits and is electrically connected to at least one signal line of any one of the two adjacent driving circuits.

2. The display substrate according to claim 1, wherein: The electrostatic discharge circuit comprises at least: a first release transistor and a second release transistor; The gate electrode and the second electrode of the first release transistor are connected to the first signal terminal, and the first electrode of the first release transistor is connected to the second signal terminal; The gate electrode and the first electrode of the second release transistor are connected to the third signal terminal, and the second electrode of the second release transistor is connected to the first signal terminal.

3. The display substrate according to claim 2, wherein: The plurality of driving circuits include: a light-emitting driving circuit and a scanning driving circuit, wherein the scanning driving circuit is located on a side of the light-emitting driving circuit close to the display area; The driving structure layer further includes: a light-emitting initial signal line, a first light-emitting clock signal line, a second light-emitting clock signal line, a first light-emitting power line, a second light-emitting power line, a scanning initial signal line, a first scanning clock signal line, a second scanning clock signal line, a first scanning power line, and a second scanning power line located in the non-display area; any one of the light-emitting initial signal line, the first light-emitting clock signal line, the second light-emitting clock signal line, the first light-emitting power line, the second light-emitting power line, the scanning initial signal line, the first scanning clock signal line, the second scanning clock signal line, the first scanning power line, and the second scanning power line extends along the first direction; The light-emitting driving circuit is electrically connected to the light-emitting initial signal line, the first light-emitting clock signal line, the second light-emitting clock signal line, the first light-emitting power line and the second light-emitting power line respectively; the scanning driving circuit is electrically connected to the scanning initial signal line, the second scanning clock signal line, the first scanning clock signal line, the first scanning power line and the second scanning power line respectively; The light-emitting initial signal line, the first light-emitting clock signal line, the second light-emitting clock signal line, the first light-emitting power line, the second light-emitting power line, the first scanning power line, the first scanning clock signal line, the second scanning clock signal line, the scanning initial signal line and the second scanning power line are arranged in sequence along a direction close to the display area.

4. The display substrate according to claim 3, wherein: The orthographic projection of the electrostatic discharge circuit on the substrate partially overlaps with the first scanning power line and the second light emitting power line, and at least a portion of the electrostatic discharge circuit is located between the second light emitting power line and the first scanning power line.

5. The display substrate according to claim 4, wherein: The driving structure layer further includes: a light-emitting output signal line and a scanning output signal line located in the non-display area, and a light-emitting signal line and a scanning signal line at least partially located in the display area; any one of the scanning output signal line, the light-emitting signal line and the scanning signal line at least partially extends along a second direction, and the first direction intersects the second direction; the pixel circuit is connected to the light-emitting signal line and the scanning signal line respectively; The light-emitting driving circuit comprises: a plurality of cascaded light-emitting shift registers, and the scanning driving circuit comprises: a plurality of cascaded scanning shift registers; The light-emitting output signal line is electrically connected to the light-emitting shift register and at least one light-emitting signal line respectively; The scan output signal lines are electrically connected to the scan shift register and the scan signal lines respectively.

6. The display substrate according to claim 5, wherein: The first signal end of the electrostatic discharge circuit is electrically connected to the light output signal line, the second signal end of the electrostatic discharge circuit is electrically connected to the second light power line, and the third signal end of the electrostatic discharge circuit is electrically connected to the first scanning power line.

7. The display substrate according to any one of claims 3 to 6, wherein: A distance between the second light emitting power line and the first scanning power line is approximately 8 micrometers to 15 micrometers.

8. The display substrate according to claim 6, wherein: The light-emitting shift register includes a plurality of light-emitting transistors and a plurality of light-emitting capacitors, the scanning shift register includes a plurality of scanning transistors and a plurality of scanning capacitors, the light-emitting capacitors and the scanning capacitors each include a first electrode plate and a second electrode plate, the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence, the first scanning clock signal line includes: a first sub-clock signal line and a second sub-clock signal line electrically connected to each other, the second scanning clock signal line includes: a third sub-clock signal line and a fourth sub-clock signal line electrically connected to each other; The semiconductor layer at least includes: an active layer of a plurality of light emitting transistors, an active layer of a plurality of scanning transistors, an active layer of a first release transistor, and an active layer of a second release transistor; The first conductive layer at least includes: a light-emitting signal line, a scanning signal line, gate electrodes of a plurality of light-emitting transistors, first plates of a plurality of light-emitting capacitors, gate electrodes of a plurality of scanning transistors, first plates of a plurality of scanning capacitors, a gate electrode of a first release transistor, and a gate electrode of a second release transistor; The second conductive layer at least includes: a plurality of second plates of light-emitting capacitors, a plurality of second plates of scanning capacitors, a scanning output signal line and a light-emitting output signal line; The third conductive layer at least includes: a light-emitting initial signal line, a first light-emitting clock signal line, a second light-emitting clock signal line, a first light-emitting power line, a second light-emitting power line, a scan initial signal line, a first sub-clock signal line of the first scan clock signal line, a third sub-clock signal line of the second scan clock signal line, a first scan power line, a second scan power line, first and second electrodes of a plurality of light-emitting transistors, first and second electrodes of a plurality of scan transistors, first and second electrodes of a first release transistor, and first and second electrodes of a second release transistor; The fourth conductive layer includes at least: a second sub-clock signal line of the first scanning clock signal line and a fourth sub-clock signal line of the second scanning clock signal line.

9. The display substrate according to claim 8, wherein: The first and second electrodes of multiple light-emitting transistors are located between the first light-emitting power line and the second light-emitting power line, the first and second electrodes of the first release transistor and the first and second electrodes of the second release transistor are located between the second light-emitting power line and the first scanning power line, the first and second electrodes of some scanning transistors are located between the scanning initial signal line and the second scanning power line, and the first and second electrodes of another part of the scanning transistors can be located on the side of the second scanning power line close to the display area.

10. The display substrate according to claim 8, wherein: At least one of the light-emitting output signal lines comprises: an output connection portion and at least one output line, the output connection portion extends along a first direction, and the at least one output line is arranged along the first direction; The output connection part is electrically connected to the light emitting shift register and at least one output line respectively. The output line corresponds to the light emitting signal line connected to the light emitting output signal line one by one and is electrically connected to the corresponding light emitting signal line.

11. The display substrate according to claim 10, wherein: The output line comprises: an output main body portion extending at least partially along the second direction and an output connection portion extending along the first direction, the output main body portion being electrically connected to the output connection portion; The second electrode of the first release transistor and the second electrode of the second release transistor are an integrated structure, and the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the output connection portion on the substrate, and the integrated structure of the second electrode of the first release transistor and the second electrode of the second release transistor is electrically connected to the output connection portion.

12. The display substrate according to claim 11, wherein: The active layer of the first release transistor and the active layer of the second release transistor are an integrated structure and extend along the second direction; An orthographic projection of the output connection portion on the substrate does not overlap with an orthographic projection of an integrated structure of an active layer of the first release transistor and an active layer of the second release transistor on the substrate.

13. The display substrate according to claim 10, wherein: The active layer of the first release transistor and the active layer of the second release transistor are an integrated structure, and include: an active main body portion and an active connecting portion, the active main body portion and the active connecting portion are electrically connected, and the active main body portion and the active connecting portion are arranged along a first direction; The active main body portion extends along the second direction, and the active connecting portion at least partially extends along the first direction; The active connection portion is in a zigzag shape.

14. The display substrate according to claim 13, wherein: The output line at least partially extends along the second direction; the second electrode of the first release transistor and the second electrode of the second release transistor are integrally structured; The orthographic projection of the active connecting portion on the substrate at least partially overlaps with the orthographic projection of the second electrode of the first release transistor and the second electrode of the second release transistor and the output line on the substrate, and is electrically connected to the second electrode of the first release transistor and the second electrode of the second release transistor and the output line respectively.

15. The display substrate according to claim 13 or 14, wherein: The width of the active connection portion is smaller than the width of the active main body portion.

16. The display substrate according to claim 8, wherein: The scan shift register comprises: a first scan capacitor, a second electrode plate of the first scan capacitor is electrically connected to the first scan power line, and the second electrode plate of the first scan capacitor extends along the second direction; The orthographic projection of the second electrode plate of the first scanning capacitor on the substrate at least partially overlaps with the orthographic projections of the first scanning power line, the second scanning power line, the first scanning clock signal line, the second scanning clock signal line and the scanning initial signal line on the substrate.

17. The display substrate according to claim 1, wherein: The display area includes: a first display area and a second display area located at least on one side of the first display area, the display substrate also includes: a light-emitting device and an anode connection line located in the display area, and a pixel circuit is electrically connected to the light-emitting device; the pixel circuit includes: a first pixel circuit and a second pixel circuit located in the second display area, the light-emitting device includes: a first light-emitting device located in the first display area and a second light-emitting device located in the second display area, the first pixel circuit is electrically connected to the first light-emitting device, and the second pixel circuit is electrically connected to the second light-emitting device; The orthographic projection of the first pixel circuit on the substrate at least partially overlaps with the orthographic projection of the first light-emitting device connected to the first pixel circuit on the substrate; The anode connection line is electrically connected to the second light emitting device and the second pixel circuit connected to the second light emitting device respectively.

18. The display substrate according to claim 17, wherein: The driving structure layer further includes: a first power line, a data signal line and a data connection line at least partially located in the display area; the first power line and the data signal line at least partially extend along the first direction, and the data connection line at least partially extends along the second direction; The driving structure layer further includes: a fourth conductive layer and a fifth conductive layer sequentially stacked on the third conductive layer; The third conductive layer at least includes: a data connection line; The fourth conductive layer at least includes: a first power line and a data signal line; The fifth conductive layer at least includes: an anode connection line; The fifth conductive layer is a transparent conductive layer.

19. The display substrate according to claim 18, wherein: The driving structure layer further includes: a flat layer located between the third conductive layer and the fourth conductive layer, wherein the flat layer is provided with a groove; The orthographic projection of the electrostatic discharge circuit on the substrate at least partially overlaps with the orthographic projection of the groove on the substrate.

20. The display substrate according to claim 19, wherein: The driving structure layer further comprises: at least one initial power supply line located in the non-display area and at least one initial signal line at least partially located in the display area; the initial power supply line is located on a side of the scan driving circuit close to the display area, the initial power supply line at least partially extends along the first direction, and the initial signal line at least partially extends along the second direction; the initial power supply line comprises a first sub-initial power supply line and a second sub-initial power supply line electrically connected to each other; At least one initial signal line corresponds to at least one initial power supply line one by one, and the initial signal line is electrically connected to the pixel circuit and the corresponding initial power supply line respectively; The second conductive layer at least includes: an initial signal line; The third conductive layer at least includes: a first sub-initial power supply line of the initial power supply line; The fourth conductive layer at least includes: a second sub-initial power supply line of the initial power supply line.

21. A display device, comprising: The display substrate and photosensor according to any one of claims 1 to 20, wherein the photosensor is located inside the display substrate.

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