Fault detection circuit, display panel, and fault detection method

Abstract

A fault detection circuit (20), a display panel (10), and a fault detection method. The fault detection circuit comprises a first detection unit (21) and a second detection unit (22). The first detection unit (21) performs short-circuit detection on a pixel unit (P), and if the pixel unit (P) is abnormal, the second detection unit (22) detects the pixel unit (P). Performing detection by means of the two detection units can improve the detection accuracy.

Description

Fault detection circuit, display panel and fault detection method

[0001] This application claims priority to the Chinese patent application filed with the Patent Office of China on April 4, 2023, application number CN202310350800.5, and application name “Fault Detection Circuit, Display Panel and Fault Detection Method”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a fault detection circuit, a display panel, and a fault detection method. Background Art

[0003] Electronic Paper Display (EPD) technology is a new technology that utilizes ambient light for display. Its display principle involves encapsulating black and white charged particles in a microcapsule structure. An external electric field controls the movement of these differently charged particles, creating a monochrome display. Under the influence of the electric field, the two different ink droplets continuously move. When the white ink droplets rise to the upper surface, all ambient light hitting the upper surface is completely reflected, resulting in a white display. The two different ink droplets, mixed in proportion, can create different colors, including black and white and grayscale.

[0004] Currently, abnormality detection for e-paper display panels primarily involves configuring transistors to drive data lines and scan lines separately, and then determining whether the entire display area is functioning properly based on the panel's display quality. However, this approach involves testing the display area directly after the finished product is completed. If an abnormality is detected, reassembly can damage the pixel units of the e-paper film within the display area and the driver integrated circuits that drive these units, resulting in a waste of resources. Therefore, improving detection accuracy before the e-paper is finished is an urgent issue.

[0005] Summary of the Invention

[0006] In view of the above-mentioned deficiencies in the prior art, the present application proposes a fault detection circuit, a display panel, and a fault detection method that can effectively improve detection accuracy.

[0007] The present application provides a fault detection circuit, which is applied to a display panel including multiple pixel units for performing image display, and includes a first detection unit, a second detection unit and a control unit. The control unit is connected to the first detection unit and the second detection unit. The first detection unit is used to perform short circuit or open circuit detection on the pixel units in the display panel under the control of the control unit. If at least one pixel unit displays an abnormality and is determined to be a first abnormal pixel unit, the control unit controls the second detection unit to re-execute the detection. If the second detection unit detects that the first abnormal pixel unit displays normally, it indicates that the first detection unit has a fault. If the second detection unit detects that the first abnormal pixel unit displays abnormally, it indicates that the first abnormal pixel unit has a fault.

[0008] Optionally, a pixel unit that displays abnormality when the second detection unit performs detection is determined to be a second abnormal pixel unit. When the first abnormal pixel unit is different from the second abnormal pixel unit detected by the second detection unit, it indicates that the first detection unit and the second abnormal pixel unit are faulty.

[0009] Optionally, the display panel includes a scan test terminal, a data test terminal, a plurality of scan lines extending along a first direction, and a plurality of data lines extending along a second direction, wherein the first direction is different from the second direction, and the first detection unit is connected to the first control signal output terminal, the scan test terminal, the data test terminal, the plurality of data lines, and the plurality of scan lines of the control unit, and is used to receive a first control signal from the first control signal output terminal and receive and transmit a test scan signal from the scan test terminal based on the first control signal, and receive and transmit a test data signal from the data test terminal to the pixel unit, so as to control the pixel unit to display an image. The second detection unit is connected to the second control signal output terminal, the scan test terminal, the data test terminal, the plurality of data lines, and the plurality of scan lines of the control unit, and is used to receive a second control signal from the second control signal output terminal and receive and transmit a test scan signal from the scan test terminal based on the second control signal, and receive and transmit a test data signal from the data test terminal to the pixel unit, so as to control the pixel unit to display an image.

[0010] Optionally, the display panel includes a first data test terminal, a second data test terminal, a first scan test terminal, a second scan test terminal, a plurality of scan lines extending along a first direction, and a plurality of data lines extending along a second direction, wherein the first direction is different from the second direction, and the first detection unit is connected to the first scan test terminal, the first data test terminal, the plurality of data lines, and the plurality of scan lines, and is used to receive and transmit a first test scan signal from the first scan test terminal and receive and transmit a first test data signal from the first data test terminal to the pixel unit according to a control signal output by the control unit, so as to control the pixel unit to display an image. The second detection unit is connected to the second scan test terminal, the second data test terminal, the plurality of data lines, and the plurality of scan lines, and is used to receive and transmit a second test scan signal from the second scan test terminal and receive and transmit a second test data signal from the second data test terminal to the pixel unit according to a control signal, so as to control the pixel unit to display an image.

[0011] Optionally, the first detection unit includes a plurality of first switching transistors and a plurality of second switching transistors, wherein the gates of the plurality of first switching transistors are connected to the first control signal output terminal, the sources of the plurality of first switching transistors are connected to the scan test terminal, and the drains of the plurality of first switching transistors are respectively connected to a plurality of scan lines, and are configured to be turned on according to the first control signal and receive a test scan signal from the scan test terminal and transmit the test scan signal to the pixel unit. The gates of the plurality of second switching transistors are connected to the first control signal output terminal, the sources of the plurality of second switching transistors are connected to the data test terminal, and the drains of the plurality of second switching transistors are respectively connected to a plurality of data lines, and are configured to be turned on according to the first control signal and receive a test data signal from the data test terminal and transmit the test data signal to the pixel unit.

[0012] Optionally, the second detection unit includes multiple third switching tubes and multiple fourth switching tubes, the gates of the multiple third switching tubes are connected to the second control signal output end, the sources of the multiple third switching tubes are connected to the scan test end, and the drains of the multiple third switching tubes are respectively connected to multiple scan lines, used to be turned on according to the second control signal and receive test scan signals from the scan test end and transmit them to the pixel unit, the gates of the multiple fourth switching tubes are connected to the second control signal output end, the sources of the multiple fourth switching tubes are connected to the data test end, and the drains of the multiple fourth switching tubes are respectively connected to multiple data lines, used to be turned on according to the second control signal and receive test data signals from the data test end and transmit them to the pixel unit.

[0013] Optionally, the display panel includes a display area and a non-display area that are adjacent to each other, the first detection unit and the second detection unit are adjacent to each other and are arranged in the non-display area on the same side of the display area, multiple first switching tubes and multiple third switching tubes are arranged in sequence in a one-to-one correspondence, and the source of any corresponding first switching tube and third switching tube is connected to the scan test end, and the drain is connected to the same scan line, for transmitting test scan signals at different times, multiple second switching tubes and multiple fourth switching tubes are arranged in sequence in a one-to-one correspondence, and the source of any corresponding second switching tube and fourth switching tube is connected to the data test end, and the drain is connected to the same data line, for transmitting test data signals at different times.

[0014] Optionally, the first detection unit and the second detection unit are arranged opposite to each other and are respectively arranged in the non-display areas on different sides of the display area.

[0015] Optionally, the pixel unit includes a plurality of micro liquid capsules, which are sealed spheres that encapsulate white particles, black particles and a transparent dispersion medium. The white particles and the black particles are two types of particles with different charges. The white particles and the black particles are completely immersed in the transparent dispersion medium and move accordingly in the transparent dispersion medium according to the action of the electric field force.

[0016] The present application also discloses a display panel, including a data driving circuit, a scan driving circuit, a plurality of pixel units arranged in an array, and the aforementioned fault detection circuit, wherein the scan driving circuit is used to output a scan signal to the pixel unit, the data driving circuit is used to output a data signal to the pixel unit, the pixel unit is used to receive the data signal under the control of the scan signal to display an image, and the fault detection circuit is used to detect short circuit or open circuit of the pixel unit.

[0017] The present application also provides a fault detection method, which is applied to the aforementioned fault detection circuit, including: controlling a first detection unit to perform short circuit or open circuit detection on pixel units in a display panel, and if all pixel units display normally, it indicates that the pixel units are not faulty; if the first detection unit detects that at least one pixel unit displays abnormally, it is determined to be a first abnormal pixel unit, and controlling a second detection unit to re-detect; if the second detection unit detects that the first abnormal pixel unit displays normally, it indicates that the first detection unit has a fault; if the second detection unit detects that the first abnormal pixel unit displays abnormally, it indicates that the first abnormal pixel unit has a fault.

[0018] Optionally, "controlling the second detection unit to re-detect" includes: controlling the second detection unit to re-detect the pixel units in the display area; "if the second detection unit detects that the first abnormal pixel unit displays normally, it indicates that the first detection unit is faulty" includes: if the second detection unit detects that all pixel units display normally, it indicates that the first abnormal pixel unit is not faulty, and the first detection unit is faulty.

[0019] Optionally, "if the second detection unit detects that the first abnormal pixel unit displays abnormally, it indicates that the first abnormal pixel unit is faulty" includes: if a pixel unit that displays abnormally when the second detection unit performs detection is determined to be a second abnormal pixel unit, when the first abnormal pixel unit is different from the second abnormal pixel unit detected by the second detection unit, it indicates that the first detection unit and the second abnormal pixel unit are faulty.

[0020] Compared with the existing technical problems, the fault detection quality of the display panel can be effectively improved by performing fault detection on the pixel units in the display panel through the first detection unit and the second detection unit respectively, and the second detection unit can be controlled to re-inspect the abnormal pixel units, effectively reducing the material waste caused by excessive screening of the display panel due to the failure of the first detection unit, and saving the production cost of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians, other drawings can be obtained based on these drawings without creative work.

[0022] FIG1 is a schematic diagram of the side structure of a display panel provided in an embodiment of the present application;

[0023] FIG2 is a schematic diagram of a planar layout of an array substrate in the display panel shown in FIG1 ;

[0024] FIG3 is a schematic structural diagram of the display medium layer in FIG2 ;

[0025] FIG4 is a schematic diagram of the circuit structure of a fault detection circuit provided in a second embodiment of the present application;

[0026] FIG5 is a schematic diagram of the circuit structure of the fault detection circuit in FIG4 provided in a third embodiment of the present application;

[0027] FIG6 is a schematic diagram of the planar layout of the fault detection circuit in FIG5 ;

[0028] FIG7 is a schematic diagram of a planar layout of a fault detection circuit as shown in FIG4 according to a fourth embodiment of the present application;

[0029] FIG8 is a schematic diagram of the circuit structure of a fault detection circuit provided in a fifth embodiment of the present application;

[0030] FIG9 is a schematic diagram of the layout of the fault detection circuit in FIG8 ;

[0031] FIG10 is a schematic diagram of a planar layout of a fault detection circuit as shown in FIG8 provided in a sixth embodiment of the present application;

[0032] FIG11 is a flow chart of a fault detection method provided in the seventh embodiment of the present application. DETAILED DESCRIPTION

[0033] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0034] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be used to implement. The serial numbers of the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application include direct and indirect connections (couplings) unless otherwise specified. The directional terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal connections between two components. A person of ordinary skill in the art will understand the specific meanings of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," and so on, in the specification, claims, and accompanying drawings of this application are used to distinguish between different objects, not to describe a specific order. Furthermore, the terms "include," "may include," "comprise," or "may include" as used in this application indicate the presence of the corresponding functions, operations, components, etc. disclosed, and do not limit the presence or absence of one or more additional functions, operations, components, etc. Furthermore, the terms "include" or "comprising" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions. It should also be understood that "at least one" as used herein means one or more, such as one, two, or three, and "a plurality" means at least two, such as two or three, unless otherwise specifically defined. The terms "step 1," "step 2," and so on in the specification, claims, and drawings of this application are used to distinguish between different objects, not to describe a specific order.

[0036] In the field of display technology, a display device may generally include a display panel and a backlight assembly, wherein the display panel is mounted to the light-emitting side of the backlight assembly, and the backlight assembly is used to provide backlight to the display panel to adjust the display panel to display different images.

[0037] Please refer to Figure 1, which is a schematic diagram of the side structure of a display panel provided in an embodiment of the present application. As shown in Figure 1, the display panel 10 includes an image display area 10a and a non-display area 10b. The display area 10a is used to perform image display, and the non-display area 10b is arranged around the display area 10a to set other auxiliary components or modules. Specifically, the display panel 10 includes an array substrate (AS) 10c and an opposing substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the opposing substrate 10d. Driving elements are set on the array substrate 10c and the opposing substrate 10d to generate corresponding electric fields according to data signals (Data), thereby driving the display medium layer 10e to transmit light of corresponding grayscale to perform image display.

[0038] Please refer to Figure 2, which is a schematic diagram of the planar layout of the array substrate in the display panel shown in Figure 1. As shown in Figure 2, the array substrate 10c corresponding to the image display area 10a includes a plurality of m*n pixel units P arranged in a matrix, m data lines S1-Sm, and n scan lines G1-Gn, where m and n are natural numbers greater than 1.

[0039] The n scan lines G1 to Gn extend along the first direction F1 and are insulated from each other and arranged in parallel along the second direction F2. The m data lines S1 to Sm extend along the second direction F2 and are insulated from each other and arranged in parallel along the first direction F1. The first direction F1 and the second direction F2 are perpendicular to each other.

[0040] Corresponding to the non-display area 10b of the display panel 10 ( FIG. 1 ), the display panel 10 further includes a timing control circuit 11 for driving pixel units to display images, a data driving circuit 12 , and a scan driving circuit 13 disposed on the array substrate 10c .

[0041] The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13 to control the operation timing of the data driving circuit 12 and the scan driving circuit 13. That is, the timing control circuit 11 outputs corresponding timing control signals to the data driving circuit 12 and the scan driving circuit 13 to control when to output the corresponding scan signals and data signals.

[0042] The data driving circuit 12 is electrically connected to the m data lines S1 -Sm and is used to transmit data signals (Data) to be displayed to the plurality of pixel units P in the form of data voltages through the m data lines S1 -Sm.

[0043] The scan driving circuit 13 is electrically connected to the n scan lines G1-Gn and is configured to output scan signals through the n scan lines G1-Gn for controlling when the pixel units P receive data signals. The scan driving circuit 13 outputs scan signals from the n scan lines G1-Gn in sequence according to the scan period.

[0044] In this embodiment, the circuit elements in the scan driving circuit 13 and the pixel units P in the array substrate 10 c are manufactured in the same process in the array substrate 10 c , which is also the GOA (Gate Driver on Array) technology.

[0045] Please refer to FIG3 , which is a schematic structural diagram of the dielectric layer shown in FIG2 .

[0046] As shown in Figure 3, the display medium layer 10e is an electronic paper film comprising a plurality of micro-liquid capsules e. The micro-liquid capsules e are sealed spheres encapsulating white particles a, black particles b, and a transparent dispersion medium c. The white particles a and black particles b are particles with different charges. For example, the white particles a are positively charged and the black particles b are negatively charged, or the white particles a are negatively charged and the black particles b are positively charged. The white particles a and black particles b are completely immersed in the transparent dispersion medium c and can move freely within the transparent dispersion medium c. When the electrodes at both ends of the micro-liquid capsules e form an electric field, the positively charged white particles a and the slightly negatively charged black particles b move accordingly under the influence of the electric field. Each micro-liquid capsule e will appear black or white to a certain degree on the side closest to the opposing substrate 10d. Ultimately, all the micro-liquid capsules e together form a specific image on the side of the opposing substrate 10d.

[0047] Please refer to FIG4 , which is a schematic diagram of a circuit structure of a fault detection circuit provided in a second embodiment of the present application. As shown in FIG4 , the fault detection circuit 20 is disposed in the non-display area 10 b of the display panel 10 . The fault detection circuit 20 includes a first detection unit 21 and a control unit 23 . The control unit 23 is connected to the first detection unit 21 . The first detection unit 21 is connected to the data test terminal 14 , the scan test terminal 15 , m data lines S1 to Sm, and n scan lines G1 to Gn . The first detection unit 21 is configured to receive a first control signal from the control unit 23 and electrically connect the m data lines S1 to Sm and the n scan lines G1 to Gn at a cross-section under the control of the first control signal. The first detection unit 21 is configured to receive a test data signal from the data test terminal 14 and a test scan signal from the scan test terminal 15 . The pixel units P in the display panel 10 display an image based on the test scan signal and the test data signal. The first detection unit 21 determines whether a line or lines of the scan lines or data lines have an open circuit or short circuit fault based on the image display result. The data test terminal 14 and the scan test terminal 15 are used to connect to an external signal output unit, and are used to receive a test scan signal and a test data signal from the external signal output unit and transmit them to the pixel unit P.

[0048] The first detection unit 21 is used to detect and identify short circuits or open circuits in the pixel units within the display area under the control of the control unit 23. If at least one pixel unit displays an abnormality and is determined to be a first abnormal pixel unit, the control unit 23 controls the second detection unit 22 to re-perform the test. If the second detection unit 22 detects that the first abnormal pixel unit displays normally, it indicates that the first detection unit 21 has failed. If the second detection unit 22 detects that the first abnormal pixel unit displays an abnormality, it indicates that the first abnormal pixel unit has failed. The pixel unit that displays an abnormality when the second detection unit 22 performs the test is determined to be a second abnormal pixel unit. If the first abnormal pixel unit and the second abnormal pixel unit detected by the second detection unit 22 are different, it indicates that both the first detection unit 21 and the second abnormal pixel unit have failed.

[0049] During testing, if the color displayed by a row of pixel cells P is significantly different from the color displayed by adjacent pixel cells, it indicates that the scan line G controlling the image display of the pixel cells in that row P has failed. If the color displayed by a column of pixel cells P is significantly different from the color displayed by adjacent pixel cells, it indicates that the data line S controlling the image display of the pixel cells in that column P has failed. For example, if a row of pixel cells displays pure white while multiple adjacent rows of pixel cells display black, it indicates that the scan line G corresponding to the pixel cells in that row P is open or short-circuited. If a column of pixel cells displays pure white while multiple adjacent columns of pixel cells display black, it indicates that the scan line G corresponding to the pixel cells in that column P is open or short-circuited.

[0050] Specifically, the first detection unit 21 includes multiple first switching tubes T1 and multiple second switching tubes T2, the gate of the first switching tube T1 is connected to the control unit 23, the source of the first switching tube T1 is connected to the scan test terminal 15, and the drain of the first switching tube T1 is connected to the scan line G in the display panel 10, and is used to be turned on according to the first control signal output by the control unit 23, and transmit the test scan signal output by the scan test terminal 15 to the pixel unit P in the display panel 10.

[0051] The gate of the second switch transistor T2 is connected to the control unit 23, the source of the second switch transistor T2 is connected to the data test terminal 14, and the drain of the second switch transistor T2 is connected to the data line S in the display panel 10. The second switch transistor T2 is turned on according to the second control signal output by the control unit 23, and transmits the test data signal output by the data test terminal 14 to the pixel unit P in the display panel 10. The pixel unit P displays an image based on the received test data signal and the test scan signal. The first detection unit 21 includes n first switch transistors T1 and m second switch transistors T2. The n first switch transistors T1 are respectively connected to the n scan lines G1 to Gn, and the m second switch transistors T2 are respectively connected to the m data lines S1 to Sm.

[0052] Please refer to FIG5 , which is a schematic diagram of the circuit structure of the fault detection circuit shown in FIG4 , provided in a third embodiment of the present application. As shown in FIG5 , the display panel 10 further includes a data test terminal 14 and a scan test terminal 15 , and the fault detection circuit 20 includes a first detection unit 21 , a second detection unit 22 , and a control unit 23 . The control unit 23 is connected to the first detection unit 21 and the second detection unit 22 and is configured to control the first detection unit 21 or the second detection unit 22 to perform fault detection on the pixel units P in the display area 10 a.

[0053] The first detection unit 21 is connected to the first control signal output terminal 231 of the control unit 23, m data lines S1-Sm, and n scan lines G1-Gn. The first detection unit 21 is connected to the data test terminal 14 via the data signal line 140 and to the scan test terminal 15 via the scan signal line 150. The first detection unit 21 is configured to receive a first control signal from the first control signal output terminal 231 and, under the control of the first control signal, electrically connect the m data lines S1-Sm and the n scan lines G1-Gn at their intersections. The first detection unit 21 is configured to receive a test data signal from the data test terminal 14 and a test scan signal from the scan test terminal 15. The pixel cells P in the display panel 10 display an image based on the test scan signal and the test data signal. Based on the image display results, the first detection unit 21 determines whether a row or rows of scan lines or data lines have an open circuit or short circuit fault. The data test terminal 14 and the scan test terminal 15 are configured to connect to an external signal output unit, receive the test scan signal and the test data signal from the external signal output unit, and transmit them to the pixel cells P.

[0054] The second detection unit 22 is connected to the second control signal output terminal 232 of the control unit 23, m data lines S1~Sm and n scan lines G1~Gn, and is connected to the data test terminal 14 via the data signal line 140 and is connected to the scan test terminal 15 via the scan signal line 150. It is used to receive the second control signal from the second control signal output terminal 232, and electrically connect the m data lines S1~Sm and the n scan lines G1~Gn at the intersection under the control of the second control signal, and is used to receive the test data signal from the data test terminal 14 and the test scan signal from the scan test terminal 15. The pixel unit P in the display panel 10 displays an image based on the test scan signal and the test data signal, and determines whether a row or multiple rows of scan lines or data lines have an open circuit or short circuit fault based on the image display result.

[0055] When the color displayed by a row of pixel cells P is significantly different from the color displayed by adjacent pixel cells, it indicates that the scan line G controlling the image display of the pixel cells in that row P has failed. When the color displayed by a column of pixel cells P is significantly different from the color displayed by adjacent pixel cells, it indicates that the data line S controlling the image display of the pixel cells in that column P has failed. For example, when a row of pixel cells displays pure white while multiple adjacent rows of pixel cells display black, it indicates that the scan line G corresponding to the pixel cells in that row P is open or short-circuited. When a column of pixel cells displays pure white while multiple adjacent columns of pixel cells display black, it indicates that the scan line G corresponding to the pixel cells in that column P is open or short-circuited.

[0056] When the detection results of the first detection unit 21 and the second detection unit 22 on the display panel 10 are both normal, it indicates that the display panel 10 has no short circuit or open circuit fault. When the detection results of the first detection unit 21 and the second detection unit 22 on the display panel 10 are that the pixel units in the same row or column have abnormalities, it indicates that the display panel 10 has a short circuit or a short circuit fault.

[0057] When the detection result of the first detection unit 21 on the display panel 10 is abnormal and the detection result of the second detection unit 22 on the display panel is normal, it indicates that the first detection unit 21 has a fault and the display panel 10 has no fault.

[0058] When the first detection unit 21 detects an abnormality in the display panel, the second detection unit also detects an abnormality in the display panel 10 , but the abnormal pixel units are located in different rows or columns, indicating that both the display panel 10 and the first detection unit 21 are faulty.

[0059] By performing fault detection on the pixel units in the display panel 10 by the first detection unit 21 and the second detection unit 22 respectively, the fault detection quality of the display panel 10 can be effectively improved, and the second detection unit 22 can be controlled to re-inspect the abnormal pixel units, effectively reducing the material waste caused by excessive screening of the display panel 10 due to the failure of the first detection unit 21, thereby saving the production cost of the display panel 10.

[0060] Specifically, the first detection unit 21 includes multiple first switching tubes T1 and multiple second switching tubes T2. The gate of the first switching tube T1 is connected to the first control signal output terminal 231, the source of the first switching tube T1 is connected to the scan test terminal 15 via the scan signal line 150, and the drain of the first switching tube T1 is connected to the scan line G in the display panel 10. It is used to be turned on according to the first control signal output by the control unit 23, and transmit the test scan signal output by the scan test terminal 15 to the pixel unit P in the display panel 10.

[0061] The gate of the second switch transistor T2 is connected to the first control signal output terminal 231. The source of the second switch transistor T2 is connected to the data test terminal 14 via the data signal line 140. The drain of the second switch transistor T2 is connected to the data line S in the display panel 10. The second switch transistor T2 is configured to be turned on in response to the second control signal output by the control unit 23, and transmit the test data signal output by the data test terminal 14 to the pixel unit P in the display panel 10. The pixel unit P displays an image based on the received test data signal and the test scan signal. The first detection unit 21 includes n first switches T1 and m second switches T2. The n first switches T1 are respectively connected to the n scan lines G1 to Gn, and the m second switches T2 are respectively connected to the m data lines S1 to Sm.

[0062] The second detection unit 22 includes a plurality of third switching transistors T3 and a plurality of fourth switching transistors T4. The gate of the third switching transistor T3 is connected to the second control signal output terminal 232. The source of the third switching transistor T3 is connected to the scan test terminal 15 via the scan signal line 150. The drain of the third switching transistor T3 is connected to the scan line G in the display panel 10. The third switching transistor T3 is turned on according to the second control signal output by the control unit 23, and the test scan signal output by the scan test terminal 15 is transmitted to the pixel unit P in the display panel 10.

[0063] The gate of the fourth switch transistor T4 is connected to the second control signal output terminal 232, the source of the fourth switch transistor T4 is connected to the data test terminal 14 via the data signal line 140, and the drain of the fourth switch transistor T4 is connected to the data line S in the display panel 10. The fourth switch transistor T4 is configured to be turned on in response to the second control signal output by the control unit 23, and transmit the test data signal output by the data test terminal 14 to the pixel unit P in the display panel 10. The pixel unit P displays an image based on the received test data signal and the test scan signal.

[0064] The second detection unit 22 includes n third switching transistors T3 and m fourth switching transistors T4 , the n third switching transistors T3 are respectively connected to n scan lines G1 -Gn, and the m fourth switching transistors T4 are respectively connected to m data lines S1 -Sm.

[0065] Please refer to FIG6 , which is a schematic diagram of the planar layout of the fault detection circuit in FIG5 .

[0066] As shown in Figure 6, the first detection unit 21 and the second detection unit 22 are adjacent and disposed on the same side of the display area 10a. In the first detection unit 21, n first switching transistors T1 are arranged sequentially along the first direction F1 and are respectively connected to the scan signal line 150, the control unit 23, and the n scan lines G1 to Gn. M second switching transistors T2 are arranged sequentially along the first direction F1 and are disposed in the same row as the n first switching transistors T1. They are respectively connected to the data signal line 140, the control unit 23, and the m data lines S1 to Sm.

[0067] In the second detection unit 22, n third switching transistors T3 are spaced a predetermined distance apart from the n first switching transistors T1 along the second direction F2 and are arranged in a one-to-one correspondence with each other. They are respectively connected to the scan signal line 150, the control unit 23, and the n scan lines G1 to Gn. M fourth switching transistors T4 are spaced a predetermined distance apart from the m second switching transistors T2 along the second direction F2 and are arranged in the same row as the n third switching transistors T3. They are respectively connected to the data signal line 140, the control unit 23, and the m data lines S1 to Sm.

[0068] The first switching transistor T1 and the third switching transistor T3, which are separated by a preset distance and arranged in a one-to-one correspondence, are considered a switching transistor group TB. The sources of the first switching transistor T1 and the third switching transistor T3 in the switching transistor group TB are connected to the scan driving circuit 13 via the same scan signal line 150, and the drains are connected to the same scan line. These switching transistors are configured to receive the test scan signal from the scan driving circuit 13 and transmit it to the pixel unit P at different times. That is, when the control unit 23 outputs the first control signal to the first switching transistor T1, the first switching transistor T1 is turned on and transmits the test scan signal. When the control unit outputs the second control signal to the third switching transistor T3, the third switching transistor T3 is turned on and transmits the test scan signal.

[0069] The second switch transistors T2 and the fourth switch transistors T4, which are separated by a preset distance and arranged in a one-to-one correspondence, are regarded as a switch transistor group TB. The sources of the second switch transistors T2 and the fourth switch transistors T4 in the switch transistor group TB are connected to the data driving circuit 12 via the same data signal line 140, and the drains are connected to the same data line. They are used to receive the test data signal and transmit it to the pixel unit P at different times. That is, when the control unit 23 outputs the first control signal to the second switch transistor T2, the second switch transistor T2 is turned on and transmits the test data signal. When the control unit outputs the second control signal to the fourth switch transistor T4, the fourth switch transistor T4 is turned on and transmits the test data signal.

[0070] Please refer to Figure 7, which is a schematic diagram of the planar layout of the fault detection circuit shown in Figure 4, providing a fourth embodiment of the present application. As shown in Figure 7, the first detection unit 21 and the second detection unit 22 are arranged opposite each other, respectively, on different sides of the display area 10a. In the first detection unit 21, n first switching transistors T1 are arranged in sequence along the first direction F1, and are respectively connected to the scan signal line 150, the control unit 23, and the n scan lines G1 to Gn. M second switching transistors T2 are arranged in sequence along the first direction F1 and are arranged in the same row as the n first switching transistors T1, and are respectively connected to the data signal line 140, the control unit 23, and the m data lines S1 to Sm.

[0071] Please refer to Figure 8, which is a schematic diagram of the circuit structure of a fault detection circuit provided in a fifth embodiment of the present application. As shown in Figure 8, the display panel 10 further includes a first data test terminal 14a, a second data test terminal 14b, a first scan test terminal 15a, and a second scan test terminal 15b. The fault detection circuit 20 includes a first detection unit 21, a second detection unit 22, and a control unit 23. The control unit 23 is connected to the first detection unit 21 and the second detection unit 22 and is configured to control the first detection unit 21 or the second detection unit 22 to perform fault detection on the pixel units P in the display area 10a.

[0072] Specifically, the first detection unit 21 is connected to the first data test terminal 14a via the first data signal line 141, is connected to the first scan test terminal 15a via the first scan signal line 151, and is connected to m data lines S1~Sm and n scan lines G1~Gn. It is used to receive a control signal from the control unit 23, and electrically connect the m data lines S1~Sm and the n scan lines G1~Gn at the intersection position according to the control signal, and is used to receive a first test data signal from the first data test terminal 14a and a first test scan signal from the first scan test terminal 15a. The pixel unit P in the display panel 10 displays an image based on the first test scan signal and the first test data signal, and determines whether a certain row or multiple rows of scan lines or data lines have an open circuit or short circuit fault based on the image display result. Among them, the first data test terminal 14a, the second data test terminal 14b, the first scan test terminal 15a and the second scan test terminal 15b are used to connect to the external signal output unit, and are used to receive the first test data signal and the second test data signal, the first test scan signal and the second test scan signal from the external signal output unit and transmit them to the pixel unit P.

[0073] The second detection unit 22 is connected to the second data test terminal 14b via the second data signal line 142 and to the second scan test terminal 15b via the second scan signal line 152, and is connected to m data lines S1~Sm and n scan lines G1~Gn. It is used to receive a control signal from the control unit 23, and electrically connect the m data lines S1~Sm and the n scan lines G1~Gn at the intersection position according to the control signal, and is used to receive a second test data signal from the second data test terminal 14b and a second test scan signal from the second scan test terminal 15b. The pixel unit P in the display panel 10 displays an image according to the second test scan signal and the second test data signal, and determines whether a row or multiple rows of scan lines or data lines have an open circuit or short circuit fault based on the image display result.

[0074] Specifically, the first detection unit 21 includes a plurality of first switching tubes T1 and a plurality of second switching tubes T2. The gate of the first switching tube T1 is connected to the control unit 23. The source of the first switching tube T1 is connected to the first scanning test end 15a via the first scanning signal line 151. The drain of the first switching tube T1 is connected to the scanning line G in the display panel 10. The first switching tube T1 is turned on according to the control signal output by the control unit 23 and transmits the output first test scanning signal to the pixel unit P in the display panel 10.

[0075] The gate of the second switch transistor T2 is connected to the control unit 23. The source of the second switch transistor T2 is connected to the first data test terminal 14a via the first data signal line 141. The drain of the second switch transistor T2 is connected to the data line S in the display panel 10. The second switch transistor T2 is turned on according to the control signal output by the control unit 23 and transmits the output first test data signal to the pixel unit P in the display panel 10. The pixel unit P displays an image based on the received first test data signal and the first test scan signal. The first detection unit 21 includes n first switches T1 and m second switches T2. The n first switches T1 are respectively connected to the n scan lines G1 to Gn, and the m second switches T2 are respectively connected to the m data lines S1 to Sm.

[0076] The second detection unit 22 includes a plurality of third switching transistors T3 and a plurality of fourth switching transistors T4. The gate of the third switching transistor T3 is connected to the control unit 23. The source of the third switching transistor T3 is connected to the second scan test terminal 15b via the second scan signal line 152. The drain of the third switching transistor T3 is connected to the scan line G in the display panel 10. The third switching transistor T3 is turned on according to the control signal output by the control unit 23 and transmits the output second test scan signal to the pixel unit P in the display panel 10.

[0077] The gate of the fourth switch transistor T4 is connected to the control unit 23, the source of the fourth switch transistor T4 is connected to the second data test terminal 14b via the second data signal line 142, and the drain of the fourth switch transistor T4 is connected to the data line S in the display panel 10. The fourth switch transistor T4 is configured to be turned on according to the control signal output by the control unit 23 to transmit the output second test data signal to the pixel unit P in the display panel 10. The pixel unit P displays an image according to the received second test data signal and the second test scan signal.

[0078] The second detection unit 22 includes n third switching transistors T3 and m fourth switching transistors T4 , the n third switching transistors T3 are respectively connected to n scan lines G1 -Gn, and the m fourth switching transistors T4 are respectively connected to m data lines S1 -Sm.

[0079] Please refer to FIG9 , which is a schematic diagram of the layout of the fault detection circuit in FIG8 .

[0080] As shown in Figure 9, the first detection unit 21 and the second detection unit 22 are adjacent and located on the same side of the display area 10a. In the first detection unit 21, n first switching transistors T1 are arranged sequentially along the first direction F1 and are respectively connected to the first scan signal line 151, the control unit 23, and the n scan lines G1 to Gn. m second switching transistors T2 are arranged sequentially along the first direction F1 and are located in the same row as the n first switching transistors T1. They are respectively connected to the first data signal line 141, the control unit 23, and the m data lines S1 to Sm. The gates of the first and second switching transistors T1 and T2 are connected to the same line.

[0081] In the second detection unit 22, the n third switching transistors T3 are spaced a predetermined distance apart from the n first switching transistors T1 along the second direction F2 and are arranged in a one-to-one correspondence with each other. They are respectively connected to the second scan signal line 152, the control unit 23, and the n scan lines G1 to Gn. The m fourth switching transistors T4 are spaced a predetermined distance apart from the m second switching transistors T2 along the second direction F2 and are arranged in the same row as the n third switching transistors T3. They are respectively connected to the second data signal line 142, the control unit 23, and the m data lines S1 to Sm.

[0082] The first switching transistor T1 and the third switching transistor T3, which are separated by a preset distance and arranged in a one-to-one correspondence, are regarded as a switching transistor group TB. The sources of the first switching transistor T1 and the third switching transistor T3 in the switching transistor group TB are respectively connected to the scan driving circuit 13 via the first scanning signal line 151 and the second scanning signal line 152, and the drains are connected to the same scanning line. They are used to receive the test scanning signal from the scan driving circuit 13 and transmit it to the pixel unit P at different times. That is, when the control unit 23 outputs the first control signal to the first switching transistor T1, the first switching transistor T1 is turned on to receive the test scanning signal from the first scanning signal line 151 and transmit it to the pixel unit P. When the control unit outputs the second control signal to the third switching transistor T3, the third switching transistor T3 is turned on to receive the test scanning signal from the second scanning signal line 152 and transmit it to the pixel unit P.

[0083] The second switch transistor T2 and the fourth switch transistor T4, which are separated by a preset distance and arranged in a one-to-one correspondence, are regarded as a switch transistor group TB. The sources of the second switch transistor T2 and the fourth switch transistor T4 in the switch transistor group TB are respectively connected to the data driving circuit 12 via the first data signal line 141 and the second data signal line 142, and the drains are connected to the same data line. They are used to receive the test data signal and transmit it to the pixel unit P at different times. That is, when the control unit 23 outputs the first control signal to the second switch transistor T2, the second switch transistor T2 is turned on and receives the test data signal from the first data signal line 141 and transmits it to the pixel unit P. When the control unit outputs the second control signal to the fourth switch transistor T4, the fourth switch transistor T4 is turned on and receives the test data signal from the second data signal line 142 and transmits it to the pixel unit P.

[0084] Please refer to Figure 10, which is a schematic diagram of the planar layout of the fault detection circuit shown in Figure 8, provided in accordance with the sixth embodiment of the present application. As shown in Figure 10, the first detection unit 21 and the second detection unit 22 are arranged relative to each other, respectively, on different sides of the display area 10a. In the first detection unit 21, n first switching transistors T1 are arranged in sequence along the first direction F1, and are respectively connected to the first scan signal line 151, the control unit 23, and the n scan lines G1 to Gn. m second switching transistors T2 are arranged in sequence along the first direction F1 and are arranged in the same row as the n first switching transistors T1, and are respectively connected to the first data signal line 141, the control unit 23, and the m data lines S1 to Sm.

[0085] In the second detection unit 22, n third switching transistors T3 are sequentially arranged along the first direction F1 and are respectively connected to the second scan signal line 152, the control unit 23, and the n scan lines G1 to Gn. M fourth switching transistors T4 are sequentially arranged along the first direction F1 and are disposed in the same row as the n third switching transistors T3. They are respectively connected to the second data signal line 142, the control unit 23, and the m data lines S1 to Sm.

[0086] Please refer to Figure 11, which is a flow chart of a fault detection method provided by the seventh embodiment of the present application. As shown in Figure 11, the display panel 10 is short-circuited or short-circuited by the fault detection circuit 20, and the specific steps are as follows:

[0087] S101 , controlling a first detection unit to perform short circuit or open circuit detection on pixel units in a display panel. If all pixel units display normally, it indicates that there is no fault in the pixel units.

[0088] The control unit 23 outputs a first control signal to the first detection unit 21. The first detection unit 21 turns on all the first switching transistors T1 and all the second switching transistors T2 according to the first control signal, so that the scan test terminal 15 is connected to the n scan lines G1 to Gn via the n first switching transistors T1, and the data test terminal 14 is connected to the m data lines S1 to Sm via the m second switching transistors T2. The n scan lines G1 to Gn and the m data lines S1 to Sm are short-circuited with each other in the display area 10a.

[0089] The scan test terminal 15 outputs a test scan signal to the multiple pixel units P via the multiple first switch tubes T1, and the data test terminal 14 outputs a test data signal to the multiple pixel units P via the multiple second switch tubes T2. When the display panel 10 displays a pure color image, that is, all black or all white, it indicates that there is no short circuit or open circuit fault in the pixel unit P in the display panel 10.

[0090] S102: If the first detection unit detects that at least one pixel unit displays abnormality, it is determined to be a first abnormal pixel unit, and the second detection unit is controlled to re-detect.

[0091] When white stripes or black stripes appear on the display panel 10 , it indicates that the pixel unit P in the display panel 10 may be faulty.

[0092] S103: If the second detection unit detects that the first abnormal pixel unit displays normally, it indicates that the first detection unit has a fault.

[0093] When the first detection unit 21 detects a first abnormal pixel unit, that is, when it detects that the display panel 10 has a fault, the control unit 23 outputs a second control signal to the second detection unit 22. The second detection unit 22 turns on all third switch tubes T3 and all fourth switch tubes T4 according to the second control signal, so that the scan test terminal 15 is connected to n scan lines G1~Gn through n third switch tubes T3, and the data test terminal 14 is connected to m data lines S1~Sm through m fourth switch tubes T4. The n scan lines G1~Gn and the m data lines S1~Sm are short-circuited with each other in the display area 10a.

[0094] The scan test end 15 outputs a test scan signal to the multiple pixel units P via multiple third switch tubes T3, and the data test end 14 outputs a test data signal to the multiple pixel units P via multiple fourth switch tubes T4. When the display panel 10 displays a pure color picture, that is, all black or all white, it indicates that the display panel 10 has no short circuit or open circuit fault, which indicates that the first detection unit 21 has a fault, and the pixel unit P in the display panel 10 has no fault, that is, the first abnormal pixel unit has no fault.

[0095] S104: If the second detection unit detects that the first abnormal pixel unit displays abnormally, it indicates that the first abnormal pixel unit is faulty.

[0096] When the second detection unit 22 controls the display panel 10 to display white stripes or black stripes and the positions of the stripes are the same as the positions of the stripes detected by the display panel 10 for the first time, it indicates that the first abnormal pixel unit is faulty and the first detection unit 21 is not faulty.

[0097] If a pixel unit that displays an abnormality when the second detection unit 22 performs detection is determined to be a second abnormal pixel unit, when the first abnormal pixel unit is different from the second abnormal pixel unit detected by the second detection unit, it indicates that the first detection unit and the second abnormal pixel unit are faulty. That is, when the second detection unit 22 controls the display panel 10 to display white stripes or black stripes and the position of the stripes is different from the position of the stripes appearing in the first detection of the display panel 10, it indicates that both the first detection unit 21 and the display panel 10 are faulty.

[0098] Re-inspecting the display panel 10 inspected by the first inspection unit 21 through the second inspection unit 22 can effectively improve the inspection quality of the first inspection unit 21, solve the material waste caused by excessive screening of the display panel 10 due to the failure of the first inspection unit 21, and effectively save the waste of display panel 10 material.

[0099] It should be understood that the application of this application is not limited to the above examples. For ordinary technicians in this field, they can make improvements or changes based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to this application.

Claims

1. A fault detection circuit, applied to a display panel including a plurality of pixel units for performing image display, wherein: The invention comprises a first detection unit, a second detection unit and a control unit, wherein the control unit is connected to the first detection unit and the second detection unit, the first detection unit is used to perform short circuit or open circuit detection on the pixel units in the display panel under the control of the control unit, if at least one of the pixel units displays abnormally and is determined to be a first abnormal pixel unit, the control unit controls the second detection unit to re-execute the detection, if the second detection unit detects that the first abnormal pixel unit displays normally, then it indicates that the first detection unit is faulty, and if the second detection unit detects that the first abnormal pixel unit displays abnormally, then it indicates that the first abnormal pixel unit is faulty.

2. The fault detection circuit according to claim 1, wherein: A pixel unit that displays abnormality when the second detection unit performs detection is determined as a second abnormal pixel unit. When the first abnormal pixel unit is different from the second abnormal pixel unit detected by the second detection unit, it indicates that the first detection unit and the second abnormal pixel unit are faulty.

3. The fault detection circuit according to claim 2, wherein: The display panel comprises a scan test terminal, a data test terminal, a plurality of scan lines extending along a first direction and a plurality of data lines extending along a second direction, wherein the first direction is different from the second direction; The first detection unit is connected to the first control signal output terminal of the control unit, the scan test terminal, the data test terminal, the plurality of data lines and the plurality of scan lines, and is used to receive a first control signal from the first control signal output terminal and receive and transmit a test scan signal from the scan test terminal and receive and transmit a test data signal from the data test terminal to the pixel unit according to the first control signal, so as to control the pixel unit to display an image; The second detection unit is connected to the second control signal output terminal of the control unit, the scan test terminal, the data test terminal, the multiple data lines and the multiple scan lines, and is used to receive a second control signal from the second control signal output terminal and receive and transmit the test scan signal from the scan test terminal according to the second control signal, and receive and transmit the test data signal from the data test terminal to the pixel unit, so as to control the pixel unit to display an image.

4. The fault detection circuit according to claim 2, wherein: The display panel comprises a first data test terminal, a second data test terminal, a first scan test terminal, a second scan test terminal, a plurality of scan lines extending along a first direction, and a plurality of data lines extending along a second direction, wherein the first direction is different from the second direction; The first detection unit is connected to the first scan test end, the first data test end, the plurality of data lines and the plurality of scan lines, and is used to receive and transmit a first test scan signal from the first scan test end and receive and transmit a first test data signal from the first data test end to the pixel unit according to a control signal output by the control unit, so as to control the pixel unit to display an image; The second detection unit is connected to the second scan test end, the second data test end, the multiple data lines and the multiple scan lines, and is used to receive and transmit a second test scan signal from the second scan test end and receive and transmit a second test data signal from the second data test end to the pixel unit according to the control signal, so as to control the pixel unit to display an image.

5. The fault detection circuit according to claim 3, wherein: The first detection unit includes a plurality of first switch tubes and a plurality of second switch tubes, wherein the gates of the plurality of first switch tubes are connected to the first control signal output terminal, the sources of the plurality of first switch tubes are connected to the scan test terminal, and the drains of the plurality of first switch tubes are respectively connected to the plurality of scan lines, and are used to be turned on according to the first control signal and receive the test scan signal from the scan test terminal and transmit it to the pixel unit; The gates of the multiple second switch tubes are connected to the first control signal output terminal, the sources of the multiple second switch tubes are connected to the data test terminal, and the drains of the multiple second switch tubes are respectively connected to the multiple data lines, and are used to be turned on according to the first control signal and receive the test data signal from the data test terminal and transmit it to the pixel unit.

6. The fault detection circuit according to claim 5, wherein: The second detection unit includes a plurality of third switch tubes and a plurality of fourth switch tubes, wherein the gates of the plurality of third switch tubes are connected to the second control signal output terminal, the sources of the plurality of third switch tubes are connected to the scan test terminal, and the drains of the plurality of third switch tubes are respectively connected to the plurality of scan lines, and are used to be turned on according to the second control signal and receive the test scan signal from the scan test terminal and transmit it to the pixel unit; The gates of the multiple fourth switch tubes are connected to the second control signal output terminal, the sources of the multiple fourth switch tubes are connected to the data test terminal, and the drains of the multiple fourth switch tubes are respectively connected to the multiple data lines, and are used to be turned on according to the second control signal and receive the test data signal from the data test terminal and transmit it to the pixel unit.

7. The fault detection circuit according to claim 6, wherein: The display panel comprises a display area and a non-display area which are adjacently arranged, the first detection unit and the second detection unit are adjacently arranged and arranged in the non-display area on the same side of the display area, the plurality of first switch tubes and the plurality of third switch tubes are arranged in sequence one by one, and the source of any correspondingly arranged first switch tube and the third switch tube is connected to the scan test end, and the drain is connected to the same scan line, so as not to transmit the test scan signal at the same time; The multiple second switch tubes and the multiple fourth switch tubes are arranged in sequence one by one, and the source of any correspondingly arranged second switch tube and fourth switch tube is connected to the data test end, and the drain is connected to the same data line for transmitting the test data signal at different times.

8. The fault detection circuit according to claim 7, wherein: The first detection unit and the second detection unit are arranged opposite to each other and are respectively arranged in non-display areas at different sides of the display area.

9. The fault detection circuit according to claim 1, wherein: The pixel unit includes a plurality of micro liquid capsules, which are sealed spheres, and white particles, black particles and a transparent dispersion medium are encapsulated inside. The white particles and the black particles are two types of particles with different charges. The white particles and the black particles are completely immersed in the transparent dispersion medium and move accordingly in the transparent dispersion medium according to the action of the electric field force.

10. A display panel, wherein: It comprises a data driving circuit, a scanning driving circuit, a plurality of pixel units arranged in an array, and a fault detection circuit, wherein the scanning driving circuit is used to output a scanning signal to the pixel unit, the data driving circuit is used to output a data signal to the pixel unit, the pixel unit is used to receive the data signal under the control of the scanning signal to display an image, and the fault detection circuit is used to detect a short circuit or a disconnection of the pixel unit; The fault detection circuit includes a first detection unit, a second detection unit and a control unit, the control unit is connected to the first detection unit and the second detection unit, the first detection unit is used to perform short circuit or open circuit detection on the pixel units in the display panel under the control of the control unit, if at least one of the pixel units displays abnormally and is determined to be a first abnormal pixel unit, the control unit controls the second detection unit to re-execute the detection, if the second detection unit detects that the first abnormal pixel unit displays normally, it indicates that the first detection unit has a fault, if the second detection unit detects that the first abnormal pixel unit displays abnormally, it indicates that the first abnormal pixel unit has a fault.

11. The display panel according to claim 10, wherein: A pixel unit that displays abnormality when the second detection unit performs detection is determined as a second abnormal pixel unit. When the first abnormal pixel unit is different from the second abnormal pixel unit detected by the second detection unit, it indicates that the first detection unit and the second abnormal pixel unit are faulty.

12. The display panel according to claim 11, wherein: The display panel comprises a scan test terminal, a data test terminal, a plurality of scan lines extending along a first direction and a plurality of data lines extending along a second direction, wherein the first direction is different from the second direction; The first detection unit is connected to the first control signal output terminal of the control unit, the scan test terminal, the data test terminal, the plurality of data lines and the plurality of scan lines, and is used to receive a first control signal from the first control signal output terminal and receive and transmit a test scan signal from the scan test terminal and receive and transmit a test data signal from the data test terminal to the pixel unit according to the first control signal, so as to control the pixel unit to display an image; The second detection unit is connected to the second control signal output terminal of the control unit, the scan test terminal, the data test terminal, the multiple data lines and the multiple scan lines, and is used to receive a second control signal from the second control signal output terminal and receive and transmit the test scan signal from the scan test terminal according to the second control signal, and receive and transmit the test data signal from the data test terminal to the pixel unit, so as to control the pixel unit to display an image.

13. The display panel according to claim 11, wherein: comprising a first data test terminal, a second data test terminal, a first scan test terminal, a second scan test terminal, a plurality of scan lines extending along a first direction, and a plurality of data lines extending along a second direction, wherein the first direction is different from the second direction; The first detection unit is connected to the first scan test end, the first data test end, the plurality of data lines and the plurality of scan lines, and is used to receive and transmit a first test scan signal from the first scan test end and receive and transmit a first test data signal from the first data test end to the pixel unit according to a control signal output by the control unit, so as to control the pixel unit to display an image; The second detection unit is connected to the second scan test end, the second data test end, the multiple data lines and the multiple scan lines, and is used to receive and transmit a second test scan signal from the second scan test end and receive and transmit a second test data signal from the second data test end to the pixel unit according to the control signal, so as to control the pixel unit to display an image.

14. A fault detection method, applied to a fault detection circuit, the fault detection circuit comprising a first detection unit, a second detection unit and a control unit, the control unit being connected to the first detection unit and the second detection unit, the first detection unit being used to perform short circuit or open circuit detection on the pixel units in the display panel under the control of the control unit, if at least one of the pixel units displays abnormally and is determined to be a first abnormal pixel unit, the control unit controls the second detection unit to re-execute the detection, if the second detection unit detects that the first abnormal pixel unit displays normally, it indicates that the first detection unit is faulty, if the second detection unit detects that the first abnormal pixel unit displays abnormally, it indicates that the first abnormal pixel unit is faulty; in, include: Controlling the first detection unit to perform short circuit or open circuit detection on the pixel units in the display panel, and if all the pixel units display normally, it indicates that the pixel units are not faulty; If the first detection unit detects that at least one of the pixel units displays abnormality, it is determined to be a first abnormal pixel unit, and the second detection unit is controlled to re-detect; If the second detection unit detects that the first abnormal pixel unit displays normally, it indicates that the first detection unit fails; If the second detection unit detects that the first abnormal pixel unit displays abnormally, it indicates that the first abnormal pixel unit fails.

15. The fault detection method according to claim 14, wherein: "Control the second detection unit to re-detect" includes: control the second detection unit to re-detect the pixel units in the display area; "If the second detection unit detects that the first abnormal pixel unit displays normally, it indicates that the first detection unit is faulty" includes: if the second detection unit detects that all pixel units display normally, it indicates that the first abnormal pixel unit is not faulty, and the first detection unit is faulty.

16. The fault detection method according to claim 14, wherein: If a pixel unit that displays abnormality when the second detection unit performs detection is determined to be a second abnormal pixel unit, when the first abnormal pixel unit is different from the second abnormal pixel unit detected by the second detection unit, it indicates that the first detection unit and the second abnormal pixel unit are faulty.

Images