Thin-film transistor, and array substrate and preparation method therefor

Abstract

A thin-film transistor comprises a first electrode (231), a second electrode (232), an active layer (230) and a gate electrode (233), which are arranged on a substrate (100), wherein the first electrode (231) is located on the side of the active layer (230) close to the substrate (100); a first insulating layer (101) is provided between the first electrode (231) and the active layer (230), and the first insulating layer (101) is provided with a first via hole (K1); the active layer (230) is electrically connected to the first electrode (231) by means of the first via hole (K1); a second insulating layer (102) is provided between the gate electrode (233) and the active layer (230); an orthographic projection of the gate electrode (233) on the substrate (100) at least partially overlaps with an orthographic projection of the first via hole (K1) on the substrate (100); a surface of the side of the gate electrode (233) close to the substrate (100) is a first surface (2331), and a surface of the side of the gate electrode (233) away from the substrate (100) is a second surface (2332); and the flatness of the first surface (2331) is different from that of the second surface (2332).

Description

Thin film transistor, array substrate and manufacturing method thereof Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a thin film transistor, an array substrate, and a preparation method thereof. Background Art

[0002] In recent years, with the development of augmented reality (AR) and virtual reality (VR) technologies, the demand for ultra-high-definition display technology has continued to increase. Due to the ultra-high pixel density (PPI) required for AR / VR display technology, the aperture ratio of the display area has dropped significantly, and backlight power consumption has increased significantly.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a thin film transistor, an array substrate, and a method for manufacturing the same.

[0006] In one aspect, an embodiment of the present disclosure provides a thin-film transistor, comprising: a first electrode, a second electrode, an active layer, and a gate electrode disposed on a substrate. The active layer is electrically connected to the first electrode and the second electrode; the gate electrode is located on a side of the active layer away from the substrate; the first electrode is located on a side of the active layer closer to the substrate; a first insulating layer is disposed between the first electrode and the active layer; the first insulating layer is provided with a first via hole; the active layer is electrically connected to the first electrode via the first via hole; the orthographic projection of the active layer on the substrate overlaps the orthographic projection of the first via hole on the substrate; a second insulating layer is disposed between the gate electrode and the active layer; the orthographic projection of the gate electrode on the substrate at least partially overlaps the orthographic projection of the first via hole on the substrate; the surface of the gate electrode closer to the substrate is a first surface; the surface of the gate electrode farther from the substrate is a second surface; the first and second surfaces have different flatnesses.

[0007] In some exemplary embodiments, the second surface of the gate is a flat surface, and vertical distances between the first electrode and the second electrode and the substrate are different.

[0008] In some exemplary embodiments, the active layer includes a channel region, the orthographic projection of the channel region onto the substrate being located within the orthographic projection of the gate onto the substrate. The channel region includes a first channel portion and a second channel portion connected to each other, the orthographic projection of the first channel portion onto the substrate at least partially overlapping with the orthographic projection of the sidewall of the first via onto the substrate. The second channel portion is located on a surface of the first insulating layer facing away from the substrate and does not overlap with the orthographic projection of the first via onto the substrate.

[0009] In some exemplary embodiments, in a plane perpendicular to the substrate and parallel to an extension direction of the active layer, an angle between the first channel portion and the second channel portion ranges from 90 degrees to 160 degrees.

[0010] In some exemplary embodiments, a ratio of the lengths of the second channel portion to the first channel portion is greater than or equal to 1, and a ratio of the thicknesses of the second channel portion to the first channel portion is greater than or equal to 1.

[0011] In some exemplary embodiments, the length of the first channel portion is greater than 0 and less than or equal to 5 micrometers, and the length of the second channel portion is greater than 0 and less than or equal to 5 micrometers.

[0012] In some exemplary embodiments, the second electrode is located on a side of the active layer close to the substrate, and the active layer is directly connected to the second electrode.

[0013] In some exemplary embodiments, the active layer, the second insulating layer, and the gate are sequentially disposed in the first via hole.

[0014] In some exemplary embodiments, a planar layer is disposed between the second insulating layer and the gate, and an orthographic projection of the planar layer on the substrate at least covers an orthographic projection of the first via hole on the substrate.

[0015] In some exemplary embodiments, the orthographic projection of the planar layer on the substrate covers the orthographic projection of the gate on the substrate, and the second surface of the gate is a planar surface.

[0016] In some exemplary embodiments, the orthographic projection of the second insulating layer on the substrate at least covers the orthographic projection of the first via hole and the gate on the substrate.

[0017] In some exemplary embodiments, the second insulating layer includes: a plurality of stacked inorganic film layers, wherein the plurality of inorganic film layers satisfy at least one of the following: a dielectric constant of at least one inorganic film layer is greater than or equal to 7, and a thickness of each inorganic film layer is greater than or equal to 50 nanometers.

[0018] On the other hand, an embodiment of the present disclosure provides an array substrate, comprising: a substrate and at least one thin film transistor as described above, at least one data line, at least one gate line and at least one pixel electrode arranged on the substrate; the gate of the thin film transistor is electrically connected to the gate line, the first electrode of the thin film transistor is electrically connected to the data line, and the second electrode of the thin film transistor is electrically connected to the pixel electrode.

[0019] In some exemplary embodiments, the first electrode of the thin film transistor and the data line are an integral structure, the gate of the thin film transistor and the gate line are an integral structure, and the second electrode of the thin film transistor and the pixel electrode are an integral structure.

[0020] In some example embodiments, an orthographic projection of the active layer of the thin film transistor on the substrate partially overlaps an orthographic projection of at least one of the data line and the gate line on the substrate.

[0021] In some exemplary embodiments, the substrate includes a display area, the at least one data line and the at least one gate line intersect in the display area to form a plurality of sub-pixel areas, the sub-pixel area includes an opening area for display and a non-opening area located on at least one side of the opening area, the pixel electrode is located at least in the opening area; the thin film transistor, the data line and the gate line are located in the non-opening area.

[0022] In some exemplary embodiments, a second insulating layer is disposed between the gate electrode of the thin film transistor and the active layer, a planarization layer is disposed between the second insulating layer and the gate electrode, and the planarization layer does not overlap with the opening region.

[0023] In some exemplary embodiments, the array substrate further includes: a third insulating layer and a common electrode located on a side of the gate line away from the substrate, the common electrode being located at least within the opening area, and an orthographic projection of the common electrode on the substrate at least partially overlapping with an orthographic projection of the pixel electrode on the substrate.

[0024] In some exemplary embodiments, the array substrate further includes: a fourth insulating layer located on a side of the third insulating layer away from the substrate, wherein the fourth insulating layer does not overlap with the opening region.

[0025] On the other hand, an embodiment of the present disclosure provides a method for preparing an array substrate, comprising: forming a first conductive layer on a substrate, the first conductive layer comprising: a first electrode of at least one thin film transistor; forming a first insulating layer on the first conductive layer, the first insulating layer having a first via hole to expose at least a portion of the surface of the first electrode; forming a second conductive layer and a semiconductor layer on the first insulating layer, the semiconductor layer comprising: an active layer of the thin film transistor, the active layer being electrically connected to the first electrode through the first via hole, the orthographic projection of the active layer on the substrate covering the orthographic projection of the first via hole on the substrate, the second conductive layer comprising at least: a second electrode of the thin film transistor; forming a second insulating layer; forming a third conductive layer on the second insulating layer, the third conductive layer comprising at least: a gate of the thin film transistor, the surface of the gate on the side close to the substrate being a first surface, the surface of the gate on the side away from the substrate being a second surface, and the flatness of the first surface and the second surface being different.

[0026] In some exemplary embodiments, the first conductive layer further includes: at least one data line, and the first electrode of the at least one thin film transistor is an integral structure with the connected data line; the second conductive layer further includes: at least one pixel circuit, and the second electrode of the at least one thin film transistor is an integral structure with the connected pixel circuit; the third conductive layer further includes: at least one gate line, and the gate of the at least one thin film transistor is an integral structure with the connected gate line.

[0027] In some exemplary embodiments, the manufacturing method further includes: coating a flat film on the substrate after forming the second insulating layer, patterning the flat film to form a flat layer; or coating a flat film on the substrate after forming the second insulating layer, forming a third conductive layer on the flat film, and etching the flat film using the third conductive layer as a hard mask to form a flat layer. The flat layer's orthographic projection on the substrate covers the orthographic projection of the first via on the substrate.

[0028] In some exemplary embodiments, forming the second insulating layer includes: sequentially depositing a plurality of inorganic film layers on the substrate after forming the semiconductor layer to form the second insulating layer; or sequentially depositing a plurality of inorganic film layers on the substrate after forming the semiconductor layer, and after forming the third conductive layer, etching at least one of the plurality of inorganic film layers using the third conductive layer as a hard mask to form the second insulating layer. The plurality of inorganic film layers satisfy at least one of the following requirements: at least one of the inorganic film layers has a dielectric constant greater than or equal to 7, and each inorganic film layer has a thickness greater than or equal to 50 nanometers.

[0029] In some exemplary embodiments, the above-mentioned preparation method further includes: after forming the third conductive layer, sequentially forming a third insulating layer and a fourth conductive layer, or sequentially forming the third insulating layer, the fourth insulating layer, and the fourth conductive layer. The fourth conductive layer includes at least a common electrode; the third insulating layer is an inorganic insulating layer, and the fourth insulating layer is an organic insulating layer. The substrate includes a display area, wherein at least one data line and at least one gate line provided in the display area intersect to form a plurality of sub-pixel regions, each of which includes an opening region for display and a non-opening region located at least to one side of the opening region; and the fourth insulating layer does not overlap with the opening region.

[0030] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0031] Summary of the Figures

[0032] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0033] FIG1 is a schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0034] FIG2 is a partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0035] FIG3 is a partial plan view of a display area of ​​an array substrate according to at least one embodiment of the present disclosure;

[0036] FIG4 is a schematic partial cross-sectional view along the QQ' direction in FIG3;

[0037] FIG5A is a schematic plan view of the array substrate after the first conductive layer is formed in FIG3 ;

[0038] FIG5B is a schematic plan view of the array substrate after the first insulating layer is formed in FIG3 ;

[0039] FIG5C is a schematic plan view of the array substrate after the second conductive layer is formed in FIG3 ;

[0040] FIG5D is a schematic plan view of the array substrate after the semiconductor layer is formed in FIG3 ;

[0041] FIG6 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0042] FIG7 is another partial plan view of the display area of ​​the array substrate according to at least one embodiment of the present disclosure;

[0043] FIG8 is a schematic partial cross-sectional view along the PP' direction in FIG7;

[0044] FIG9A is a plan view of the array substrate after the second conductive layer is formed in FIG7 ;

[0045] FIG9B is a schematic plan view of the array substrate after the semiconductor layer is formed in FIG7 ;

[0046] FIG10 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0047] FIG11A is another partial plan view of the display area of ​​the array substrate according to at least one embodiment of the present disclosure;

[0048] FIG11B is a plan view of the flat layer and the film layer on the side of the flat layer close to the substrate in FIG11A;

[0049] FIG11C is a plan view of the array substrate after the semiconductor layer is formed in FIG11A ;

[0050] FIG12 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0051] FIG13 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0052] FIG14 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0053] FIG15 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0054] FIG16A is another partial plan view of the display area of ​​the array substrate according to at least one embodiment of the present disclosure;

[0055] FIG16B is a plan view of the array substrate after the semiconductor layer is formed in FIG16A;

[0056] FIG16C is a plan view of the array substrate after the second conductive layer is formed in FIG16A;

[0057] FIG17 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0058] FIG18 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0059] FIG19 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0060] FIG20 is another partial cross-sectional schematic diagram of the array substrate according to at least one embodiment of the present disclosure;

[0061] FIG. 21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0062] Details

[0063] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0064] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of various components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0065] In the present disclosure, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. In the present disclosure, "plurality" refers to a number of two or more.

[0066] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0067] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0068] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0069] In this disclosure, to distinguish the two electrodes of a transistor other than the gate electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode. The first electrode can be a source electrode or a drain electrode, and the second electrode can be a drain electrode or a source electrode. In addition, the gate electrode of the transistor is referred to as the control electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0070] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0071] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0072] The terms “approximately” and “substantially” in the present disclosure do not strictly define the limits and allow for errors within the range of process and measurement errors.

[0073] In this disclosure, flatness can refer to surface roughness observed at a macroscopic scale, such as the surface roughness observable with the naked eye or an optical microscope; it can also refer to the surface roughness and flatness of a corresponding cross-section observed at a microscopic scale using microscopic morphology characterization methods and instruments, such as a scanning electron microscope (SEM) or an atomic force microscope (AFM). A flat surface means a surface without noticeable undulations at the corresponding scale.

[0074] In some implementations, vertical thin film transistors (VTs) are significantly smaller than etch-stopper layer (ESL) and back-channel etch (BCE) TFTs, demonstrating their potential for use in ultra-high PPI display products. VTs have high carrier mobility and can be used in devices with higher frequencies and lower operating bias voltages.

[0075] This embodiment provides a thin film transistor, an array substrate, a method for manufacturing the same, and a display device, which can improve the performance of vertical thin film transistors, thereby reducing the driving power consumption of the array substrate, and can also increase the aperture ratio of the array substrate and simplify the manufacturing process.

[0076] This embodiment provides a thin film transistor, comprising: a first electrode, a second electrode, an active layer, and a gate electrode, disposed on a substrate. The active layer is electrically connected to the first electrode and the second electrode; the gate electrode is located on a side of the active layer away from the substrate; the first electrode is located on a side of the active layer closer to the substrate; a first insulating layer is disposed between the first electrode and the active layer; a first via hole is formed in the first insulating layer; the active layer is electrically connected to the first electrode via the first via hole; the orthographic projection of the active layer on the substrate overlaps the orthographic projection of the first via hole on the substrate; a second insulating layer is disposed between the gate electrode and the active layer; the orthographic projection of the gate electrode on the substrate at least partially overlaps the orthographic projection of the first via hole on the substrate; the surface of the gate electrode on the side closer to the substrate is a first surface; the surface of the gate electrode on the side farther from the substrate is a second surface; the first surface and the second surface have different flatnesses.

[0077] The thin film transistor provided in this embodiment can ensure the flatness of the film layer, reduce the process difficulty of the preparation process, and improve the performance of the vertical thin film transistor.

[0078] In some exemplary embodiments, the second surface of the gate may be a flat surface, and the vertical distances between the first and second electrodes of the thin film transistor and the substrate may be different. For example, the gate may be filled in the first via hole, and at a macroscopic scale, the flatness of the first and second surfaces of the gate may be different, and the second surface may be a flat surface.

[0079] In some exemplary embodiments, the second electrode of the thin film transistor can be located on the side of the active layer closest to the substrate, and the active layer of the thin film transistor and the second electrode can be directly overlapped. In this example, by directly overlapping the active layer and the second electrode of the thin film transistor, the hole opening process can be reduced and the manufacturing process can be simplified. However, this embodiment is not limited to this. In other examples, the second electrode and the active layer of the thin film transistor can be an integrated structure.

[0080] In some exemplary embodiments, a flat layer may be provided between the second insulating layer and the gate, and the orthographic projection of the flat layer on the substrate may at least cover the orthographic projection of the first via on the substrate. In some examples, the orthographic projection of the flat layer on the substrate may cover the orthographic projection of the gate on the substrate, and the second surface of the gate may be a flat surface. In this example, a flat layer is provided on the side of the gate close to the substrate, and the flat layer may be filled in the first via. The first surface of the gate contacts the flat layer. Due to the influence of the etching process, the flatness of the first surface and the second surface of the gate at the microscopic scale is different. By providing a flat layer in this example, the distance between the gate and the first electrode of the thin film transistor can be ensured to improve the voltage resistance of the thin film transistor.

[0081] In some exemplary embodiments, the second insulating layer may include: a plurality of stacked inorganic film layers. The plurality of inorganic film layers satisfy at least one of the following: the dielectric constant (K value) of at least one inorganic film layer may be greater than or equal to 7, and the thickness of each inorganic film layer may be greater than or equal to 50 nanometers. In some examples, the K value of at least one of the plurality of inorganic film layers is greater than or equal to 7, and the thickness of each inorganic film layer is greater than or equal to 50 nanometers. For example, the K value of one of the plurality of inorganic film layers may be greater than or equal to 10. For example, the thickness of at least one inorganic film layer may be greater than or equal to 50 nanometers and less than or equal to 300 nanometers. This example ensures the on and off characteristics of the thin film transistor while ensuring the insulation effect by setting the second insulating layer to a plurality of stacked inorganic film layers and limiting the K value and thickness of the inorganic film layer.

[0082] In some examples, the multiple inorganic film layers include at least two of the following: an oxide insulating layer, a silicon nitride film layer, and an HKL film layer. For example, the K value of the HKL film layer can be greater than or equal to 10. In some examples, the second insulating layer may include: an oxide insulating layer and a silicon nitride film layer sequentially arranged in a direction away from the substrate; or, an oxide insulating layer, an HKL film layer, and a silicon nitride film layer sequentially arranged in a direction away from the substrate; or, an oxide insulating layer and an HKL film layer sequentially arranged in a direction away from the substrate. In this example, by setting an oxide insulating layer, the via coverage can be improved; by setting a silicon nitride film layer, the via coverage can be improved, and the electrostatic discharge and short circuit problems caused by cracking of the second insulating layer can be avoided, and the dielectric properties of the second insulating layer can be improved, and the resistance to electrical breakdown can be improved; by setting an HKL film layer, the dielectric properties of the second insulating layer can be improved, the leakage current can be reduced, and the resistance to electrical breakdown can be improved.

[0083] This embodiment further provides an array substrate, comprising: a substrate, and at least one thin film transistor, at least one data line, at least one gate line, and at least one pixel electrode disposed on the substrate; the gate electrode of the thin film transistor is electrically connected to the gate line, the first electrode of the thin film transistor is electrically connected to the data line, and the second electrode of the thin film transistor is electrically connected to the pixel electrode. The structure of the thin film transistor in this embodiment can be as described above.

[0084] The array substrate provided in this embodiment can reduce the process difficulty of the manufacturing process by ensuring the flatness of the film layer, improve the performance of the vertical thin film transistor, and further reduce the driving power consumption of the array substrate.

[0085] In some exemplary embodiments, the orthographic projection of the thin film transistor's active layer on the substrate may at least partially overlap with the orthographic projection of the data line on the substrate. For example, the orthographic projection of the thin film transistor's active layer on the substrate may be located within the orthographic projection of the data line on the substrate. In this example, by forming the thin film transistor at the location of the data line, no additional space is occupied, thereby increasing the aperture ratio of the display area.

[0086] In some exemplary embodiments, the orthographic projection of the active layer of the thin film transistor on the substrate may at least partially overlap with the orthographic projection of the gate line on the substrate. For example, the orthographic projection of the active layer of the thin film transistor on the substrate may be located within the orthographic projection of the gate line on the substrate. In this example, by forming the thin film transistor at the gate line location, no additional space is occupied, thereby increasing the aperture ratio of the display area.

[0087] In some exemplary embodiments, the display device including the array substrate of this embodiment may be a liquid crystal display device. The liquid crystal display device may include the array substrate of this embodiment, an opposing substrate, and a liquid crystal layer disposed between the array substrate and the opposing substrate. In some examples, the display device may be an advanced super-dimensional field switch (ADS) type display device with a horizontal electric field, or a high-aperture ratio advanced super-dimensional field switch (HADS) type display device, or a vertical electric field (VA) type display device. The pixel electrodes and common electrodes included in the array substrate may be configured to generate an electric field that deflects the liquid crystal molecules in the liquid crystal layer. For example, the opposing substrate may include a base substrate, a color filter layer, and a black matrix. However, this embodiment is not limited to this.

[0088] The solution of this embodiment is illustrated below through multiple examples.

[0089] Figure 1 is a schematic diagram of an array substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1 , the array substrate may include a display area AA and a border area BB located around the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. For example, the first border area B1 may include the bottom border of the array substrate, and the second border area B2 may include the top, left, and right borders of the array substrate.

[0090] In some examples, as shown in FIG1 , the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate. The plurality of gate lines GL may extend along a first direction X and be sequentially arranged along a second direction Y different from the first direction X. The plurality of data lines DL may extend along the second direction Y and be sequentially arranged along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located in different film layers; for example, the plurality of data lines DL may be located on a side of the plurality of gate lines GL closer to the substrate.

[0091] In some examples, as shown in FIG1 , a plurality of data lines DL and a plurality of gate lines GL may intersect to form a plurality of sub-pixel areas. The area defined by the intersection of adjacent data lines DL and adjacent gate lines GL may be a sub-pixel area. A sub-pixel may be provided in a corresponding sub-pixel area. The sub-pixel area may include an opening area and a non-opening area surrounding the opening area. The non-opening area may be an area blocked by the black matrix of the opposing substrate of the array substrate, and the opening area may be an area not blocked by the black matrix of the opposing substrate. Adjacent gate lines GL and data lines DL may both be located within the non-opening area. The array substrate of this embodiment may be used to implement a display function, and the opening area of ​​each sub-pixel area may be configured for display. The non-opening area surrounds the opening area and does not display. However, this embodiment is not limited to this. In some examples, the array substrate may be used to implement other functions.

[0092] In some examples, the display area AA may include: a plurality of pixel units arranged on a substrate. At least one pixel unit may include: three sub-pixels (for example, a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence along the first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged in sequence in the order of blue sub-pixels, green sub-pixels, and red sub-pixels. As shown in FIG1 , at least one sub-pixel may include: a pixel electrode 21 and a common electrode (not shown in FIG1 ), the pixel electrode 21 and the common electrode may be located at least within the opening area, and the pixel electrode 21 and the common electrode of the sub-pixel may overlap in their orthographic projection on the substrate. The common electrodes of the plurality of sub-pixels in the display area AA may be an integrated structure. For example, the common electrode may be located on the side of the pixel electrode 21 away from the substrate. The sub-pixel may further include: a thin film transistor 23. The thin film transistor 23 may include a gate, a first electrode, and a second electrode; the gate of the thin film transistor 23 may be electrically connected to the gate line GL, the first electrode of the thin film transistor 23 may be electrically connected to the data line DL, and the second electrode of the thin film transistor 23 may be electrically connected to the pixel electrode 21 of a sub-pixel. The thin film transistor 23 may be configured to provide a data signal transmitted by the data line DL to the pixel electrode 21 of the sub-pixel under the control of the gate line GL. In some examples, the thin film transistor 23 may be an oxide thin film transistor or a low-temperature polysilicon thin film transistor. The following examples are described using an oxide thin film transistor as an example. However, this embodiment is not limited to this.

[0093] Figure 2 is a partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2, the array substrate may include, in a direction perpendicular to the array substrate, a substrate 100, a first conductive layer 111, a first insulating layer 101, a second conductive layer 112, a semiconductor layer 110, a second insulating layer 102, a third conductive layer 113, a third insulating layer 103, and a fourth conductive layer 114, sequentially disposed on the substrate 100. The first insulating layer 101 and the third insulating layer 103 may also be referred to as interlayer dielectric (ILD) layers, and the second insulating layer 102 may also be referred to as a gate insulation (GI) layer. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may all be inorganic insulating layers.

[0094] In some examples, as shown in FIG2 , the first conductive layer 111 may include a first electrode 231 of a thin-film transistor and a data line DL. The first electrode 231 and the data line DL may be integrally formed. The semiconductor layer 110 may include an active layer 230 of the thin-film transistor located in the display area AA. The first insulating layer 101 may be provided with a first via K1, through which the active layer 230 of the thin-film transistor may be electrically connected to the first electrode 231 of the thin-film transistor. The orthographic projection of the active layer 230 of the thin-film transistor on the substrate may overlap the orthographic projection of the first via K1 on the substrate. The second conductive layer 112 may include a second electrode 232 of the thin-film transistor located in the display area AA and a pixel electrode 21. The second electrode 232 of the thin-film transistor and the pixel circuit 21 may be integrally formed and directly overlap the active layer 230. The third conductive layer 113 may include a gate electrode 233 and a gate line GL of the thin-film transistor located in the display area AA, as well as a first trace 31 located in the frame area BB. The gate electrode 233 of the thin-film transistor and the gate line GL may be integrally formed. The fourth conductive layer 114 may include: a common electrode 22 located in the display area AA, and a second trace 32 located in the frame area BB. The orthographic projection of the common electrode 22 on the substrate may overlap with the orthographic projection of the pixel electrode 21 on the substrate. For example, the common electrode 22 may have multiple slits, and the multiple slits may pass through the common electrode 22. The extension directions of the multiple slits may be consistent, for example, extending along the second direction Y. However, this embodiment is not limited to this. The common electrode may have slits in two different directions to form a dual-domain structure, or may have slits in multiple different directions to form a multi-domain structure. In other examples, the common electrode may be a sheet-like electrode structure without slits.

[0095] Figure 3 is a partial plan view of the display area of ​​the array substrate of at least one embodiment of the present disclosure. Figure 4 is a schematic diagram of a partial cross-section taken along the Q-Q' direction in Figure 3. Figure 5A is a schematic plan view of the array substrate after the first conductive layer is formed in Figure 3. Figure 5B is a schematic plan view of the array substrate after the first insulating layer is formed in Figure 3. Figure 5C is a schematic plan view of the array substrate after the second conductive layer is formed in Figure 3. Figure 5D is a schematic plan view of the array substrate after the semiconductor layer is formed in Figure 3.

[0096] The preparation process of the array substrate of this example is exemplarily described below with reference to Figures 2 to 5D. The "patterning process" mentioned in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in this disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0097] As used in this specification, "A and B are provided in the same layer" means that A and B are formed simultaneously using the same material through the same patterning process. The "thickness" of a film layer refers to the dimension of the film layer perpendicular to the display substrate. "The orthographic projection of B is within the orthographic projection of A" or "The orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0098] The preparation process of the array substrate of this example may include the following steps.

[0099] (1-1) Providing a substrate. In some examples, the substrate can be a transparent substrate. For example, the substrate can be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate can include, but is not limited to, one or more of glass and quartz; the material of the flexible substrate can include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. However, this embodiment is not limited to this.

[0100] (1-2) Forming a first conductive layer. In some examples, a first conductive film is deposited on a substrate, and the first conductive film is patterned by a patterning process to form a first conductive layer disposed on the substrate.

[0101] In some examples, as shown in FIG5A , the first conductive layer of the display region may include a data line DL and a first electrode 231 of a thin film transistor. The data line DL may be a strip-shaped structure extending along the second direction Y. The data line DL and the first electrode 231 of the thin film transistor may be an integrated structure. For example, a portion of the data line DL may serve as the first electrode of the thin film transistor.

[0102] In some examples, the first conductive layer can be made of a metal material, such as any one or more of titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), or alloy materials of the above metals, such as molybdenum alloy (MTD), aluminum neodymium alloy (AlNd), molybdenum titanium alloy (MoTi) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Al / Mo, Mo / Cu / Mo, MTD / Cu / MTD, MoTi / Cu / MoTi, etc.; or, the first conductive layer can be made of a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0103] (1-3) Forming a first insulating layer. In some examples, a first insulating film is deposited on the substrate forming the aforementioned structure, and the first insulating film is patterned by a patterning process to form the first insulating layer.

[0104] In some examples, as shown in FIG5B , the first insulating layer may have a first via K1 in the display area. The first insulating layer within the first via K1 may be removed, exposing a portion of the surface of the data line DL in the first conductive layer. The orthographic projection of the first via K1 on the substrate may be within the orthographic projection of the data line DL on the substrate. The first via K1 may be configured to achieve overlap between the first electrode 231 of the thin-film transistor located in the first conductive layer and the active layer 230 located in the semiconductor layer. For example, the sidewalls of the first via K1 may be smooth, and the surface of the first electrode of the thin-film transistor exposed at the bottom of the first via K1 may be smooth, thereby ensuring a good overlap between the first electrode 231 of the thin-film transistor and the active layer 230. For example, the slope angle of the sidewalls of the first via K1 may be less than 80 degrees. The slope angle of the sidewalls of the first via K1 refers to the angle between the plane of the sidewalls and the horizontal plane of the substrate 100.

[0105] In some examples, the thickness of the first insulating layer can be greater than 0.5 microns. The first insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), aluminum oxide (Al2O3), and hafnium dioxide (HfO2), and can be a single layer, a multilayer, or a composite layer. However, this embodiment is not limited to this.

[0106] The provision of the first insulating layer in this example can control the length of the channel region of the active layer, which is beneficial to increasing the startup current of the thin film transistor and reducing the area of ​​the thin film transistor to increase the aperture ratio of the display area.

[0107] (1-4) Forming a second conductive layer. In some examples, a second conductive film is deposited on the substrate forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second conductive layer.

[0108] In some examples, as shown in FIG5C , the second conductive layer of the display area may include: a pixel electrode 21 and a second electrode 232 of a thin film transistor. The second electrode 232 of the thin film transistor and the pixel electrode 21 may be an integral structure. The orthographic projection of the second electrode 232 of the thin film transistor on the substrate may overlap with the orthographic projection of the data line DL on the substrate, and the pixel electrode 21 may be located at least within the opening area OP of the display area. The orthographic projections of the pixel electrode 21 and the second electrode 232 of the thin film transistor on the substrate do not overlap with the orthographic projection of the first via K1 on the substrate. The vertical distances between the second electrode 232 of the thin film transistor and the substrate 100 are different from those between the first electrode 231. For example, the vertical distance between the second electrode 232 of the thin film transistor and the substrate 100 may be greater than the vertical distance between the first electrode 231 and the substrate 100.

[0109] In some examples, the second conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0110] (1-5) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on the substrate forming the aforementioned structure, and the semiconductor thin film is patterned by a patterning process to form a semiconductor layer.

[0111] In some examples, as shown in FIG5D , the semiconductor layer in the display area may include an active layer 230 of a thin-film transistor. The orthographic projection of the active layer 230 on the substrate may at least partially overlap with the orthographic projection of the data line DL on the substrate. For example, the orthographic projection of the active layer 230 on the substrate may be located within the orthographic projection of the data line DL on the substrate. The active layer 230 may cover at least a portion of the second electrode 232 of the thin-film transistor, for example, the overlapping portion of the second electrode 232 of the thin-film transistor and the data line DL, thereby directly overlapping the second electrode 232 of the thin-film transistor. The active layer 230 may extend along a second direction Y. The orthographic projection of the active layer 230 on the substrate may overlap the orthographic projection of the first via K1 on the substrate. The active layer 230 may be electrically connected to the first electrode 231 of the thin-film transistor through the first via K1. By directly overlapping the second electrode 232 of the thin-film transistor and the active layer 230 in this example, the hole-forming process can be reduced and the manufacturing steps can be simplified. By disposing the active layer 230 on the data line DL, the opening area space occupied by the thin film transistor can be reduced, which is beneficial to improving the aperture ratio of the display area.

[0112] In some examples, the semiconductor film may be a transparent semiconductor film. The material of the semiconductor layer may include an oxide semiconductor material. For example, the semiconductor layer may be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO). That is, the embodiments of the present disclosure are applicable to transistors manufactured based on oxide technology.

[0113] In this example, the second electrode of the thin film transistor is provided on the data line to achieve overlap between the active layer and the second electrode of the thin film transistor. However, this embodiment is not limited to this. In other examples, the second electrode of the thin film transistor and the integrated structure of the pixel electrode can both be located in the opening area, and the active layer of the semiconductor layer is provided to extend into the opening area to achieve electrical connection between the active layer and the integrated structure of the second electrode of the thin film transistor and the pixel electrode.

[0114] (1-6) Forming a second insulating layer and a third conductive layer. In some examples, a second insulating film and a third conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the third conductive film is patterned by a patterning process to form a second insulating layer and a third conductive layer disposed on the second insulating layer, as shown in FIG3 .

[0115] In some examples, the second insulating layer may be made of any one or more of silicon oxide (SiOx, x>0), aluminum oxide (Al2O3), and hafnium dioxide (HfO2), and may be a single layer, multiple layers, or a composite layer. However, this embodiment is not limited thereto.

[0116] In some examples, as shown in Figures 2 to 4, the third conductive layer may include at least: a gate 232 and a gate line GL of a thin film transistor located in the display area, and a first trace 31 located in the peripheral area. The gate line GL may be a strip-shaped structure extending along the first direction X. The gate 233 of the thin film transistor in the display area and the gate line GL may be an interconnected integral structure. For example, a portion of the gate line GL may serve as the gate 233 of the thin film transistor. The orthographic projection of the integrated structure of the gate line GL and the gate 233 of the thin film transistor on the substrate may overlap the orthographic projection of the first via K1 on the substrate.

[0117] In some examples, after forming the third conductive layer, the semiconductor layer not covered by the third conductive layer may be subjected to a conductive treatment. For example, the conductive treatment may include plasma treatment or doping treatment using gases such as hydrogen (H), ammonia (NH3), helium (He), and argon (Ar). This embodiment is not limited to this.

[0118] In some examples, the active layer 230 of the thin film transistor can be defined into a channel region 2300, a first region 2301, and a second region 2302 through a conductorization process. The conductivity of the first region 2301 and the second region 2302 can be higher than the conductivity of the channel region 2300. The channel region 2300 can be connected between the first region 2301 and the second region 2302, and the first region 2301 of the active layer 230 can be electrically connected to the integrated structure of the pixel electrode 21 and the second electrode 232 of the thin film transistor. The integrated structure of the pixel electrode 21 and the second electrode 232 of the thin film transistor can, for example, contact the second region 2302 of the active layer 230 without contacting the channel region. The first region 2301 of the active layer 230 can be electrically connected to the integrated structure of the first electrode 231 of the thin film transistor and the data line DL.

[0119] In some examples, as shown in Figures 3 and 4, the channel region 2300 of the active layer 230 may include a first channel portion 2300a and a second channel portion 2300b that are connected to each other. The first channel portion 2300a may be disposed around the sidewall of the first via hole K1, and the second channel portion 2300b may be disposed around the outside of the first channel portion 2300a and located on a horizontal surface of the first insulating layer 101 away from the substrate 100. The first channel portion 2300a is connected to the first region 2301 of the active layer 230, and the second channel portion 2300b is connected to the second region 2302.

[0120] In some examples, as shown in FIG3 and FIG4 , a first angle a may be formed between the first channel portion 2300a and the second channel portion 2300b in a plane perpendicular to the substrate plane and parallel to the extension direction of the active layer 230. The first angle a may range from 90 degrees to 160 degrees. For example, the first angle a may be approximately 120 degrees, or approximately 100 degrees, or approximately 135 degrees.

[0121] In some examples, the first channel portion 2300a may have a first length L1 in the extending direction of the channel region 2300. For example, the first length L1 may be approximately the length of the sidewall of the first via hole K1. The first length of the first channel portion 2300a may refer to the effective length of the first channel portion 2300a. The first length L1 may be greater than 0 and less than or equal to 5 micrometers. For example, the first length L1 may be approximately 0.5 micrometers, or may be approximately 1 micrometer.

[0122] In some examples, the second channel portion 2300b may have a second length d1 in the extending direction of the channel region 2300. For example, the second length d1 may be the distance between the edge of the first via hole K1 and the edge of the gate line GL in the extending direction of the active layer 230. The second length d1 may be greater than 0 and less than or equal to 5 microns. For example, the second length d1 may be greater than 0 and less than or equal to 2 microns. For example, the second length d1 may be approximately 1 micron, or may be approximately 2 microns.

[0123] In some examples, the ratio of the lengths of the second channel portion 2300b to the first channel portion 2300a (i.e., the ratio of d1 to L1) can be greater than or equal to 1. For example, the length of the second channel portion 2300b can be the same as the length of the first channel portion 2300a, or the length of the second channel portion 2300b can be greater than the length of the first channel portion 2300a.

[0124] In some examples, the thickness of the first channel portion 2300a can be the vertical distance between the surface of the first channel portion 2300a away from the sidewall of the first via and the surface close to the sidewall of the first via. The thickness of the second channel portion 2300b can be the vertical distance between the surface of the second channel portion 2300b away from the first insulating layer 101 and the surface close to the first insulating layer 101. In some examples, the thickness of the first channel portion 2300a can be greater than or equal to 1 nanometer (nm) and less than or equal to 200 nm, and the thickness of the second channel portion 2300b can be greater than or equal to 1 nm and less than or equal to 200 nm. In some examples, the ratio of the thickness of the second channel portion 2300b to the first channel portion 2300a can be greater than or equal to 1. For example, the thickness of the second channel portion 2300b can be approximately the same as the thickness of the first channel portion 2300a, or the thickness of the second channel portion 2300b can be greater than the thickness of the first channel portion 2300a.

[0125] In some examples, by controlling the angle between the first channel portion and the second channel portion, the length of the first channel portion and the second channel portion, and the thickness of the first channel portion and the second channel portion, the switching characteristics of the thin film transistor can be guaranteed, and on the basis of ensuring the transistor characteristics, the occupied space of the thin film transistor can be reduced to achieve ultra-high-resolution display technology.

[0126] In some examples, the switching characteristics of the thin film transistor's channel region can be controlled by controlling the second length d1. For example, when the second length d1 is large, the thin film transistor is more likely to maintain switching characteristics, but the startup current Ion is reduced. When the second length d1 is small, the thin film transistor is more likely to experience conductivity issues, but a higher startup current can be achieved. In some examples, the second length can be adjusted based on the characteristics control capability and patterning process capabilities. For example, the second length d1 can be greater than 0 and less than or equal to 2 microns to ensure the switching characteristics of the thin film transistor's channel region.

[0127] In some examples, as shown in FIG4 , the surface of the gate 233 of the thin-film transistor on the side closest to the substrate 100 is a first surface 2331, and the surface of the gate 233 on the side away from the substrate 100 is a second surface 2332. The second surface 2332 of the gate 233 can be a flat surface. The active layer 230, the second insulating layer 102, and the gate 233 can be sequentially disposed within the first via K1. In this example, the gate 233 partially fills the first via K1. On a macroscopic scale, the flatness of the first surface 2331 of the gate 233 is different from the flatness of the second surface 2332. In this example, the gate 233 is used to planarize the first via K1, eliminating the need for a film layer to planarize the first via K1 on the side of the third conductive layer away from the substrate. Furthermore, since no vias are provided in the opening area, no planarization film layer is required, thereby simplifying the process steps and saving costs.

[0128] In some examples, the third conductive layer can be made of a metal material, such as any one or more of titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), or an alloy material of the above metals, such as molybdenum alloy (MTD), aluminum neodymium alloy (AlNd), molybdenum titanium alloy (MoTi) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Al / Mo, Mo / Cu / Mo, MTD / Cu / MTD, MoTi / Cu / MoTi, etc.; or, the first conductive layer can be made of a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0129] (1-7) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate forming the aforementioned structure, and the third insulating film is patterned by a patterning process to form a third insulating layer.

[0130] In some examples, as shown in FIG2 , the third insulating layer may have multiple vias in the frame area BB, such as a second via K2. The third insulating layer 103 within the second via K2 may be removed, exposing a portion of the surface of the first trace 31 located in the third conductive layer. The third insulating layer in the display area does not need to have vias, which helps improve the aperture ratio of the display area.

[0131] In some examples, the third insulating layer may be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), aluminum oxide (Al2O3), and hafnium dioxide (HfO2), and may be a single layer, a multilayer, or a composite layer. However, this embodiment is not limited thereto.

[0132] (1-8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate forming the aforementioned structure, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer.

[0133] In some examples, as shown in FIG2 , the fourth conductive layer may include: a common electrode 22 at least located in the display area AA and a second trace 32 located in the frame area BB. The second trace 32 may be electrically connected to the first trace 31 through a second via K2 provided in the third insulating layer 103. For example, the first trace 31 may be an integral structure with at least one gate line, and the first trace 31 and the second trace 32 may be electrically connected to each other to transmit the scanning signal from the frame area to the display area, thereby achieving transmission and switching of the scanning signal. For another example, by providing vias in the third insulating layer, the second insulating layer, and the first insulating layer in the frame area, the data line located in the first conductive layer and the data connection line located in the fourth conductive layer may be electrically connected, thereby achieving input and switching of data signals. In this example, the signal input and switching are both achieved by providing vias in the frame area, and there is no need to provide vias in the opening area of ​​the display area, which is beneficial to improving the aperture ratio of the display area.

[0134] In some examples, the fourth conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0135] In this example, as shown in Figures 2 and 4, the active layer 230 of the thin film transistor, the second insulating layer 102 and the top gate 233 of the thin film transistor are sequentially arranged in the first via K1, so that the second surface 2332 of the top gate 233 away from the substrate 100 can be a flat surface. There is no need to set a flat layer on the side of the third conductive layer away from the substrate, which can reduce the preparation process and reduce costs.

[0136] During the fabrication of the array substrate in this example, seven patterning processes are performed to form the first conductive layer, first insulating layer, second conductive layer, semiconductor layer, third conductive layer, third insulating layer, and fourth conductive layer, respectively. This reduces the number of masks required during fabrication and helps lower costs. Furthermore, the display area of ​​the array substrate only requires the formation of a first via in the first insulating layer to electrically connect the active layer of the thin-film transistor and the data line, which helps improve the aperture ratio of the array substrate and facilitates the realization of a high-resolution array substrate.

[0137] The structure and fabrication process of the array substrate in the disclosed embodiments are merely exemplary. In some examples, the corresponding structure can be modified and patterning processes can be added or removed based on actual needs. For example, a first insulating film and a second conductive film can be sequentially deposited on a substrate, followed by patterning the second conductive film to form a second conductive layer, and then patterning the first insulating film to form a first insulating layer. However, this embodiment is not limited to this.

[0138] Figure 6 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6, in a direction perpendicular to the array substrate, the array substrate may include: a substrate 100, a first conductive layer 111, a first insulating layer 101, a second conductive layer 112, a semiconductor layer 110, a second insulating layer 102, a third conductive layer 113, a third insulating layer 103, a fourth insulating layer 104, and a fourth conductive layer 114, sequentially disposed on the substrate 100. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers, and the fourth insulating layer 104 may be an organic insulating layer.

[0139] In some examples, as shown in FIG6 , the first conductive layer 111 may include a first electrode 231 of a thin-film transistor and a data line DL located in the non-opening region of the display area AA. The data line DL and the connected first electrode 231 of the thin-film transistor may be an integral structure. The semiconductor layer 110 may include an active layer 230 of the thin-film transistor located in the non-opening region of the display area AA. The first insulating layer 101 may have a first via K1 defined in the non-opening region of the display area AA. The active layer 230 may be electrically connected to the first electrode 231 of the thin-film transistor through the first via K1. The orthographic projection of the active layer 230 on the substrate 100 may overlap the orthographic projection of the first via K1 on the substrate 100. The second conductive layer 112 may include a second electrode 232 of the thin-film transistor and a pixel electrode 21. For example, the second electrode 232 of the thin-film transistor may be located in the non-opening region of the display area AA, and the pixel electrode 21 may be located at least in the opening region OP of the display area AA. The second electrode 232 of the thin-film transistor and the pixel electrode 21 may be an integral structure, directly overlapping the active layer 230 in the non-opening region. The third conductive layer 113 may include at least: a gate electrode 233 and a gate line GL of a thin-film transistor located in the non-opening area of ​​the display area AA, and a first trace 31 located in the frame area BB. The gate electrode 233 and the gate line GL of the thin-film transistor may be integrally formed. The fourth conductive layer 114 may include: a common electrode 22 located in the display area AA, and a second trace 32 located in the frame area BB. The orthographic projection of the fourth insulating layer 104 on the substrate 100 may not overlap with the opening area OP of the display area AA. In other words, the fourth insulating layer 104 within the opening area OP of the display area AA may be removed. The fourth insulating layer 104 in the frame area BB may have a third via K3 defined therein. The fourth insulating layer 104 within the third via K3 may be removed to expose the surface of the third insulating layer 103. The third insulating layer 103 may have a fourth via K4 defined therein in the frame area BB. The third insulating layer 103 within the fourth via K4 may be removed to expose a portion of the surface of the first trace 31. The orthographic projection of the third via K3 on the substrate may overlap the orthographic projection of the fourth via K4 on the substrate. The second trace 32 may be electrically connected to the first trace 31 through the fourth via K4 and the third via K3 .

[0140] In some examples, the fourth insulating layer 104 may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate, but this embodiment is not limited thereto.

[0141] In some examples, as shown in FIG6 , during the preparation process of the array substrate of this example, after forming the third conductive layer 113, a third insulating film can be deposited on the substrate 100 having the aforementioned structure, and a fourth insulating film can be coated (e.g., spin-coated). The fourth insulating film is patterned by a patterning process to form a fourth insulating layer 104. The fourth insulating layer 104 can have a third via K3 in the frame area BB that exposes the surface of the third insulating film, and the fourth insulating layer 104 in the opening area OP of the display area AA can be removed. Subsequently, the third insulating film is patterned by a patterning process to form a third insulating layer 103. The third insulating layer 103 has a fourth via K4 in the frame area BB that exposes a portion of the surface of the third conductive layer 113. The third via K3 and the fourth via K4 are connected, so that the second trace 32 located in the fourth conductive layer is electrically connected to the first trace 31 through the third via K3 and the fourth via K4.

[0142] The array substrate of this example, by providing a fourth insulating layer 104 in the non-opening area of ​​the display region, can reduce crosstalk between the gate line GL's transmission signal and the common electrode 22, thereby reducing the parasitic capacitance between the gate line GL and the common electrode 22. By removing the fourth insulating layer from the opening area OP of the display region AA, the liquid crystal deflection electric field is ensured, thereby enhancing the liquid crystal electric field effect. Furthermore, in the display region AA, only the first via K1 needs to be formed in the first insulating layer 101 to electrically connect the active layer of the thin-film transistor and the data line, which can help improve the aperture ratio of the array substrate and facilitate the realization of a high-resolution array substrate.

[0143] The remaining structures and preparation steps of the array substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be described again here.

[0144] Figure 7 is another partial plan view of the display area of ​​the array substrate according to at least one embodiment of the present disclosure. Figure 8 is a schematic partial cross-sectional view taken along the P-P' direction in Figure 7. Figure 9A is a plan view of the array substrate after forming the second conductive layer in Figure 7. Figure 9B is a schematic plan view of the array substrate after forming the semiconductor layer in Figure 7.

[0145] The following is an exemplary description of the manufacturing process of the array substrate of this example with reference to Figures 7 to 9B . The manufacturing process of the array substrate of this example may include the following steps.

[0146] (2-1) Provide a substrate.

[0147] (2-2) Forming a first conductive layer. In some examples, a first conductive film is deposited on a substrate, and the first conductive film is patterned by a patterning process to form a first conductive layer disposed on the substrate.

[0148] In some examples, as shown in FIG9A , the first conductive layer may include: a data line DL and a first electrode 231 of a thin film transistor. The data line DL and the first electrode 231 of the thin film transistor may be an integrated structure.

[0149] (2-3) Forming a first insulating layer. In some examples, a first insulating film is deposited on the substrate forming the aforementioned structure and patterned using a patterning process to form the first insulating layer. As shown in FIG9A , the first insulating layer has a first via K1 defined in the display area. The orthographic projection of the first via K1 on the substrate can be within the orthographic projection of the data line DL on the substrate.

[0150] (2-4) Forming a second conductive layer. In some examples, a second conductive film is deposited on the substrate forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second conductive layer. As shown in FIG9A , the second conductive layer in the display area may include: a pixel electrode 21 and a second electrode 232 of a thin film transistor. The second electrode 232 of the thin film transistor and the pixel electrode 21 may be an integral structure. The orthographic projection of the integral structure of the second electrode 232 of the thin film transistor and the pixel electrode 21 on the substrate may not overlap with the orthographic projection of the data line DL on the substrate.

[0151] In other examples, a first insulating film and a second conductive film may be sequentially deposited on the substrate, and then the second conductive film may be patterned to form the second conductive layer, and then the first insulating film may be patterned to form the first insulating layer. This embodiment is not limited to this.

[0152] (2-5) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on the substrate forming the aforementioned structure, and the semiconductor thin film is patterned through a patterning process to form a semiconductor layer. In some examples, as shown in FIG9B , the semiconductor layer in the display area may include: an active layer 230 of a thin film transistor. The active layer 230 and the second electrode 232 of the thin film transistor may overlap in their orthographic projection on the substrate, thereby achieving direct overlap between the active layer 230 and the second electrode 232 of the thin film transistor. The active layer 230 may extend along a first direction X, and the orthographic projection of the active layer 230 on the substrate may cover the orthographic projection of the first via K1 on the substrate, thereby electrically connecting to the first electrode 231 of the thin film transistor through the first via K1. In this example, by directly overlapping the second electrode 232 of the thin film transistor with the active layer 230, the hole opening process can be reduced and the preparation steps can be simplified. In other examples, the second electrode of the thin film transistor and the pixel electrode may be disposed within the opening region, and the active layer may extend into the opening region and directly overlap the second electrode of the thin film transistor within the opening region.

[0153] (2-6) Forming a second insulating layer and a third conductive layer. In some examples, a second insulating film and a third conductive film are sequentially deposited on the substrate forming the aforementioned structure. The third conductive film is patterned through a patterning process to form a second insulating layer and a third conductive layer disposed on the second insulating layer. In some examples, as shown in FIG7 , the third conductive layer may include at least: a gate electrode 233 of a thin film transistor located in the display area and a gate line GL. The gate line GL may be a strip-shaped structure extending along the first direction X. The gate line GL and the gate electrode 233 of the thin film transistor to which it is connected may be an integral structure. The orthographic projection of the integral structure of the gate line GL and the gate electrode 233 of the thin film transistor on the substrate may overlap the orthographic projection of the first via K1 on the substrate and at least partially overlap the orthographic projection of the second electrode 232 of the thin film transistor on the substrate, for example, overlapping the orthographic projection of the second electrode 232 on the substrate. The orthographic projection of the gate line GL on the substrate may at least partially overlap the orthographic projection of the active layer 230 on the substrate, for example, the orthographic projection of the gate line GL on the substrate may overlap the orthographic projection of the active layer 230 on the substrate. In this example, by providing an active layer on the gate line, the opening area space occupied by the thin film transistor can be reduced, which is beneficial to improving the aperture ratio of the display area.

[0154] In some examples, the active layer 230 of the thin-film transistor is located below the gate line GL, eliminating the need for a conductorization process for the semiconductor layer. The transistor can be switched on and off using a scan signal transmitted by the gate line GL, simplifying the manufacturing process. The connection between the active layer 230 of the thin-film transistor and the second electrode 232 can be located below the gate line GL, thereby preventing crosstalk from signals transmitted by the data line DL on the pixel electrode. Because the scan signal transmitted by the gate line GL has a low frequency of change, the crosstalk effect on the pixel electrode can be reduced.

[0155] In other examples, when the active layer partially overlaps the gate line, a conductorization process may be used to conduct the semiconductor layer not covered by the gate line. This embodiment is not limited to this.

[0156] In some examples, as shown in Figures 3 and 4, the channel region 2300 of the active layer 230 of the thin film transistor may include a first channel portion 2300a and a second channel portion 2300b connected to each other. For example, the first channel portion 2300a may surround the sidewall of the first via hole K1, and the second channel portion 2300b may surround the outside of the first channel portion 2300a and be located on the horizontal surface of the first insulating layer 101 away from the substrate 100.

[0157] In some examples, the first channel portion 2300a may have a third length L2 along the extension direction of the channel region 2300. For example, the third length L2 may be approximately the length of the sidewall of the first via K1. The third length of the first channel portion 2300a may refer to the effective length of the first channel portion 2300a. The second channel portion 2300b may have a fourth length d2 along the extension direction of the channel region 2300. The fourth length d2 of the second channel portion may be the distance between the edge of the first via K1 and the edge of the second electrode of the thin film transistor. In some examples, the third length L2 may be greater than 0 and less than or equal to 5 microns. For example, the third length L2 may be approximately 0.5 microns or approximately 1 micron. The fourth length d2 may be greater than 0 and less than or equal to 5 microns. For example, the fourth length d2 may be greater than 0 and less than or equal to 2 microns. For example, the fourth length d2 may be approximately 1 micron or approximately 2 microns.

[0158] In some examples, the ratio of the lengths of the second channel portion 2300b to the first channel portion 2300a (i.e., the ratio of d2 to L2) can be greater than or equal to 1. For example, the length of the second channel portion 2300b can be the same as the length of the first channel portion 2300a, or the length of the second channel portion 2300b can be greater than the length of the first channel portion 2300a.

[0159] In some examples, the thickness of the first channel portion 2300a can be the vertical distance between the surface of the first channel portion 2300a away from the sidewall of the first via and the surface close to the sidewall of the first via. The thickness of the second channel portion 2300b can be the vertical distance between the surface of the second channel portion 2300b away from the first insulating layer 101 and the surface close to the first insulating layer 101. In some examples, the thickness of the first channel portion 2300a can be greater than or equal to 1 nanometer (nm) and less than or equal to 200 nm, and the thickness of the second channel portion 2300b can be greater than or equal to 1 nm and less than or equal to 200 nm. In some examples, the ratio of the thickness of the second channel portion 2300b to the first channel portion 2300a can be greater than or equal to 1. For example, the thickness of the second channel portion 2300b can be approximately the same as the thickness of the first channel portion 2300a, or the thickness of the second channel portion 2300b can be greater than the thickness of the first channel portion 2300a.

[0160] In some examples, by controlling the angle between the first channel portion and the second channel portion, the length of the first channel portion and the second channel portion, and the thickness of the first channel portion and the second channel portion, the switching characteristics of the thin film transistor can be guaranteed, and on the basis of ensuring the transistor characteristics, the occupied space of the thin film transistor can be reduced to achieve ultra-high-resolution display technology.

[0161] In some examples, by controlling the fourth length d2, the switching characteristics of the channel region of the thin film transistor can be controlled. For example, when the fourth length d2 is large, the thin film transistor is easier to ensure the switching characteristics, but the startup current Ion will be reduced; when the fourth length d2 is small, the thin film transistor is more likely to have conductor problems, but a larger startup current can be obtained. In some examples, the size of the second length can be adjusted according to the characteristic control capability and the patterning process capability. For example, the fourth length d1 can be greater than 0 and less than or equal to 2 microns to ensure the switching characteristics of the channel region of the thin film transistor. In this example, by controlling the size of the fourth length, the short channel effect can be avoided.

[0162] In some examples, as shown in Figures 7 and 8, the surface of the thin-film transistor's gate 233 on the side closest to the substrate 100 is a first surface 2331, and the surface of the gate 233 on the side away from the substrate 100 is a second surface 2332. The second surface 2332 of the gate 233 can be a flat surface. The active layer 230, the second insulating layer 102, and the gate 233 can be sequentially disposed within the first via K1. In this example, the gate 233 partially fills the first via K1. On a macroscopic scale, the flatness of the first surface 2331 of the gate 233 differs from the flatness of the second surface 2332. In this example, the gate 233 is used to planarize the first via K1, eliminating the need for a planarizing film layer on the side of the third conductive layer away from the substrate. Furthermore, since no vias are provided in the opening area, a planarizing film layer is also not required, simplifying the process steps and saving costs.

[0163] (2-7) A third insulating layer and a fourth conductive layer are formed in sequence, or a third insulating layer, a fourth insulating layer, and a fourth conductive layer are formed in sequence. For example, the fourth conductive layer may include at least a common electrode located in the display area. The fourth insulating layer in the opening area of ​​the display area may be removed. By providing the fourth insulating layer in the non-opening area of ​​the display area, crosstalk of the transmission signal of the gate line to the common electrode can be reduced, and the parasitic capacitance between the gate line and the common electrode can be reduced; by removing the fourth insulating layer in the opening area of ​​the display area, the liquid crystal deflection electric field can be ensured, and the liquid crystal electric field effect can be enhanced.

[0164] The preparation process of the array substrate of this example can reduce the number of required masks, which is conducive to reducing costs. In addition, the display area of ​​the array substrate only needs to form a first via in the first insulating layer to achieve electrical connection between the active layer of the thin film transistor and the data line. No via is set in the opening area of ​​the display area, which can help improve the aperture ratio of the array substrate and facilitate the realization of a high-resolution array substrate. In addition, the active layer of the thin film transistor is located below the gate line, which can avoid crosstalk caused by the data signal to the pixel electrode, and can reduce the additional space occupied by the thin film transistor. Minimizing the space occupied by the thin film transistor can realize ultra-high resolution (for example, greater than 2000PPI) display technology.

[0165] The remaining structure and preparation process of the array substrate of this example can be referred to the description of the aforementioned embodiment, so they will not be described again here.

[0166] Figure 10 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure. Figure 11A is another partial plan view of the display area of ​​an array substrate according to at least one embodiment of the present disclosure. Figure 11B is a plan view of the planar layer and the film layer on the side of the planar layer close to the substrate in Figure 11A. Figure 11C is a plan view of the array substrate after the semiconductor layer is formed in Figure 11A.

[0167] In some examples, as shown in FIG10 , in a direction perpendicular to the array substrate, the array substrate may include: a substrate 100, a first conductive layer 111, a first insulating layer 101, a second conductive layer 112, a semiconductor layer 110, a second insulating layer 102, a planarization layer 105, a third conductive layer 113, a third insulating layer 103, and a fourth conductive layer 114, which are sequentially disposed on the substrate 100. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers, and the planarization layer 105 may be an organic film layer.

[0168] The following is an exemplary description of the manufacturing process of the array substrate of this example with reference to Figures 10 to 11C. The manufacturing process of the array substrate of this example may include the following steps.

[0169] (3-1) Provide a substrate.

[0170] (3-2) Forming a first conductive layer. In some examples, a first conductive film is deposited on a substrate and patterned using a patterning process to form a first conductive layer disposed on the substrate. In some examples, as shown in FIG11C , the first conductive layer in the display area may include data lines DL. The data lines DL may be strip-shaped structures extending along the second direction Y. A portion of the data lines DL may serve as the first electrode 231 of the thin-film transistor.

[0171] (3-3) Forming a first insulating layer. In some examples, a first insulating film is deposited on the substrate forming the aforementioned structure, and the first insulating film is patterned through a patterning process to form a first insulating layer. In some examples, as shown in FIG11C , the first insulating layer may have a first via K1 formed in the display area. The first insulating layer within the first via K1 may be removed to expose a portion of the surface of the data line DL. The exposed portion of the data line DL may serve as the first electrode 231 of the thin film transistor and be electrically connected to the active layer 230.

[0172] (3-4) Forming a second conductive layer. In some examples, a second conductive film is deposited on the substrate forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second conductive layer. In some examples, as shown in FIG11C , the second conductive layer of the display area may include: a pixel electrode 21. The orthographic projection of the pixel electrode 21 on the substrate may overlap with the orthographic projection of the data line DL on the substrate. The overlapping portion of the orthographic projection of the pixel electrode 21 and the data line DL on the substrate may serve as the second pole 232 of the thin film transistor to directly overlap with the active layer 230. However, this embodiment is not limited to this. In other examples, the pixel electrode 21 may be located in the opening area OP, and the active layer of the thin film transistor may extend into the opening area OP to achieve overlap with the pixel electrode 21.

[0173] In other examples, after forming the first conductive layer, a first insulating film and a second conductive film can be deposited on the substrate in sequence, and then the second conductive film is patterned to form the second conductive layer, and then the first insulating film is patterned to form the first insulating layer.

[0174] (3-5) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on the substrate forming the aforementioned structure, and the semiconductor thin film is patterned through a patterning process to form a semiconductor layer. In some examples, as shown in Figures 10 and 11C, the semiconductor layer in the display area may include: an active layer 230 of a thin film transistor. The orthographic projection of the active layer 230 on the substrate may at least partially overlap with the orthographic projection of the data line DL on the substrate. For example, the orthographic projection of the active layer 230 on the substrate may be located within the orthographic projection of the data line DL on the substrate. The active layer 230 may extend along the second direction Y. The orthographic projection of the active layer 230 on the substrate may cover the orthographic projection of the first via K1 on the substrate. The active layer 230 may be electrically connected to the first electrode 231 of the thin film transistor through the first via K1 and directly overlap the second electrode 232 of the thin film transistor. In this example, by directly overlapping the second electrode 232 of the thin film transistor with the active layer 230, the hole opening process can be reduced and the preparation steps can be simplified. By disposing the active layer 230 on the data line DL, the opening area space occupied by the thin film transistor can be reduced, which is beneficial to improving the aperture ratio of the display area.

[0175] (3-6) Forming a second insulating layer. In some examples, a second insulating film is deposited on the substrate forming the aforementioned structure to form a second insulating layer. In some examples, the second insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), silicon oxynitride (SiOxNy, x, y>0), aluminum oxide (Al2O3) and hafnium dioxide (HfO2), and can be a single layer, a multilayer or a composite layer, for example, a stacked structure of SiOx and SiNx. However, this embodiment is not limited to this.

[0176] (3-7) Forming a flat layer and a third conductive layer. In some examples, a flat layer (FL) film is coated on the substrate forming the aforementioned structure. The flat layer can have a strong flatness and can withstand high temperatures. For example, the material of the flat layer can be an organic material that is resistant to high temperatures and has low gas release, such as a synthetic resin, an organic siloxane, etc. The thickness of the flat layer can be 0.3 μm to 1.0 μm.

[0177] In some examples, a third conductive film is deposited on the substrate forming the aforementioned structure, and the third conductive film is patterned through a patterning process to form a third conductive layer. As shown in Figures 10 and 11A, the third conductive layer may include: a gate line GL located in the display area, and a first trace 31 located in the peripheral area. The orthographic projection of the gate line GL on the substrate may overlap with the orthographic projection of the active layer on the substrate. A portion of the gate line GL may serve as the gate 233 of the thin film transistor. The orthographic projection of the gate line GL on the substrate may overlap the orthographic projection of the first via K1 on the substrate.

[0178] In some examples, after forming the third conductive layer, the third conductive layer can be used as a hard mask to etch the flat film to form a flat layer 105. As shown in Figures 11A and 11B, the flat film that is not blocked by the third conductive layer can be etched away, and the flat film blocked by the third conductive layer can be retained to form the flat layer 105. In this example, the active layer, the second insulating layer and the flat layer can be sequentially arranged in the first via K1, so that the surface of the gate line GL away from the substrate side (i.e., the second surface of the gate) can be roughly flat. At the microscopic scale, due to the influence of the etching process, the flatness of the first surface and the second surface is different. In this example, the third conductive layer is used as a hard mask to etch the flat film, which can ensure the conductor effect of the semiconductor layer.

[0179] In some examples, the switching characteristics of the channel region of the thin film transistor can be controlled by controlling the distance between the edge of the first via hole K1 and the edge of the adjacent gate line GL in the extension direction of the active layer 230 (i.e., the aforementioned second length d1). The first length can be adjusted based on the characteristic control capability and patterning process capability. For example, the second length d1 can be greater than 0 and less than or equal to 2 microns to ensure the switching characteristics of the channel region of the thin film transistor.

[0180] In some examples, after forming the third conductive layer and the planar layer 105, the semiconductor layer not covered by the third conductive layer may be subjected to a conductorization process. For example, the conductorization process may include plasma treatment or doping treatment using gases such as hydrogen (H), ammonia (NH3), helium (He), and argon (Ar). This embodiment is not limited to this.

[0181] (3-8) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate forming the aforementioned structure, and the third insulating film is patterned through a patterning process to form a third insulating layer. As shown in FIG10 , the third insulating layer may have vias in the frame region, such as second vias K2. The third insulating layer in the display region does not need to have vias, which helps improve the aperture ratio of the display region.

[0182] (3-9) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on a substrate forming the aforementioned structure, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer. As shown in FIG10 , the fourth conductive layer 114 may include: a common electrode 22 located at least in the display area AA and a second trace 32 located in the frame area BB. The second trace 32 may be electrically connected to the first trace 31 through a second via K2 opened in the third insulating layer 103. In this example, the signal input and transfer are both realized by opening vias in the frame area, and there is no need to set vias in the opening area of ​​the display area, which is beneficial to improving the aperture ratio of the display area.

[0183] In the array substrate of this example, a flat layer with strong leveling ability is provided so that the surface of the gate of the thin film transistor close to the substrate side (i.e., the second plane) is roughly a flat surface, thereby increasing the distance between the gate of the thin film transistor and the first electrode to improve the voltage resistance of the thin film transistor.

[0184] The remaining structure and preparation instructions of the array substrate of this example can refer to the description of the aforementioned embodiment, so they are not repeated here.

[0185] Figure 12 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure. A planar schematic diagram of the display area of ​​the array substrate of this example can be referenced to Figure 7 . In some examples, as shown in Figure 12 , in a direction perpendicular to the array substrate, the array substrate may include: a substrate 100, a first conductive layer 111, a first insulating layer 101, a second conductive layer 112, a semiconductor layer 110, a second insulating layer 102, a planar layer 105, a third conductive layer 113, a third insulating layer 103, and a fourth conductive layer 114, sequentially disposed on the substrate 100. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers, and the planar layer 105 may be an organic film layer.

[0186] In this example, the semiconductor layer 110 may include an active layer 230 of a thin film transistor. As shown in FIG7 , the orthographic projection of the gate line GL on the substrate may cover the orthographic projection of the active layer 230 on the substrate. The active layer 230 of the thin film transistor is located below the gate line GL, and there is no need to perform a conductorization process on the semiconductor layer. The transistor can be switched on and off by a scanning signal transmitted by the gate line GL, which can simplify the manufacturing process. Since this example does not require a conductorization process, a flat layer can be formed directly after coating the flat film without patterning. The flat film of this example does not need to be etched and will not affect the semiconductor layer.

[0187] In the array substrate of this example, a flat layer with strong leveling ability is provided so that the surface of the gate of the thin film transistor close to the substrate side (i.e., the second surface) is roughly a flat surface, thereby increasing the distance between the gate of the thin film transistor and the first electrode to improve the voltage resistance of the thin film transistor.

[0188] The remaining structure and preparation instructions of the array substrate of this example can refer to the description of the aforementioned embodiment, so they are not repeated here.

[0189] Figure 13 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure. A planar schematic diagram of the display area of ​​the array substrate of this example can be referenced to Figure 7 . In some examples, as shown in Figure 13 , in a direction perpendicular to the array substrate, the array substrate may include: a substrate 100, a first conductive layer 111, a first insulating layer 101, a second conductive layer 112, a semiconductor layer 110, a second insulating layer 102, a planar layer 105, a third conductive layer 113, a third insulating layer 103, and a fourth conductive layer 114, sequentially disposed on the substrate 100. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers, and the planar layer 105 may be an organic film layer.

[0190] In this example, as shown in FIG. 13 , the planar layer 105 in the opening region OP of the display area AA may be removed, thereby ensuring the electric field effect of the opening region OP.

[0191] In this example, the array substrate is provided with a planar layer with strong leveling capabilities, making the surface of the thin-film transistor's gate closest to the substrate (i.e., the second surface) substantially flat. This increases the distance between the thin-film transistor's gate and the first electrode, thereby improving the thin-film transistor's voltage resistance. Furthermore, by removing the planar layer from the opening area, the electric field effect in the opening area can be effectively maintained.

[0192] The remaining structure and preparation instructions of the array substrate of this example can refer to the description of the aforementioned embodiment, so they are not repeated here.

[0193] Figure 14 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure. A planar schematic diagram of the display area of ​​the array substrate of this example can be shown with reference to Figure 11A . In some examples, as shown in Figure 14 , in a direction perpendicular to the array substrate, the array substrate may include: a substrate 100, a first conductive layer 111, a first insulating layer 101, a second conductive layer 112, a semiconductor layer 110, a second insulating layer 102, a planar layer 105, a third conductive layer 113, a third insulating layer 103, and a fourth conductive layer 114, sequentially disposed on the substrate 100. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers, and the planar layer 105 may be an organic film layer.

[0194] In this example, semiconductor layer 110 may include an active layer 230 of a thin-film transistor. As shown in FIG11A , the orthographic projection of the data line DL on the substrate may overlap the orthographic projection of the active layer 230 on the substrate. The active layer 230 of the thin-film transistor is located below the data line DL, which can reduce the aperture area occupied by the thin-film transistor, thereby improving the aperture ratio of the display area.

[0195] In this example, as shown in FIG14 , after forming the semiconductor layer, a second insulating film can be deposited and a planarizing film can be applied, followed by forming a third conductive layer. After forming the third conductive layer, the planarizing film and the second insulating film can be etched using the third conductive layer as a hard mask to form a planarizing layer 105 and a second insulating layer 102. The orthographic projection of the second insulating layer 102 on the substrate can overlap with the orthographic projection of the planarizing layer 105 on the substrate. In this example, by etching away the second insulating film and the planarizing film not covered by the third conductive layer, the conductive effect of the semiconductor layer can be ensured.

[0196] In this example, the active layer 230, the second insulating layer 102 and the flat layer 105 can be sequentially arranged in the first via hole K1 opened in the first insulating layer 101, so that the surface of the gate of the thin film transistor close to the substrate side (i.e., the second plane) can be roughly a flat surface, thereby increasing the distance between the gate of the thin film transistor and the first electrode, thereby improving the voltage resistance of the thin film transistor.

[0197] The remaining structure and preparation instructions of the array substrate of this example can be referred to the description of the aforementioned embodiment, so they are not repeated here.

[0198] Figure 15 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure. Figure 16A is another partial plan view of the display area of ​​the array substrate according to at least one embodiment of the present disclosure. Figure 16B is a plan view of the array substrate after the semiconductor layer is formed in Figure 16A. Figure 16C is a plan view of the array substrate after the second conductive layer is formed in Figure 16A.

[0199] In some examples, as shown in FIG15 , in a direction perpendicular to the array substrate, the array substrate may include: a substrate 100, a first conductive layer 111, a first insulating layer 101, a second conductive layer 112, a semiconductor layer 110, a second insulating layer 102, a planarization layer 105, a third conductive layer 113, a third insulating layer 103, and a fourth conductive layer 114, which are sequentially disposed on the substrate 100. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers, and the planarization layer 105 may be an organic film layer.

[0200] In some examples, as shown in Figures 15 and 16, the first conductive layer 111 may include a data line DL. The data line DL may be a strip-shaped structure extending along the second direction Y. A portion of the data line DL may serve as the first electrode 231 of a thin-film transistor. The first insulating layer 101 may have a first via hole K1 in the display area AA. The first insulating layer 101 within the first via hole K1 may be removed, exposing a portion of the surface of the data line DL. The exposed portion of the data line DL may serve as the first electrode 231 of the thin-film transistor and electrically connect to the active layer 230. The second conductive layer 112 may include a pixel electrode 21. The orthographic projection of the pixel electrode 21 on the substrate may overlap with the orthographic projection of the data line DL on the substrate. The overlapping portion of the pixel electrode 21 and the data line DL on the substrate may serve as the second electrode 232 of the thin-film transistor, directly connecting to the active layer 230. The semiconductor layer 110 may include an active layer 230 of the thin-film transistor. The orthographic projection of the active layer 230 on the substrate may be within the orthographic projection of the data line DL on the substrate. The active layer 230 may extend along the second direction Y. The orthographic projection of the active layer 230 on the substrate may cover the orthographic projection of the first via K1 on the substrate. The active layer 230 may be electrically connected to the first electrode 231 of the thin film transistor through the first via K1 and directly overlap the second electrode 232 of the thin film transistor.

[0201] In some examples, as shown in FIG15 , the flat layer 105 may not overlap with the opening area OP. In other words, the flat layer 105 within the opening area OP may be removed to ensure the electric field effect of the opening area OP. The flat layer 105 may flatten the first via K1 of the first insulating layer, so that the surface of the gate line GL close to the substrate side may be roughly flat, thereby increasing the distance between the gate and the first electrode of the thin film transistor to improve the voltage resistance of the thin film transistor. In some examples, the flat layer 105 in the non-opening area of ​​the display area may be retained in its entirety, or the flat layer 105 in the non-opening area of ​​the display area may be partially retained, with only the portion covering the first via K1 retained. For example, the third conductive layer may be used as a hard mask to etch the flat film to form a flat layer.

[0202] In some examples, as shown in Figures 15 and 16A, the third conductive layer 113 may include: a gate line GL located in the display area, and a first trace 31 located in the peripheral area. The orthographic projection of the gate line GL on the substrate may overlap with the orthographic projection of the active layer on the substrate. A portion of the gate line GL may serve as the gate 233 of the thin-film transistor. The orthographic projection of the gate line GL on the substrate may partially overlap with the orthographic projection of the first via K1 on the substrate. For example, the gate line GL may be located on the side of the first via K1 close to the pixel electrode 21. For example, the area of ​​the first via K1 covered by the gate line GL may account for half of the total area of ​​the first via K1. In other words, the gate line GL may cover half of the area of ​​the first via K1. In this example, by reducing the overlapping area between the gate line and the first electrode of the thin-film transistor, the capacitance between the gate and the first electrode of the thin-film transistor can be reduced, thereby reducing power consumption; and the space occupied by the gate line in the opening area can be reduced, thereby improving the aperture ratio of the display area.

[0203] In some examples, as shown in FIG16A , the orthographic projections of the gate line GL and the pixel electrode 21 on the substrate may not overlap, and the switching characteristics of the channel region of the thin film transistor can be controlled by controlling the distance (e.g., corresponding to the second length d1) between the edge of the first via hole K1 and the edge of the adjacent gate line GL in the extension direction of the active layer 230. In other examples, when the orthographic projections of the gate line and the pixel electrode on the substrate overlap, the switching characteristics of the channel region of the thin film transistor can be controlled by controlling the distance (e.g., corresponding to the fourth length d2) between the edge of the first via hole K1 and the edge of the adjacent pixel electrode in the extension direction of the active layer.

[0204] 15 , the fourth conductive layer 114 may include: a common electrode 22 located at least in the display area AA and a second trace 32 located in the frame area BB. The orthographic projection of the common electrode 22 on the substrate overlaps with the orthographic projection of the pixel electrode 21 on the substrate.

[0205] The remaining structure and preparation instructions of the array substrate of this example can refer to the description of the aforementioned embodiment, so they are not repeated here.

[0206] Figure 17 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure. A planar schematic diagram of the display area of ​​the array substrate of this example can be shown in Figure 3 . In some examples, as shown in Figure 17 , in a direction perpendicular to the array substrate, the array substrate may include: a substrate 100, a first conductive layer 111, a first insulating layer 101, a second conductive layer 112, a semiconductor layer 110, a second insulating layer 102, a third conductive layer 113, a third insulating layer 103, and a fourth conductive layer 114, sequentially disposed on the substrate 100. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers. The second insulating layer 102 may include a first sub-insulating layer 1021 and a second sub-insulating layer 1022, with the second sub-insulating layer 1022 located on the side of the first sub-insulating layer 1021 away from the substrate 100.

[0207] In this example, the semiconductor layer 110 may include an active layer 230 of a thin-film transistor. As shown in FIG3 , the orthographic projection of the data line GL on the substrate may overlap the orthographic projection of the active layer 230 on the substrate. Positioning the active layer 230 of the thin-film transistor below the data line GL simplifies the fabrication process and reduces the space occupied by the thin-film transistor, thereby increasing the aperture ratio of the display area.

[0208] In some examples, as shown in FIG17 , the first sub-insulating layer 1021 and the second sub-insulating layer 1022 may both be inorganic insulating layers, for example, including one or more stacked inorganic film layers. In this example, the first sub-insulating layer 1021 and the second sub-insulating layer 1022 may not be etched.

[0209] In some examples, the dielectric constant (K value) of at least one of the multiple inorganic film layers included in the second insulating layer 102 can be greater than or equal to 7, and the thickness of each inorganic film layer can be greater than or equal to 50 nanometers. For example, the K value of one of the multiple inorganic film layers can be greater than or equal to 10. For example, the thickness of at least one inorganic film layer can be greater than or equal to 50 nanometers and less than or equal to 300 nanometers. In this example, by setting the second insulating layer to be a plurality of stacked inorganic film layers and limiting the K value and thickness of the inorganic film layer, it is possible to ensure the on and off characteristics of the thin film transistor while ensuring the insulation effect.

[0210] In some examples, the first sub-insulating layer 1021 can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), silicon oxynitride (SiOxNy, x, y>0), aluminum oxide (Al2O3) and hafnium dioxide (HfO2), and can be, for example, a single layer or multiple layers. The at least one inorganic film layer included in the first sub-insulating layer 1021 can be an oxidized insulating layer, which can be deposited, for example, by atomic layer deposition (ALD), wherein the insulating layer deposited by ALD can be referred to as an ALD oxidized insulating layer. In this example, by providing the first sub-insulating layer, the coverage of the second insulating layer on the semiconductor layer can be improved.

[0211] In some examples, the second sub-insulating layer 1022 may be made of any one or more of silicon nitride (SiNx, x>0) and HKL (High K Layer) materials, and may be a single layer, a multilayer, or a composite layer. The second sub-insulating layer 1022 may include at least one of the following inorganic film layers: a silicon nitride film layer, an HKL film layer. The K value of the HKL film layer may be greater than or equal to 7, for example, greater than or equal to 10. For example, the second sub-insulating layer 1022 may be a single layer of SiNx, or may be a stacked structure of SiNx and HKL. In this example, by providing the second sub-insulating layer 1022 with SiNx, the via coverage can be improved, and the risk of cracks in the second insulating layer can be reduced, which can prevent the third conductive layer and the semiconductor layer or the first conductive layer from short-circuiting or burning through the crack area. By providing the second sub-insulating layer 1022 with HKL, the leakage current of the thin film transistor can be reduced by improving the dielectric capacity of the second insulating layer, and the breakdown voltage between the gate and the first electrode of the thin film transistor can be increased to improve the resistance to electrical breakdown. In some examples, the HKL material may include at least one of: hafnium dioxide (HfO 2 ), zirconium dioxide (ZrO 2 ), hafnium diselenide (HfSe 2 ), and zirconium diselenide (ZrSe 2 ).

[0212] In some examples, the second insulating layer 102 may have a thickness of approximately 2000 angstroms to 4000 angstroms. For example, the first sub-insulating layer 1021 may include a SiOx film layer having a thickness of approximately 1000 angstroms to 3000 angstroms; the second sub-insulating layer 1022 may include a SiNx film layer having a thickness of approximately 1000 angstroms to 3000 angstroms. In another example, the first sub-insulating layer 1021 may include a stacked ALD oxide insulating layer and a SiOx film layer, the ALD oxide insulating layer being located on the side of the SiOx film layer closer to the substrate, wherein the ALD oxide insulating layer may have a thickness of approximately 500 angstroms to 1000 angstroms, and the SiOx film layer may have a thickness of approximately 1000 angstroms to 2000 angstroms; the second sub-insulating layer 1022 may include a SiNx film layer having a thickness of approximately 1000 angstroms to 3000 angstroms. For another example, the first sub-insulating layer 1021 may include a SiOx film layer having a thickness of approximately 1000 to 2000 angstroms; the second sub-insulating layer 1022 may include a stacked HKL film layer and a SiNx film layer, wherein the HKL film layer is located on the side of the SiNx film layer closer to the substrate, and the HKL film layer may have a thickness of approximately 1000 to 2000 angstroms, while the SiNx film layer may have a thickness of approximately 1000 to 2000 angstroms. For another example, the first sub-insulating layer 1021 may include a stacked ALD oxide insulating layer and a SiOx film layer, wherein the ALD oxide insulating layer is located on the side of the SiOx film layer closer to the substrate, wherein the ALD oxide insulating layer may have a thickness of approximately 500 to 1000 angstroms, while the SiOx film layer may have a thickness of approximately 1000 to 2000 angstroms; and the second sub-insulating layer 1022 may include a HKL film layer having a thickness of approximately 1000 to 2000 angstroms. For another example, the first sub-insulating layer 1021 may include an ALD oxide insulating layer and may have a thickness of approximately 500 angstroms to 1000 angstroms; the second sub-insulating layer 1022 may include an HKL film layer and may have a thickness of approximately 1000 angstroms to 2000 angstroms. For another example, the first sub-insulating layer 1021 may include a SiOx film layer and may have a thickness of approximately 1000 angstroms to 2000 angstroms; the second sub-insulating layer 1022 may include an HKL film layer and may have a thickness of approximately 1000 angstroms to 2000 angstroms.

[0213] In this example, by setting the second insulating layer to include a SiNx film layer, the via coverage can be improved, electrostatic discharge (ESD) and short circuit problems caused by cracks can be avoided, and the dielectric properties of the second insulating layer can be improved, thereby improving the anti-breakdown capability; by setting the second insulating layer to include an ALD oxidation insulating layer, the occurrence of gaps at the front channel interface or the introduction of water vapor impurities can be avoided, thereby ensuring the front channel characteristics; by setting the second insulating layer to include an HKL film layer, the leakage current of the thin film transistor can be reduced, thereby improving the anti-electrical breakdown capability.

[0214] The remaining structures and preparation steps of the array substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be described again here.

[0215] Figure 18 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure. A planar schematic diagram of the display area of ​​the array substrate of this example can be shown in Figure 3 . In some examples, as shown in Figure 17 , in a direction perpendicular to the array substrate, the array substrate may include: a substrate 100, a first conductive layer 111, a first insulating layer 101, a second conductive layer 112, a semiconductor layer 110, a second insulating layer 102, a third conductive layer 113, a third insulating layer 103, and a fourth conductive layer 114, sequentially disposed on the substrate 100. The second insulating layer 102 may include a first sub-insulating layer 1021 and a second sub-insulating layer 1022, with the second sub-insulating layer 1022 being located on a side of the first sub-insulating layer 1021 away from the substrate 100.

[0216] In some examples, since the thickness of the second insulating layer 102 is greater than 2000 angstroms, there is a situation where the conductorization effect is affected, resulting in a poor conductorization effect. In this example, after the third conductive layer is formed, the third conductive layer can be used as a hard mask to etch the second insulating layer 102. The first sub-insulating layer 1021 and the second sub-insulating layer 1022 covered by the third conductive layer can be retained, and the first sub-insulating layer 1021 and the second sub-insulating layer 1022 not covered by the third conductive layer can both be etched away. In this example, the orthographic projections of the first sub-insulating layer 1021 and the second sub-insulating layer 1022 on the substrate can cover the orthographic projections of the first via K1 on the substrate to ensure coverage of the via. In this example, by etching both the first sub-insulating layer and the second sub-insulating layer, the conductorization effect of the semiconductor layer can be ensured.

[0217] The remaining structure and preparation instructions of the array substrate of this example can be referred to the description of the embodiment shown in Figure 17, so they are not repeated here.

[0218] Figure 19 is another partial cross-sectional schematic diagram of the array substrate of at least one embodiment of the present disclosure. In some examples, as shown in Figure 19, the second insulating layer 102 of this example can be partially etched, for example, the second sub-insulating layer 1022 can be etched. For example, after forming the third conductive layer, the third conductive layer can be used as a hard mask to etch the second sub-insulating layer 1022, while retaining the first sub-insulating layer 1021, and not etching the first sub-insulating layer 1021. By partially etching the second insulating layer, this example can avoid the thickness of the second insulating layer being too large to affect the conductorization effect, and can ensure the conductorization effect of the semiconductor layer. In other examples, when at least one of the first sub-insulating layer and the second sub-insulating layer is a multi-film stacked structure, at least one of the film layers can be etched to avoid the thickness of the second insulating layer being too large to affect the conductorization effect.

[0219] The remaining structure and preparation instructions of the array substrate of this example can be referred to the description of the embodiments shown in Figures 17 and 18, so they are not repeated here.

[0220] Figure 20 is another partial cross-sectional schematic diagram of an array substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 20, in a direction perpendicular to the array substrate, the array substrate may include: a substrate 100, a first conductive layer 111, a first insulating layer 101, a second conductive layer 112, a semiconductor layer 110, a second insulating layer 102, a third conductive layer 113, a third insulating layer 103, a fourth insulating layer 104, and a fourth conductive layer 114, sequentially disposed on the substrate 100. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers, and the fourth insulating layer 104 may be an organic insulating layer. The second insulating layer 102 may include a first sub-insulating layer 1021 and a second sub-insulating layer 1022, with the second sub-insulating layer 1022 located on the side of the first sub-insulating layer 1021 away from the substrate 100.

[0221] In some examples, as shown in FIG20 , the orthographic projection of the fourth insulating layer 104 on the substrate 100 may not overlap with the opening area OP of the display area AA. In other words, the fourth insulating layer 104 within the opening area OP of the display area AA may be removed. In some examples, the fourth insulating layer 104 may be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited thereto.

[0222] The array substrate of this example can reduce the crosstalk of the transmission signal of the gate line to the common electrode and reduce the parasitic capacitance between the gate line and the common electrode by setting a fourth insulating layer in the non-opening area of ​​the display area; by removing the fourth insulating layer in the opening area of ​​the display area, the liquid crystal deflection electric field can be ensured and the liquid crystal electric field effect can be improved.

[0223] The remaining structure and preparation instructions of the array substrate of this example can be referred to the description of the embodiments shown in Figures 17 to 19, so they are not repeated here.

[0224] In other examples, the solutions of the above embodiments can be combined with each other. For example, the second insulating layer of the embodiment shown in Figures 2 to 16C can adopt the material and structure of the embodiment shown in Figures 17 to 19.

[0225] This embodiment also provides a method for preparing an array substrate, comprising: forming a first conductive layer on a substrate, the first conductive layer comprising: a first electrode of at least one thin film transistor; forming a first insulating layer on the first conductive layer, the first insulating layer having a first via hole to expose at least a portion of the surface of the first electrode; forming a second conductive layer and a semiconductor layer on the first insulating layer, the semiconductor layer comprising: an active layer of the thin film transistor, the active layer being electrically connected to the first electrode through the first via hole, the orthographic projection of the active layer on the substrate covering the orthographic projection of the first via hole on the substrate, the second conductive layer comprising at least: a second electrode of the thin film transistor; forming a second insulating layer; forming a third conductive layer on the second insulating layer, the third conductive layer comprising at least: a gate of the thin film transistor, the surface of the gate on the side close to the substrate being the first surface, the surface of the gate on the side away from the substrate being the second surface, and the flatness of the first surface and the second surface being different.

[0226] In some exemplary embodiments, the first conductive layer may further include: at least one data line, the first electrode of at least one thin film transistor and the data line are an integrated structure; the second conductive layer further includes: at least one pixel circuit, the second electrode of at least one thin film transistor and the pixel circuit are an integrated structure; the third conductive layer further includes: at least one gate line, the gate of at least one thin film transistor and the gate line are an integrated structure.

[0227] In some exemplary embodiments, the preparation method of this example may further include: forming a planarization layer after forming the second insulating layer, wherein the orthographic projection of the planarization layer on the substrate can cover the orthographic projection of the first via on the substrate. The description of this example can refer to the description of the embodiments shown in Figures 10 to 15 above, and therefore will not be repeated here. This example utilizes the ability of the planarization layer to fill the first via to ensure the distance between the gate and the first electrode of the thin film transistor, thereby improving the voltage resistance of the thin film transistor.

[0228] In some exemplary embodiments, forming the planar layer may include: coating a planar film on the substrate after forming the second insulating layer, and patterning the planar film to form the planar layer. The description of this example can refer to the description of the embodiments shown in Figures 13 and 15 above, and therefore will not be repeated here. In other examples, forming the planar layer may include: coating a planar film on the substrate after forming the second insulating layer, forming a third conductive layer on the planar film, and then etching the planar film using the third conductive layer as a hard mask to form the planar layer. The description of this example can refer to the description of the embodiments shown in Figures 10 and 14, and therefore will not be repeated here.

[0229] In some exemplary embodiments, the substrate may include a display area, and at least one data line and at least one gate line provided in the display area may intersect to form a plurality of sub-pixel areas, wherein the sub-pixel area includes an opening area for display and a non-opening area located on at least one side of the opening area. The flat layer and the opening area may not overlap. The description of this example can refer to the description of the embodiment shown in FIG15, so it is not repeated here. In this example, by removing the flat layer in the opening area, the electric field effect in the opening area can be ensured.

[0230] In some exemplary embodiments, forming the second insulating layer may include: depositing a plurality of inorganic film layers in sequence on the substrate after forming the semiconductor layer to form the second insulating layer. The plurality of inorganic film layers satisfy at least one of the following: the dielectric constant of at least one inorganic film layer is greater than or equal to 7, and the thickness of each inorganic film layer is greater than or equal to 50 nanometers. The description of this example can refer to the description of the embodiment shown in Figure 17, so it is not repeated here. In other examples, forming the second insulating layer may include: depositing a plurality of inorganic film layers in sequence on the substrate after forming the semiconductor layer, and after forming the third conductive layer, etching at least one of the plurality of inorganic film layers using the third conductive layer as a hard mask to form the second insulating layer. The plurality of inorganic film layers may include at least two of the following: an oxide insulating layer, a silicon nitride film layer, and an HKL film layer. The description of this example can refer to the description of the embodiments shown in Figures 18 to 20. In some examples, the second insulating layer may include: an oxide insulating layer and a silicon nitride film layer arranged in sequence along a direction away from the substrate; or, an oxide insulating layer, an HKL film layer, and a silicon nitride film layer arranged in sequence along a direction away from the substrate; or, an oxide insulating layer and an HKL film layer arranged in sequence along a direction away from the substrate.

[0231] In some exemplary embodiments, the preparation method of this example may further include: after forming the third conductive layer, sequentially forming a third insulating layer and a fourth conductive layer, or sequentially forming a third insulating layer, a fourth insulating layer, and a fourth conductive layer. The fourth conductive layer may include at least: a common electrode. The third insulating layer may be an inorganic insulating layer, and the fourth insulating layer may be an organic insulating layer. In some examples, the fourth insulating layer may not overlap with the opening area. The description of this example can refer to the description of the embodiments shown in Figures 6 and 20. This example can enhance the liquid crystal electric field effect by removing the fourth insulating layer in the opening area.

[0232] The rest of the description about the method for preparing the array substrate of this embodiment can refer to the description of the aforementioned embodiment, and thus will not be repeated here.

[0233] FIG21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG21 , this embodiment provides a display device 91 , which may include the array substrate 910 described above.

[0234] In some examples, the display device 91 may include an array substrate 910, an opposing substrate, and a liquid crystal layer disposed between the array substrate and the opposing substrate. The pixel electrodes and common electrodes included in the array substrate 910 may be configured to generate an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer. In some examples, the opposing substrate may include a base substrate, and a black matrix and a color filter layer disposed on the base substrate. However, this embodiment is not limited to this.

[0235] In some examples, the display device 91 may be any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator. This embodiment is not limited thereto.

[0236] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

Claims

1. A thin film transistor, comprising: A first electrode, a second electrode, an active layer and a gate are arranged on a substrate; The active layer is electrically connected to the first electrode and the second electrode, the gate is located on a side of the active layer away from the substrate, the first electrode is located on a side of the active layer close to the substrate, a first insulating layer is provided between the first electrode and the active layer, a first via hole is provided in the first insulating layer, the active layer is electrically connected to the first electrode through the first via hole, and the orthographic projection of the active layer on the substrate covers the orthographic projection of the first via hole on the substrate; A second insulating layer is provided between the gate and the active layer; The orthographic projection of the gate on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate, the surface of the gate on the side close to the substrate is a first surface, and the surface of the gate on the side away from the substrate is a second surface, and the first surface and the second surface have different flatness.

2. The thin film transistor according to claim 1, wherein: The second surface of the gate is a flat surface, and the vertical distances between the first electrode and the second electrode and the substrate are different.

3. The thin film transistor according to claim 1 or 2, wherein: The active layer comprises a channel region, and the orthographic projection of the channel region on the substrate is located within the orthographic projection range of the gate on the substrate; The channel region includes a first channel portion and a second channel portion connected to each other, wherein an orthographic projection of the first channel portion on the substrate at least partially overlaps an orthographic projection of a sidewall of the first via hole on the substrate; The second channel portion is located on a surface of the first insulating layer away from the substrate and has no overlap with an orthographic projection of the first via hole on the substrate.

4. The thin film transistor according to claim 3, wherein: In a plane perpendicular to the substrate and parallel to the extension direction of the active layer, an angle between the first channel portion and the second channel portion ranges from 90 degrees to 160 degrees.

5. The thin film transistor according to claim 3 or 4, wherein: A ratio of the lengths of the second channel portion to the first channel portion is greater than or equal to 1, and a ratio of the thicknesses of the second channel portion to the first channel portion is greater than or equal to 1.

6. The thin film transistor according to any one of claims 3 to 5, wherein: The length of the first channel portion is greater than 0 and less than or equal to 5 micrometers, and the length of the second channel portion is greater than 0 and less than or equal to 5 micrometers.

7. The thin film transistor according to any one of claims 1 to 6, wherein: The second pole is located on a side of the active layer close to the substrate, and the active layer is directly overlapped with the second pole.

8. The thin film transistor according to any one of claims 1 to 7, wherein: The active layer, the second insulating layer and the gate are sequentially disposed in the first via hole.

9. The thin film transistor according to any one of claims 1 to 7, wherein: A planar layer is disposed between the second insulating layer and the gate, and an orthographic projection of the planar layer on the substrate at least covers an orthographic projection of the first via hole on the substrate.

10. The thin film transistor according to claim 9, wherein: The orthographic projection of the planar layer on the substrate covers the orthographic projection of the gate on the substrate, and the second surface of the gate is a planar surface.

11. The thin film transistor according to any one of claims 1 to 10, wherein: The orthographic projection of the second insulating layer on the substrate at least covers the orthographic projection of the first via hole and the gate on the substrate.

12. The thin film transistor according to claim 11, wherein: The second insulating layer includes: a plurality of stacked inorganic film layers, wherein the plurality of inorganic film layers satisfy at least one of the following conditions: a dielectric constant of at least one inorganic film layer is greater than or equal to 7, and a thickness of each inorganic film layer is greater than or equal to 50 nanometers.

13. An array substrate, comprising: A substrate and at least one thin film transistor as described in any one of claims 1 to 12, at least one data line, at least one gate line and at least one pixel electrode arranged on the substrate; the gate of the thin film transistor is electrically connected to the gate line, the first electrode of the thin film transistor is electrically connected to the data line, and the second electrode of the thin film transistor is electrically connected to the pixel electrode.

14. The array substrate according to claim 13, wherein: The first electrode of the thin film transistor and the data line are an integrated structure, the gate electrode of the thin film transistor and the gate line are an integrated structure, and the second electrode of the thin film transistor and the pixel electrode are an integrated structure.

15. The array substrate according to claim 13 or 14, wherein: An orthographic projection of an active layer of the thin film transistor on the substrate partially overlaps an orthographic projection of at least one of the data line and the gate line on the substrate.

16. The array substrate according to any one of claims 13 to 15, wherein: The substrate includes a display area, the at least one data line and the at least one gate line intersect in the display area to form a plurality of sub-pixel areas, the sub-pixel area includes an opening area for display and a non-opening area located at least on one side of the opening area, the pixel electrode is at least located in the opening area; the thin film transistor, the data line and the gate line are located in the non-opening area.

17. The array substrate according to claim 16, wherein: A second insulating layer is arranged between the gate electrode and the active layer of the thin film transistor, a planar layer is arranged between the second insulating layer and the gate electrode, and the planar layer does not overlap with the opening area.

18. The array substrate according to claim 16, further comprising: A third insulating layer and a common electrode are located on a side of the gate line away from the substrate. The common electrode is at least located in the opening area, and an orthographic projection of the common electrode on the substrate at least partially overlaps with an orthographic projection of the pixel electrode on the substrate.

19. The array substrate according to claim 18, further comprising: A fourth insulating layer is located on a side of the third insulating layer away from the substrate, and the fourth insulating layer does not overlap with the opening area.

20. A method for preparing an array substrate, comprising: A first conductive layer is formed on a substrate, wherein the first conductive layer comprises: a first electrode of at least one thin film transistor; forming a first insulating layer on the first conductive layer, wherein the first insulating layer is provided with a first via hole to expose at least a portion of the surface of the first electrode; A second conductive layer and a semiconductor layer are formed on the first insulating layer, wherein the semiconductor layer includes: an active layer of the thin film transistor, the active layer is electrically connected to the first electrode through the first via hole, the orthographic projection of the active layer on the substrate covers the orthographic projection of the first via hole on the substrate, and the second conductive layer includes at least: a second electrode of the thin film transistor; forming a second insulating layer; A third conductive layer is formed on the second insulating layer, the third conductive layer at least comprising: a gate of the thin film transistor; a surface of the gate close to the substrate is a first surface, a surface of the gate away from the substrate is a second surface, and the first surface and the second surface have different flatnesses.

21. The preparation method according to claim 20, wherein: The first conductive layer also includes: at least one data line, and the first electrode of the at least one thin film transistor is an integrated structure with the connected data line; the second conductive layer also includes: at least one pixel circuit, and the second electrode of the at least one thin film transistor is an integrated structure with the connected pixel circuit; the third conductive layer also includes: at least one gate line, and the gate of the at least one thin film transistor is an integrated structure with the connected gate line.

22. The preparation method according to claim 20 or 21, further comprising: After forming the second insulating layer, a flat film is coated on the substrate, and the flat film is patterned to form a flat layer; or, After forming the second insulating layer, a flat film is coated on the substrate, and after forming a third conductive layer on the flat film, the flat film is etched using the third conductive layer as a hard mask to form a flat layer; The orthographic projection of the planar layer on the substrate covers the orthographic projection of the first via hole on the substrate.

23. The preparation method according to claim 20, wherein: The forming of the second insulating layer comprises: After forming the semiconductor layer, a plurality of inorganic film layers are sequentially deposited on the substrate to form the second insulating layer; or, Depositing a plurality of inorganic film layers in sequence on the substrate after forming the semiconductor layer, and after forming the third conductive layer, etching at least one of the plurality of inorganic film layers using the third conductive layer as a hard mask to form the second insulating layer; The plurality of inorganic film layers satisfy at least one of the following conditions: a dielectric constant of at least one inorganic film layer is greater than or equal to 7, and a thickness of each inorganic film layer is greater than or equal to 50 nanometers.

24. The preparation method according to any one of claims 20 to 23, further comprising: After forming the third conductive layer, sequentially forming a third insulating layer and a fourth conductive layer, or sequentially forming the third insulating layer, the fourth insulating layer and the fourth conductive layer; Among them, the fourth conductive layer at least includes: a common electrode; the third insulating layer is an inorganic insulating layer, and the fourth insulating layer is an organic insulating layer; the substrate includes a display area, and at least one data line and at least one gate line arranged in the display area cross to form a plurality of sub-pixel areas, and the sub-pixel area includes an opening area for display and a non-opening area located on at least one side of the opening area; the fourth insulating layer does not overlap with the opening area.

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