Thin film transistor, array substrate, and display device

Abstract

A thin film transistor, an array substrate, and a display device. The thin film transistor comprises an active layer, a first gate insulating layer, and a first gate. The active layer comprises a channel region, and a first conductive region and a second conductive region which are separated by the channel region. The first gate insulating layer is located on a first side of the active layer. The first gate is located on the side of the first gate insulating layer away from the active layer. At least part of the first conductive region, at least part of the channel region, and at least part of the second conductive region are arranged along a first direction. The channel region comprises a narrowed part, and the average size of the narrowed part in the first direction is smaller than the average size of the channel region in the first direction. Therefore, by designing the special-shaped channel region comprising the narrowed part, the channel lengths of different regions of the channel region are different, and it is possible to increase the subthreshold swing of the thin film transistor, so that the driving current provided by a driving transistor is not sensitive to the fluctuation of a gate voltage.

Description

Thin film transistor, array substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 2023104513903 filed on April 24, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a thin film transistor, an array substrate, and a display device. Background Art

[0003] With the continuous development of display technology, liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs) have gradually become mainstream display devices. Both LCDs and OLEDs require pixel driver circuits to drive each sub-pixel for display. Thin-film transistors (TFTs) are crucial components in these circuits, directly impacting their driving performance.

[0004] On the other hand, compared to silicon-based thin-film transistors, oxide thin-film transistors have a carrier concentration approximately ten times that of silicon-based thin-film transistors, and a carrier mobility 20-30 times that of silicon-based thin-film transistors. Therefore, oxide thin-film transistors can significantly increase the charge and discharge rates of thin-film transistors, improve the response speed of sub-pixels, and thus achieve faster refresh rates. This enables oxide thin-film transistors to meet application scenarios that require fast response and high current, such as high-frequency, high-resolution, large-size liquid crystal displays and organic light-emitting diode displays.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a thin-film transistor, an array substrate, and a display device. By designing a profiled channel region including a narrowed portion, different channel lengths are achieved in different regions of the channel region, resulting in a leader effect similar to the hump effect in the thin-film transistor. This increases the subthreshold swing of the thin-film transistor, thereby improving the data voltage range of the drive transistor and making the drive current provided by the drive transistor insensitive to gate voltage fluctuations.

[0007] At least one embodiment of the present disclosure provides a thin film transistor, comprising: an active layer including a channel region and a first conductive region and a second conductive region separated by the channel region; a first gate insulating layer located on a first side of the active layer; and a first gate located on a side of the first gate insulating layer away from the active layer, wherein at least a portion of the first conductive region, at least a portion of the channel region, and at least a portion of the second conductive region are arranged along a first direction, the channel region includes a narrowed portion, and an average size of the narrowed portion in the first direction is smaller than an average size of the channel region in the first direction.

[0008] For example, in a thin film transistor provided in an embodiment of the present disclosure, the first conductive region and the second conductive region are spaced apart from each other, and define a connection region between the first conductive region and the second conductive region, and the narrowed portion is located in the connection region.

[0009] For example, in a thin film transistor provided by an embodiment of the present disclosure, the connection region includes a center line extending along the first direction, and the narrowed portion overlaps with the center line.

[0010] For example, in a thin film transistor provided in an embodiment of the present disclosure, the first conductive region is located on a first side of the channel region, and the second conductive region is located on a second side of the channel region; the narrowed portion narrows from both the first side and the second side toward a center line of the channel region extending in a second direction intersecting the first direction.

[0011] For example, in a thin film transistor provided in an embodiment of the present disclosure, the channel region includes a plurality of the narrowed portions arranged along a second direction intersecting with the first direction.

[0012] For example, in a thin film transistor provided in an embodiment of the present disclosure, the plurality of narrowed portions are staggered in the first direction.

[0013] For example, in a thin film transistor provided in an embodiment of the present disclosure, at least one of the first conductive region and the second conductive region includes a protruding portion connected to the narrowed portion, and a shape of the protruding portion is complementary to a shape of the narrowed portion.

[0014] For example, in a thin film transistor provided in an embodiment of the present disclosure, the channel region includes a first side and a second side, the first side contacts the first conductor region, and the second side contacts the second conductor region; at least one of the first side and the second side includes a bending portion, and the bending portion bends from the first conductor region or the second conductor region toward the channel region.

[0015] For example, in a thin film transistor provided in an embodiment of the present disclosure, the bending portion includes at least one of an oblique line and an arc line, and the angle between the oblique line and the first direction is less than 90 degrees.

[0016] For example, in a thin film transistor provided in an embodiment of the present disclosure, the first side includes a first bending portion, bending from the first conductive region to the channel region, and the second side includes a second bending portion, bending from the second conductive region to the channel region.

[0017] For example, in a thin film transistor provided in an embodiment of the present disclosure, the first bending portion and the second bending portion overlap in the first direction.

[0018] For example, in a thin film transistor provided in an embodiment of the present disclosure, the size of the first bending portion in the first direction is larger than the size of the second bending portion in the first direction, or the size of the first bending needle portion in the first direction is smaller than the size of the second bending portion in the first direction.

[0019] For example, in a thin film transistor provided in an embodiment of the present disclosure, the ratio of the area of ​​the narrowed portion to the area of ​​the channel region is in the range of 1 / 16-3 / 16.

[0020] For example, in a thin film transistor provided in an embodiment of the present disclosure, the minimum dimension of the narrowed portion in the first direction is greater than or equal to 1 micron, and the ratio of the dimension of the narrowed portion in a second direction intersecting with the first direction to the dimension of the channel region in the second direction is in the range of 10%-20%.

[0021] For example, the thin film transistor provided in one embodiment of the present disclosure also includes: a second gate insulating layer, located on the second side of the active layer; and a second gate, located on the side of the second gate insulating layer away from the active layer, and the orthographic projection of the second gate on the active layer completely covers the orthographic projection of the first gate on the active layer.

[0022] For example, in a thin film transistor provided in an embodiment of the present disclosure, the channel region includes a first side and a second side, the first side contacts the first conductor region, and the second side contacts the second conductor region; the shortest distance between the first side and the edge of the orthographic projection of the second gate on the active layer is greater than 1.0 micron; the shortest distance between the second side and the edge of the orthographic projection of the second gate on the active layer is greater than 1.0 micron.

[0023] For example, the thin film transistor provided in one embodiment of the present disclosure further includes: a first electrode electrically connected to the first conductive region; and a second electrode electrically connected to the second conductive region, wherein the first electrode is electrically connected to the second gate.

[0024] For example, in a thin film transistor provided in an embodiment of the present disclosure, the first conductive region is a source region, and the second conductive region is a drain region; or, the first conductive region is a drain region, and the second conductive region is a source region.

[0025] At least one embodiment of the present disclosure further provides an array substrate, which includes: a base substrate; and any of the above-mentioned thin film transistors.

[0026] For example, an array substrate provided by an embodiment of the present disclosure further includes: a plurality of pixel driving circuits arranged in an array, each of the pixel driving circuits includes a driving thin film transistor, and the driving thin film transistor includes the thin film transistor.

[0027] For example, in the array substrate provided in one embodiment of the present disclosure, the multiple pixel driving circuits include: a first pixel driving circuit, configured to drive the first sub-pixel to emit light of a first color; a second pixel driving circuit, configured to drive the second sub-pixel to emit light of a second color; and a third pixel driving circuit, configured to drive the third sub-pixel to emit light of a third color, and the size of the narrowed portion of the driving thin film transistor of the first pixel driving circuit, the size of the narrowed portion of the driving thin film transistor of the second pixel driving circuit, and the size of the narrowed portion of the driving thin film transistor of the third pixel driving circuit are different.

[0028] At least one embodiment of the present disclosure further provides a display device, comprising any of the above array substrates.

[0029] At least one embodiment of the present disclosure further provides a thin film transistor, comprising: an active layer, comprising a channel region and a first conductive region and a second conductive region separated by the channel region; a first gate insulating layer, located on a first side of the active layer; and a first gate, located on a side of the first gate insulating layer away from the active layer, at least a portion of the first conductive region, at least a portion of the channel region, and at least a portion of the second conductive region are arranged along a first direction; the channel region comprises a first side and a second side, the first side contacts the first conductive region, and the second side contacts the second conductive region, at least one of the first side and the second side comprises a bending portion, and the bending portion bends from the first conductive region or the second conductive region toward the channel region.

[0030] For example, in the thin film transistor provided in at least one embodiment of the present disclosure, the first side includes a first bending portion bending from the first conductive region to the channel region, and the second side includes a second bending portion bending from the second conductive region to the channel region.

[0031] For example, the thin film transistor provided by at least one embodiment of the present disclosure also includes: a second gate insulating layer located on the second side of the active layer; and a second gate located on the side of the second gate insulating layer away from the active layer, and the orthographic projection of the second gate on the active layer completely covers the orthographic projection of the first gate on the active layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0033] FIG1 is a schematic diagram of a pixel driving circuit;

[0034] FIG2 is a schematic plan view of a thin film transistor provided in one embodiment of the present disclosure;

[0035] FIG3 is a cross-sectional schematic diagram of a thin film transistor provided in one embodiment of the present disclosure;

[0036] FIG4A is a graph showing output currents of a main portion and a partially narrowed portion of a thin film transistor provided in one embodiment of the present disclosure;

[0037] FIG4B is a graph showing the final output current of a main portion and a partially narrowed portion of a thin film transistor provided in one embodiment of the present disclosure;

[0038] FIG5 is a graph showing an output current of a thin film transistor according to an embodiment of the present disclosure;

[0039] FIG6 is a schematic plan view of another thin film transistor provided by an embodiment of the present disclosure;

[0040] FIG7 is a cross-sectional schematic diagram of another thin film transistor provided by an embodiment of the present disclosure;

[0041] FIG8 is a schematic plan view of another thin film transistor provided by an embodiment of the present disclosure;

[0042] FIG9 is a cross-sectional schematic diagram of another thin film transistor provided by an embodiment of the present disclosure;

[0043] FIG10 is a schematic plan view of another thin film transistor provided in one embodiment of the present disclosure;

[0044] FIG11 is a cross-sectional schematic diagram of another thin film transistor provided in one embodiment of the present disclosure;

[0045] FIG12 is a schematic plan view of another thin film transistor provided by an embodiment of the present disclosure;

[0046] FIG13 is a schematic cross-sectional view of another thin film transistor provided in one embodiment of the present disclosure;

[0047] FIG14 is a schematic plan view of another thin film transistor provided by an embodiment of the present disclosure;

[0048] FIG15 is a schematic cross-sectional view of another thin film transistor provided in one embodiment of the present disclosure;

[0049] FIG16 is a schematic plan view of another thin film transistor provided by an embodiment of the present disclosure;

[0050] FIG17 is a schematic cross-sectional view of another thin film transistor provided in one embodiment of the present disclosure;

[0051] FIG18 is a schematic plan view of another thin film transistor provided by an embodiment of the present disclosure;

[0052] FIG19 is a schematic plan view of another thin film transistor provided by an embodiment of the present disclosure;

[0053] FIG20 is a schematic plan view of another thin film transistor provided by an embodiment of the present disclosure;

[0054] FIG21 is a plan view of an array substrate provided in accordance with an embodiment of the present disclosure;

[0055] FIG22A is a schematic plan view of a driving thin film transistor provided in one embodiment of the present disclosure;

[0056] FIG22B is a schematic plan view of another driving thin film transistor provided by an embodiment of the present disclosure; and

[0057] FIG23 is a schematic plan view of a display device provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0059] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0060] Unless otherwise defined, the features such as “parallel”, “perpendicular” and “identical” used in the embodiments of the present disclosure include situations such as “parallel”, “perpendicular” and “identical” in a strict sense, as well as situations such as “approximately parallel”, “approximately perpendicular” and “approximately identical” that contain a certain error. For example, the above-mentioned “approximately” may mean that the difference between the compared objects is 10% of the average value of the compared objects, or within 5%. When the number of a component or element is not specifically indicated below in the embodiments of the present disclosure, it means that the component or element may be one or more, or may be understood as at least one. “At least one” refers to one or more, and “plurality” refers to at least two.

[0061] In an organic light-emitting diode display device, each subpixel includes a pixel driver circuit and a light-emitting element. The light-emitting element includes an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The pixel driver circuit is connected to the anode to provide a current signal to the anode, thereby driving the light-emitting element to emit light. Typically, the pixel driver circuit is composed of thin-film transistors and capacitors; for example, the pixel driver circuit can adopt a 3T1C structure, a 5T1C structure, a 7T1C structure, or an 8T1C structure, where T represents a thin-film transistor and C represents a capacitor.

[0062] Below, a pixel driving circuit is briefly described using 7T1C as an example. Figure 1 is a schematic diagram of a pixel driving circuit. As shown in Figure 1, the pixel driving circuit includes a driving transistor T1, a compensation transistor T3, a data writing transistor T2, a first light-emitting control transistor T4, a second light-emitting control transistor T5, an initialization transistor T6, and an electrode reset transistor T7. The first electrode of the driving transistor T1, the second electrode of the data writing transistor T2, and the second electrode of the first light-emitting control transistor T4 are electrically connected. The second electrode of the driving transistor T1, the first electrode of the compensation transistor T3, and the first electrode of the second light-emitting control transistor T5 are electrically connected. The gate of the driving transistor T1, the second electrode of the compensation transistor T3, and the second electrode of the initialization transistor T6 are electrically connected. The second electrode of the second light-emitting control transistor T5, the second electrode of the electrode reset transistor T7, and the anode of the light-emitting element 10 are electrically connected. The first plate of the storage capacitor Cst is connected to the first electrode of the first light-emitting control transistor T4 and is configured to be connected to a power supply voltage. The second plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, the second electrode of the compensation transistor T3, and the second electrode of the initialization transistor T6.

[0063] As shown in Figure 1, the electrode reset transistor T7 is configured to reset the anode of the light-emitting element 10 in response to a Reset signal, and the initialization transistor T6 is configured to initialize the gate of the drive transistor T1 and the second plate of the storage capacitor Cst in response to the Reset signal. Subsequently, the data write transistor T2 and the compensation transistor T3 are turned on by the gate signal Gate, and the data signal Vd is transmitted through the data write transistor T2. At this time, the drive transistor T1 is turned on, and the data signal Vd is applied to the gate of the drive transistor T1 through the data write transistor T2 and the compensation thin-film transistor T3. At this time, the voltage applied to the gate of the drive transistor T1 is the compensation voltage Vd + Vth, and the compensation voltage applied to the gate of the drive transistor T1 is also applied to the second plate of the storage capacitor Cst. Subsequently, the drive voltage Vel is applied to the first plate of the storage capacitor Cst, while the voltage on the second plate is the compensation voltage Vd + Vth. This causes a charge corresponding to the voltage difference between the voltages applied to the two plates of the storage capacitor Cst to be stored in the storage capacitor Cst, and the drive transistor T1 is turned on for a predetermined time. Subsequently, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are both turned on. When the driving signal Vel passes through the driving transistor T1 turned on by the storage capacitor Cst, the voltage of the first electrode of the driving transistor T1 is Vel, and the voltage of the gate of the driving transistor T1 is Vd+Vth. This can put the driving transistor T1 into a saturated state, so that the driving transistor T1 generates a driving current Ids; then, the driving current Ids is applied to the anode of the light-emitting element 10 through the second light-emitting control transistor T5, so that the light-emitting element emits light.

[0064] As described above, the driving transistor T1 provides a driving current to the anode of the light-emitting element 10 during the light-emitting process of the light-emitting element 10. Therefore, maintaining a stable current in the driving transistor T1 during the light-emitting period (one frame) of the light-emitting element 10 can significantly improve display quality and improve mura. By increasing the subthreshold swing (SS) of the driving transistor, the data voltage range of the driving transistor can be increased, making the driving current provided by the driving transistor insensitive to fluctuations in the gate voltage, thereby reducing the sensitivity of the light-emitting element's luminance to voltage fluctuations, significantly improving display quality, and improving mura.

[0065] On the other hand, in high-generation lines, oxide thin-film transistors (Oxide TFTs) have huge advantages in terms of cost, uniformity, and leakage, and have become a research hotspot and development direction for major manufacturers. However, the inventors of this application found that in conventional low-temperature polysilicon thin-film transistors (LTPS TFTs), the driving transistor can obtain a larger subthreshold swing by changing the channel length, while the subthreshold swing of current oxide thin-film transistors is insensitive to the channel length, and it is impossible to obtain a larger subthreshold swing for the driving transistor by designing different channel lengths. Therefore, how to obtain a larger subthreshold swing for the driving transistor by other means is an urgent problem to be solved. It should be noted that the channel length of the channel region of a conventional thin-film transistor is uniform in different regions, so the above-mentioned method of changing the channel length is to increase or decrease the channel length as a whole.

[0066] In response to the above-mentioned problems, an embodiment of the present disclosure provides a thin film transistor. The thin film transistor includes an active layer, a first gate insulation layer, and a first gate; the active layer includes a channel region and a first conductive region and a second conductive region separated by the channel region; the first gate insulation layer is located on a first side of the active layer; the first gate is located on a side of the first gate insulation layer away from the active layer; at least a portion of the first conductive region, at least a portion of the channel region, and at least a portion of the second conductive region are arranged along a first direction, and the channel region includes a narrowing portion, and the average size of the narrowing portion in the first direction is smaller than the average size of the channel region in the first direction. Therefore, the present disclosure designs a special-shaped channel region including a narrowing portion, so that the channel lengths of different regions of the channel region are different, so that the thin film transistor produces a leader effect similar to the hump effect, thereby increasing the subthreshold swing of the thin film transistor, and further improving the data voltage range of the driving transistor, so that the driving current provided by the driving transistor is insensitive to fluctuations in the gate voltage.

[0067] The present disclosure also provides an array substrate comprising the aforementioned thin-film transistor. Thus, the array substrate can employ thin-film transistors with a large subthreshold swing as drive transistors, thereby making the drive current provided by the drive transistor insensitive to voltage fluctuations. This reduces the sensitivity of the sub-pixel's luminance to voltage fluctuations, significantly improving display quality and alleviating mura defects.

[0068] The present disclosure also provides a display device comprising the array substrate described above. Thus, the display device can have better display quality, improve Mura defects, and can also be used in electronic products requiring high frequency, high resolution, and large size.

[0069] Hereinafter, the thin film transistor, array substrate and display device provided by the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0070] An embodiment of the present disclosure provides a thin film transistor. FIG2 is a plan view of a thin film transistor provided by an embodiment of the present disclosure; FIG3 is a cross-sectional view of a thin film transistor provided by an embodiment of the present disclosure.

[0071] As shown in Figures 2 and 3, the thin film transistor 100 includes an active layer 110, a first gate insulator 120, and a first gate 130. The active layer 110 includes a channel region 113 and a first conductive region 111 and a second conductive region 112 separated by the channel region 113. The conductivity of the first conductive region 111 and the second conductive region 112 is greater than that of the channel region 113. The first gate insulator 120 is located on a first side of the active layer 110, the first side being a side perpendicular to the main surface of the active layer 110. The first gate 130 is located on a side of the first gate insulator 120 away from the active layer 110. At least a portion of the first conductive region 111, at least a portion of the channel region 113, and at least a portion of the second conductive region 112 are arranged along a first direction X. In this case, the first direction X can also be considered the length direction of the channel region 113. The channel region 113 includes a narrowed portion 113B. The average size of the narrowed portion 113B in the first direction X is smaller than the average size of the channel region 113 in the first direction X. That is, the average channel length of the narrowed portion 113B is smaller than the average channel length of the entire channel region 113 .

[0072] In the thin-film transistor provided in the embodiments of the present disclosure, since the channel region includes a narrowed portion, and the average size of the narrowed portion in the first direction is smaller than the average size of the channel in the first direction, the channel region has a smaller channel length in the narrowed portion and a larger channel length in the other portion (also referred to as the main portion). In this case, taking the channel region of the thin-film transistor as an N-type channel region as an example, when the gate voltage on the first gate is insufficient to turn on the other portions of the channel region and only the narrowed portion is turned on, the thin-film transistor can produce a leading effect similar to the hump effect, the narrowed portion is turned on, and the output current of the thin-film transistor is mainly from the narrowed portion; when the gate voltage on the first gate increases to a level that can turn on the other portions of the channel region, the other portions can also be turned on, and the output current of the thin-film transistor is mainly from the other portions. Thus, the thin film transistor is designed with a special-shaped channel region including a narrowed portion so that the channel lengths of different areas of the channel region are different, so that the thin film transistor produces a leader effect similar to the hump effect, which increases the subthreshold swing of the thin film transistor, thereby improving the data voltage range (Data Range) of the thin film transistor, and thus making the driving current provided by the driving transistor insensitive to voltage fluctuations. When the display device adopts the above-mentioned thin film transistor as a driving transistor, the display quality can be significantly improved and the Mura defect can be improved. It is worth noting that the above-mentioned leader effect reflects the relationship between the gate voltage and the output current. When the thin film transistor is applied to the pixel driving circuit of the display device, the thin film transistor can operate in the saturation region (the saturation region reflects the relationship between the drain-source voltage and the output current).

[0073] It should be noted that, under a specific drain-source voltage Vds, different data voltages (corresponding to the gate voltage) correspond to different output currents, and thus to different brightness or grayscales of the light-emitting element or sub-pixel. The aforementioned Data Range is the difference between the gate voltage Vg or gate-source voltage Vgs corresponding to the output current corresponding to two grayscales. The larger this value, the smaller the change in output current caused by gate voltage fluctuations or errors, and the smaller the corresponding brightness or grayscale error. Therefore, increasing the Data Range of thin-film transistors can make the driving current insensitive to voltage fluctuations, improve the accuracy of the grayscale displayed by the sub-pixel, and thus significantly improve display quality and reduce mura defects.

[0074] On the other hand, increasing the subthreshold swing of the thin film transistor can enable the thin film transistor to generate a driving current (for example, 10 -11 A to 10 -7A) The range of gate voltage increases, and the driving current corresponds to different grayscales of the light-emitting element or sub-pixel; therefore, if the above-mentioned subthreshold swing increases, the range of gate voltage also increases, and the range of gate voltage allocated to a single grayscale also increases, that is, the data range is increased.

[0075] In some examples, as shown in Figures 2 and 3 , the channel region 113 further includes a main portion 113A connected to the narrowed portion 113B. The main portion 113A has a dimension in a first direction X that is greater than the maximum dimension of the narrowed portion 113B in the first direction X. For example, the channel lengths of the main portion 113A at different locations in a second direction Y intersecting the first direction X are substantially equal. It should be noted that the main portion may be any of the other portions described above; furthermore, the main portion may be located on one side of the narrowed portion or on both sides of the narrowed portion.

[0076] In some examples, as shown in FIG. 2 and FIG. 3 , the first conductive region 111 may be a source region, and the second conductive region 112 may be a drain region; or, the first conductive region 111 may be a drain region, and the second conductive region 112 may be a source region.

[0077] In some examples, the first conductive region 111 and the second conductive region 112 may be conductively connected by doping. Of course, the embodiments of the present disclosure include but are not limited to this, and the first conductive region and the second conductive region may also be conductively connected by other methods.

[0078] Figure 4A is a graph showing the output current of the main body and partially narrowed portion of a thin-film transistor according to one embodiment of the present disclosure; Figure 4B is a graph showing the final output current of the main body and partially narrowed portion of a thin-film transistor according to one embodiment of the present disclosure. The partially narrowed portion mentioned above refers to a portion of the narrowed portion having a certain width.

[0079] As shown in Figures 4A and 4B, Curve 1 shows the output current of the portion of the narrowed portion with a certain channel length, and Curve 2 shows the output current of the main portion. It can be seen that when the gate voltage on the first gate is insufficient to turn on the main portion, turning on only the narrowed portion, the thin-film transistor can produce a leading effect similar to the hump effect, turning on the narrowed portion, and the output current of the thin-film transistor is mainly from the narrowed portion. When the gate voltage on the first gate increases to a level that can turn on other portions of the channel region, the other portions can also turn on, and the output current of the thin-film transistor is mainly from the other portions.

[0080] In some examples, as shown in Figures 2 and 3, the narrowing portion 113B includes an extremely narrow portion 113C, and the dimension of the extremely narrow portion 113C in the first direction X is the minimum dimension of the narrowing portion 113B in the first direction X; the narrowing portion 113B is connected to the main body 113A, and the dimension of the narrowing portion 113B in the first direction X gradually decreases from the connection position between the narrowing portion 113B and the main body 113A to the extremely narrow portion 113C.

[0081] Figure 5 is a graph of the output current of a thin-film transistor provided in accordance with an embodiment of the present disclosure. As shown in Figure 5, since the dimension of the narrowed portion in the first direction X gradually decreases from the connection point between the narrowed portion and the main portion to the extremely narrow portion, the narrowed portion can be considered as a combination of multiple sub-portions with different channel lengths. Each sub-portion can produce the aforementioned hump effect, and ultimately, when superimposed together, the final output current curve of the thin-film transistor is a smooth curve. This allows different gate voltages to better correspond to different output currents, thereby enabling the thin-film transistor to operate more stably and avoiding defects such as grayscale discontinuity.

[0082] For example, as shown in Figures 2 and 5, the narrowed portion 113B can be divided into a first sub-portion 1 and second sub-portions 2 located on both sides of the first sub-portion 1, and the main portion 113A includes two third sub-portions 3 located in the two second sub-portions 2 away from the first sub-portion 1. As shown in Figure 5, as the gate voltage on the first gate increases, the first sub-portion 1 turns on first, then the second sub-portion 2 turns on, and finally the third sub-portion 3 turns on, thereby superimposing and forming a smooth output current curve.

[0083] In some examples, as shown in FIG2 , the narrowed portion 113B includes an edge extending from the main portion 113A to the extremely narrow portion 113C. The edge may be shaped like an oblique line, thereby gradually reducing the size of the narrowed portion in the first direction X. Of course, embodiments of the present disclosure include but are not limited to this, and the aforementioned edge may also include an arc, a step line, etc. It should be noted that the aforementioned oblique line refers to a straight line having an angle less than 90 degrees with the first direction X.

[0084] In some examples, the ratio of the width of the narrowed portion 113B in the second direction Y intersecting the first direction X to the width of the channel region 113 in the second direction Y is less than 20%. This configuration ensures that the final output current of the thin film transistor is still mainly from the main portion.

[0085] In some examples, the ratio of the area of ​​the narrowed portion 113B to the area of ​​the channel region 113 is in the range of 1 / 16 to 3 / 16. Thus, the thin film transistor can achieve a good leader effect while avoiding the thin film transistor exhibiting only the characteristics of the narrowed portion.

[0086] In some examples, the minimum dimension of the narrowed portion 113B in the first direction X is greater than or equal to 1 micron, and the ratio of the dimension of the narrowed portion 113B in a second direction Y intersecting the first direction X to the dimension of the channel region 113 in the second direction Y is in a range of 10%-20%. Thus, the thin film transistor can achieve a good leader effect while avoiding the thin film transistor only exhibiting the characteristics of the narrowed portion.

[0087] In some examples, as shown in FIG2 , the first conductive area 111 and the second conductive area 112 are spaced apart from each other, and define a connecting area 210 between the first conductive area 111 and the second conductive area 112. The narrowed portion 113B is located in the connecting area 210. The connecting area 210 overlaps both the first conductive area 111 and the second conductive area 112 in the first direction X. As a result, the narrowed portion can better produce the aforementioned leading effect.

[0088] In some examples, as shown in FIG2 , the connection region 210 includes a center line extending along the first direction X, and the narrowed portion 113B overlaps with the center line. Thus, when the above-mentioned thin film transistors are manufactured on a large scale, for example, when they are used in an array substrate, overlapping the narrowed portion with the center line extending along the first direction X of the connection region can avoid performance differences between different thin film transistors due to process errors. It should be noted that if the narrowed portion is formed at the edge of the channel region, if process errors occur in some thin film transistors, the area of ​​the narrowed portion may be smaller. However, if the narrowed portion is overlapped with the center line extending along the first direction X of the connection region, even if process errors occur in some thin film transistors, the narrowed portion is still located in the connection region and its area remains unchanged.

[0089] In some examples, as shown in FIG2 , the narrowed portion 113B includes a transition portion 113D connected to the extremely narrow portion 113C and the main portion 113A; the extremely narrow portion 113C may be a linear portion extending along the first direction X, or may be a strip portion extending along the first direction X, that is, the planar shape of the extremely narrow portion 113C includes a linear shape or a strip shape; in this case, the shape of the transition portion 113D includes a trapezoid.

[0090] In some examples, as shown in Figure 2, the first conductive region 111 is located on a first side of the channel region 113, and the second conductive region 112 is located on a second side of the channel region 113. The narrowed portion 113B narrows from both the first and second sides toward the centerline of the channel region 113 extending in a second direction Y intersecting the first direction X, i.e., from both sides of the channel region. Thus, the thin-film transistor can achieve good symmetry between the first and second conductive regions. It should be noted that the first and second sides of the channel region can be opposite sides in the first direction X.

[0091] In some examples, as shown in Figure 2, at least one of the first conductive region 111 and the second conductive region 112 includes a protrusion 111B / 112B that connects to the narrowed portion 113B. The shape of the protrusion 111B / 112B is complementary to the shape of the narrowed portion 113B. In other words, the areas on both sides of the narrowed portion in the first direction X are both conductive. As a result, the narrowed portion can better produce the aforementioned pilot effect. Furthermore, during the fabrication of the thin-film transistor, by aligning the shape of the protrusion with the shape of the narrowed portion, the active layer can be conveniently conductively fabricated using the first gate as a mask. It should be noted that the complementary shapes mentioned above mean that the planar shapes of the protrusion and the narrowed portion together form a rectangle.

[0092] In some examples, as shown in FIG2 , the shape of the protrusion 111B / 112B includes a triangle, thereby gradually reducing the size of the narrowed portion in the first direction X and making the final output current curve of the thin film transistor a smooth curve, thereby better matching different gate voltages with different output currents, thereby enabling the thin film transistor to operate more stably and avoiding defects such as grayscale discontinuity. Of course, embodiments of the present disclosure include but are not limited to this, and the shape of the protrusion may also include at least one of a trapezoidal, semicircular, and arched shape.

[0093] 2 , the first conductive region 111 includes a first protruding portion 111B connected to the narrowed portion 113B, and the second conductive region 112 includes a second protruding portion 112B connected to the narrowed portion 113. Both the first protruding portion 111B and the second protruding portion 112B are conductive regions.

[0094] 2 , the first protrusion 111B and the second protrusion 112B are mirror-symmetrical about a center line of the channel region 113 extending along the second direction Y. Thus, the thin film transistor can provide good symmetry between the first and second conductive regions.

[0095] In some examples, as shown in Figure 2, the orthographic projection of the first gate 130 on the active layer 110 has the same shape as the channel region 113C. Thus, the first gate can be used as a mask to perform a conductive process (e.g., a doping process) on the active layer to form the aforementioned special-shaped channel region.

[0096] In some examples, as shown in FIG2 , the first gate 130 may include a gate main portion corresponding to the main portion 113A of the channel region 113 and a gate narrowing portion corresponding to the narrowing portion 113B of the channel region 113. Since the shape of the orthographic projection of the first gate on the active layer is the same as the shape of the channel region, the positional relationship between the gate main portion and the gate narrowing portion, as well as the shapes and dimensions of the gate main portion and the gate narrowing portion themselves, can be found in the description and definition of the main portion and the narrowing portion of the channel region, and will not be further elaborated herein in the presently disclosed embodiments.

[0097] In some examples, as shown in FIG2 , the thin film transistor 100 further includes a first electrode 181 and a second electrode 182. The first electrode 181 is electrically connected to the first conductive region 111, and the second electrode 182 is electrically connected to the second conductive region 112. The first electrode 181 can be a source electrode, and the second electrode can be a drain electrode; alternatively, the first electrode 181 can be a drain electrode, and the second electrode 182 can be a source electrode.

[0098] In some examples, as shown in Figures 2 and 3, a passivation layer 170 is provided between the film layer where the first electrode 181 and the second electrode 182 are located and the active layer 110, and the first electrode 181 is electrically connected to the first conductive area 111 of the active layer 110 through a first via 171 penetrating the passivation layer 170, and the second electrode 182 is electrically connected to the second conductive area 112 of the active layer 110 through a second via 172 penetrating the passivation layer 170.

[0099] FIG6 is a schematic plan view of another thin film transistor provided in accordance with an embodiment of the present disclosure; FIG7 is a schematic cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0100] As shown in Figures 6 and 7, the thin film transistor 100 includes an active layer 110, a first gate insulating layer 120, and a first gate electrode 130. The active layer 110 includes a channel region 113 and a first conductive region 111 and a second conductive region 112 separated by the channel region 113. The conductivity of the first conductive region 111 and the second conductive region 112 is greater than that of the channel region 113. The first gate insulating layer 120 is located on a first side of the active layer 110, the first side being a side perpendicular to the main surface of the active layer 110. The first gate electrode 130 is located on a side of the first gate insulating layer 120 away from the active layer 110.

[0101] 6 , at least a portion of the first conductive region 111 , at least a portion of the channel region 113 , and at least a portion of the second conductive region 112 are arranged along the first direction X. For example, the entire first conductive region 111 , the entire channel region 113 , and the entire second conductive region 112 are arranged along the first direction X.

[0102] As shown in Figures 6 and 7, the first direction X can also be considered the length direction of the channel region 113. The channel region 113 includes a narrowing portion 113B. The average dimension of the narrowing portion 113B in the first direction X is smaller than the average dimension of the channel region 113 in the first direction X. In other words, the average channel length of the narrowing portion 113B is smaller than the average channel length of the entire channel region 113. From another perspective, the channel region 113 includes a first side 1131 and a second side 1132. The first side 1131 contacts the first conductive region 111, and the second side 1132 contacts the second conductive region 112. At least one of the first side 1131 and the second side 1132 includes a bend 1131B / 1132B. The bend 1131B / 1132B bends from the first conductive region 111 or the second conductive region 112 toward the channel region 113, thereby forming the narrowing portion 113B.

[0103] In the thin film transistor provided in the embodiment of the present disclosure, since at least one of the first side and the second side of the channel region includes a bend, and the bend bends from the first conductive region or the second conductive region toward the channel region, the portion of the channel region corresponding to the bend has a smaller channel length, and the other portion (also referred to as the main portion) has a larger channel length. At this time, taking the channel region of the thin film transistor as an N-type channel region as an example, when the gate voltage on the first gate is insufficient to turn on the other portions of the channel region and only the portion of the channel region corresponding to the bend is turned on, the thin film transistor can produce a leading effect similar to the hump effect, where the portion of the channel region corresponding to the bend is turned on first, and the output current of the thin film transistor is mainly from this portion; and when the gate voltage on the first gate increases to a level that can turn on the other portions of the channel region, the other portions can also be turned on, and the output current of the thin film transistor is mainly from the other portions. Thus, the thin film transistor is designed with a special-shaped channel region including the above-mentioned bent portion, so that the channel lengths of different areas of the channel region are different, so that the thin film transistor produces a leading effect similar to the hump effect, thereby increasing the subthreshold swing of the thin film transistor, thereby improving the data range of the thin film transistor, and further making the driving current provided by the driving transistor insensitive to voltage fluctuations. When the display device adopts the above-mentioned thin film transistor as a driving transistor, it can significantly improve the display quality and improve the mura defect. Regarding the principle of how the data range is increased by increasing the subthreshold swing of the thin film transistor, please refer to the relevant description of Figures 2 and 3, which will not be repeated here.

[0104] In some examples, as shown in Figure 6, the first direction X is perpendicular to the second direction Y. Of course, the embodiments of the present disclosure include but are not limited to this, and the first direction and the second direction may also intersect and form an angle not equal to 90 degrees.

[0105] In some examples, as shown in Figure 6, the first side 1131 includes a first bending portion 1131B, which bends from the first conductive region 111 to the channel region 113, and the second side 1132 includes a second bending portion 1132B, which bends from the second conductive region 112 to the channel region 113, so that it can be bent from both sides of the channel region to the center of the channel region.

[0106] In some examples, as shown in FIG6 , the first bend portion 1131B and the second bend portion 1132B overlap in the first direction X, thereby forming a narrowed portion of the channel region. Of course, embodiments of the present disclosure include but are not limited to this, and the first bend portion and the second bend portion may also be staggered in the first direction to form two narrowed portions.

[0107] In some examples, as shown in FIG6 , the first bend portion 1131B and the second bend portion 1132B include oblique lines, such as two oblique lines forming a V-shape; the oblique lines are straight lines with an angle less than 90 degrees with the first direction X. Of course, the embodiments of the present disclosure include but are not limited to this, and the first bend portion and the second bend portion may also include arcs or stepped lines.

[0108] In some examples, as shown in FIG6 , the channel region 113 further includes a main portion 113A connected to the narrowed portion 113B. The main portion 113A has a dimension in the first direction X that is greater than the maximum dimension of the narrowed portion 113B in the first direction X. In this case, the first side 1131 includes a straight line connected to the first bent portion 1131B, and the second side 1132 also includes a straight line connected to the second bent portion 1132B. These straight lines may extend along the second direction Y.

[0109] In some examples, as shown in FIG6 , the first edge 1131 includes the first bend 1131B and two straight lines on both sides of the first bend 1131B; the second edge 1132 includes the second bend 1132B and two straight lines on both sides of the second bend 1132B.

[0110] In some examples, as shown in FIG6 , the first conductive region 111 may be a source region, and the second conductive region 112 may be a drain region; or the first conductive region 111 may be a drain region, and the second conductive region 112 may be a source region.

[0111] In some examples, the first conductive region 111 and the second conductive region 112 may be conductively connected by doping. Of course, the embodiments of the present disclosure include but are not limited to this, and the first conductive region and the second conductive region may also be conductively connected by other methods.

[0112] In some examples, as shown in Figures 6 and 7, the thin film transistor 100 also includes a second gate insulating layer 140 and a second gate 150; the second gate insulating layer 140 is located on the second side of the active layer 110, and the second side of the active layer 110 and the first side of the active layer 110 mentioned above may be two opposite sides in a direction perpendicular to the main surface of the active layer 110, such as an upper and lower sides; the second gate 150 is located on the side of the second gate insulating layer 140 away from the active layer 110, and the orthographic projection of the second gate 150 on the active layer 110 completely covers the orthographic projection of the first gate 130 on the active layer 110.

[0113] In some examples, as shown in FIG. 6 , the first gate 130 and the second gate 150 may be electrically connected via a first connection electrode 191 .

[0114] In the thin film transistor provided in this example, by connecting the second gate and the first gate, and the orthographic projection of the second gate on the active layer completely covering the orthographic projection of the first gate on the active layer, the thin film transistor can be formed into a dual-gate structure, thereby increasing the on-state current Ion, for example, it can be increased to 3 to 5 times that of the thin film transistor without the above-mentioned second gate. Therefore, the thin film transistor can greatly improve the charge and discharge efficiency; combined with the design of the above-mentioned special-shaped channel region, the thin film transistor can meet the requirements of high refresh rate and high-resolution products for on-state current, and can increase the subthreshold swing, so that the thin film transistor is insensitive to the gate voltage, significantly improves the display quality, and improves Mura. In addition, by making the orthographic projection of the second gate on the active layer completely cover the orthographic projection of the first gate on the active layer, the thin film transistor can avoid the characteristic deviation caused by the second gate being retracted into the range of the orthographic projection of the first gate.

[0115] In some examples, as shown in FIG6 , the channel region 113 includes a first edge 1131 and a second edge 1132. The first edge 1131 contacts the first conductive region 111, and the second edge 1132 contacts the second conductive region 112. The shortest distance between the first edge 1131 and the edge of the orthographic projection of the second gate 150 on the active layer 110 is greater than 1.0 micron. The shortest distance between the second edge 1132 and the edge of the orthographic projection of the second gate 150 on the active layer 110 is greater than 1.0 micron. Thus, by setting the aforementioned g value, the thin film transistor can better avoid characteristic deviation and also prevent characteristic differences between different thin film transistors during mass production due to process errors.

[0116] 6 , the first conductive region 111 includes a first protruding portion 111B connected to the first bent portion 1131B, and the second conductive region 112 includes a second protruding portion 112B connected to the second bent portion 1132B. Both the first protruding portion 111B and the second protruding portion 112B are conductive regions.

[0117] 6 , the first protrusion 111B and the second protrusion 112B are mirror-symmetrical about a center line of the channel region 113 extending along the second direction Y. Thus, the thin film transistor can provide good symmetry between the first and second conductive regions.

[0118] 6 , the orthographic projection of the first gate 130 on the active layer 110 is the same as the shape of the channel region 113C. Thus, the first gate can be used as a mask to perform a conductive process (e.g., a doping process) on the active layer to form the aforementioned special-shaped channel region.

[0119] In some examples, as shown in FIG6 , the first gate 130 may include a gate main portion corresponding to the main portion 113A of the channel region 113 and a gate narrowing portion corresponding to the narrowing portion 113B of the channel region 113. Since the shape of the orthographic projection of the first gate on the active layer is the same as the shape of the channel region, the positional relationship between the gate main portion and the gate narrowing portion, as well as the shapes and dimensions of the gate main portion and the gate narrowing portion themselves, can be found in the description and definition of the main portion and the narrowing portion of the channel region, and will not be further elaborated herein in the presently disclosed embodiments.

[0120] In some examples, as shown in FIG6 , the thin film transistor 100 further includes a first electrode 181 and a second electrode 182. The first electrode 181 is electrically connected to the first conductive region 111, and the second electrode 182 is electrically connected to the second conductive region 112. The first electrode 181 can be a source electrode, and the second electrode can be a drain electrode; alternatively, the first electrode 181 can be a drain electrode, and the second electrode 182 can be a source electrode.

[0121] In some examples, as shown in Figures 6 and 7, a passivation layer 170 is provided between the film layer where the first electrode 181 and the second electrode 182 are located and the active layer 110, and the first electrode 181 is electrically connected to the first conductive area 111 of the active layer 110 through a first via 171 penetrating the passivation layer 170, and the second electrode 182 is electrically connected to the second conductive area 112 of the active layer 110 through a second via 172 penetrating the passivation layer 170.

[0122] FIG8 is a schematic plan view of another thin film transistor provided in accordance with an embodiment of the present disclosure; FIG9 is a schematic cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0123] As shown in Figures 8 and 9, the thin film transistor 100 includes an active layer 110, a first gate insulating layer 120, a first gate electrode 130, a second gate insulating layer 140, a second gate electrode 150, a first electrode 181, and a second electrode 182. The active layer 110 includes a channel region 113 and a first conductive region 111 and a second conductive region 112 separated by the channel region 113. The conductivity of the first conductive region 111 and the second conductive region 112 is greater than that of the channel region 113. The first gate insulating layer 120 is located on a first side of the active layer 110, and the second gate insulating layer 140 is located on a second side of the active layer 110. The first side and the second side are opposite sides in a direction perpendicular to the main surface of the active layer 110.

[0124] As shown in Figures 8 and 9, the first gate 130 is located on a side of the first gate insulating layer 120 away from the active layer 110, and the second gate 150 is located on a side of the second gate insulating layer 120 away from the active layer 110. At least a portion of the first conductive region 111, at least a portion of the channel region 113, and at least a portion of the second conductive region 112 are arranged along a first direction X. The first electrode 181 is electrically connected to the first conductive region 111, and the second electrode 182 is electrically connected to the second conductive region 112. For example, the first conductive region 111 can be a source region, the first electrode 181 can be a source electrode, the second conductive region 112 can be a drain region, and the second electrode 182 can be a drain electrode. Alternatively, the first conductive region 111 can be a drain region, the first electrode 181 can be a drain electrode, the second conductive region 112 can be a source region, and the second electrode 182 can be a source electrode.

[0125] As shown in Figures 8 and 9, the first direction X can also be considered as the length direction of the channel region 113. The channel region 113 includes a narrowed portion 113B. The average size of the narrowed portion 113B in the first direction X is smaller than the average size of the channel region 113 in the first direction X. In other words, the average channel length of the narrowed portion 113B is smaller than the average channel length of the entire channel region 113.

[0126] In the thin film transistor provided in the embodiment of the present disclosure, since the channel region includes a narrowing portion, and the average size of the narrowing portion in the first direction is smaller than the average size of the channel in the first direction, the channel region has a smaller channel length in the narrowing portion and a larger channel length in the other portion (also referred to as the main portion). In this case, taking the channel region of the thin film transistor as an N-type channel region as an example, when the gate voltage on the first gate is insufficient to turn on the other portions of the channel region and only the narrowing portion is turned on, the thin film transistor can produce a leader effect similar to the hump effect, the narrowing portion is turned on, and the output current of the thin film transistor is mainly from the narrowing portion; when the gate voltage on the first gate increases to a level that can turn on the other portions of the channel region, the other portions can also be turned on, and the output current of the thin film transistor is mainly from the other portions. Therefore, by designing a special-shaped channel region including a narrowing portion, the channel lengths of different regions of the channel region are different, causing the thin film transistor to produce a leader effect similar to the hump effect, thereby increasing the subthreshold swing of the thin film transistor, thereby improving the data range of the thin film transistor, and further making the drive current provided by the drive transistor insensitive to voltage fluctuations. When a display device uses the above-mentioned thin film transistor as a driving transistor, it can significantly improve display quality and reduce mura defects. For the principle of how increasing the subthreshold swing of the thin film transistor increases the data range, please refer to the relevant description of Figures 2 and 3, which will not be repeated here.

[0127] In some examples, as shown in Figure 8, the first direction X and the second direction Y are perpendicular to each other. Of course, the embodiments of the present disclosure include but are not limited to this, and the first direction and the second direction may also intersect and form an angle not equal to 90 degrees.

[0128] In some examples, as shown in FIG8 , the first electrode 181 is electrically connected to the second gate 150, for example, via a via connection structure. Thus, based on the aforementioned special-shaped channel region, by connecting the first electrode to the second gate, the thin film transistor can further increase the subthreshold swing, thereby further improving the data range of the thin film transistor, thereby making the drive current provided by the drive transistor insensitive to voltage fluctuations.

[0129] In some examples, as shown in FIG. 8 , the second gate 150 includes an extension portion, and the first electrode 181 is connected to the extension portion of the second gate 150 through a via connection structure.

[0130] 8 , the orthographic projection of the second gate 150 on the active layer 110 completely covers the orthographic projection of the first gate 130 on the active layer 110. Thus, the thin film transistor can avoid characteristic deviation caused by the second gate being retracted into the orthographic projection of the first gate.

[0131] In some examples, as shown in FIG8 , the channel region 113 includes a first edge 1131 and a second edge 1132. The first edge 1131 contacts the first conductive region 111, and the second edge 1132 contacts the second conductive region 112. The shortest distance between the first edge 1131 and the edge of the orthographic projection of the second gate 150 on the active layer 110 is greater than 1.0 micron. The shortest distance between the second edge 1132 and the edge of the orthographic projection of the second gate 150 on the active layer 110 is greater than 1.0 micron. Thus, by setting the aforementioned g value, the thin film transistor can better avoid characteristic deviation and also prevent characteristic differences between different thin film transistors during mass production due to process errors.

[0132] In some examples, as shown in Figure 8, the first side 1131 includes a first bending portion 1131B, which bends from the first conductive region 111 to the channel region 113, and the second side 1132 includes a second bending portion 1132B, which bends from the second conductive region 112 to the channel region 113, so that it can be bent from both sides of the channel region to the center of the channel region.

[0133] In some examples, as shown in FIG8 , the first bend portion 1131B and the second bend portion 1132B overlap in the first direction X, thereby forming a narrowed portion of the channel region. Of course, embodiments of the present disclosure include but are not limited to this, and the first bend portion and the second bend portion may also be staggered in the first direction to form two narrowed portions.

[0134] In some examples, as shown in FIG8 , the first bend portion 1131B and the second bend portion 1132B include oblique lines, such as two oblique lines forming a V-shape; the oblique lines are straight lines with an angle less than 90 degrees with the first direction X. Of course, the embodiments of the present disclosure include but are not limited to this, and the first bend portion and the second bend portion may also include arcs or stepped lines.

[0135] In some examples, as shown in FIG8 , the channel region 113 further includes a main portion 113A connected to the narrowed portion 113B. The main portion 113A has a dimension in the first direction X that is greater than the maximum dimension of the narrowed portion 113B in the first direction X. In this case, the first side 1131 includes a straight line connected to the first bent portion 1131B, and the second side 1132 also includes a straight line connected to the second bent portion 1132B. These straight lines may extend along the second direction Y.

[0136] In some examples, as shown in FIG8 , the first edge 1131 includes the first bend 1131B and two straight lines on both sides of the first bend 1131B; the second edge 1132 includes the second bend 1132B and two straight lines on both sides of the second bend 1132B.

[0137] In some examples, as shown in FIG8 , the first conductive region 111 may be a source region, and the second conductive region 112 may be a drain region; or, the first conductive region 111 may be a drain region, and the second conductive region 112 may be a source region.

[0138] In some examples, the first conductive region 111 and the second conductive region 112 may be conductively connected by doping. Of course, the embodiments of the present disclosure include but are not limited to this, and the first conductive region and the second conductive region may also be conductively connected by other methods.

[0139] 8 , the first conductive region 111 includes a first protruding portion 111B connected to the first bent portion 1131B, and the second conductive region 112 includes a second protruding portion 112B connected to the second bent portion 1132B. Both the first protruding portion 111B and the second protruding portion 112B are conductive regions.

[0140] 8 , the first protrusion 111B and the second protrusion 112B are mirror-symmetrical about a center line of the channel region 113 extending along the second direction Y. Thus, the thin film transistor can provide good symmetry between the first and second conductive regions.

[0141] In some examples, as shown in Figure 8, the orthographic projection of the first gate 130 on the active layer 110 has the same shape as the channel region 113C. Thus, the first gate can be used as a mask to perform a conductive process (e.g., a doping process) on the active layer to form the aforementioned special-shaped channel region.

[0142] In some examples, as shown in FIG8 , the first gate 130 may include a gate main portion corresponding to the main portion 113A of the channel region 113 and a gate narrowing portion corresponding to the narrowing portion 113B of the channel region 113. Since the shape of the orthographic projection of the first gate on the active layer is the same as the shape of the channel region, the positional relationship between the gate main portion and the gate narrowing portion, as well as the shapes and dimensions of the gate main portion and the gate narrowing portion themselves, can be found in the description and definition of the main portion and the narrowing portion of the channel region, and will not be further elaborated herein in the presently disclosed embodiments.

[0143] In some examples, as shown in Figures 8 and 9, a passivation layer 170 is provided between the film layer where the first electrode 181 and the second electrode 182 are located and the active layer 110, and the first electrode 181 is electrically connected to the first conductive area 111 of the active layer 110 through a first via 171 penetrating the passivation layer 170, and the second electrode 182 is electrically connected to the second conductive area 112 of the active layer 110 through a second via 172 penetrating the passivation layer 170.

[0144] FIG10 is a schematic plan view of another thin film transistor provided in accordance with an embodiment of the present disclosure; FIG11 is a schematic cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0145] As shown in Figures 10 and 11, the thin film transistor 100 includes an active layer 110, a first gate insulator 120, and a first gate electrode 130. The active layer 110 includes a channel region 113 and a first conductive region 111 and a second conductive region 112 separated by the channel region 113. The first gate insulator 120 is located on a first side of the active layer 110, where the first side is perpendicular to the main surface of the active layer 110. The first gate electrode 130 is located on a side of the first gate insulator 120 away from the active layer 110. At least a portion of the first conductive region 111, at least a portion of the channel region 113, and at least a portion of the second conductive region 112 are arranged along a first direction X. In this case, the first direction X can also be considered the length direction of the channel region 113. The channel region 113 includes a plurality of narrowed portions 113B arranged along a second direction Y intersecting the first direction X, and an average size of each narrowed portion 113B in the first direction X is smaller than an average size of the channel region 113 in the first direction X. That is, an average channel length of the narrowed portion 113B is smaller than an average channel length of the entire channel region 113.

[0146] In the aforementioned thin-film transistor, the channel region includes multiple narrowed portions arranged along a second direction Y intersecting the first direction X. Each narrowed portion can produce a leader effect similar to the hump effect. Thus, by designing a shaped channel region including multiple narrowed portions, the thin-film transistor has different channel lengths in different areas of the channel region, causing the thin-film transistor to produce a leader effect similar to the hump effect. This increases the subthreshold swing of the thin-film transistor, thereby improving the data range of the thin-film transistor and making the drive current provided by the drive transistor insensitive to voltage fluctuations. When a display device uses this thin-film transistor as a drive transistor, it can significantly improve display quality and reduce mura defects.

[0147] In some examples, the first direction X and the second direction Y are perpendicular to each other. Of course, the embodiments of the present disclosure include but are not limited to this. The first direction X and the second direction Y may intersect each other at a certain angle, but are not strictly perpendicular to each other.

[0148] In some examples, the number of narrowed portions included in the channel region can be set according to actual conditions, and the embodiments of the present disclosure are not limited thereto.

[0149] In some examples, as shown in FIG10 , the channel region 113 includes a main portion 113A and a narrowed portion 113B, wherein the average size of the narrowed portion 113B in the first direction X is smaller than the average size of the main portion 113A in the first direction X; and the plurality of narrowed portions 113B are staggered in the first direction X.

[0150] In some examples, as shown in FIG10 , the channel region 113 includes two narrowed portions 113B, the first conductive region 111 is located on a first side of the channel region 113, and the second conductive region 112 is located on a second side of the channel region 113; one of the two narrowed portions 113B included in the channel region 113 is narrowed from the first side toward the center line of the channel region 113 extending along a second direction Y intersecting the first direction X, and the other of the two narrowed portions 113B included in the channel region 113 is narrowed from the second side toward the center line of the channel region 113 extending along the second direction Y intersecting the first direction X.

[0151] In some examples, as shown in FIG10 , the first conductive region 111 includes a first protruding portion 111B connected to one of the two narrowed portions 113B included in the channel region 113, and the second conductive region 112 includes a second protruding portion 112B connected to the other of the two narrowed portions 113B included in the channel region 113. Both the first protruding portion 111B and the second protruding portion 112B are conductive regions.

[0152] For example, as shown in FIG10 , the first conductive region 111 is a source region, and the second conductive region 112 is a drain region; or the first conductive region 111 is a drain region, and the second conductive region 112 is a source region.

[0153] In some examples, as shown in FIG10 , the thin film transistor 100 further includes a first electrode 181 and a second electrode 182. The first electrode 181 is electrically connected to the first conductive region 111, and the second electrode 182 is electrically connected to the second conductive region 112. The first electrode 181 can be a source electrode, and the second electrode can be a drain electrode; alternatively, the first electrode 181 can be a drain electrode, and the second electrode 182 can be a source electrode.

[0154] In some examples, as shown in Figures 10 and 11, a passivation layer 170 is provided between the film layer where the first electrode 181 and the second electrode 182 are located and the active layer 110, and the first electrode 181 is electrically connected to the first conductive area 111 of the active layer 110 through a first via 171 penetrating the passivation layer 170, and the second electrode 182 is electrically connected to the second conductive area 112 of the active layer 110 through a second via 172 penetrating the passivation layer 170.

[0155] FIG12 is a schematic plan view of another thin film transistor provided in accordance with an embodiment of the present disclosure; FIG13 is a schematic cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0156] As shown in Figures 12 and 13, the thin film transistor 100 includes an active layer 110, a first gate insulator 120, and a first gate 130. The active layer 110 includes a channel region 113 and a first conductive region 111 and a second conductive region 112 separated by the channel region 113. The first gate insulator 120 is located on a first side of the active layer 110, where the first side is perpendicular to the main surface of the active layer 110. The first gate 130 is located on a side of the first gate insulator 120 away from the active layer 110. At least a portion of the first conductive region 111, at least a portion of the channel region 113, and at least a portion of the second conductive region 112 are arranged along a first direction X. In this case, the first direction X can also be considered the length direction of the channel region 113. The channel region 113 includes a main portion 113A and a narrowed portion 113B. The average size of the narrowed portion 113B in the first direction X is smaller than the average size of the main portion 113A in the first direction X. That is, the average channel length of the narrowed portion 113B is smaller than the average channel length of the entire channel region 113.

[0157] As shown in Figures 12 and 13, the narrowing portion 113B includes an extremely narrow portion 113C, and the dimension of the extremely narrow portion 113C in the first direction X is the minimum dimension of the narrowing portion 113B in the first direction X; the narrowing portion 113B is connected to the main body 113A, and the dimension of the narrowing portion 113B in the first direction X gradually decreases from the connection position between the narrowing portion 113B and the main body 113A to the extremely narrow portion 113C. The narrowing portion 113B includes an edge extending from the main body 113A to the extremely narrow portion 113C, and the shape of the edge includes an arc or a curve. In other words, the gradual reduction of the dimension of the narrowing portion in the first direction X can be achieved by providing an arc-shaped or curved edge. It should be noted that although the arc or curve shown in Figure 12 is an arc or curve concave toward the channel region, the embodiments of the present disclosure include but are not limited to this, and the above-mentioned edge may also be an arc or curve protruding from the channel region.

[0158] In the aforementioned thin-film transistor, a narrowed portion with an arc-shaped or curved edge can also produce a leading effect similar to the hump effect. Thus, by designing the thin-film transistor to include the aforementioned profiled channel region, different regions of the channel region have different channel lengths, causing the thin-film transistor to produce a leading effect similar to the hump effect. This increases the subthreshold swing of the thin-film transistor, thereby improving the data range of the thin-film transistor and making the drive current provided by the drive transistor insensitive to voltage fluctuations. When a display device uses the aforementioned thin-film transistor as a drive transistor, it can significantly improve display quality and reduce mura defects.

[0159] In some examples, as shown in FIG12 , first conductive region 111 includes a first protruding portion 111B connected to narrowed portion 113B, and second conductive region 112 includes a second protruding portion 112B connected to narrowed portion 113B. Both first protruding portion 111B and second protruding portion 112B are conductive regions. The shapes of first protruding portion 111B and second protruding portion 112B complement those of narrowed portion 113B.

[0160] In some examples, as shown in FIG. 12 , the first conductive region 111 is a source region, and the second conductive region 112 is a drain region; or, the first conductive region 111 is a drain region, and the second conductive region 112 is a source region.

[0161] In some examples, as shown in FIG12 , the thin film transistor 100 further includes a first electrode 181 and a second electrode 182. The first electrode 181 is electrically connected to the first conductive region 111, and the second electrode 182 is electrically connected to the second conductive region 112. The first electrode 181 can be a source electrode, and the second electrode can be a drain electrode; alternatively, the first electrode 181 can be a drain electrode, and the second electrode 182 can be a source electrode.

[0162] In some examples, as shown in Figures 12 and 13, a passivation layer 170 is provided between the film layer where the first electrode 181 and the second electrode 182 are located and the active layer 110, and the first electrode 181 is electrically connected to the first conductive area 111 of the active layer 110 through a first via 171 penetrating the passivation layer 170, and the second electrode 182 is electrically connected to the second conductive area 112 of the active layer 110 through a second via 172 penetrating the passivation layer 170.

[0163] FIG14 is a schematic plan view of another thin film transistor provided in accordance with an embodiment of the present disclosure; FIG15 is a schematic cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0164] As shown in Figures 14 and 15, the thin film transistor 100 includes an active layer 110, a first gate insulator 120, and a first gate electrode 130. The active layer 110 includes a channel region 113 and a first conductive region 111 and a second conductive region 112 separated by the channel region 113. The first gate insulator 120 is located on a first side of the active layer 110, where the first side is perpendicular to the main surface of the active layer 110. The first gate electrode 130 is located on a side of the first gate insulator 120 away from the active layer 110. At least a portion of the first conductive region 111, at least a portion of the channel region 113, and at least a portion of the second conductive region 112 are arranged along a first direction X. In this case, the first direction X can also be considered the length direction of the channel region 113.

[0165] As shown in Figures 14 and 15, the channel region 113 includes a main body 113A and a narrowed portion 113B located on both sides of the main body 113A. The average size of the narrowed portion 113B in the first direction X is smaller than the average size of the main body 113A in the first direction X. That is, the average channel length of the narrowed portion 113B is smaller than the average channel length of the channel region 113 as a whole.

[0166] In the aforementioned thin-film transistor, the constricted portions located on either side of the main body can also produce a leading effect similar to the hump effect. Thus, by designing the thin-film transistor to include the aforementioned profiled channel region, the channel lengths in different regions of the channel region vary, causing the thin-film transistor to produce a leading effect similar to the hump effect. This increases the subthreshold swing of the thin-film transistor, thereby improving the data range of the thin-film transistor and making the drive current provided by the drive transistor insensitive to voltage fluctuations. When a display device uses the aforementioned thin-film transistor as a drive transistor, it can significantly improve display quality and reduce mura defects.

[0167] In some examples, as shown in FIG. 14 , the first conductive area 111 and the second conductive area 112 are spaced apart from each other and define a connection area 210 between the first conductive area 111 and the second conductive area 112 . The narrowed portion 113B is located in the connection area 210 .

[0168] In some examples, as shown in FIG. 14 , the connection region 210 includes a center line extending along the first direction X, and the narrowed portions 113B located on both sides of the main body portion 113A do not overlap with the center line.

[0169] In some examples, as shown in FIG. 14 , the first conductive region 111 is a source region, and the second conductive region 112 is a drain region; or, the first conductive region 111 is a drain region, and the second conductive region 112 is a source region.

[0170] In some examples, as shown in Figures 14 and 15, the thin film transistor 100 further includes a first electrode 181 and a second electrode 182. The first electrode 181 is electrically connected to the first conductive region 111, and the second electrode 182 is electrically connected to the second conductive region 112. The first electrode 181 can be a source electrode, and the second electrode can be a drain electrode; alternatively, the first electrode 181 can be a drain electrode, and the second electrode 182 can be a source electrode.

[0171] FIG16 is a plan view schematically illustrating another thin film transistor provided in accordance with an embodiment of the present disclosure; FIG17 is a cross-sectional view schematically illustrating another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0172] As shown in Figures 16 and 17, the thin film transistor 100 includes an active layer 110, a first gate insulator 120, and a first gate electrode 130. The active layer 110 includes a channel region 113 and a first conductive region 111 and a second conductive region 112 separated by the channel region 113. The conductivity of the first conductive region 111 and the second conductive region 112 is greater than that of the channel region 113. The first gate insulator 120 is located on a first side of the active layer 110, the first side being a side perpendicular to the main surface of the active layer 110. The first gate electrode 130 is located on a side of the first gate insulator 120 away from the active layer 110. At least a portion of the first conductive region 111, at least a portion of the channel region 113, and at least a portion of the second conductive region 112 are arranged along a first direction X. In this case, the first direction X can also be considered the length direction of the channel region 113. The channel region 113 includes a narrowed portion 113B. The average size of the narrowed portion 113B in the first direction X is smaller than the average size of the channel region 113 in the first direction X. That is, the average channel length of the narrowed portion 113B is smaller than the average channel length of the entire channel region 113 .

[0173] In the thin film transistor provided in the embodiment of the present disclosure, since the channel region includes a narrowing portion, and the average size of the narrowing portion in the first direction is smaller than the average size of the channel in the first direction, the channel region has a smaller channel length in the narrowing portion and a larger channel length in the other portion (also referred to as the main portion). In this case, taking the channel region of the thin film transistor as an N-type channel region as an example, when the gate voltage on the first gate is insufficient to turn on the other portions of the channel region and only the narrowing portion is turned on, the thin film transistor can produce a leader effect similar to the hump effect, the narrowing portion is turned on, and the output current of the thin film transistor is mainly from the narrowing portion; when the gate voltage on the first gate increases to a level that can turn on the other portions of the channel region, the other portions can also be turned on, and the output current of the thin film transistor is mainly from the other portions. Therefore, by designing a special-shaped channel region including a narrowing portion, the channel lengths of different regions of the channel region are different, causing the thin film transistor to produce a leader effect similar to the hump effect, thereby increasing the subthreshold swing of the thin film transistor, thereby improving the data range of the thin film transistor, and further making the drive current provided by the drive transistor insensitive to voltage fluctuations. When a display device uses the above-mentioned thin film transistor as a driving transistor, it can significantly improve display quality and reduce mura defects. For the principle of how increasing the subthreshold swing of the thin film transistor increases the data range, please refer to the relevant description of Figures 2 and 3, which will not be repeated here.

[0174] In some examples, as shown in Figure 16, the first direction X is perpendicular to the second direction Y. Of course, the embodiments of the present disclosure include but are not limited to this, and the first direction and the second direction may also intersect and form an angle not equal to 90 degrees.

[0175] In some examples, as shown in FIG16 , the first conductive area 111 and the second conductive area 112 are spaced apart from each other, and define a connecting area 210 between the first conductive area 111 and the second conductive area 112. The narrowed portion 113B is located in the connecting area 210. The connecting area 210 overlaps both the first conductive area 111 and the second conductive area 112 in the first direction X. As a result, the narrowed portion can better produce the aforementioned leading effect.

[0176] In some examples, as shown in FIG16 , unlike the thin film transistor shown in FIG2 , the connection region 210 includes a centerline extending along the first direction X, and the narrowed portion 113B is offset from the centerline, i.e., does not overlap. FIG18 is a plan view schematic diagram of another thin film transistor provided in an embodiment of the present disclosure. As shown in FIG18 , the thin film transistor 100 includes an active layer 110 , a first gate insulator (not shown), and a first gate 130 ; the active layer 110 includes a channel region 113 and a first conductive region 111 and a second conductive region 112 separated by the channel region 113 . The first gate insulating layer 120 is located on a first side of the active layer 110, where the first side is a side perpendicular to the main surface of the active layer 110. The first gate 130 is located on a side of the first gate insulating layer 120 away from the active layer 110. At least a portion of the first conductive region 111, at least a portion of the channel region 113, and at least a portion of the second conductive region 112 are arranged along a first direction X. In this case, the first direction X can also be considered as the length direction of the channel region 113.

[0177] As shown in FIG18 , the planar shape of the channel region 113 is generally rectangular, and the planar shape of the gate 130 is generally L-shaped. The gate 130 includes a first rectangular portion 132 and a second rectangular portion 134, with the first rectangular portion of the gate 130 overlapping the channel region 113. The channel region 113 also includes a first extension portion 1112 connected to the first conductive region 111 and a second extension portion 1122 connected to the second conductive region 112. The first extension portion 1112 and the second extension portion 1122 can be connected to other conductive structures.

[0178] As shown in Figure 18, the channel region 113 includes a main portion 113A and a narrowed portion 113B. The average size of the narrowed portion 113B in the first direction X is smaller than the average size of the main portion 113A in the first direction X. That is, the average channel length of the narrowed portion 113B is smaller than the average channel length of the channel region 113 as a whole.

[0179] In the aforementioned thin-film transistor, the narrowed portion can produce a leading effect similar to the hump effect. Thus, by designing the thin-film transistor to include the aforementioned profiled channel region, the channel lengths in different regions of the channel region vary. This creates a leading effect similar to the hump effect in the thin-film transistor, increasing the subthreshold swing of the thin-film transistor and thereby improving the data range of the thin-film transistor. This in turn makes the drive current provided by the driver transistor insensitive to voltage fluctuations. When a display device employs the aforementioned thin-film transistor as a driver transistor, it can significantly improve display quality and mitigate mura defects.

[0180] In some examples, as shown in FIG18 , the thin film transistor 100 further includes a second gate 150 , which is located on a side of the active layer 110 away from the first gate 130 and is insulated from the active layer 110 ; the orthographic projection of the second gate 150 on the active layer 110 completely covers the orthographic projection of the first gate 130 on the active layer 110 , thereby forming a dual-gate thin film transistor.

[0181] In some examples, as shown in FIG18 , the first conductive region 111 is electrically connected to the second gate 150. For example, the first extension 1112 of the channel region 113 is electrically connected to the second gate 150 via the third connection electrode 191. Thus, based on the aforementioned special-shaped channel region, by connecting the first conductive region to the second gate, the thin-film transistor can further increase the subthreshold swing, thereby further improving the data range of the thin-film transistor and making the drive current provided by the driver transistor insensitive to voltage fluctuations.

[0182] FIG19 is a schematic plan view of another thin film transistor provided in accordance with an embodiment of the present disclosure. As shown in FIG19 , the thin film transistor 100 includes an active layer 110, a first gate insulator (not shown), and a first gate 130. The active layer 110 includes a channel region 113 and a first conductive region 111 and a second conductive region 112 separated by the channel region 113. The first gate insulator 120 is located on a first side of the active layer 110, where the first side is perpendicular to the main surface of the active layer 110. The first gate 130 is located on a side of the first gate insulator 120 away from the active layer 110. At least a portion of the first conductive region 111, at least a portion of the channel region 113, and at least a portion of the second conductive region 112 are arranged along a first direction X. In this case, the first direction X can also be considered the length direction of the channel region 113.

[0183] As shown in FIG19 , the planar shape of the channel region 113 is generally rectangular, and the planar shape of the gate 130 is generally L-shaped. The gate 130 includes a first rectangular portion 132 and a second rectangular portion 134, with the first rectangular portion of the gate 130 overlapping the channel region 113. The channel region 113 also includes a first extension portion 1112 connected to the first conductive region 111 and a second extension portion 1122 connected to the second conductive region 112. The first extension portion 1112 and the second extension portion 1122 can be connected to other conductive structures.

[0184] As shown in FIG19 , the channel region 113 includes a main portion 113A and two narrowed portions 113B. A virtual straight line extending in the first direction passes through a position where one of the two narrowed portions 113B is connected to the first extension portion 1112 and the first conductive region 111. Another virtual straight line extending in the first direction passes through a position where the other of the two narrowed portions 113B is connected to the second extension portion 1122 and the second conductive region 112, thereby better enabling the thin film transistor to produce a leading effect similar to the hump effect.

[0185] FIG20 is a schematic plan view of another thin film transistor provided in accordance with an embodiment of the present disclosure. As shown in FIG20 , the thin film transistor 100 includes an active layer 110, a first gate insulator (not shown), and a first gate 130. The active layer 110 includes a channel region 113 and a first conductive region 111 and a second conductive region 112 separated by the channel region 113. The first gate insulator 120 is located on a first side of the active layer 110, where the first side is perpendicular to the main surface of the active layer 110. The first gate 130 is located on a side of the first gate insulator 120 away from the active layer 110. At least a portion of the first conductive region 111, at least a portion of the channel region 113, and at least a portion of the second conductive region 112 are arranged along a first direction X. In this case, the first direction X can also be considered the length direction of the channel region 113.

[0186] As shown in FIG20 , the planar shape of the channel region 113 is roughly Ω-shaped, and the planar shape of the gate is roughly rectangular; the channel region 113 includes a main portion 113A and a narrowed portion 113B, and the average size of the narrowed portion 113B in the first direction X is smaller than the average size of the main portion 113A in the first direction X. That is, the average channel length of the narrowed portion 113B is smaller than the average channel length of the entire channel region 113.

[0187] In the aforementioned thin-film transistor, the narrowed portion can produce a leading effect similar to the hump effect. Thus, by designing the thin-film transistor to include the aforementioned profiled channel region, the channel lengths in different regions of the channel region vary. This creates a leading effect similar to the hump effect in the thin-film transistor, increasing the subthreshold swing of the thin-film transistor and thereby improving the data range of the thin-film transistor. This in turn makes the drive current provided by the driver transistor insensitive to voltage fluctuations. When a display device employs the aforementioned thin-film transistor as a driver transistor, it can significantly improve display quality and mitigate mura defects.

[0188] In some examples, as shown in FIG20 , the thin film transistor 100 further includes a second gate 150 , which is located on a side of the active layer 110 away from the first gate 130 and is insulated from the active layer 110 ; the orthographic projection of the second gate 150 on the active layer 110 completely covers the orthographic projection of the first gate 130 on the active layer 110 , thereby forming a thin film transistor with a dual-gate structure.

[0189] In some examples, as shown in FIG20 , the first conductive region 111 is electrically connected to the second gate 150. For example, the first conductive region 111 is electrically connected to the second gate 150 via the third connection electrode 193. Thus, based on the aforementioned special-shaped channel region, by connecting the first conductive region to the second gate, the thin-film transistor can further increase the subthreshold swing, thereby further improving the data range of the thin-film transistor, thereby making the drive current provided by the driver transistor insensitive to voltage fluctuations.

[0190] At least one embodiment of the present disclosure further provides an array substrate. Figure 21 is a planar schematic diagram of an array substrate provided by one embodiment of the present disclosure. As shown in Figure 21, the array substrate 300 includes a base substrate 310 and a thin film transistor 100 according to any example. Thus, the array substrate can use a thin film transistor with a large subthreshold swing as a drive transistor, thereby making the drive current provided by the drive transistor insensitive to voltage fluctuations, thereby reducing the sensitivity of the sub-pixel's luminance to voltage fluctuations, thereby significantly improving display quality and improving mura defects.

[0191] In some examples, as shown in FIG21 , the array substrate 300 further includes a plurality of pixel driving circuits 320 arranged in an array. Each pixel driving circuit 320 includes a driving thin film transistor (DTFT), and the driving thin film transistor (DTFT) is the aforementioned thin film transistor 100. Thus, the array substrate can use a thin film transistor with a large subthreshold swing as a driving transistor, thereby making the driving current provided by the driving transistor insensitive to voltage fluctuations, thereby reducing the sensitivity of the sub-pixel's luminance to voltage fluctuations, thereby significantly improving display quality and reducing mura defects.

[0192] In some examples, as shown in FIG21 , the plurality of pixel driving circuits 320 include a first pixel driving circuit 321, a second pixel driving circuit 322, and a third pixel driving circuit 323. The first pixel driving circuit 321 is configured to drive the first subpixel to emit light of a first color; the second pixel driving circuit 322 is configured to drive the second subpixel to emit light of a second color; and the third pixel driving circuit 323 is configured to drive the third subpixel to emit light of a third color. The dimensions of the narrowed portion of the driving thin film transistor (DTFT) of the first pixel driving circuit 321, the narrowed portion of the driving thin film transistor (DTFT) of the second pixel driving circuit 322, and the narrowed portion of the driving thin film transistor (DTFT) of the third pixel driving circuit 323 are different. The first color, the second color, and the third color are different colors.

[0193] Light-emitting elements that emit different colors have different efficiencies. High-efficiency light-emitting elements, with lower operating currents, are more sensitive to voltage fluctuations and mura. Therefore, thin-film transistors with larger subthreshold swings are required as driver thin-film transistors. Therefore, by varying the sizes of the narrowed portions of the driver thin-film transistors in the first pixel driver circuit, the second pixel driver circuit, and the third pixel driver circuit, the array substrate can match the driving capabilities of the pixel driver circuits for sub-pixels emitting different colors, thereby achieving a better display effect.

[0194] In some examples, the first color is red, the second color is green, and the third color is blue. Since green light-emitting elements generally have a higher luminous efficiency, the size of the narrowed portion of the driving thin film transistor of the second pixel driving circuit is smaller than the size of the narrowed portion of the driving thin film transistor of the first pixel driving circuit and the size of the narrowed portion of the driving thin film transistor of the third pixel driving circuit. It should be noted that the size of the narrowed portion can be the average size of the narrowed portion in the first direction X, or the size of the extremely narrow portion of the narrowed portion in the first direction X.

[0195] FIG22A is a schematic plan view of a driving thin film transistor provided in accordance with an embodiment of the present disclosure; FIG22B is a schematic plan view of another driving thin film transistor provided in accordance with an embodiment of the present disclosure.

[0196] As shown in Figures 22A and 22B , the size of the narrowed portion of the driving thin film transistor shown in Figure 22A is smaller than that of the narrowed portion of the driving thin film transistor shown in Figure 22B .

[0197] At least one embodiment of the present disclosure also provides a display device. Figure 23 is a schematic plan view of a display device provided by one embodiment of the present disclosure. As shown in Figure 23, the display device 500 includes the aforementioned array substrate 300. As a result, the display device can achieve better display quality and improve mura, and can also be used in electronic products requiring high frequency, high resolution, and large size.

[0198] In some examples, the display device may be an organic light emitting diode display device. Of course, the embodiments of the present disclosure include but are not limited to this, and the display device may also be a light emitting diode display device or a quantum dot display device.

[0199] In some examples, the display device may be an electronic product with display function, such as a mobile phone, a computer, a television, a navigation system, a car display, a tablet computer, an electronic picture frame, an electronic photo album, etc.

[0200] There are a few points to note:

[0201] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0202] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0203] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A thin film transistor, comprising: An active layer, comprising a channel region and a first conductor region and a second conductor region separated by the channel region; A first gate insulating layer, located on a first side of the active layer; as well as a first gate, located on a side of the first gate insulating layer away from the active layer; At least part of the first conductor region, at least part of the channel region and at least part of the second conductor region are arranged along a first direction, the channel region includes a narrowing portion, and an average size of the narrowing portion in the first direction is smaller than an average size of the channel region in the first direction.

2. The thin film transistor according to claim 1, wherein: The first conductor area and the second conductor area are arranged with a relative spacing, and define a connection area between the first conductor area and the second conductor area, and the narrowed portion is located in the connection area.

3. The thin film transistor according to claim 2, wherein: The connection area includes a center line extending along the first direction, and the narrowed portion overlaps the center line.

4. The thin film transistor according to any one of claims 1 to 3, wherein: The first conductor region is located at a first side of the channel region, and the second conductor region is located at a second side of the channel region; The narrowed portion is narrowed from both the first side and the second side toward a center line of the channel region extending along a second direction intersecting the first direction.

5. The thin film transistor according to any one of claims 1 to 3, wherein: The channel region includes a plurality of the narrowed portions arranged along a second direction intersecting the first direction.

6. The thin film transistor according to claim 5, wherein: The plurality of narrowed portions are staggered in the first direction.

7. The thin film transistor according to any one of claims 1 to 6, wherein: At least one of the first conductor area and the second conductor area includes a protrusion connected to the narrowing portion, and a shape of the protrusion is complementary to a shape of the narrowing portion.

8. The thin film transistor according to any one of claims 1 to 6, wherein: The channel region comprises a first side and a second side, the first side is in contact with the first conductive region, and the second side is in contact with the second conductive region; At least one of the first side and the second side includes a bending portion, and the bending portion bends from the first conductive region or the second conductive region toward the channel region.

9. The thin film transistor according to claim 8, wherein: The bending portion includes at least one of an oblique line and an arc line, and an angle between the oblique line and the first direction is less than 90 degrees.

10. The thin film transistor according to claim 8, wherein: The first side includes a first bending portion bending from the first conductive region toward the channel region, and the second side includes a second bending portion bending from the second conductive region toward the channel region.

11. The thin film transistor according to claim 10, wherein: The first bending portion overlaps with the second bending portion in the first direction.

12. The thin film transistor according to claim 10, wherein: The size of the first bent portion in the first direction is greater than the size of the second bent portion in the first direction. Alternatively, a size of the first bending needle portion in the first direction is smaller than a size of the second bending portion in the first direction.

13. The thin film transistor according to any one of claims 1 to 12, wherein: The ratio of the area of ​​the narrowed portion to the area of ​​the channel region ranges from 1 / 16 to 3 / 16.

14. The thin film transistor according to any one of claims 1 to 12, wherein: The minimum dimension of the narrowed portion in the first direction is greater than or equal to 1 micrometer, and the ratio of the dimension of the narrowed portion in a second direction intersecting the first direction to the dimension of the channel region in the second direction is in the range of 10%-20%.

15. The thin film transistor according to any one of claims 1 to 14, further comprising: A second gate insulating layer, located on a second side of the active layer; as well as a second gate, located on a side of the second gate insulating layer away from the active layer, The orthographic projection of the second gate on the active layer completely covers the orthographic projection of the first gate on the active layer.

16. The thin film transistor according to claim 15, wherein: The channel region comprises a first side and a second side, the first side is in contact with the first conductive region, and the second side is in contact with the second conductive region; The shortest distance between the first side and the edge of the orthographic projection of the second gate on the active layer is greater than 1.0 micron; the shortest distance between the second side and the edge of the orthographic projection of the second gate on the active layer is greater than 1.0 micron.

17. The thin film transistor according to claim 15, further comprising: A first electrode electrically connected to the first conductive region; as well as a second electrode electrically connected to the second conductive region; Wherein, the first electrode is electrically connected to the second gate.

18. The thin film transistor according to any one of claims 1 to 17, wherein: The first conductive region is a source region, and the second conductive region is a drain region; or the first conductive region is a drain region, and the second conductive region is a source region.

19. An array substrate, comprising: substrate substrate; as well as A thin film transistor according to any one of claims 1 to 18.

20. The array substrate according to claim 19, further comprising: A plurality of pixel driving circuits arranged in an array, Wherein, each of the pixel driving circuits includes a driving thin film transistor, and the driving thin film transistor includes the thin film transistor.

21. The array substrate according to claim 20, wherein: The plurality of pixel driving circuits include: A first pixel driving circuit is configured to drive the first sub-pixel to emit light of a first color; A second pixel driving circuit is configured to drive the second sub-pixel to emit light of a second color; and The third pixel driving circuit is configured to drive the third sub-pixel to emit light of a third color, The size of the narrowed portion of the driving thin film transistor of the first pixel driving circuit, the size of the narrowed portion of the driving thin film transistor of the second pixel driving circuit and the size of the narrowed portion of the driving thin film transistor of the third pixel driving circuit are different.

22. A display device comprising the array substrate according to any one of claims 19 to 21.

23. A thin film transistor, comprising: An active layer, comprising a channel region and a first conductor region and a second conductor region separated by the channel region; A first gate insulating layer, located on a first side of the active layer; as well as a first gate, located on a side of the first gate insulating layer away from the active layer; Wherein, at least a portion of the first conductive region, at least a portion of the channel region, and at least a portion of the second conductive region are arranged along a first direction; The channel region includes a first side and a second side, the first side contacts the first conductor region, the second side contacts the second conductor region, and at least one of the first side and the second side includes a bending portion, the bending portion bends from the first conductor region or the second conductor region to the channel region.

24. The thin film transistor according to claim 23, wherein: The first side includes a first bending portion bending from the first conductive region toward the channel region, and the second side includes a second bending portion bending from the second conductive region toward the channel region.

25. The thin film transistor according to claim 23 or 24, further comprising: A second gate insulating layer, located on a second side of the active layer; as well as a second gate, located on a side of the second gate insulating layer away from the active layer, The orthographic projection of the second gate on the active layer completely covers the orthographic projection of the first gate on the active layer.

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