Memory device

Abstract

The present invention relates to a memory device including a memory cell for storing n-bit data according to operations of a word line and a bit line, the memory device comprising: at least one memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; a plurality of sense amplifiers combined with each of the plurality of bit lines, converting first specific level voltages stored in each of the plurality of memory cells respectively into pieces of first n-bit data and outputting the first n-bit data in a read mode, wherein n is an integer equal to or greater than 2 and first order-wise bit values of each of the pieces of first n-bit data are sequentially output, and converting pieces of second n-bit data into second specific level voltages and storing the second specific level voltages in each of the plurality of memory cells in a write mode, wherein k global input / output lines corresponding to a prefetch size, wherein k is an integer equal to or greater than 1, are respectively combined with k sense amplifiers in each of sense amplifier groups in which the plurality of sense amplifiers are grouped into groups of k; and at least one MUX / DEMUX that outputs pieces of k-bit output data by multiplexing the first order-wise bit values of each of the k sense amplifiers in the read mode, and demultiplexes each of pieces of k-bit input data into second order-wise bit values and applies the second order-wise bit values to each of the k sense amplifiers respectively through the k global input / output lines in the write mode.

Description

memory device

[0001] The present invention relates to a memory device, and more particularly, to a memory device that can minimize time delay in reading and writing data in a memory cell storing n-bit data and increase the density of the memory cell.

[0002] DRAM, a representative element in semiconductor memory devices, records data in memory cells composed of one transistor and one capacitor. By charging or discharging the capacitor, one bit of information, for example, “0” and “1,” is recorded in the memory cell.

[0003] In addition, multi-level DRAMs have been recently proposed to increase data storage capacity by storing more than one bit of data in a single memory cell, unlike memory cells that store one bit of information, i.e., one bit of information of “0” or “1”, in a memory cell that includes one transistor and one capacitor.

[0004] And, in DRAM, the word line determines whether to access the capacitor by turning the transistor on or off, and data is stored in the capacitor or read from the capacitor through the bit line.

[0005] In these DRAMs, a sense amplifier is used to read data stored in a capacitor through a bit line. The sense amplifier reads data stored in a memory cell by amplifying the voltage change of the bit line, which changes slightly due to charge sharing between the capacitor and the bit line when the transistor is activated by the word line.

[0006] However, in conventional multi-level DRAM, n-bit data of a memory cell sensed through a sense amplifier is read, and then each rank bit value in the n-bit data is transmitted to a MUX / DEMUX through each different global input / output (GIO) line.

[0007] That is, referring to the multi-level DRAM storing 2-bit data of Fig. 1, each sense amplifier is connected to two global input / output lines to store 2-bit data in a memory cell or to read 2-bit data stored in a memory cell.

[0008] Therefore, the number of memory cells that can be accessed in one cycle through one mux / demux that transmits and receives data using eight global input / output lines depending on the prefetch size is limited to four, and accordingly, a time delay occurs in reading and writing data to memory cells in the memory cell array.

[0009] Meanwhile, a sense amplifier for reading n-bit data stored in a memory cell or writing n-bit data to a memory cell includes an analog-to-digital converter that senses a specific level of voltage stored in the memory cell and converts it into n-bit data, and a digital-to-analog converter that converts n-bit data into a specific level of voltage and stores it in the memory cell. The analog-to-digital converter is divided into a type that converts data in parallel, such as a flash analog-to-digital converter, and a type that converts data sequentially, such as a successive approximate register analog-to-digital converter.

[0010] Referring back to FIG. 1, when using an analog-to-digital converter that converts data in parallel, such as a flash analog-to-digital converter, eight bit values ​​corresponding to four memory cells storing 2-bit data can be transmitted in one cycle through eight global input / output lines, which has the advantage of a short time delay required for data access to the memory cells. However, since the data must be converted in parallel, each comparator corresponding to each rank bit is required, which increases the area occupied by the analog-to-digital converter area within the memory device.

[0011] Meanwhile, when using an analog-to-digital converter that converts data sequentially, such as a sequential comparison type analog-to-digital converter, there is an advantage in that the area within the memory device does not increase significantly compared to an analog-to-digital converter that converts data in parallel, since the number of comparators required for data conversion does not increase. However, since it takes each cycle, i.e., two cycles, to transmit the most significant bit (MSB) and the least significant bit (MSB) of each of the four memory cells by converting data sequentially, there is a problem in that a time delay occurs in accessing data in the memory cells.

[0012] The purpose of the present invention is to solve all of the above-described problems.

[0013] In addition, the present invention has another purpose of minimizing the time delay for data access in a memory cell storing n-bit data.

[0014] In addition, another object of the present invention is to increase the density of memory cells storing n-bit data.

[0015] In addition, another object of the present invention is to enable efficient transmission of data in a memory cell storing n-bit data.

[0016] According to one embodiment of the present invention for achieving the above object, there is provided a memory device including a memory cell storing n-bit data by the operation of a word line and a bit line, the memory device comprising: at least one memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; a plurality of sense amplifiers coupled to each of the plurality of bit lines, and configured to, in a read mode, convert first specific level voltages stored in each of the plurality of memory cells into respective first n-bit data, wherein n is an integer greater than or equal to 2, and output the converted first-rank bit values ​​of each of the first n-bit data sequentially, and, in a write mode, convert second n-bit data into second specific level voltages and store the converted second n-bit data in each of the plurality of memory cells; And a memory device is provided, which includes at least one mux / demux, wherein each of k global input / output lines corresponding to a prefetch size, wherein k is an integer greater than or equal to 1, is coupled to each of k sense amplifiers in each of k sense amplifier groups that group the plurality of sense amplifiers, and in the read mode, multiplexes the first-order bit values ​​of each of the k sense amplifiers to output k-bit output data, and in the write mode, demultiplexes each of the k-bit input data into second-order bit values ​​and applies the demultiplexed data to each of the k sense amplifiers through each of the k global input / output lines.

[0017] In the above embodiment, (R) in the read mode, in the (R_1) 1_1 cycle, each of the first to k-th sense amplifiers, which are the k sense amplifiers, outputs a 1_1_1 rank bit value of the 1_1 n-bit data to a 1_k_1 rank bit value of the 1_k n-bit data corresponding to a 1_1 specific level voltage to a 1_k specific level voltage stored in each of the first to k-th memory cells corresponding to the 1_1 to k-th sense amplifiers, respectively, and in the (R_2) 1_i cycle, where i is an integer increasing from 2 to n, each of the first to k-th sense amplifiers outputs a 1_1_i rank bit value of the 1_1 n-bit data to a 1_k_i rank bit value of the 1_k n-bit data, and the mux / demux outputs a 1_1_(i-1) rank bit value of the 1_1 n-bit data to a 1_k_i rank bit value of the 1_k n-bit data, respectively, and the mux / demux outputs a 1_1_(i-1) rank bit value transmitted through each of the 1st global input / output lines to the kth global input / output lines. The (i-1) k-bit output data is output by multiplexing the rank bit value to the 1_k_(i-1)-th rank bit value and the 1_1_(i-1)-th rank bit value to the 1_k_(i-1)-th rank bit value, and (R_3) in the 1_(n+1)-th cycle, the mux / demux multiplexes the 1_1_n-th rank bit value to the 1_k_n-th rank bit value transmitted through the 1st global input / output line to the kth global input / output line, respectively, and outputs the nk-th bit output data by multiplexing the 1_1_n-th rank bit value to the 1_k_n-th rank bit value, and (W) in the write W_1) 2_1-th cycle, the mux / demux demultiplexes the 1 k-bit input data and outputs the 2_1_1-th rank bit value to the 2_k_1-th rank bit value through the 1st global input / output line to the kth global input / output line, respectively, and (W_2) in the 2_i-th cycle, the mux / demux demultiplexes the 1 k-bit input data and outputs the 2_1_1-th rank bit value to the 2_k_1-th rank bit value through the 1st global input / output line to the kth global input / output line, respectively. In the cycle,The above mux / demux demultiplexes the ik-bit input data and outputs the 2_1_i-th rank bit value to the 2_k_i-th rank bit value through the first global input / output line to the k-th global input / output line, respectively, and the first sense amplifier to the k-th sense amplifier latches the 2_1_(i-1)-th rank bit value to the 2_k_(i-1)-th rank bit value transmitted through the first global input / output line to the k-th global input / output line, respectively, and in the (W_3) 2_(n+1)-th cycle, the first sense amplifier to the k-th sense amplifier latches the 2_1_n-th rank bit value to the 2_k_n-th rank bit value transmitted through the first global input / output line to the k-th global input / output line, respectively, and outputs the 2_1_n-bit data composed of the latched 2_1_1-th rank bit value to the latched 2_1_n-th rank bit value to the latched Each of the 2_1 specific level voltages to the 2_k specific level voltages corresponding to each of the 2_k n-bit data consisting of the 2_k_1 rank bit value to the latched 2_k_n rank bit value can be stored in each of the first memory cell to the k-th memory cell.

[0018] In the above embodiment, each of the first to kth bit lines coupled to each of the k sense amplifiers is located in the same memory cell array, and each of the k sense amplifiers can be coupled to each of the k global input / output lines coupled to one of the multiplexers / demuxers.

[0019] In the above embodiment, each of the first to kth bit lines coupled to each of the k sense amplifiers is located in a different memory cell array, and each of the k sense amplifiers can be coupled to a global input / output line of each of the k muxes / demuxes.

[0020] In the above embodiment, each of the k sense amplifiers may include sequential analog-to-digital converters that sequentially output the first rank-based bit values ​​of each of the first n-bit data.

[0021] In the above embodiment, each of the k sense amplifiers may include respective input terminals into which each of the second-order bit values ​​is input, respective terminal switches sequentially activating each of the input terminals, and respective digital-to-analog converters that apply the second specific level voltages corresponding to the second-order bit values ​​sequentially input through each of the terminal switches to each of the plurality of bit lines.

[0022] In the above embodiment, each of the k sense amplifiers can use at least some of the specific rank-based bit values ​​among the first rank-based bit values ​​to refresh each of the k memory cells corresponding to the k sense amplifiers.

[0023] In the above embodiment, each of the k sense amplifiers is coupled to each of the k global input / output lines through each of the k global switches, and when the specific rank-based bit values ​​are used to refresh each of the k memory cells, each of the k global switches can be deactivated.

[0024] According to the present invention, the following effects are achieved.

[0025] The present invention can minimize time delay for data access in a memory cell storing n-bit data.

[0026] The present invention can increase the density of memory cells storing n-bit data.

[0027] The present invention can efficiently transmit data in a memory cell storing n-bit data.

[0028] Figure 1 schematically illustrates a memory device including a memory cell that stores conventional 2-bit data.

[0029] FIG. 2 schematically illustrates a memory device including a memory cell storing 2-bit data according to one embodiment of the present invention.

[0030] FIG. 3 schematically illustrates a sense amplifier in a memory device according to one embodiment of the present invention.

[0031] FIG. 4 schematically illustrates an analog-to-digital converter of a sense amplifier in a memory device according to one embodiment of the present invention.

[0032] FIG. 5 schematically illustrates another configuration of a global input / output line in a memory device according to one embodiment of the present invention.

[0033] FIG. 6 schematically illustrates a read mode for reading data in a memory device according to one embodiment of the present invention.

[0034] FIG. 7 schematically illustrates a write mode for writing data in a memory device according to one embodiment of the present invention.

[0035] The following detailed description of the present invention refers to the accompanying drawings, which illustrate specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. It should be understood that the various embodiments of the present invention, while different from each other, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the positions or arrangements of individual components within each disclosed embodiment may be modified without departing from the spirit and scope of the present invention. Accordingly, the following detailed description is not intended to be limiting, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly described. Like reference numerals in the drawings designate the same or similar functionality throughout the several aspects.

[0036] Hereinafter, in order to enable those skilled in the art to easily carry out the present invention, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. A memory device according to the present invention may be any one of random access memories (RAMs) including DRAM (Dynamic Random Access Memory), SDRAM (Synchronous DRAM), SRAM (Static RAM), DDR SDRAM (Double Date Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), etc., and the following description will focus on DRAM. In addition, a memory cell includes a switch element that is switched by a word line signal and a cell capacitor that stores a charge, but for the convenience of explanation, the cell capacitor may also be referred to as a memory cell.

[0037] In addition, for the convenience of explanation, the present invention will be described in detail below using drawings created based on 2-bit data in a memory cell, but the present invention is not limited to the drawings. In addition, for the convenience of explanation, the drawings only illustrate one mux / demux having eight memory cells, eight sense amplifiers, and eight global input / output lines, but the present invention is not limited thereto.

[0038] FIG. 2 schematically illustrates a memory device including a memory cell storing 2-bit data according to one embodiment of the present invention.

[0039] A memory device according to one embodiment of the present invention may include at least one memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. In this case, each of the plurality of memory cells may store a specific level voltage corresponding to n-bit data, and when the corresponding specific word line is activated by a row address, each of the plurality of memory cells may be turned on to perform charge sharing with each of the corresponding bit lines. The n may be an integer greater than or equal to 2.

[0040] As an example, referring to FIG. 2, one memory cell array (MAT) in a memory device (100) according to one embodiment of the present invention is illustrated, and eight memory cells (C_1, C_2, …, C_8) that are turned on according to the activation of a specific word line (WL) and eight bit lines (BL_1, BL_2, …, BL_8) connected to each of the eight memory cells (C_1, C_2, …, C_8) are illustrated. Accordingly, in the memory device (100) of the present invention, a specific word line (WL) is activated by a row address, and accordingly, eight memory cells (C_1, C_2, …, C_8) coupled to the specific word line (WL) are turned on, and each of the eight turned-on memory cells (C_1, C_2, …, C_8) can perform charge sharing with each of the eight bit lines (BL_1, BL_2, …, BL_8).

[0041] And, a memory device according to one embodiment of the present invention may include a plurality of sense amplifiers coupled to each of a plurality of bit lines, and in a read mode, converting first specific level voltages stored in each of a plurality of memory cells into first n-bit data and outputting the converted first order bit values ​​of each of the first n-bit data sequentially, and in a write mode, converting second n-bit data into second specific level voltages and storing the converted second n-bit data in each of the plurality of memory cells.

[0042] For example, referring to FIG. 2, eight sense amplifiers (SA_1, SA_2, …, SA_8) are illustrated, and according to this, each of the eight sense amplifiers (SA_1, SA_2, …, SA_8) of the memory device (100) according to one embodiment of the present invention can be coupled to each of eight bit lines (BL_1, BL2, …, BL_8). At this time, each of the eight sense amplifiers (SA_1, SA_2, …, SA_8) is activated by a column address in the read mode of the memory device (100), and converts each of the eight first specific level voltages stored in each of the eight memory cells (C_1, C_2, …, C_8) through each of the eight bit lines (BL_1, BL_2, …, BL_8) into each of the eight first n-bit data and outputs the converted first-rank bit values ​​of each of the eight first n-bit data in sequence. That is, each of the eight sense amplifiers (SA_1, SA_2, …, SA_8) can sequentially output eight first-rank bit values ​​to eight n-th-rank bit values ​​of each of the eight first n-bit data. At this time, the first to nth ranks may be ranks from the MSB (Most Significant Bit) to the LSB (Least Significant Bit) in n-bit data, or ranks from the LSB (Least Significant Bit) to the MSB (Most Significant Bit). In addition, each of the eight sense amplifiers (SA_1, SA_2, …, SA_8) is activated by a column address in the write mode of the memory device (100), converts each of the eight second n-bit data into each of the eight second specific level voltages, and stores each of the eight second specific level voltages in each of the eight memory cells (C_1, C_2, …, C_8) through each of the eight bit lines (BL_1, BL_2, …, BL_8).

[0043] At this time, referring to FIG. 3, each of the plurality of sense amplifiers may include an analog-to-digital converter (ADC) that converts a specific level voltage stored in a memory cell into n-bit data in a read mode, and a digital-to-analog converter (DAC) that converts n-bit data into a specific level voltage in a write mode to be stored in the memory cell. In addition, the digital-to-analog converter (DAC) may sequentially receive bit values ​​of n-bit data by rank through one input terminal, latch or buffer the input bit values ​​by rank, and then convert them into a specific level voltage when all bit values ​​of rank are input, or may receive bit values ​​by rank through a terminal switch (SW_2) that forms input terminals into which each bit value by rank is input, and sequentially activates the input terminals, latch or buffer the input bit values ​​by rank, and then convert them into a specific level voltage when all bit values ​​of rank are input. Meanwhile, the switch (SW_1) will be described later.

[0044] In addition, referring to FIG. 4, the analog-to-digital converter (ADC) included in each of the plurality of sense amplifiers may be configured as a sequential comparison type analog-to-digital converter that converts a specific level voltage stored in a memory cell into n-bit data using a single comparator (comp), and sequentially outputs bit values ​​of the n-bit data in order.

[0045] And, a memory device according to one embodiment of the present invention may include at least one mux / demux, each of k global input / output lines corresponding to a prefetch size, coupled to each of k sense amplifiers included in each of k sense amplifier groups that group a plurality of sense amplifiers. The k may be an integer greater than or equal to 1.

[0046] For example, referring to FIG. 2, a case where k is 8 is illustrated, and according to this, a memory device (100) according to an embodiment of the present invention may include at least one mux / demux (10) in which each of eight global input / output lines (GIO_1, GIO_2, …, GIO_8) corresponding to a prefetch size is coupled to each of eight sense amplifiers (SA_1, SA_2, …, SA_8) included in one sense amplifier group.

[0047] And, in a memory device according to one embodiment of the present invention, the mux / demux can, in a read mode, multiplex the bit values ​​of each of the first ranks of the k sense amplifiers to output k-bit output data, and, in a write mode, demultiplex each of the k-bit input data into bit values ​​of each of the second ranks and apply them to each of the k sense amplifiers through each of the k global input / output lines.

[0048] For example, referring to FIG. 2, the mux / demux (10) in the memory device according to one embodiment of the present invention, in the read mode of the memory device (100), in a specific cycle in a continuous cycle, which is the time from the time when a memory cell is accessed once until the start of the next access, can multiplex eight specific rank bit values ​​output from each of eight sense amplifiers (SA_1, SA_2, …, SA_8) to output one 8-bit output data. In addition, the mux / demux (10) in the memory device according to one embodiment of the present invention, in the write mode of the memory device (100), in a specific cycle, can demultiplex 8-bit input data to generate eight specific rank bit values, and cause each of the eight specific rank bit values ​​to be input to each of the eight sense amplifiers (SA_1, SA_2, …, SA_8).

[0049] At this time, in the memory device according to one embodiment of the present invention, each of the k sense amplifiers may be respectively coupled to k global input / output lines coupled to one mux / demux, and each of the k bit lines, i.e., the first bit line to the kth bit line, coupled to each of the k sense amplifiers may be located in the same memory cell array. However, the present invention is not limited thereto, and each of the k bit lines may be located in a different memory cell array.

[0050] For example, referring to FIG. 2, in a memory device (100) according to an embodiment of the present invention, each of eight sense amplifiers (SA_1, SA_2, …, SA_8) included in one sense amplifier group may be coupled to each of eight global input / output lines (GIO_1, GIO_2, …, GIO_8) of a mux / demux (10). In addition, the first bit line (BL_1) to the eighth bit line (BL_8) coupled to each of the eight sense amplifiers (SA_1, SA_2, …, SA_8) may be located in the same memory cell array (MAT). At this time, the first bit line (BL_1) to the eighth bit line (BL_8) may be arranged at consecutive positions within the same memory cell array (MAT), or at least some of the first bit line (BL_1) to the eighth bit line (BL_8) may be arranged at non-contiguous positions.

[0051] Additionally, in a memory device according to one embodiment of the present invention, each of the k sense amplifiers may be coupled to a global input / output line of each of the k muxes / demuxes, and each of the first to kth bit lines coupled to each of the k sense amplifiers may be located in different memory cell arrays. However, the present invention is not limited thereto, and each of the k bit lines may be located in the same memory cell array.

[0052] For example, referring to FIG. 5, in a memory device (100) according to one embodiment of the present invention, each of the first sense amplifier (SA_1) to the eighth sense amplifier (SA_8), which are eight sense amplifiers (SA_1, SA_2, …, SA_8) included in one sense amplifier group, may be respectively coupled to the first global input / output lines (GIO_1) of each of the first mux / demux (10_1) to the eighth mux / demux (10_8), which are eight mux / demux (10_1, 10_2, …, 10_8). At this time, it is illustrated that each of the first sense amplifier (SA_1) to the eighth sense amplifier (SA_8) is connected to the first global input / output lines (GIO_1) of each of the first mux / demux (10_1) to the eighth mux / demux (10_8), but the present invention is not limited thereto, and each of the first sense amplifier (SA_1) to the eighth sense amplifier (SA_8) may be connected to global input / output lines of different ranks of each of the first mux / demux (10_1) to the eighth mux / demux (10_8). In addition, in FIG. 5, the first bit line (BL_1) to the eighth bit line (BL_8) coupled to the first sense amplifier (SA_1) to the eighth sense amplifier (SA_8) are illustrated as being arranged at consecutive positions within the same memory cell array (MAT), but the present invention is not limited thereto, and at least some of the first bit line (BL_1) to the eighth bit line (BL_8) may be arranged at non-contiguous positions within the same memory cell array (MAT), and in addition, at least some of the first bit line (BL_1) to the eighth bit line (BL_8) may be arranged in different memory cell arrays (MAT).

[0053] An operation in read mode for reading n-bit data stored in a memory cell in a memory device according to one embodiment of the present invention is described as follows.

[0054] A specific word line is activated by a row address, and accordingly, memory cells associated with the specific word line are turned on, and each of the turned-on memory cells performs charge sharing with each associated bit line.

[0055] And, in the 1_1 cycle, which is the first cycle for reading n-bit data stored in memory cells, each of the first to k-th sense amplifiers, which are k sense amplifiers corresponding to a column address, can output the 1_1_1 rank bit value of the 1_1 n-bit data to the 1_k_1 rank bit value of the 1_k n-bit data corresponding to the 1_1 specific level voltage to the 1_k specific level voltage stored in each of the first to k-th memory cells corresponding to the 1_1 to k-th sense amplifiers, respectively.

[0056] Thereafter, in the 1_i-th cycle, the first sense amplifier to the k-th sense amplifier can output the 1_1_i-th rank bit value of the 1_1 n-bit data to the 1_k_i-th rank bit value of the 1_k n-bit data, respectively. The i can be an integer increasing from 2 to n. At the same time, the mux / demux can multiplex the 1_1_(i-1)-th rank bit value to the 1_k_(i-1)-th rank bit value transmitted through the 1st global input / output line to the k-th global input / output line, respectively, to output the (i-1)-th k-bit output data composed of the 1_1_(i-1)-th rank bit value to the 1_k_(i-1)-th rank bit value.

[0057] And, in the 1st_(n+1) cycle, the mux / demux can multiplex the 1_1_nth rank bit value to the 1_k_nth rank bit value transmitted through the 1st global input / output line to the kth global input / output line, respectively, to output nk-th bit output data composed of the 1_1_nth rank bit value to the 1_k_nth rank bit value.

[0058] That is, a memory device according to one embodiment of the present invention can read k n-bit data recorded in k memory cells as n k-bit data composed of bit values ​​by rank.

[0059] The read operation in the memory device according to one embodiment of the present invention is described below based on the 2-bit data of FIGS. 2 and 6. In this case, the memory device is exemplified as outputting 8-bit output data according to the prefetch size.

[0060] As a specific word line (WL) is activated by a row address, the first memory cell (C_1) to the eighth memory cell (C_8) coupled to the specific word line (WL) are turned on and charge-shared with the first bit line (BL_1) to the eighth bit line (BL_8), respectively.

[0061] And, in the first cycle (tCAS_MSB), the first sense amplifier (SA_1) to the eighth sense amplifier (SA_8) corresponding to the column address senses the first specific level voltage to the eighth specific level voltage stored in the first memory cell (C_1) to the eighth memory cell (C_8) through the first bit line (BL_1) to the eighth bit line (BL_8), respectively, and outputs the first most significant bit value (D) in the first 2-bit data corresponding to the first specific level voltage. 1,M ) to the 8th most significant bit value (D) in the 8th 2-bit data corresponding to the 8th specific level voltage. 8,M ) can be printed respectively.

[0062] Thereafter, in the second cycle (tCAS_LSB = tBUSRT_MSB), each of the first to eighth sense amplifiers (SA_1) to (SA_8) outputs the first least significant bit value (D) in the first 2-bit data corresponding to the first specific level voltage. 1,L ) to the 8th least significant bit value (D) in the 8th 2-bit data corresponding to the 8th specific level voltage. 8,L ) can be printed respectively.

[0063] At the same time, the MUX / DEMUX (10) receives the first most significant bit value (D) from the first sense amplifier (SA_1) transmitted in parallel through the first global input / output line (GIO_1) to the eighth global input / output line (GIO_8). 1,M ) to the 8th most significant bit value (D) from the 8th sense amplifier (SA_8) 8,M ) by multiplexing the first most significant bit value (D 1,M ) to the 8th most significant bit value (D 8,M ) can be output as the first 8-bit output data.

[0064] And, in the third cycle (tBURST_LSB), the mux / demux (10) receives the first least significant bit value (D) from the first sense amplifier (SA_1) transmitted in parallel through the first global input / output line (GIO_1) to the eighth global input / output line (GIO_8). 1,L ) to the 8th least significant bit value (D) from the 8th sense amplifier (SA_8) 8,L ) by multiplexing the first least significant bit value (D 1,L ) to the 8th least significant bit value (D 8,L ) can be output as a second 8-bit output data.

[0065] Meanwhile, in the above, both the highest bit values ​​and the lowest bit values ​​are used as data of the memory device, but some bit values ​​of different ranks are used as data of the memory device, and some bit values ​​of different ranks can be used for refresh.

[0066] For example, as shown in Fig. 3, when a global switch (SW_1) is installed between a sense amplifier and a global input / output line, the global switch (SW_1) can be activated so that the most significant bit value is transmitted to the mux / demux, and the global switch (SW_1) can be deactivated for refresh so that the least significant bit value is transmitted to the digital-to-analog converter. At this time, the digital-to-analog converter can replicate the input least significant bit value so that a specific level voltage corresponding to 2-bit data can be stored in the memory cell.

[0067] Meanwhile, in the above, the digital-to-analog converter replicates the input least significant bit value so that a specific level voltage corresponding to 2-bit data can be stored in the memory cell. However, in contrast, the global switch (SW_1) may be activated so that the most significant bit value is transmitted to the mux / demux while the most significant bit value is input to the digital-to-analog converter so that the digital-to-analog converter latches the most significant bit value, and the global switch (SW_1) may be deactivated for refresh so that the least significant bit value is transmitted only to the digital-to-analog converter, so that the digital-to-analog converter latches the least significant bit value, and a specific level voltage corresponding to 2-bit data composed of the latched most significant bit value and the latched least significant bit value can be stored in the memory cell.

[0068] In addition, an operation in a write mode for writing n-bit data to a memory cell in a memory device according to one embodiment of the present invention is described as follows.

[0069] A specific word line is activated by a row address, and accordingly, the memory cells associated with the specific word line can be turned on.

[0070] And, in the 2_1 cycle, which is the first cycle for writing the 2nd n-bit data to the memory cells, the mux / demux can demultiplex the 1st k-bit input data and output the 2_1_1-th rank bit value to the 2_k_1-th rank bit value through the 1st global input / output line to the kth global input / output line, respectively.

[0071] Thereafter, in the 2_i-th cycle, the mux / demux can demultiplex the i k-bit input data to output the 2_1_i-th rank bit value to the 2_k_i-th rank bit value, respectively, through the first global input / output line to the k-th global input / output line. At the same time, the first sense amplifier to the k-th sense amplifier can latch the 2_1_(i-1)-th rank bit value to the 2_k_(i-1)-th rank bit value transmitted through the first global input / output line to the k-th global input / output line, respectively.

[0072] And, in the 2nd_(n+1) cycle, the first sense amplifier to the kth sense amplifier each latch the 2nd_1_nth rank bit value to the 2nd_k_nth rank bit value transmitted through the 1st global input / output line to the kth global input / output line, and the 2nd_1_nth specific level voltage to the 2nd_k_nth specific level voltage corresponding to the 2nd_1_nth bit data formed of the latched 2nd_1_1_th rank bit value to the 2nd_k_nth rank bit value to the 2nd_k_nth bit data formed of the latched 2nd_k_1_th rank bit value to the 2nd_k_nth rank bit value can be stored in the 1st memory cell to the kth memory cell, respectively.

[0073] That is, a memory device according to one embodiment of the present invention can generate k n-bit data using bit values ​​in order of rank from n k-bit input data, and record each of the n-bit data in k memory cells.

[0074] The write operation in the memory device according to one embodiment of the present invention will be described below based on the 2-bit data of FIGS. 2 and 7. In this case, the memory device is exemplified as writing 8-bit input data according to the prefetch size.

[0075] As a specific word line (WL) is activated by a row address, the first memory cell (C_1) to the eighth memory cell (C_8) coupled to the specific word line (WL) can be turned on.

[0076] And, in the first cycle (tBURST_MSB), corresponding to the column address, the mux / demux (10) demultiplexes the first 8-bit input data to obtain the first most significant bit value (D 1,M ) to the 8th most significant bit value (D 8,M ) and generate the first most significant bit value (D 1,M ) to the 8th most significant bit value (D 8,M ) can be transmitted through each of the first global input / output line (GIO_1) to the eighth global input / output line (GIO_8).

[0077] Afterwards, in the second cycle (tBURST_LSB = tCAS_MSB), the mux / demux (10) demultiplexes the second 8-bit input data to produce the first least significant bit value (D 1,L ) to the 8th least significant bit value (D 8,L ) and generate the first least significant bit value (D 1,L ) to the 8th least significant bit value (D 8,L ) can be transmitted through each of the first global input / output line (GIO_1) to the eighth global input / output line (GIO_8).

[0078] At the same time, each of the first sense amplifier (SA_1) to the eighth sense amplifier (SA_8) receives the first most significant bit value (D) transmitted through the first global input / output line (GIO_1). 1,M) to the 8th most significant bit value (D) transmitted through the 8th global input / output line (GIO_8). 8,M ) can latch each.

[0079] And, in the third cycle (tCAS_LSB), each of the first sense amplifier (SA_1) to the eighth sense amplifier (SA_8) receives the first least significant bit value (D) transmitted through the first global input / output line (GIO_1). 1,L ) to the 8th least significant bit value (D) transmitted through the 8th global input / output line (GIO_8). 8,L ) can be latched, and the latched first most significant bit value (D 1,M ) and the first least significant bit value (D 1,L ) consisting of the first 2-bit data or the latched 8th most significant bit value (D 8,M ) and the 8th least significant bit value (D 8,L ) can be stored in each of the first memory cell (C_1) to the eighth memory cell (C_8), respectively, corresponding to each of the eighth 2-bit data.

[0080] Although the present invention has been described above with specific details such as specific components and limited examples and drawings, these are provided only to help a more general understanding of the present invention, and the present invention is not limited to the above examples, and those with ordinary knowledge in the technical field to which the present invention pertains can make various modifications and variations from this description.

[0081] Therefore, the idea of ​​the present invention should not be limited to the embodiments described above, and all things that are modified equally or equivalently to the following claims as well as the claims are considered to fall within the scope of the idea of ​​the present invention.

Claims

1. In a memory device including a memory cell that stores n-bit data by the operation of a word line and a bit line, At least one memory cell array comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; A plurality of sense amplifiers coupled to each of the plurality of bit lines, and in a read mode, converting first specific level voltages stored in each of the plurality of memory cells into first n-bit data, where n is an integer greater than or equal to 2, and outputting the converted first order bit values ​​of each of the first n-bit data sequentially, and in a write mode, converting second n-bit data into second specific level voltages and storing them in each of the plurality of memory cells; and At least one mux / demux, each of k global input / output lines corresponding to a prefetch size, wherein k is an integer greater than or equal to 1, is coupled to each of k sense amplifiers in each of k sense amplifier groups in which the plurality of sense amplifiers are grouped into groups of k, and in the read mode, multiplexes the bit values ​​of each of the k sense amplifiers to output k-bit output data, and in the write mode, demultiplexes each of the k-bit input data into bit values ​​of each of the second priorities and applies the demultiplexed bit values ​​to each of the k sense amplifiers through each of the k global input / output lines; A memory device containing.

2. In paragraph 1, (R) In the read mode, (R_1) in the 1_1 cycle, each of the first to k-th sense amplifiers, which are the k sense amplifiers, outputs the 1_1_1 rank bit value of the 1_1 n-bit data to the 1_k_1 rank bit value of the 1_k n-bit data corresponding to the 1_1 specific level voltage to the 1_k specific level voltage stored in each of the first to k-th memory cells corresponding to the 1_1 to k-th sense amplifiers, respectively, and (R_2) in the 1_i cycle, where i is an integer increasing from 2 to n, each of the first to k-th sense amplifiers outputs the 1_1_i rank bit value of the 1_1 n-bit data to the 1_k_i rank bit value of the 1_k n-bit data, and the mux / demux outputs the 1_1_(i-1) rank bit value to the 1_k_i rank bit value of the 1_k n-bit data transmitted through each of the 1st global input / output lines to the kth global input / output lines. The (i-1) k-bit output data is output by multiplexing the 1_k_(i-1)-th rank bit value and consisting of the 1_1_(i-1)-th rank bit value to the 1_k_(i-1)-th rank bit value, and in the (R_3) 1_(n+1)-th cycle, the mux / demux multiplexes the 1_1_n-th rank bit value to the 1_k_n-th rank bit value transmitted through the 1st global input / output line to the k-th global input / output line, respectively, and outputs the nk-th bit output data by consisting of the 1_1_n-th rank bit value to the 1_k_n-th rank bit value, (W) In the light mode, (W_1) in the 2_1 cycle, the mux / demux demultiplexes the 1 k-bit input data and outputs the 2_1_1-th rank bit value to the 2_k_1-th rank bit value through the 1st global input / output line to the kth global input / output line, respectively, and (W_2) in the 2_i-th cycle, the mux / demux demultiplexes the ik-bit input data and outputs the 2_1_i-th rank bit value to the 2_k_i-th rank bit value through the 1st global input / output line to the kth global input / output line, respectively, and the 1st sense amplifier to the kth sense amplifier latches the 2_1_(i-1)-th rank bit value to the 2_k_(i-1)-th rank bit value transmitted through the 1st global input / output line to the kth global input / output line, respectively, and (W_3) in the 2_(n+1) cycle, the 1st sense amplifier to the kth sense amplifier A memory device that latches each of the 2_1_n-th rank bit values ​​to the 2_k_n-th rank bit values ​​transmitted through the first global input / output line to the k-th global input / output line, and stores each of the 2_1-th specific level voltage to the 2_k-th specific level voltage corresponding to each of the 2_1 n-bit data formed of the latched 2_1_1-th rank bit value to the latched 2_1_n-th rank bit value to each of the 2_k n-bit data formed of the latched 2_k_1-th rank bit value to the latched 2_k_n-th rank bit value in each of the first memory cells to the k-th memory cells.

3. In paragraph 1 Each of the first to kth bit lines coupled to each of the above k sense amplifiers is located in the same memory cell array, Each of the above k sense amplifiers is a memory device coupled to each of the above k global input / output lines coupled to one of the above mux / demux.

4. In paragraph 1, Each of the first to kth bit lines coupled to each of the above k sense amplifiers is located in a different memory cell array, Each of the above k sense amplifiers is a memory device coupled to a global input / output line of each of the k muxes / demuxes.

5. In paragraph 1, A memory device in which each of the k sense amplifiers includes sequential analog-to-digital converters that sequentially output the bit values ​​of the first rank of each of the first n-bit data.

6. In paragraph 1, A memory device in which each of the k sense amplifiers includes respective input terminals into which each of the second-order bit values ​​is input, respective terminal switches that sequentially activate each of the input terminals, and respective digital-to-analog converters that apply the second specific level voltages corresponding to the second-order bit values ​​sequentially input through each of the terminal switches to each of the plurality of bit lines.

7. In paragraph 1, A memory device in which each of the k sense amplifiers uses at least some of the specific rank-based bit values ​​among the first rank-based bit values ​​to refresh each of the k memory cells corresponding to the k sense amplifiers.

8. In paragraph 7, Each of the above k sense amplifiers is coupled to each of the above k global input / output lines through each of the k global switches, A memory device in which each of the k global switches is deactivated when the bit values ​​of the specific rank are used to refresh each of the k memory cells.

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