Information processing apparatus

Abstract

An information processing apparatus, comprising: a mainboard (101), which has a first surface, wherein the first surface is provided with a central processing unit (102) electrically connected to the mainboard (101); a compressed additional memory module (103), which is located on one side of the first surface, wherein at least one surface of the compressed additional memory module (103) is provided with a plurality of chips (104); and an external connection structure (105), which is located on one side of the first surface, and is configured to electrically connect to the compressed additional memory module (103) and the central processing unit (102), wherein the central processing unit (102) is configured to read data from each chip (104) and write data into each chip (104) at least via the external connection structure (105).

Description

Information processing device

[0001] Cross-references

[0002] This application claims priority to Chinese patent application entitled “Information Processing Device” and application number 202310728159.4, filed on June 16, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to an information processing device. Background Art

[0004] A Compression Attached Memory Module (CAMM) is a new type of memory module. It connects multiple chips, securing them to the motherboard and electrically connecting them. The CPU, electrically connected to the motherboard, can write data to and read data from the chips. Compared to traditional memory modules, CAMMs are thinner and have better heat dissipation.

[0005] Signal transmission between the chip and the central processing unit is usually achieved through signal lines located in the motherboard. However, as the number of chips connected to the CAMM increases, the number of signal lines in the motherboard also increases. This not only increases the thickness of the motherboard and slows down the heat dissipation of the motherboard, but also increases the routing density of the signal lines in the motherboard, resulting in severe crosstalk between the signal lines and causing signal distortion.

[0006] Summary of the Invention

[0007] An embodiment of the present disclosure provides an information processing device.

[0008] An embodiment of the present disclosure provides a signal processing device, comprising: a mainboard having a first surface, the first surface having a central processing unit electrically connected to the mainboard; a compressed additional memory module located on one side of the first surface, at least one surface of the compressed additional memory module having a plurality of chips; and an external connection structure located on one side of the first surface, configured to electrically connect the compressed additional memory module and the central processing unit, the central processing unit being configured to read and write data from each of the chips via at least the external connection structure.

[0009] In some embodiments, a motherboard has multiple signal lines, each of which electrically connects the central processing unit and the compressed additional memory module, and the central processing unit is configured to read and write data to each chip via the signal lines and the external connection structure.

[0010] In some embodiments, the external connection structure is located on a side of the compressed additional memory module facing the central processing unit.

[0011] In some embodiments, the height of the CAM module relative to the motherboard is greater than the height of the CPU relative to the motherboard.

[0012] In some embodiments, the system further includes: a central processing unit connector, the central processing unit connector being located on the first surface, and a height of the central processing unit connector relative to the motherboard being greater than a height of the central processing unit relative to the motherboard.

[0013] In some embodiments, the height of the CPU connector relative to the motherboard is the same as the height of the CAM module relative to the motherboard.

[0014] In some embodiments, a bottom surface of the CPU connector facing the first surface is electrically connected to the CPU, and a top surface of the CPU connector away from the first surface is electrically connected to the external connection structure.

[0015] In some embodiments, the motherboard is configured to: electrically connect the central processing unit connector and the central processing unit, the central processing unit and the motherboard are electrically connected through a gold finger or a ball grid array; the central processing unit connector and the external connection structure are electrically connected through any one of a ball grid array, a press-type connector or a silicon interposer.

[0016] In some embodiments, it further includes: a first adapter, located between the mainboard and the compressed additional memory module, for electrically connecting the mainboard and the compressed additional memory module, and the first adapter is also used to electrically connect the external connection structure and the compressed additional memory module.

[0017] In some embodiments, the external connection structure is in electrical contact with a surface of the first adapter facing the CAM module.

[0018] In some embodiments, the present invention further includes: a first adapter located between the mainboard and the compression additional memory module, for electrically connecting the mainboard and the compression additional memory module; and a second adapter located on a side of the compression additional memory module away from the mainboard, the second adapter electrically connecting the external connection structure and the compression additional memory module.

[0019] In some embodiments, the number of the compressed additional memory modules is two, the two compressed additional memory modules are stacked in a direction perpendicular to the first surface, and the two compressed additional memory modules are electrically connected to the central processing unit through the same external connection structure.

[0020] In some embodiments, the first adapter is a silicon interposer or a z-axis compression connector; and the external connection structure is a flexible circuit board.

[0021] In some embodiments, the compressed additional memory module has the multiple chips on one of its surfaces along a direction perpendicular to the first surface; or, the compressed additional memory module has the multiple chips on two opposite surfaces along a direction perpendicular to the first surface.

[0022] In some embodiments, it also includes: a top pad, located on the surface of the compressed additional memory module away from the mainboard, the top pad having at least one mounting hole; a bottom pad, fixed to the first surface, the bottom pad is located on the surface of the compressed additional memory module facing the mainboard, the bottom pad having at least one pin corresponding to the mounting hole; a fastener, matching the pin, the fastener is used to fix the pin after the pin passes through the mounting hole, so that the top pad and the bottom pad clamp and fix the compressed additional memory module. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] FIG1 is a schematic cross-sectional view of a first information processing device provided by an embodiment of the present disclosure;

[0025] FIG2 is a schematic cross-sectional view of a second information processing device provided by an embodiment of the present disclosure;

[0026] FIG3 is a schematic diagram of the three-dimensional structure of an information processing device provided by an embodiment of the present disclosure;

[0027] FIG4 is a schematic cross-sectional view of a third information processing device provided by an embodiment of the present disclosure;

[0028] FIG5 is a schematic cross-sectional view of a fourth information processing device provided by an embodiment of the present disclosure;

[0029] FIG6 is a schematic cross-sectional view of a fifth information processing device provided by an embodiment of the present disclosure;

[0030] FIG7 is a schematic cross-sectional view of a sixth information processing device provided by an embodiment of the present disclosure;

[0031] FIG8 is a schematic cross-sectional view of a seventh information processing device provided by an embodiment of the present disclosure;

[0032] FIG9 is a schematic cross-sectional view of an eighth information processing device provided by an embodiment of the present disclosure;

[0033] FIG10 is a schematic cross-sectional view of a ninth information processing device provided by an embodiment of the present disclosure;

[0034] FIG11 is a schematic cross-sectional view of a tenth information processing device provided by an embodiment of the present disclosure;

[0035] FIG12 is a schematic diagram of the three-dimensional structure of another information processing device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] As can be seen from the background, the motherboards in current signal processing devices have relatively poor heat dissipation capabilities. Analysis has revealed that one of the reasons for this poor heat dissipation is the large number of signal lines within the motherboard, which are used to electrically connect the central processing unit (CPU) and the compressed additional memory modules (CAMs). As the number of chips connected to the CAMs increases, the number of signal lines within the motherboard increases, leading to an increasing thickness of the motherboard and a significant reduction in its heat dissipation capabilities.

[0037] An embodiment of the present disclosure provides a signal processing device, in which an external connection structure is arranged on one side of the first surface of a mainboard for electrically connecting a compressed additional memory module and a central processing unit. That is, the external connection structure is routed from the outside of the mainboard to connect the compressed additional memory module and the central processing unit. In this way, the number of signal lines in the mainboard for electrically connecting the central processing unit and the compressed additional memory module can be reduced, and the provision of signal lines in the mainboard can even be eliminated, thereby greatly reducing the thickness of the mainboard and greatly increasing the heat dissipation capacity of the mainboard.

[0038] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0039] FIG1 is a schematic cross-sectional view of a first information processing device according to an embodiment of the present disclosure.

[0040] 1 to 3 , the signal processing device includes a mainboard 101 having a first surface, with a central processing unit 102 electrically connected to the mainboard 101 on the first surface. The signal processing device also includes a compressed additional memory module 103 located on one side of the first surface, with multiple chips 104 located on at least one surface of the compressed additional memory module 103. The signal processing device also includes an external connection structure 105 located on one side of the first surface and configured to electrically connect the compressed additional memory module 103 and the central processing unit 102. The central processing unit 102 is configured to read and write data from each chip 104 via at least the external connection structure 105.

[0041] The central processing unit 102, referred to as CPU for short, serves as the computing and control core of the computer system and is the final execution unit for information processing and program execution.

[0042] Mainboard 101, also known as a motherboard, can serve as a carrier for central processing unit 102 and compressed additional memory module 103 and electrically connect central processing unit 102 and compressed additional memory module 103. In some embodiments, mainboard 101 can be a system board, a logic board, or any other printed circuit board.

[0043] The compression attached memory module 103, also known as the "Compression Attached Memory Module" or CAMM for short, is a new form of notebook memory that is different from the traditional SO-DIMM. Its structure includes: a PCB circuit board and a chip 104 that can be installed on both sides.

[0044] When writing data to chip 104, CPU 102 sends address information via the address lines, then issues a memory write command via the control lines to select chip 104, and then writes data to the selected chip 104 via external connection structure 105. When reading data from chip 104, CPU 102 sends address information via the address lines, then issues a memory read command via the control lines to select chip 104. The selected chip 104 then sends the data in chip 104 to CPU 102 via external connection structure 105.

[0045] In some embodiments, the chip 104 may include any one of DRAM (Dynamic Random Access Memory), SRAM (Static Random-Access Memory), or SDRAM (Synchronous Dynamic Random-Access Memory).

[0046] In a specific example, chip 104 may be a DRAM, specifically some variant of synchronous DRAM, such as DDR3 (DDR version 3), DDR4 (DDR version 4), DDR5 (DDR version 5), LPDDR3 (Low Power DDR version 3), LPDDR4 (LPDDR version 4), LPDDR5 (LPDDR version 5), or other memory technologies or combinations thereof.

[0047] The external connection structure 105 is located on one side of the first surface of the motherboard 101. That is, the external connection structure 105 is set outside the motherboard 101 to realize the electrical connection between the central processing unit 102 and the compressed additional memory module 103. Since the chip 104 is electrically connected to the compressed additional memory module 103, the central processing unit 102 can read and write data to the chip 104 through the external connection structure 105 and the compressed additional memory module 103.

[0048] FIG2 is a schematic cross-sectional structural diagram of a second signal processing device provided in an embodiment of the present disclosure, and FIG3 is a schematic three-dimensional structural diagram of an information processing device provided in an embodiment of the present disclosure.

[0049] Referring to Figures 2 and 3 , in some embodiments, a motherboard 101 includes multiple signal lines 10. Each signal line 10 electrically connects a central processing unit 102 and a compressed additional memory module 103. The central processing unit 102 is configured to read and write data from each chip 104 via the signal lines 10 and the external connection structure 105. In other words, the external connection structure 105 and the signal lines 10 both enable signal transmission between the central processing unit 102 and the chips 104. The signal lines 10 are located within the motherboard 101, while the external connection structure 105 is located outside the motherboard 101. This significantly reduces the number of signal lines 10 within the motherboard 101. This reduces the volume occupied by the signal lines 10 within the motherboard 101, reducing the thickness of the motherboard 101 and facilitating heat dissipation. Furthermore, it significantly reduces the routing density of the signal lines 10 within the motherboard 101, thereby avoiding crosstalk between signals transmitted on different signal lines 10 and distortion of the signals transmitted on the signal lines 10, which can be caused by excessive routing density.

[0050] By jointly realizing signal transmission between the central processing unit 102 and the chip 104 through the external connection structure 105 and the signal line 10, the flexibility of the wiring of the external connection structure 105 and the signal line 10 can be enhanced, and the problem of too dense routing of the external connection structure 105 and the problem of too dense routing of the signal line 10 can be avoided, thereby greatly reducing the risk of signal distortion caused by excessive routing density.

[0051] Referring to FIG4 , in some embodiments, the motherboard 101 further includes a plurality of signal lines 10, and the signal processing device further includes: first pins 21 located on the first surface, with the central processing unit 102 electrically connected to the first pins 21 to achieve electrical connection with the motherboard 101. The signal lines 10 are electrically connected to some of the first pins 21, thereby electrically connecting the central processing unit 102 and the compressed additional memory module 103.

[0052] The signal processing device further includes a second pin 22 located on the first surface. The second pin 22 is electrically connected to the remaining first pins 21 and the second pin 22 is electrically connected to the external connection structure 105 to achieve an electrical connection between the central processing unit 102 and the external connection structure 105. In some embodiments, the mainboard 101 further includes a first lead 20. The first lead 20 is used to electrically connect the first pin 21 and the second pin 22, so that the second pin 22 can be electrically connected to the central processing unit 102, and further enable the external connection structure 105 electrically connected to the second pin 22 to be electrically connected to the central processing unit 102.

[0053] In some embodiments, the second pin 22 is located on the first surface between the central processing unit 102 and the compressed additional memory module 103 and is disposed adjacent to the first pin 21. This shortens the length of the first lead 20 in the motherboard 101, thereby reducing transmission loss of the signal transmitted in the first lead 20. Furthermore, since the shorter length of the first lead 20 reduces signal loss in the first lead 20, the diameter of the first lead 20 can be reduced, thereby reducing the volume occupied by the first lead 20 in the motherboard 101 and avoiding an increase in the thickness of the motherboard 101 due to the provision of the first lead 20.

[0054] In some embodiments, the diameter of the first lead 20 may be smaller than the diameter of the signal line 10. In this way, it can be ensured that the provision of the first lead 20 does not lead to a further increase in the thickness of the mainboard 101.

[0055] It is understood that in some embodiments, the signal line 10 may not be provided in the motherboard 101, so that the signal transmission between the chip 104 and the central processing unit 102 is only carried out through the external connection structure 105. In this way, the thickness of the motherboard 101 can be greatly reduced, and the heat dissipation of the motherboard 101 can be further enhanced.

[0056] In some embodiments, the chip 104 and the central processing unit 102 transmit signals only through the external connection structure 105 , and the signal processing device further includes: a first pin located on the first surface, and the central processing unit 102 is electrically connected to the first pin to achieve electrical connection with the motherboard 101 .

[0057] The signal processing device further includes a second pin located on the first surface, the second pin being electrically connected to the first pin, and the second pin being electrically connected to the external connection structure 105, so as to achieve an electrical connection between the central processing unit 102 and the external connection structure 105. In some embodiments, the mainboard 101 further includes a first lead, the first lead being used to electrically connect the first pin and the second pin.

[0058] In some embodiments, the first pin may be a gold finger or a ball grid array, and the second pin may be a gold finger or a ball grid array.

[0059] Gold finger is a structure composed of multiple golden conductive contacts. It is called gold finger because its surface is gold-plated and the conductive contacts are arranged like fingers.

[0060] The ball grid array is a spherical contact arrayed on the first surface of the motherboard 101. In some embodiments, the spherical contact may be solder balls arranged in an array.

[0061] Gold fingers and ball grid arrays can be formed on the first surface in a manner well known to those skilled in the art, and electrically contact the CPU 102 .

[0062] In some embodiments, the first lead 20 can be formed within the mainboard 101 by electroplating. The present disclosure does not limit the specific routing and shape of the first lead 20 within the mainboard 101; it is sufficient that the first lead 20 can electrically connect the first pin 21 and the second pin 22. The first lead 20 can be made of a metal material, such as at least one of copper, tungsten, nickel, silver, copper, or other conductive materials known to those skilled in the art.

[0063] With reference to Figures 1 to 3, in some embodiments, the external connection structure 105 is located on the side of the compressed additional memory module 103 facing the central processing unit 102. The central processing unit 102 and the compressed additional memory module 103 are both located on the first surface, and the central processing unit 102 and the compressed additional memory module 103 are arranged opposite each other. The external connection structure 105 can be located between the central processing unit 102 and the compressed additional memory module 103. The external connection structure 105 is located on the side of the compressed additional memory module 103 facing the central processing unit 102, that is, the external connection structure 105 is directly opposite the compressed additional memory module 103, and the height of the external connection structure 105 relative to the first surface is no higher than the height of the compressed additional memory module 103 relative to the first surface. In other words, the external connection structure 105 can be set up by utilizing the empty space between the compressed additional memory module 103 and the central processing unit 102. Moreover, since the height of the external connection structure 105 is no higher than the height of the compressed additional memory module 103, the external connection structure 105 does not occupy too much additional volume, thereby preventing the problem of the thickness of the information processing device being unable to be further reduced due to the excessive thickness of the external connection structure 105.

[0064] In some embodiments, the height of the CAM module relative to the motherboard 101 is greater than the height of the CPU 102 relative to the motherboard 101. In other words, the height of the CAM module 103 relative to the first surface, which is located away from the motherboard 101, is greater than the height of the CPU 102 relative to the first surface, which is located away from the motherboard 101.

[0065] 5 , in some embodiments, the signal processing device further includes a central processing unit connector 106, which is located on the first surface and is used to electrically connect the external connection structure 105 to the central processing unit 102. The central processing unit connector 106 is located between the central processing unit 102 and the compressed additional memory module 103 and is disposed adjacent to the central processing unit 102. This shortens the distance between the central processing unit connector 106 and the central processing unit 102, thereby enhancing electrical transmission performance between the central processing unit 102 and the external connection structure 105.

[0066] In some embodiments, the bottom surface of the CPU connector 106 facing the first surface is electrically connected to the CPU 102, and the top surface of the CPU connector 106 facing away from the first surface is electrically connected to the external connection structure 105. The bottom surface of the CPU connector 106 is electrically connected to the gold finger or ball grid array located on the first surface, and the top surface of the CPU connector 106 has a ball grid array or a press-type connector. The CPU connector 106 is electrically connected to the external connection structure 105 through any of the ball grid array, press-type connector, or silicon interposer located on the top surface.

[0067] One end of the external connection structure 105 is electrically connected to the CPU 102, and the other end is electrically connected to the compressed additional memory module 103. Specifically, the external connection structure 105 extends in the direction from the CPU 102 toward the compressed additional memory module 103. Because the height of the compressed additional memory module 103 relative to the first surface is higher than the height of the CPU 102 relative to the first surface, there is a significant height difference between the compressed additional memory module 103 and the CPU 102. This can result in inconsistent heights at both ends of the external connection structure 105, causing the external connection structure 105 to tilt relative to the first surface, which in turn causes the external connection structure 105 to occupy a larger space.

[0068] Based on the above considerations, in some embodiments, the height of the CPU connector 106 relative to the motherboard 101 is greater than the height of the CPU 102 relative to the motherboard 101. In other words, the height of the surface of the CPU connector 106 away from the motherboard 101 is greater than the height of the surface of the CPU 102 away from the motherboard 101. This ensures that the height difference between the CPU connector 106 and the CADMM module 103 is smaller than the height difference between the CPU 102 and the CADMM module 103. Because the external connection structure 105 is electrically connected to the CPU connector 106, the height difference between the external connection structure 105 and the CADMM module 103 is smaller than if it were directly connected to the CPU 102. This reduces the inclination of the external connection structure 105 relative to the first surface, thereby alleviating the problem of the large space occupied by the external connection structure 105.

[0069] Referring to Figure 6, in some embodiments, the bottom surface of the CPU connector 106, which faces the first surface, is electrically connected to the CPU 102, while the top surface of the CPU connector 106, which faces away from the first surface, is electrically connected to the external connection structure 105. This allows the height of the external connection structure 105 to be higher than the height of the CPU connector 106, minimizing the height difference between the external connection structure 105 and the compressed additional memory module 103. Because the two ends of the external connection structure 105 are electrically connected to the CPU connector 106 and the compressed additional memory module 103, respectively, reducing the height difference between the two ends of the external connection structure 105 can reduce the height difference to zero, thereby allowing the external connection structure 105 to be placed horizontally or nearly horizontally. Here, horizontal placement refers to placement parallel to the first surface. Compared with the external connection structure 105 being placed obliquely relative to the first surface, the external connection structure 105 is placed horizontally. On the one hand, it is beneficial to maintain the stability of the external connection structure 105. On the other hand, it makes the space occupied by the external connection structure 105 smaller, which can provide more space for the arrangement of other components on the surface of the mainboard 101, which is beneficial to the arrangement of wiring.

[0070] In some embodiments, the height of the CPU connector relative to the motherboard 101 is the same as the height of the compression add-on memory module 103 relative to the motherboard 101. In other words, the height of the surface of the CPU connector 106 away from the motherboard 101 relative to the first surface is the same as the height of the compression add-on memory module 103 relative to the motherboard 101 relative to the first surface. This allows the ends of the external connection structure 105 electrically connecting the CPU connector 106 and the compression add-on memory module 103 to be close in height relative to the first surface, resulting in a small height difference between the ends of the external connection structure 105, or even zero. This allows the external connection structure 105 to be positioned substantially parallel to the first surface, minimizing the space occupied by the external connection structure 105 on one side of the first surface.

[0071] In some embodiments, the height of the CPU connector 106 relative to the motherboard 101 is the same as the height of the CAM module 103 relative to the motherboard 101. Alternatively, the height of the surface of the CPU connector 106 away from the motherboard 101 relative to the first surface is the same as the height of the surface of the CAM module 103 facing the motherboard 101 relative to the first surface.

[0072] In some embodiments, the height of the surface of the CPU connector 106 away from the motherboard 101 relative to the first surface may be different from the height of the surface of the compression add-on memory module 103 away from the motherboard 101 relative to the first surface. For example, the height of the surface of the CPU connector 106 away from the motherboard 101 relative to the first surface may be slightly higher than the height of the surface of the compression add-on memory module 103 away from the motherboard 101 relative to the first surface. Alternatively, the height of the surface of the CPU connector 106 away from the motherboard 101 relative to the first surface may be slightly lower than the height of the surface of the compression add-on memory module 103 away from the motherboard 101 relative to the first surface.

[0073] Referring to Figure 7, in some embodiments, the motherboard 101 is configured as follows: the central processing unit connector 106 is electrically connected to the central processing unit 102, and the central processing unit 102 is electrically connected to the motherboard 101 through a gold finger or a ball grid array; the central processing unit connector 106 and the external connection structure 105 are electrically connected through any one of a ball grid array, a press-type connector or a silicon interposer.

[0074] In some embodiments, the first surface is provided with a gold finger or ball grid array, and is also provided with a first pin 21. The first pin 21 is used to electrically connect the CPU 102 to the motherboard 101. A first lead 20 is also provided within the motherboard 101. The first lead 20 is used to lead the signal from the first pin 21 to the gold finger or ball grid array on the first surface, and further to the CPU connector 106 through the gold finger or ball grid array. In a specific example, the material of the first lead 20 can be a metal material, such as at least one of copper, tungsten, nickel, silver, copper, or other conductive materials known to those skilled in the art.

[0075] In some embodiments, the surface of the CPU connector 106 is provided with any one of a ball grid array, a press-type connector, or a silicon interposer, and a connection structure is provided inside the CPU 102. The connection structure is used to transmit the signal of the CPU 102 to the ball grid array or the press-type connector located on the surface of the CPU connector 106, and then transmit it to the external connection structure 105 via the ball grid array or the press-type connector.

[0076] In some embodiments, a silicon interposer is provided on the surface of the central processing unit connector 106, and the silicon interposer includes a through silicon via (TSV). The TSV passes through the silicon interposer along the thickness direction of the silicon interposer. The bottom end of the TSV is electrically contacted with the connection structure in the central processing unit connector 106, and the top end of the TSV is electrically connected to the external connection structure 105.

[0077] In some embodiments, the connection structure may be a second lead. The present disclosure does not specify the specific routing and shape of the second lead in the CPU connector 106. The second lead only needs to be able to route signals from the CPU 102 to any of the ball grid arrays, press-type connectors, or silicon interposers located on the surface of the CPU connector 106. The second lead may be made of at least one of copper, tungsten, nickel, silver, copper, or other conductive materials known to those skilled in the art.

[0078] 6 and 7 , in some embodiments, the signal processing device further includes a first adapter 107 located between the mainboard 101 and the compressed additional memory module 103, for electrically connecting the mainboard 101 and the compressed additional memory module 103. The first adapter 107 is also used to electrically connect the external connection structure 105 and the compressed additional memory module 103. In other words, the external connection structure 105 and the mainboard 101 share the same first adapter 107, thereby saving space.

[0079] In some embodiments, the external connection structure 105 and the motherboard 101 share a common first adapter 107. The motherboard 101 includes multiple signal lines 10, each of which electrically connects the central processing unit 102 and the compressed additional memory module 103. The signal lines 10 in the motherboard 101 are electrically connected to the first adapter 107, and the external connection structure 105 is electrically connected to the first adapter 107. Both the signal lines 10 and the external connection structure 105 can implement signal transmission between the central processing unit 102 and the chip 104.

[0080] Continuing with reference to Figures 6 and 7, in some embodiments, the external connection structure is in electrical contact with the surface of the first adapter 107 facing the compression add-on memory module 103. In one specific example, the signal line 10 is electrically connected to the surface of the first adapter 107 facing the motherboard 101, and the external connection structure 105 is electrically connected to the surface of the first adapter 107 facing the compression add-on memory module 103. In other words, the external connection structure 105 and the signal line 10 are located on opposite surfaces of the first adapter 107, respectively, to avoid signal crosstalk between the external connection structure 105 and the signal line 10, which would otherwise occur if the external connection structure 105 and the signal line 10 were located on the same surface of the first adapter 107.

[0081] The side of the first adapter 107 facing the compression additional memory module 103 is also electrically connected to the compression additional memory module 103 , thereby being able to transmit the signals transmitted in the external connection structure 105 and the signal line 10 to the compression additional memory module 103 .

[0082] In some embodiments, the compressed additional memory module 103 has: a first trace 41, the first trace 41 is used to electrically connect the first connection line and the chip 104, and the first trace 41 is also used to electrically connect the first adapter 107, that is, the side of the first adapter 107 facing the compressed additional memory module 103 is electrically connected to the first trace 41, the first trace 41 is used to transmit the transmission signal from the first adapter 107 and transmit it to the chip 104, or, the signal in the chip 104 can be transmitted to the first adapter 107 through the first trace 41.

[0083] In some embodiments, the first adapter 107 may be a silicon interposer or a z-axis compression connector. In some embodiments, the external connection structure 105 may be a flexible circuit board.

[0084] In some embodiments, the first adapter 107 is a first silicon interposer, and the first silicon interposer includes a first through-silicon via 111. The first through-silicon via 111 penetrates the first silicon interposer along the thickness direction of the first silicon interposer. The first silicon interposer exposes the top and bottom ends of the first through-silicon via 111. The signal line 10 is electrically connected to the bottom end of the first through-silicon via 111 toward the mainboard 101, and the first through-silicon via 111 is electrically connected to the first trace 41 away from the top end of the mainboard 101.

[0085] In some embodiments, the surface of the first silicon interposer facing away from the motherboard may further include a third pin 31. The third pin 31 is electrically connected to the top of the first through-silicon via 111. The side of the external connection structure 105 facing the first silicon interposer is electrically connected to the third pin 31. Since the third pin 31 is electrically connected to the top of the first through-silicon via 111, and the bottom of the first through-silicon via 111 is electrically connected to the signal line 10, the external connection structure 105 and the signal line are also electrically connected. In this way, the signal transmitted in the signal line can also be transmitted to the compressed additional memory module 103 via the external connection structure 105. The remaining third pins 31 are electrically connected to the compressed additional memory module 103, used to input the signal transmitted in the signal line within the motherboard into the compressed additional memory module 103.

[0086] In some embodiments, the third pin 31 can be any one of a gold finger or a ball grid array, the electrical connection structure can be a conductive metal wire, and the material of the electrical connection structure can be at least one of copper, tungsten, nickel, silver, copper or other conductive materials known to those skilled in the art.

[0087] A flexible printed circuit board (FPC) is a highly reliable and flexible printed circuit board made from polyimide or polyester film. It features high wiring density, light weight, thin thickness, and excellent flexibility. Using a FPC as the external connection structure 105 prevents failure of the external connection structure 105 due to bending during the packaging process. Furthermore, the FPC's thinness prevents the external connection structure 105 from occupying excessive space, reducing the overall thickness of the signal processing device. This facilitates device miniaturization and enhances the overall heat dissipation capability of the signal processing device.

[0088] 8 to 10 , in some embodiments, the motherboard 101 and the external connection structure 105 may not share the same first adapter 107 . The signal processing device then includes: a first adapter 107 located between the motherboard 101 and the compressed additional memory module 103 and configured to electrically connect the motherboard 101 and the compressed additional memory module 103 ; and a second adapter 108 located on a side of the compressed additional memory module 103 away from the motherboard 101 and configured to electrically connect the external connection structure 105 and the compressed additional memory module 103 .

[0089] That is to say, the first adapter 107 and the second adapter 108 are respectively located on opposite sides of the compressed additional memory module 103, the first adapter 107 is only electrically connected to the signal line 10, and the second adapter 108 is only electrically connected to the external connection structure 105, so that the wiring density of the wiring used for signal transmission in the first adapter 107 and the second adapter 108 is relatively small, which can avoid the problem of signal crosstalk caused by excessive wiring density in the first adapter 107 and the second adapter 108.

[0090] In some embodiments, the signal line 10 within the motherboard 101 is electrically connected to a side of the first adapter 107 facing the motherboard 101, and a side of the first adapter 107 facing away from the motherboard 101 is electrically connected to the compression additional memory module 103. The external connection structure 105 is electrically connected to a side of the second adapter 108 facing away from the compression additional memory module 103, and a side of the second adapter 108 facing the compression additional memory module 103 is electrically connected to the compression additional memory module 103.

[0091] That is, in the first adapter 107, the side that is closer to the compression additional memory module 103 is electrically connected to the compression additional memory module 103, and in the second adapter 108, the side that is closer to the compression additional memory module 103 is electrically connected to the compression additional memory module 103. In this way, the wiring distance between the first adapter 107 and the compression additional memory module 103 can be reduced, and the wiring distance between the second adapter 108 and the compression additional memory module 103 can be reduced, which is conducive to saving wiring length.

[0092] In some embodiments, first adapter 107 is a first silicon interposer. The first silicon interposer includes a first through-silicon via (TSV) 111. The TSV 111 extends through the first silicon interposer along its thickness, leaving the top and bottom ends of TSV 111 exposed. Signal line 10 is electrically connected to the bottom end of TSV 111, which faces toward motherboard 101. The top end of TSV 111, which faces away from motherboard 101, is electrically connected to CRAM module 103. Second adapter 108 is a second silicon interposer. The second silicon interposer includes a second TSV 112. The second TSV 112 extends through the second silicon interposer along its thickness, leaving the top and bottom ends of TSV 112 exposed. The bottom end of second TSV 112 faces the surface of CRAM module 103 facing away from motherboard 101 and is electrically connected to the side of CRAM module 103 facing away from motherboard 101. External connection structure 105 is electrically connected to the top end of second TSV 112.

[0093] In some embodiments, the information processing device includes a first adapter 107 and a second adapter 108, and the compressed additional memory module 103 has: a first trace 41, the first trace 41 is used to electrically connect the first connection line and the chip 104, and the first trace 41 is also used to electrically connect the first adapter 107; a second trace 42, the second trace 42 is used to electrically connect the external connection structure 105 and the chip 104, and the second trace 42 is also used to electrically connect the second adapter 108.

[0094] In some embodiments, the compressed additional memory module 103 includes a third surface and a fourth surface facing each other, with the fourth surface facing the first surface. The first trace 41 and the second trace 42 are arranged in a direction parallel to the third surface. In other words, the second trace 42 is arranged horizontally with the first trace 41. This ensures that the second trace 42 and the first trace 41 do not occupy space in the thickness direction of the compressed additional memory module 103. Compared to the second trace 42 and the first trace 41 being arranged in a direction parallel to the third surface, the second trace 42 and the first trace 41 are arranged in a direction parallel to the third surface, which significantly reduces the thickness of the compressed additional memory module 103.

[0095] In some embodiments, the top of the first through silicon via 111 is electrically connected to the first trace 41 , and the bottom of the second through silicon via 112 is electrically connected to the second trace 42 , wherein the top of the first through silicon via 111 faces the third surface, and the bottom of the second through silicon via 112 faces the fourth surface.

[0096] Referring to Figure 8 , in some embodiments, the compressed additional memory module includes multiple chips 104 on one of its surfaces perpendicular to the first surface. In some embodiments, the compressed additional memory module 103 includes a third surface and a fourth surface, with the third surface facing the first surface. The multiple chips 104 may be located only on the third surface or only on the fourth surface. Each chip 104 may be electrically connected to either the external connection structure 105 or the signal line 10. In other words, the CPU 102 can read and write data to a chip 104 via either the external connection structure 105 or the signal line 10.

[0097] 9 , in some embodiments, the CAM 103 has multiple chips 104 on two opposite surfaces perpendicular to the first surface. That is, multiple chips 104 are provided on both the third and fourth surfaces, thereby increasing the integration of the chips 104.

[0098] Referring to Figure 9, in some embodiments, the signal processing device includes a first adapter 107 and a second adapter 108. The first adapter 107 is located on one side of the third surface, and the second adapter 108 is located on one side of the fourth surface. The external connection structure 105 is electrically connected to the second adapter 108, and the signal line 10 is electrically connected to the first adapter 107. The second adapter 108 can then be electrically connected to the chip 104 on the fourth surface, meaning that the central processing unit 102 can read and write data to the chip 104 on the fourth surface via the external connection structure 105. The first adapter 107 can also be electrically connected to the chip 104 on the third surface, and the central processing unit 102 can read and write data to the chip 104 on the third surface via the signal line 10 within the motherboard 101. This reduces wiring length and simplifies routing.

[0099] 8 , in some embodiments, each chip 104 of the plurality of chips 104 located on the third side may also be electrically connected to either the external connection structure 105 or the signal line 10. Each chip 104 of the plurality of chips 104 located on the fourth side may also be electrically connected to either the external connection structure 105 or the signal line 10.

[0100] Referring to FIG. 11 , in some embodiments, there are two compressed additional memory modules 103. The two compressed additional memory modules 103 are stacked in a direction perpendicular to the first surface, and the two compressed additional memory modules 103 are electrically connected to the central processing unit 102 via the same external connection structure 105. At least one surface of each of the two compressed additional memory modules 103 has multiple chips 104. Through the same external connection structure 105, the central processing unit 102 can read and write data to the chips 104 located on the surface of any compressed additional memory module 103. This increases the number of chips 104 electrically connected to the central processing unit 102 while maintaining the number of external connection structures 105, thereby improving the integration of the chips 104.

[0101] Since the external connection structure 105 is arranged outside the mainboard 101, the number of signal lines 10 in the mainboard 101 can be reduced, or even the arrangement of the signal lines 10 in the mainboard 101 can be omitted. In this way, while improving the integration of the chip 104, the heat dissipation capacity of the mainboard 101 can be enhanced, which is beneficial to ensuring the excellent performance of the mainboard 101 and ensuring that the information processing device has a higher operating speed.

[0102] In some embodiments, the two compressed additional memory modules 103 are respectively referred to as: a first compressed additional memory module 121 and a second compressed additional memory module 122 . The first compressed additional memory module 121 is adjacent to the first surface, and the second compressed additional memory module 122 is located on a side of the first compressed additional memory module 121 away from the motherboard 101 .

[0103] The information processing device may include a first adapter 107 and a second adapter 108. The first adapter 107 is located between the first compressed additional memory module 121 and the first surface and is used to electrically connect the motherboard 101 and the first compressed additional memory module 121. The second adapter 108 is located between the first compressed additional memory module 121 and the second compressed additional memory module 122 and is used to electrically connect to the external connection structure 105. The second adapter 108 is electrically connected to the first compressed additional memory module 121 and the second compressed additional memory module 122 and is used to transmit signals in the external connection structure 105 to the first compressed additional memory module 121 and the second compressed additional memory module 122, respectively.

[0104] In a specific example, the first adapter 107 may be a first silicon interposer, the second adapter 108 may be a second silicon interposer, and the first silicon interposer includes a first through-silicon via 111. The first through-silicon via 111 extends through the first silicon interposer. The top end of the first through-silicon via 111 is electrically connected to the first compressed additional memory module 121, and the bottom end of the first through-silicon via 111 is electrically connected to the motherboard 101. Specifically, the motherboard 101 may have a signal line 10 therein, the signal line 10 is electrically connected to the central processing unit 102, and the bottom end of the first through-silicon via 111 may be electrically connected to the signal line 10.

[0105] The second silicon interposer includes a second through silicon via 112 , which passes through the second silicon interposer. The top of the second through silicon via 112 is electrically connected to the second compression additional memory module 122 , and the bottom of the second through silicon via 112 is electrically connected to the first compression additional memory module 121 .

[0106] In some embodiments, the surface of the second silicon interposer may include a fourth pin 32, which is located on either a surface of the second silicon interposer facing away from the motherboard 101 or a surface of the second silicon interposer facing the motherboard 101. The surface of the external connection structure 105 facing the second silicon interposer is in electrical contact with the third pin 31, so that a signal transmitted in the external connection structure 105 can be transmitted through the third pin 31 to the second through-silicon via 112, and finally transmitted to the first compressed additional memory module 121 through the second through-silicon via 112.

[0107] The second compressed additional memory module 122 may include a fifth pin 33 facing the surface of the second silicon interposer, and the fifth pin 33 is electrically contacted with the surface of the external connection structure facing the second compressed additional memory module 122, so that the signal transmitted in the external connection structure 105 can be transmitted to the second compressed additional memory module 122 through the fifth pin 33.

[0108] In some embodiments, the fourth pin 32 may be a gold finger or a ball grid array, and the electrical connection structure may be a conductive metal wire. The material of the electrical connection structure may be at least one of copper, tungsten, nickel, silver, copper, or other conductive materials known to those skilled in the art. In some embodiments, the fifth pin 33 may be a gold finger or a ball grid array, and the electrical connection structure may be a conductive metal wire. The material of the electrical connection structure may be at least one of copper, tungsten, nickel, silver, copper, or other conductive materials known to those skilled in the art.

[0109] Referring to Figure 12, in some embodiments, the signal processing device also includes: a top pad 11, located on the surface of the compressed additional memory module 103 away from the motherboard 101, the top pad 11 has at least one mounting hole 13; a bottom pad 12, fixed to the first surface, the bottom pad 12 is located on the surface of the compressed additional memory module 103 facing the motherboard 101, the bottom pad 12 has at least one pin 14 corresponding to the mounting hole 13; a fastener 15, matching the pin 14, the fastener 15 is used to fix the pin 14 after the pin 14 passes through the mounting hole 13, so that the top pad 11 and the bottom pad 12 clamp and fix the compressed additional memory module 103.

[0110] In some embodiments, the top plate 11 may have two mounting holes 13, and the bottom plate 12 may have two latches 14, with each latch 14 corresponding to a mounting hole 13. The two mounting holes 13 are located on opposite sides of the top plate 11, thereby improving the installation stability of the top plate 11 and the bottom plate 12.

[0111] In some embodiments, the top base plate 11 may have more than two mounting holes 13, and the bottom base plate 12 may have more than two latches 14; alternatively, the top base plate 11 may have only one mounting hole 13, and the bottom base plate 12 may have only one latch 14. It is only necessary that the number of mounting holes 13 matches the number of latches 14. The number of mounting holes 13 and latches 14 can be flexibly set according to different needs.

[0112] In some embodiments, the latch 14 may be a wire screw insert, which is an internally threaded fastener 15 having internal threads on its inner side. The fastener 15 may be any screw, which is screwed into the wire screw insert to lock the wire screw insert. After the wire screw insert is inserted into the mounting hole 13, the wire screw insert is fixed in the mounting hole 13 to prevent the wire screw insert from slipping out of the mounting hole 13.

[0113] In some embodiments, the pin 14 can also be a bolt, and the fastener 15 can also be a nut. The side of the bolt has an external thread, and the inside of the nut has an internal thread that matches the external thread on the outside of the bolt. After the bolt is inserted into the mounting hole 13, the nut is screwed into the outer side of the bolt and locked with the bolt, thereby fixing the bolt in the mounting hole 13 to prevent the bolt from slipping out of the mounting hole 13, so that the top and bottom pads 12 can clamp and fix the compressed additional memory module 103 to prevent the compressed additional memory module 103 from moving.

[0114] In the information processing device provided in the above embodiment, an external connection structure 105 is provided on one side of the first surface of the motherboard 101 for electrically connecting the compressed additional memory module 103 and the central processing unit 102. In other words, the external connection structure 105 is routed from the outside of the motherboard 101, connecting the compressed additional memory module 103 and the central processing unit 102. This reduces the number of signal lines 10 in the motherboard 101 for electrically connecting the central processing unit 102 and the compressed additional memory module 103, and can even eliminate the need for signal lines 10 in the motherboard 101. This significantly reduces the thickness of the motherboard 101, significantly shortening the heat dissipation path of the motherboard 101, and thus enhancing heat dissipation of the motherboard 101.

[0115] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. An information processing device, include: A mainboard (101) having a first surface, wherein the first surface has a central processing unit (102) electrically connected to the mainboard (101); A compressed additional memory module (103) is located on one side of the first surface, and at least one surface of the compressed additional memory module (103) has a plurality of chips (104); The external connection structure (105) is located on one side of the first surface and is configured to electrically connect the compressed additional memory module (103) and the central processing unit (102); the central processing unit (102) is configured to read and write data to each of the chips (104) at least via the external connection structure (105).

2. The information processing device according to claim 1, in, The mainboard (101) has a plurality of signal lines (10), each of the signal lines (10) electrically connecting the central processing unit (102) and the compressed additional memory module (103), and the central processing unit (102) is configured to read and write data to each of the chips (104) via the signal lines (10) and the external connection structure (105).

3. The information processing device according to claim 1 or 2, in, The external connection structure (105) is located on a side of the compressed additional memory module (103) facing the central processing unit (102).

4. The information processing device according to claim 3, in, The height of the compressed additional memory module (103) compared to the mainboard (101) is greater than the height of the central processing unit (102) compared to the mainboard (101).

5. The information processing device according to any one of claims 1 to 4, in, It also includes: a central processing unit connector (106), the central processing unit connector (106) is located on the first surface, and the height of the central processing unit connector (106) compared to the mainboard (101) is greater than the height of the central processing unit (102) compared to the mainboard (101).

6. The information processing device according to claim 5, in, The height of the central processing unit connector relative to the mainboard (101) is the same as the height of the compressed additional memory module (103) relative to the mainboard (101).

7. The information processing device according to claim 5, in, The bottom surface of the CPU connector (106) facing the first surface is electrically connected to the CPU (102), and the top surface of the CPU connector (106) away from the first surface is electrically connected to the external connection structure (105).

8. The information processing device according to claim 6, in, The mainboard (101) is configured to: electrically connect the central processing unit connector (105) and the central processing unit (102), the central processing unit (102) and the mainboard (101) are electrically connected via a gold finger or a ball grid array; the central processing unit connector (106) and the external connection structure (105) are electrically connected via any one of a ball grid array, a press-type connector or a silicon interposer.

9. The information processing device according to any one of claims 1 to 5, in, The invention also comprises: a first adapter (107) located between the mainboard (101) and the compressed additional memory module (103) and used for electrically connecting the mainboard (101) and the compressed additional memory module (103); and the first adapter (107) is also used for electrically connecting the external connection structure (105) and the compressed additional memory module (103).

10. The information processing device according to claim 9, in, The external connection structure (105) is in electrical contact with a surface of the first adapter (107) on one side facing the compressed additional memory module (103).

11. The information processing device according to any one of claims 1 to 5, in, Also includes: A first adapter (107), located between the mainboard (101) and the compressed additional memory module (103), and used for electrically connecting the mainboard (101) and the compressed additional memory module (103); The second adapter (108) is located on a side of the compressed additional memory module (103) away from the mainboard (101), and the second adapter (108) electrically connects the external connection structure (105) and the compressed additional memory module (103).

12. The information processing device according to claim 11, in, The number of the compressed additional memory modules (103) is two, the two compressed additional memory modules (103) are stacked in a direction perpendicular to the first surface, and the two compressed additional memory modules (103) are electrically connected to the central processing unit (102) via the same external connection structure (105).

13. The information processing device according to claim 9 or 11, in, The first adapter (107) is a silicon interposer or a z-axis compression connector; and the external connection structure (105) is a flexible circuit board.

14. The information processing device according to any one of claims 1 to 5, 9 or 11, in, The compressed additional memory module (103) has the multiple chips (104) on one of its surfaces along a direction perpendicular to the first surface; or, the compressed additional memory module (103) has the multiple chips (104) on two opposite surfaces along a direction perpendicular to the first surface.

15. The information processing device according to any one of claims 1 to 14, in, Also includes: A top pad (11), located on a surface of the compressed additional memory module (103) away from the mainboard (101), the top pad (11) having at least one mounting hole (13); A bottom pad (12) fixed to the first surface, the bottom pad (12) being located on the surface of the compressed additional memory module (103) facing the mainboard (101), and the bottom pad (12) having at least one latch (14) corresponding to the mounting hole (13); A fastener (15) matches the latch (14), and the fastener (15) is used to fix the latch (14) after the latch (14) passes through the mounting hole (13), so that the top pad (11) and the bottom pad (12) clamp and fix the compressed additional memory module (103).

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