Display panel

Abstract

A display panel (100). In a low-frequency display mode of the display panel (100), one display frame comprises a write frame and a maintenance frame behind the write frame, and when the display panel (100) is converted from a high-frequency display mode to the low-frequency display mode, at least two of a first reset signal (VI1), a second reset signal (VI2) and a data signal (Data) are different from those in the high-frequency display mode at the write frame, and at least two of the first reset signal (VI1), the second reset signal (VI2) and the data signal (Data) are different from those in the high-frequency display mode at the maintenance frame.

Description

Display panel Technical Field

[0001] The present application relates to the field of display, and in particular to a display panel. Background Art

[0002] Organic Electroluminescence Display (OLED) panels are already widely used in our daily lives, such as in mobile phones, laptops, and television screens. With the continuous development of display technology, the demand for low power consumption is increasing, and low-frequency display drivers can effectively reduce power consumption.

[0003] However, the present applicant has discovered that when the display panel switches from high-frequency display to low-frequency display, there are display problems such as flickering and low brightness. SUMMARY OF THE INVENTION

[0004] The embodiments of the present application provide a display panel that can solve the display problems found in the present application, such as flickering and low brightness, when the display panel is converted from high-frequency display to low-frequency display.

[0005] In an embodiment of the present application, a light-emitting element and a pixel driving circuit electrically connected to the light-emitting element are included, wherein the pixel driving circuit includes a driving transistor, a first reset module, a second reset module and a writing module;

[0006] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0007] The input end of the writing module receives a data signal, and the output end of the writing module is electrically connected to the second node;

[0008] An input end of the first reset module receives a first reset signal, and an output end of the first reset module is electrically connected to a first end of the light emitting element;

[0009] An input end of the second reset module receives a second reset signal, and an output end of the second reset module is electrically connected to the first node;

[0010] The first end of the light emitting element is electrically connected to the third node;

[0011] Wherein, in the low-frequency display mode of the display panel, one display frame includes a writing frame and a sustaining frame following the writing frame;

[0012] In which, when the display panel is converted from the high-frequency display mode to the low-frequency display mode, at least two of the first reset signal, the second reset signal and the data signal in the low-frequency display mode are different from those in the high-frequency display mode in the write frame, and at least two of the first reset signal, the second reset signal and the data signal in the low-frequency display mode are different from those in the high-frequency display mode in the maintain frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0014] FIG1 is a schematic diagram showing brightness changes of a display panel when switching from high-frequency display to low-frequency display in the prior art;

[0015] FIG2 is a pixel driving circuit illustrated by way of example in an embodiment of the present application;

[0016] FIG3 is a schematic diagram of an improved timing sequence provided by an embodiment of the present application;

[0017] FIG4 is a schematic diagram showing the brightness change of the display panel when the display is switched from high-frequency display to low-frequency display in the present application. Modes for Carrying Out the Invention

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0019] Please refer to Figure 1, which is a schematic diagram of the brightness change of a display panel when switching from high-frequency display to low-frequency display in the prior art. The horizontal axis in Figure 1 represents time, and the vertical axis represents brightness. Figure 1 uses 120 Hz for high-frequency display and 10 Hz for low-frequency display as an example. As can be seen from Figure 1, when displaying at 10 Hz, a display frame includes one write frame (one write frame corresponds to one brightness pulse) and 11 hold frames following the write frame (11 hold frames correspond to 11 brightness pulses). Figure 1 illustrates the brightness of the first, second, third, fourth, and fifth display frames. As can be seen from Figure 1, the following display issues exist: the brightness of the first and second display frames is lower than that of the fourth and fifth display frames; the brightness of the hold frame in the first display frame decreases too quickly; and when switching from 120 Hz to 10 Hz, the brightness of the first and second display frames changes significantly, resulting in flicker. Therefore, in summary, current display panels have the following display issues when switching from high-frequency display to low-frequency display: flickering occurs when switching from high-frequency display to low-frequency display; the brightness of the first few display frames of low-frequency display is low; and the brightness of the sustain frames of the first few display frames of low-frequency display drops too quickly. These issues make it possible for people to perceive display issues such as flickering and low brightness when the display panel switches from high-frequency display to low-frequency display.

[0020] Based on the problems existing in the above-mentioned display panel when converting from high-frequency display to low-frequency display, in order to solve one or more of the above-mentioned display problems, the present application proposes a display panel, including a light-emitting element and a pixel driving circuit electrically connected to the light-emitting element, the pixel driving circuit including a driving transistor, a first reset module, a second reset module and a writing module; the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node; the input end of the writing module is connected to the data signal, and the output end of the writing module is electrically connected to the second node; the input end of the first reset module is connected to the first reset signal, the first reset module is electrically connected to the second node, and the second reset module is electrically connected to the third node. The output end of the bit module is electrically connected to the third node; the input end of the second reset module is connected to the second reset signal, and the output end of the second reset module is electrically connected to the first node; the first end of the light-emitting element is electrically connected to the third node; wherein, in the low-frequency display mode of the display panel, a display frame includes a write frame and a maintenance frame after the write frame; wherein, when the display panel is converted from the high-frequency display mode to the low-frequency display mode, at least two of the first reset signal, the second reset signal and the data signal in the low-frequency display mode are different in the write frame and the high-frequency display mode, and at least two of the first reset signal, the second reset signal and the data signal in the low-frequency display mode are different in the maintenance frame and the high-frequency display mode.

[0021] Optionally, in some embodiments of the present application, in the low-frequency display mode, the voltage of the second reset signal of at least the write frame of the first display frame and the write frame of the second display frame is lower than the voltage of the second reset signal in the high-frequency display mode.

[0022] Optionally, in some embodiments of the present application, a voltage of the second reset signal in the write frame of the first display frame is 0 to 0.25V lower than a voltage of the second reset signal in the high-frequency display mode;

[0023] The voltage of the second reset signal in the write frame of the second display frame is 0 to 0.25V lower than the voltage of the second reset signal in the high-frequency display mode.

[0024] Optionally, in some embodiments of the present application, the voltage of the second reset signal of the sustain frame of the first display frame and the sustain frame of the second display frame is equal to the voltage of the second reset signal in the high-frequency display mode.

[0025] Optionally, in some embodiments of the present application, in the low-frequency display mode, the voltage of the second reset signal of the Nth display frame is equal to the voltage of the second reset signal in the high-frequency display mode, and N is a positive integer greater than or equal to 3.

[0026] Optionally, in some embodiments of the present application, in the low-frequency display mode, at the same grayscale, the voltage of the data signal of at least the write frame of the first display frame and the write frame of the second display frame is lower than the voltage of the data signal in the high-frequency display mode.

[0027] Optionally, in some embodiments of the present application, a voltage of the data signal of the write frame of the first display frame is 0 to 60 mV lower than a voltage of the data signal in the high-frequency display mode;

[0028] The voltage of the data signal in the write frame of the second display frame is 0 to 60 mV lower than the voltage of the data signal in the high-frequency display mode.

[0029] Optionally, in some embodiments of the present application, a voltage of the data signal of the write frame of the first display frame is smaller than a voltage of the data signal of the write frame of the second display frame.

[0030] Optionally, in some embodiments of the present application, in the low-frequency display mode, at the same grayscale, the voltage of the data signal of the write frame of the Nth display frame is equal to the voltage of the data signal in the high-frequency display mode, and N is a positive integer greater than or equal to 3.

[0031] Optionally, in some embodiments of the present application, in the low-frequency display mode, at the same grayscale, the voltage of the data signal of the maintenance frame of the display frame is greater than the voltage of the data signal in the high-frequency display mode.

[0032] Optionally, in some embodiments of the present application, the voltage of the data signal in the sustain frame of the display frame is 0 to 2V greater than the voltage of the data signal in the high-frequency display mode.

[0033] Optionally, in some embodiments of the present application, in the low-frequency display mode, the voltage of the first reset signal of the sustain frame of the display frame is greater than the voltage of the first reset signal in the high-frequency display mode.

[0034] Optionally, in some embodiments of the present application, the voltage of the first reset signal in the sustain frame of the display frame is 0 to 0.2V greater than the voltage of the first reset signal in the high-frequency display mode.

[0035] Optionally, in some embodiments of the present application, the voltage of the first reset signal of the write frame of the display frame is equal to the voltage of the first reset signal in the high-frequency display mode.

[0036] Optionally, in some embodiments of the present application, in the low-frequency display mode, at the same grayscale, the voltage of the data signal of at least the write frame of the first display frame and the write frame of the second display frame is lower than the voltage of the data signal in the high-frequency display mode.

[0037] It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0038] Please refer to Figures 2 and 3. Figure 2 illustrates a pixel driving circuit according to an embodiment of the present application; Figure 3 illustrates an improved timing diagram according to an embodiment of the present application. While the present application uses the pixel driving circuit in Figure 2 as an example for illustration, the present invention is applicable to other pixel driving circuits and other display panels.

[0039] As shown in Figure 2, the display panel 100 includes a plurality of light-emitting elements LD and a plurality of pixel driving circuits electrically connected to the plurality of light-emitting elements LD. The pixel driving circuit is used to drive the light-emitting elements LD to emit light. The pixel driving circuit includes: a first transistor T1 (i.e., a driving transistor), a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, the light-emitting element LD, a first storage capacitor Cst1, and a second storage capacitor Cst2.

[0040] Among them, the gate of the first transistor T1 is electrically connected to the first node Q, the drain (or source) of the first transistor T1 is electrically connected to the second node A, and the source (or drain) of the first transistor T1 is electrically connected to the third node B; the drain of the second transistor T2 is electrically connected to the data signal line to receive the data signal Data, the source of the second transistor T2 is electrically connected to the second node A, and the gate of the second transistor T2 is electrically connected to the first scan signal line to respond to the first scan signal PScan(n); the drain of the third transistor T3 is electrically connected to the third node B, and the source of the second transistor T2 is electrically connected to the first scan signal line to respond to the first scan signal PScan(n). The source of the third transistor T3 is electrically connected to the first node Q, and the gate of the third transistor T3 is electrically connected to the second scan signal line to respond to the second scan signal NScan(n); the drain of the fourth transistor T4 is electrically connected to the second reset signal line to receive the second reset signal VI2, the source of the fourth transistor T4 is electrically connected to the first node Q, and the gate of the fourth transistor T4 is electrically connected to the third scan signal line to respond to the third scan signal NScan(n-7); the gates of the fifth transistor T5 and the sixth transistor T6 are both electrically connected to the enable signal line to respond to the enable signal VI2. The drain of the fifth transistor T5 is electrically connected to the first power signal line to receive the first power signal ELVDD, the source of the fifth transistor T5 is electrically connected to the second node A, the drain of the sixth transistor T6 is electrically connected to the third node B, the source of the sixth transistor T6 is electrically connected to the first electrode (anode, or first end) of the light emitting element LD, and the cathode of the light emitting element LD is electrically connected to the second power signal line to receive the second power signal ELVSS; the drain of the seventh transistor T7 is electrically connected to the second reset signal line to receive the reset signal. The seventh transistor T7 receives the second reset signal VI2, the source of the seventh transistor T7 is electrically connected to the first electrode (anode, or first end) of the light-emitting element LD, and the gate of the seventh transistor T7 is electrically connected to the first scan signal line in response to the first scan signal PScan(n); one end of the first storage capacitor Cst1 is electrically connected to the drain of the fifth transistor T5, and the other end of the first storage capacitor Cst1 is electrically connected to the first node Q, one end of the second storage capacitor Cst2 is electrically connected to the first scan signal line, and the other end of the second storage capacitor Cst2 is electrically connected to the first node Q.

[0041] When the third scan signal NScan(n-7) is at an active level, the fourth transistor T4 is turned on, and the second reset signal VI2 is written to the first node Q to reset the first node Q. When the first scan signal PScan(n) and the second scan signal NScan(n) are at active levels, the first transistor T1, the second transistor T2, the third transistor T3, and the seventh transistor T7 are turned on, and the data signal Data is sequentially written from the second node A and the third node B to the first node Q. The first reset signal VI1 resets the anode of the light-emitting element LD. When the enable signal EM is at an active level, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned on, causing the light-emitting element LD to emit light. It can be seen that the first transistor T1 is used to generate a driving current based on the data voltage of the data signal Data to drive the light-emitting element LD to emit light, thereby causing the display panel to display a corresponding image. The second transistor T2 is used to transmit the data voltage to the first transistor T1 in response to the first scan signal PScan(n). The third transistor T3 is used to detect and compensate for the threshold voltage of the first transistor T1 in response to the second scan signal NScan(n), that is, to transmit the data voltage to the gate of the first transistor T1.

[0042] Please refer to Figures 1, 2 and 3. In the case of low-frequency display, the first scanning signal PScan(n) is 120Hz, the second scanning signal NScan(n) and the third scanning signal NScan(n-7) are 10Hz. It can be seen that each display frame includes 1 writing frame and 11 maintaining frames following the writing frame. In one display frame, the first scanning signal PScan(n) has an effective level and an ineffective level in both the writing frame and the 11 maintaining frames, that is, the second transistor T2 writes the voltage of the data signal to the second node A in both the writing frame and the 11 maintaining frames, while the second scanning signal NScan(n) and the third scanning signal NScan(n-7) are at an effective level only during writing, that is, the third transistor T3 and the fourth transistor T4 are turned on only during the writing frame, resetting the first node Q and writing the data signal to the first node Q. In the 11 write frames, the second scan signal NScan(n) and the third scan signal NScan(n-7) are both at invalid levels, the third transistor T3 and the fourth transistor T4 are turned off, and the gate of the first transistor T1 cannot be reset or the voltage of the data signal can be written. The gate of the first transistor T1 maintains the voltage of the data signal written in the write frame in the 11 maintain frames until the next write frame arrives, thereby causing a hysteresis effect in the first transistor T1 and drifting of the threshold voltage of the first transistor T1. Due to the drift of the threshold voltage of the first transistor T1, the current flowing through the first transistor T1 is different when the gate voltages in the write frame and the maintain frame are the same, thereby causing different luminous brightness of the light-emitting element LD, resulting in one or more of the above-mentioned problems on the display panel.

[0043] For the convenience of description, the moment when the second scanning signal NScan(n) and the third scanning signal NScan(n-7) are at the valid level is called the write frame of the display frame, and the 11 pulses after the write frame are called the maintenance frame. For example, the write frame in Figure 1 corresponds to a brightness pulse corresponding to the write frame, and the 11 brightness pulses from the 2nd to the 12th correspond to the maintenance frame.

[0044] The present application provides a display panel 100, which includes a light-emitting element LD and a pixel driving circuit electrically connected to the light-emitting element LD. The pixel driving circuit includes a driving transistor, a first reset module, a second reset module, and a writing module. The gate of the driving transistor is electrically connected to the first node Q, the first electrode (drain) of the driving transistor is electrically connected to the second node A, and the second electrode (source) of the driving transistor is electrically connected to the third node B. The input end of the writing module is connected to the data signal Data, and the output end of the writing module is electrically connected to the second node A. The input end of the first reset module is connected to the first reset signal VI1, and the output end of the first reset module is electrically connected to the first end D (first electrode, or anode) of the light-emitting element LD. ); the input end of the second reset module is connected to the second reset signal VI2, and the output end of the second reset module is electrically connected to the first node Q; the first end D of the light-emitting element LD is electrically connected to the third node B; wherein, in the low-frequency display mode of the display panel 100, a display frame includes a write frame and a maintenance frame after the write frame; wherein, when the display panel 100 is converted from the high-frequency display mode to the low-frequency display mode, at least two of the first reset signal VI1, the second reset signal VI2 and the data signal Data in the low-frequency display mode are different from those in the high-frequency display mode in the write frame, and at least two of the first reset signal VI1, the second reset signal VI2 and the data signal Data in the low-frequency display mode are different from those in the high-frequency display mode in the maintenance frame.

[0045] The driving transistor includes a first transistor T1 , the first reset module includes a seventh transistor T7 , the second reset module includes a fourth transistor T4 , and the writing module includes a second transistor T2 .

[0046] The following will describe in detail the changes of the first reset signal VI1, the second reset signal VI2 and the data signal Data in the low-frequency display mode when the display panel 100 is switched from the high-frequency display mode to the low-frequency display mode in combination with Figures 2 and 3. The following different embodiments can be implemented separately, or any two embodiments can be combined, or all embodiments can be combined. The effect obtained by combining two or more embodiments is the combination of the effects of all embodiments, which can better solve the multiple display problems in the above embodiments and better improve the quality of the display panel.

[0047] The following embodiments are described using the high-frequency display mode of 120 Hz and the low-frequency display mode of 10 Hz in FIG3 as an example; A1 and A2 respectively represent or correspond to the voltages of the data signal Data of the write frame of the first display frame and the write frame of the second display frame; a1 and a2 respectively represent or correspond to the voltages of the data signal Data of the maintain frame of the first display frame and the maintain frame of the second display frame; B1 and B2 respectively represent or correspond to the voltages of the first reset signal VI1 of the write frame of the first display frame and the write frame of the second display frame; b1 and b2 respectively represent or correspond to the voltages of the first reset signal VI1 of the maintain frame of the first display frame and the maintain frame of the second display frame; C1 and C2 respectively represent or correspond to the voltages of the second reset signal VI2 of the write frame of the first display frame and the write frame of the second display frame; c1 and c2 respectively represent or correspond to the voltages of the second reset signal VI2 of the maintain frame of the first display frame and the maintain frame of the second display frame. Aa1 , Bb1 , and Cc1 respectively represent or correspond to the voltage of the data signal in the high-frequency display mode, the voltage of the first reset signal VI1 , and the voltage of the second reset signal VI2 .

[0048] Example 1

[0049] In some embodiments, in the low-frequency display mode, the voltage of the second reset signal VI2 in at least the write frame of the first display frame and the write frame of the second display frame is lower than the voltage of the second reset signal VI2 in the high-frequency display mode.

[0050] Specifically, in the low-frequency display mode, the voltage of the second reset signal VI2 of at least C1 and C2 is less than the voltage of the second reset signal VI2 of Cc1, so that the potential of the first node Q is fully reset, so that the voltage of the gate of the first transistor T1 is reduced, and the current flowing through the first transistor T1 into the light-emitting element LD is increased, thereby improving the brightness of the light-emitting element LD. Therefore, at least the brightness of the first two display frames in the low-frequency display mode can be improved, or at least the brightness of the write frames of the first two display frames in the low-frequency display mode can be improved.

[0051] In some embodiments, the voltage of the second reset signal VI2 in the write frame of the first display frame and the write frame of the second display frame is smaller than the voltage of the second reset signal VI2 in the high-frequency display mode by 0 to 0.25V.

[0052] Specifically, the voltage of the second reset signal VI2 of the write frame of the first display frame is 0 to 0.25V less than the voltage of the second reset signal VI2 in the higher-frequency display mode; the voltage of the second reset signal VI2 of the write frame of the second display frame is 0 to 0.25V less than the voltage of the second reset signal VI2 in the higher-frequency display mode.

[0053] Specifically, the absolute value of the difference between the voltage of the second reset signal VI2 of at least C1 and C2 and the voltage of the second reset signal VI2 of Cc1 is greater than 0 and less than or equal to 0.25V. According to the brightness difference between the high-frequency display mode and the low-frequency display mode measured in this application, it can be found that by setting this range, the brightness difference between the high-frequency display mode and the low-frequency display mode can be minimized.

[0054] Specifically, the absolute value of the difference between the voltage of the second reset signal VI2 of C1 and the voltage of the second reset signal VI2 of Cc1 is greater than 0 and less than or equal to 0.25V; the absolute value of the difference between the voltage of the second reset signal VI2 of C2 and the voltage of the second reset signal VI2 of Cc1 is greater than 0 and less than or equal to 0.25V.

[0055] In some embodiments, the voltage of the second reset signal VI2 in the sustain frame of the first display frame and the sustain frame of the second display frame is equal to the voltage of the second reset signal VI2 in the high frequency display mode.

[0056] Specifically, the voltages of the second reset signals VI2 of c1 and c2 are equal to the voltage of the second reset signal VI2 of Cc1, which can reduce the brightness difference between the write frame and the sustain frame.

[0057] In some embodiments, in the low-frequency display mode, the voltage of the second reset signal VI2 in the Nth display frame is equal to the voltage of the second reset signal VI2 in the high-frequency display mode, where N is a positive integer greater than or equal to 3.

[0058] Specifically, in the low-frequency display mode, the voltage of the second reset signal VI2 of the Nth display frame (including the voltages of the write frame and the maintain frame) is equal to the voltage of the second reset signal VI2 of Cc1, and N is a positive integer greater than or equal to 3. When N is greater than or equal to 3, the brightness difference between the low-frequency display mode and the high-frequency display mode is small, and it is sufficient to maintain the brightness of the low-frequency display mode.

[0059] Example 2

[0060] In some embodiments, in the low-frequency display mode, at the same grayscale, the voltage of the data signal Data in at least the first display frame and the second display frame is lower than the voltage of the data signal Data in the high-frequency display mode.

[0061] Specifically, in the low-frequency display mode, at the same grayscale, the voltage of the data signal Data of at least A1 and A2 is less than the voltage of the data signal Data of Aa1, so that the voltage of the gate of the first transistor T1 is reduced, and the current flowing through the first transistor T1 into the light-emitting element LD is increased, thereby improving the brightness of the light-emitting element LD. Therefore, at least the brightness of the first two display frames in the low-frequency display mode can be improved, or at least the brightness of the write frames of the first two display frames in the low-frequency display mode can be improved.

[0062] In some embodiments, the voltage of the data signal Data in the write frame of the first display frame and the write frame of the second display frame is 0 to 60 mV smaller than the voltage of the data signal Data in the high-frequency display mode.

[0063] Specifically, the voltage of the data signal Data in the write frame of the first display frame is 0 to 60 mV smaller than the voltage of the data signal Data in the high-frequency display mode; the voltage of the data signal Data in the write frame of the second display frame is 0 to 60 mV smaller than the voltage of the data signal Data in the high-frequency display mode.

[0064] Specifically, the absolute value of the difference between the voltage of the data signal Data of A1 and A2 and the voltage of the data signal Data of Cc1 is greater than 0 and less than or equal to 60mV. According to the brightness difference between the high-frequency display mode and the low-frequency display mode measured in this application, it can be found that by setting this range, the brightness difference between the high-frequency display mode and the low-frequency display mode can be minimized.

[0065] Specifically, the absolute value of the difference between the voltage of the data signal Data of A1 and the voltage of the data signal Data of Cc1 is greater than 0 and less than or equal to 60mV; the absolute value of the difference between the voltage of the data signal Data of A2 and the voltage of the data signal Data of Cc1 is greater than 0 and less than or equal to 60mV.

[0066] Specifically, the brightness is gradually increased by writing the first display frame and the second display frame, thereby avoiding sudden brightness changes and reducing flicker.

[0067] In some embodiments, the voltage of the data signal Data in the write frame of the first display frame is lower than the voltage of the data signal Data in the write frame of the second display frame.

[0068] Specifically, the voltage of the data signal Data of A1 is smaller than the voltage of the data signal Data of A2. The smaller the brightness of the voltage of the data signal Data, the greater the current flowing through the first transistor T1 into the light-emitting element LD, the greater the brightness increase of the light-emitting element LD, and the maximum brightness reduction of the first display frame. Therefore, the greater the voltage reduction of the data signal Data of A1 is required.

[0069] In some embodiments, in the low-frequency display mode, at the same grayscale, the voltage of the data signal Data of the write frame of the Nth display frame is equal to the voltage of the data signal Data in the high-frequency display mode, where N is a positive integer greater than or equal to 3.

[0070] Specifically, in the low-frequency display mode, at the same grayscale, the voltage of the data signal Data of the write frame of the Nth display frame is equal to the voltage of the data signal Data of Aa1, and N is a positive integer greater than or equal to 3. When N is greater than or equal to 3, the brightness difference between the low-frequency display mode and the high-frequency display mode is small, and it is sufficient to maintain the brightness of the low-frequency display mode.

[0071] In some embodiments, in the low-frequency display mode, at the same grayscale, the voltage of the data signal Data in the sustain frame (all sustain frames) of the display frame is greater than the voltage of the data signal Data in the high-frequency display mode.

[0072] Specifically, in low-frequency display, at the same grayscale, the voltage of the data signal Data of the maintenance frame (all maintenance frames) of the display frame is greater than the voltage of the data signal Data in the high-frequency display mode. By adjusting the potential of the second node A and the third node B at both ends of the driving transistor, the hysteresis effect of the driving transistor can be weakened and the brightness difference between the low-frequency display mode and the high-frequency display mode can be reduced.

[0073] In some embodiments, the voltage of the data signal Data in the sustain frame of the display frame is 0 to 2V greater than the voltage of the data signal Data in the high-frequency display mode.

[0074] Specifically, the absolute value of the difference between the voltage of the data signal Data of the maintenance frame of the display frame (all maintenance frames) and the voltage of the data signal Data in the high-frequency display mode is greater than 0 and less than or equal to 2V. According to the brightness drop data of the low-frequency display mode measured in this application, it can be found that by setting this range, the brightness drop of the maintenance frame of the low-frequency display mode can be minimized.

[0075] Example 3

[0076] In some embodiments, in the low-frequency display mode, the voltage of the first reset signal VI1 in the sustain frame (all sustain frames) of the display frame is greater than the voltage of the first reset signal VI1 in the high-frequency display mode.

[0077] Specifically, in the low-frequency display mode, the voltage of the first reset signal VI1 of the maintenance frames (all maintenance frames) of display frames such as b1 and b2 is greater than the voltage of the first reset signal VI1 of Bb1, which can make the voltage of the first end (anode) of the light-emitting element LD positive, increase the current in the light-emitting element LD, so as to improve the brightness of the maintenance frame and reduce the brightness drop of the maintenance frames of display frames such as b1 and b2.

[0078] In some embodiments, the voltage of the first reset signal VI1 of the sustain frame of the display frame is 0 to 0.2V greater than the voltage of the second reset signal VI2 in the high-frequency display mode.

[0079] Specifically, the absolute value of the difference between the voltage of the first reset signal VI1 of the maintenance frame of display frames such as b1 and b2 and the voltage of the second reset signal VI2 of Bb1 is greater than 0 and less than or equal to 0.2V. According to the brightness reduction data of the low-frequency display mode measured in this application, it can be found that by setting this range, the brightness difference between the high-frequency display mode and the low-frequency display mode (maintenance frame) can be minimized.

[0080] Specifically, the absolute value of the difference between the voltage of the first reset signal VI1 of the sustain frame of the b1 display frame and the voltage of the second reset signal VI2 of Bb1 is greater than 0 and less than or equal to 0.2V; the absolute value of the difference between the voltage of the first reset signal VI1 of the sustain frame of the b2 display frame and the voltage of the second reset signal VI2 of Bb1 is greater than 0 and less than or equal to 0.2V.

[0081] In some embodiments, the voltage of the first reset signal VI1 of the write frame of the display frame is equal to the voltage of the first reset signal VI1 in the high-frequency display mode.

[0082] Specifically, the voltage of the first reset signal VI1 of B1 is equal to the voltage of the first reset signal VI1 of Bb1, which can avoid excessive brightness increase of the write frame, balance the brightness of the maintenance frame, and minimize the brightness difference between the high-frequency display mode and the low-frequency display mode (maintenance frame).

[0083] Example 4

[0084] Please refer to Figure 4, which is a schematic diagram of the brightness change of the display panel when switching from high-frequency display to low-frequency display in this application. This application combines Examples 1 to 3 and the timing sequence shown in Figure 3 to obtain the brightness change result shown in Figure 4.

[0085] Compared with Figure 1, it can be seen from Figure 4 that: the brightness of the 1st and 2nd display frames is consistent with the brightness of the 4th and 5th display frames; the brightness of the maintenance frame in the 1st display frame decreases slowly; when switching from 120HZ to 10HZ, the brightness of the 1st and 2nd display frames changes slightly, and there is no flickering. Therefore, the display panel of the present application has at least the following beneficial effects when converting from high-frequency display to low-frequency display: there is no flickering problem when converting from high-frequency display to low-frequency display; the brightness of the first few display frames of low-frequency display is consistent with the brightness of the subsequent display frames; and the brightness of the maintenance frames of the first few display frames of low-frequency display is avoided from decreasing. This solves the display problems of flickering, low brightness, etc. that occur when the existing display panel converts from high-frequency display to low-frequency display.

[0086] It should be noted that in the above-mentioned low-frequency display mode, the brightness of the first display frame and the second display frame is compensated by simultaneously adjusting the voltage of the first reset signal VI1 and the voltage of the second reset signal VI2, and inputting the full grayscale (for example, 0-255 grayscale) compensation setting according to the brightness change trend of the first frame. However, due to the characteristics of the panel, there is a trade-off between the low grayscale data signal Data and the high grayscale. At this time, compensation of the data signal at the low grayscale can meet the full grayscale flicker-free requirement. The full grayscale compensation of the voltage of the first reset signal VI1 and the second reset signal VI2 combined with the local compensation scheme of the data signal Data can effectively reduce the difficulty of compensation and minimize the complexity of the internal compensation circuit design. The local compensation of the data signal Data can effectively reduce the internal circuit design area of ​​the IC to achieve low-cost and high-efficiency compensation, while also avoiding the problem that a single compensation cannot cover the full grayscale.

[0087] An embodiment of the present application provides a display panel, comprising: a display panel including a light-emitting element and a pixel driving circuit electrically connected to the light-emitting element, the pixel driving circuit including a driving transistor, a first reset module, a second reset module, and a writing module; a gate of the driving transistor is electrically connected to a first node, a first electrode of the driving transistor is electrically connected to a second node, and a second electrode of the driving transistor is electrically connected to a third node; an input end of the writing module is connected to a data signal, and an output end of the writing module is electrically connected to the second node; an input end of the first reset module is connected to a first reset signal, and an output end of the first reset module is electrically connected to the third node; an input end of the second reset module is connected to a second reset signal, and an output end of the second reset module is electrically connected to the first node; a first end of the light-emitting element is electrically connected to the third node; wherein, in a low-frequency display mode, a display frame of the display panel includes a writing frame and a sustaining frame following the writing frame; wherein, when the display panel switches from a high-frequency display mode to a low-frequency display mode, at least two of the first reset signal, the second reset signal, and the data signal in the low-frequency display mode are different in the writing frame from that in the high-frequency display mode, and at least two of the first reset signal, the second reset signal, and the data signal in the low-frequency display mode are different in the sustaining frame from that in the high-frequency display mode. In the present application, the flickering problem when high-frequency display is converted to low-frequency display, the low brightness problem of the first few display frames of low-frequency display, and the too rapid decrease in brightness of the maintenance frames of the first few display frames of low-frequency display are solved. By solving these problems, the display problems such as flickering and low brightness when the existing display panel is converted from high-frequency display to low-frequency display are solved.

[0088] Example 5

[0089] This embodiment may be a combination of implementations of any two or three of the above embodiments, or all of the embodiments.

[0090] In addition, the present application also provides a compensation method for a display panel, including: S1, the display panel includes a storage module, which establishes a lookup table for the first reset signal VI1, or / and the second reset signal VI2, or / and the data signal Data of the low-frequency display mode in the above-mentioned embodiment, and saves these lookup tables in the storage module; S2, the display panel includes a control module, when the display panel is converted from a high-frequency display mode to a low-frequency display mode, the control module calls the information or compensation data in the lookup table and outputs it to the corresponding pixel driving circuit and light-emitting element in the display panel.

[0091] During the specific implementation of the display panel, the display panel includes a storage module and a control module, which can establish a lookup table for the first reset signal VI1, or / and the second reset signal VI2, or / and the data signal Data of the low-frequency display mode in the above-mentioned embodiment, for example, establishing a first reset signal lookup table for the first reset signal VI1 or a compensation lookup table for the first reset signal, for example, establishing a second reset signal lookup table for the second reset signal VI2 or a compensation lookup table for the second reset signal, such as establishing a data signal lookup table for the data signal Data or a compensation lookup table for the data signal. Specifically, the data signal lookup table can be the voltage information of the data signal corresponding to different gray scales in the low-frequency display mode, and the compensation lookup table of the data signal can be the compensation voltage information of the data signal corresponding to different gray scales in the low-frequency display mode; and the lookup table is stored in the storage module; when the display panel is converted from the high-frequency display mode to the low-frequency display mode, the control module calls the information or compensation data in the lookup table and outputs it to the corresponding pixel driving circuit and light-emitting element in the display panel.

[0092] The above is a detailed introduction to a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, wherein: It includes a light-emitting element and a pixel driving circuit electrically connected to the light-emitting element, wherein the pixel driving circuit includes a driving transistor, a first reset module, a second reset module and a writing module; The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node; The input end of the writing module is connected to the data signal, and the output end of the writing module is electrically connected to the second node; The input end of the first reset module is connected to the first reset signal, and the output end of the first reset module is electrically connected to the first end of the light emitting element; An input end of the second reset module is connected to a second reset signal, and an output end of the second reset module is electrically connected to the first node; The first end of the light emitting element is electrically connected to the third node; Wherein, in the low-frequency display mode of the display panel, a display frame includes a writing frame and a sustaining frame after the writing frame; Wherein, when the display panel is converted from the high-frequency display mode to the low-frequency display mode, at least two of the first reset signal, the second reset signal and the data signal in the low-frequency display mode are different from those in the high-frequency display mode in the writing frame, and at least two of the first reset signal, the second reset signal and the data signal in the low-frequency display mode are different from those in the high-frequency display mode in the maintaining frame; Wherein, in the low-frequency display mode, the voltage of the second reset signal of at least the write frame of the first display frame and the write frame of the second display frame is smaller than the voltage of the second reset signal in the high-frequency display mode; Wherein, in the low-frequency display mode, at the same gray scale, the voltage of the data signal of at least the write frame of the first display frame and the write frame of the second display frame is smaller than the voltage of the data signal in the high-frequency display mode.

2. The display panel according to claim 1, wherein: A voltage of the second reset signal in the sustain frame of the first display frame and the sustain frame of the second display frame is equal to a voltage of the second reset signal in the high-frequency display mode.

3. The display panel according to claim 2, wherein: In the low-frequency display mode, the voltage of the second reset signal of the Nth display frame is equal to the voltage of the second reset signal in the high-frequency display mode, and N is a positive integer greater than or equal to 3.

4. The display panel according to claim 2, wherein: In the low-frequency display mode, a voltage of the first reset signal in the sustain frame of the display frame is greater than a voltage of the first reset signal in the high-frequency display mode.

5. A display panel, wherein: It includes a light-emitting element and a pixel driving circuit electrically connected to the light-emitting element, wherein the pixel driving circuit includes a driving transistor, a first reset module, a second reset module and a writing module; The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node; The input end of the writing module is connected to the data signal, and the output end of the writing module is electrically connected to the second node; The input end of the first reset module is connected to the first reset signal, and the output end of the first reset module is electrically connected to the first end of the light emitting element; An input end of the second reset module is connected to a second reset signal, and an output end of the second reset module is electrically connected to the first node; The first end of the light emitting element is electrically connected to the third node; Wherein, in the low-frequency display mode of the display panel, a display frame includes a writing frame and a sustaining frame after the writing frame; Among them, when the display panel is converted from the high-frequency display mode to the low-frequency display mode, at least two of the first reset signal, the second reset signal and the data signal in the low-frequency display mode are different from those in the high-frequency display mode in the write frame, and at least two of the first reset signal, the second reset signal and the data signal in the low-frequency display mode are different from those in the high-frequency display mode in the maintain frame.

6. The display panel according to claim 5, wherein: In the low-frequency display mode, a voltage of the second reset signal of at least the write frame of the first display frame and the write frame of the second display frame is lower than a voltage of the second reset signal in the high-frequency display mode.

7. The display panel according to claim 6, wherein: The voltage of the second reset signal in the write frame of the first display frame is 0 to 0.25V lower than the voltage of the second reset signal in the high-frequency display mode; The voltage of the second reset signal in the write frame of the second display frame is 0 to 0.25V lower than the voltage of the second reset signal in the high-frequency display mode.

8. The display panel according to claim 6, wherein: A voltage of the second reset signal in the sustain frame of the first display frame and the sustain frame of the second display frame is equal to a voltage of the second reset signal in the high-frequency display mode.

9. The display panel according to claim 8, wherein: In the low-frequency display mode, the voltage of the second reset signal of the Nth display frame is equal to the voltage of the second reset signal in the high-frequency display mode, and N is a positive integer greater than or equal to 3.

10. The display panel according to claim 5, wherein: In the low-frequency display mode, at the same gray scale, voltages of the data signals of at least the write frame of the first display frame and the write frame of the second display frame are smaller than voltages of the data signals in the high-frequency display mode.

11. The display panel according to claim 10, wherein: The voltage of the data signal of the write frame of the first display frame is 0 to 60 mV lower than the voltage of the data signal in the high-frequency display mode; The voltage of the data signal in the write frame of the second display frame is 0 to 60 mV lower than the voltage of the data signal in the high-frequency display mode.

12. The display panel according to claim 10, wherein: A voltage of the data signal of the write frame of the first display frame is smaller than a voltage of the data signal of the write frame of the second display frame.

13. The display panel according to claim 12, wherein: In the low-frequency display mode, at the same gray scale, the voltage of the data signal of the write frame of the Nth display frame is equal to the voltage of the data signal in the high-frequency display mode, and N is a positive integer greater than or equal to 3.

14. The display panel according to claim 12, wherein: In the low-frequency display mode, at the same gray scale, a voltage of the data signal of the sustain frame of the display frame is greater than a voltage of the data signal in the high-frequency display mode.

15. The display panel according to claim 14, wherein: The voltage of the data signal in the sustain frame of the display frame is 0 to 2V greater than the voltage of the data signal in the high-frequency display mode.

16. The display panel according to claim 5, wherein: In the low-frequency display mode, a voltage of the first reset signal in the sustain frame of the display frame is greater than a voltage of the first reset signal in the high-frequency display mode.

17. The display panel according to claim 16, wherein: The voltage of the first reset signal in the sustain frame of the display frame is 0 to 0.2V greater than the voltage of the first reset signal in the high-frequency display mode.

18. The display panel according to claim 16, wherein: The voltage of the first reset signal in the write frame of the display frame is equal to the voltage of the first reset signal in the high-frequency display mode.

19. The display panel according to claim 16, wherein: In the low-frequency display mode, at the same gray scale, voltages of the data signals of at least the write frame of the first display frame and the write frame of the second display frame are smaller than voltages of the data signals in the high-frequency display mode.

20. The display panel according to claim 5, wherein: The pixel driving circuit further includes: The drain of the second transistor is electrically connected to the data signal line to receive the data signal, the source of the second transistor is electrically connected to the second node, and the gate of the second transistor is electrically connected to the first scan signal line to respond to the first scan signal; A drain of the third transistor is electrically connected to the third node, a source of the third transistor is electrically connected to the first node, and a gate of the third transistor is electrically connected to the second scan signal line to respond to a second scan signal; The drain of the fourth transistor is electrically connected to the second reset signal line to receive the second reset signal, the source of the fourth transistor is electrically connected to the first node, and the gate of the fourth transistor is electrically connected to the third scan signal line to respond to the third scan signal; a fifth transistor and a sixth transistor, wherein the gates of the fifth transistor and the sixth transistor are both electrically connected to the enable signal line to respond to the enable signal, the drain of the fifth transistor is electrically connected to the first power signal line to receive the first power signal, and the source of the fifth transistor is electrically connected to the second node; The drain of the sixth transistor is electrically connected to the third node, the source of the sixth transistor is electrically connected to the first electrode of the light emitting element, and the cathode of the light emitting element is electrically connected to the second power signal line to receive the second power signal; The drain of the seventh transistor is electrically connected to the second reset signal line to receive the second reset signal, the source of the seventh transistor is electrically connected to the first electrode of the light emitting element, and the gate of the seventh transistor is electrically connected to the first scan signal line to respond to the first scan signal; One end of the first storage capacitor is electrically connected to the drain of the fifth transistor, the other end of the first storage capacitor is electrically connected to the first node, one end of the second storage capacitor is electrically connected to the first scan signal line, and the other end of the second storage capacitor is electrically connected to the first node.

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