Method for preparing heterojunction solar cell, and heterojunction solar cell

Abstract

The present application relates to the field of solar cell preparation, and discloses a method for preparing a heterojunction solar cell, and a heterojunction solar cell. The method for preparing a heterojunction solar cell comprises: providing a silicon substrate; depositing a first intrinsic passivation layer on a first surface of the silicon substrate at a first deposition temperature and a first deposition rate, and depositing a second intrinsic passivation layer on the first intrinsic passivation layer at a second deposition temperature and a second deposition rate; then, depositing a third intrinsic passivation layer on a second surface of the silicon substrate at the first deposition temperature and the first deposition rate, followed by depositing a fourth intrinsic passivation layer on the third intrinsic passivation layer at the second deposition temperature and the second deposition rate. The first deposition temperature is lower than the second deposition temperature, and the first deposition rate is faster than the second deposition rate. In the present application, the first intrinsic passivation layer and the third intrinsic passivation layer deposited by employing a low-temperature and low-speed process have few defects, a high hydrogen content, and improved film quality.

Description

Preparation method of heterojunction solar cell and heterojunction solar cell Technical Field

[0001] The present application belongs to the technical field of solar cell preparation, and specifically relates to a preparation method of a heterojunction solar cell and a heterojunction solar cell. Background Art

[0002] Heterojunction solar cells are a relatively efficient type of crystalline silicon solar cell. Due to their simple manufacturing process, low processing temperature, high photoelectric conversion efficiency, ease of thinning, and lack of PID (Protection Factor) (PID), they have become a major development direction for high-efficiency cells and have been widely adopted. Existing heterojunction solar cell structures include a silicon substrate; a first intrinsic layer, an N-type doped layer, a first transparent conductive film layer, and a first electrode located on the light-receiving side of the silicon substrate; and a second intrinsic layer, a P-type doped layer, a second transparent conductive film layer, and a second electrode located on the backlight side of the silicon substrate. To optimize passivation at the silicon substrate interface and increase open-circuit voltage and fill factor, both the first and second intrinsic layers typically comprise two or more (multiple) sub-intrinsic layers.

[0003] However, in the related art, the film quality of the prepared multi-layer sub-intrinsic layer is poor, with many defects, poor conductivity and strong parasitic absorption; the large number of defects leads to poor conductivity and light transmittance of the intrinsic layer, which in turn becomes a limiting point for further improving the efficiency of heterojunction solar cells.

[0004] Therefore, there is still a need for improvement in the preparation method of heterojunction solar cells in the related art. Summary of the Invention

[0005] In view of the above-mentioned problems, the present invention aims to at least partially solve one of the technical problems in the related art. To this end, the present invention provides a method for preparing a heterojunction solar cell and a heterojunction solar cell, which are primarily used to alleviate the problem of numerous defects in the intrinsic layer currently produced, thereby improving the film quality of the intrinsic passivation layer and reducing defects in the intrinsic passivation layer.

[0006] In order to solve the above technical problems, this application is implemented as follows:

[0007] According to one aspect of the present application, an embodiment of the present application provides a method for preparing a heterojunction solar cell, the method comprising:

[0008] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface disposed opposite to each other;

[0009] Depositing a first intrinsic passivation layer on a first surface of a silicon substrate at a first deposition temperature and a first deposition rate, and depositing a second intrinsic passivation layer on the first intrinsic passivation layer at a second deposition temperature and a second deposition rate;

[0010] Depositing a third intrinsic passivation layer on the second surface of the silicon substrate at a first deposition temperature and a first deposition rate, and then depositing a fourth intrinsic passivation layer on the third intrinsic passivation layer at a second deposition temperature and a second deposition rate;

[0011] wherein the first deposition temperature is lower than the second deposition temperature, and the first deposition rate is higher than the second deposition rate, the first intrinsic passivation layer and the second intrinsic passivation layer constitute a first group of passivation layers, and the third intrinsic passivation layer and the fourth intrinsic passivation layer constitute a second group of passivation layers;

[0012] A first doping layer is formed on the second intrinsic passivation layer, and a second doping layer is formed on the fourth intrinsic passivation layer. The doping type of the second doping layer is opposite to that of the first doping layer.

[0013] In addition, the method for preparing a heterojunction solar cell according to the present application may also have the following additional technical features:

[0014] In some embodiments, the first deposition temperature is at least 20° C. lower than the second deposition temperature, and the first deposition rate and the second deposition rate are both less than 0.5 nm / s.

[0015] In some embodiments, the first deposition temperature is less than 200° C., and the second deposition temperature is greater than or equal to 200° C.; the first deposition rate is in the range of 0.2 to 0.5 nm / s, and the second deposition rate is in the range of 0.1 to 0.3 nm / s.

[0016] In some embodiments, the first deposition temperature is in the range of 140-180°C, and the second deposition temperature is in the range of 200-230°C.

[0017] In some embodiments, the hydrogen content in the first intrinsic passivation layer is higher than the hydrogen content in the second intrinsic passivation layer; the hydrogen content in the third intrinsic passivation layer is higher than the hydrogen content in the fourth intrinsic passivation layer; and / or the electronic band gap of the first intrinsic passivation layer is greater than the electronic band gap of the second intrinsic passivation layer; the electronic band gap of the third intrinsic passivation layer is greater than the electronic band gap of the fourth intrinsic passivation layer.

[0018] In some embodiments, when the first surface is a light-receiving surface and the second surface is a backlight surface, the thickness of the first intrinsic passivation layer is less than the thickness of the third intrinsic passivation layer.

[0019] In some embodiments, the first intrinsic passivation layer and the second intrinsic passivation layer are respectively deposited in different process chambers, and the third intrinsic passivation layer and the fourth intrinsic passivation layer are respectively deposited in different process chambers.

[0020] In some embodiments, after forming the first doping layer and the second doping layer, the method further includes: forming a first transparent conductive layer on the first doping layer, and forming a second transparent conductive layer on the second doping layer; forming a first electrode on the first transparent conductive layer, and forming a second electrode on the second transparent conductive layer.

[0021] In some embodiments, when preparing the first intrinsic passivation layer and the third intrinsic passivation layer, the flow ratio of hydrogen to silane in the reaction gas used is 0-50%.

[0022] According to another aspect of the present application, an embodiment of the present application provides a heterojunction solar cell, wherein the heterojunction solar cell is manufactured using the aforementioned method for manufacturing a heterojunction solar cell, and the heterojunction solar cell comprises:

[0023] A silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other, the first surface being a light-receiving surface and the second surface being a backlight surface;

[0024] a first intrinsic passivation layer located on the first surface;

[0025] a second intrinsic passivation layer located on a surface of the first intrinsic passivation layer, wherein the first intrinsic passivation layer and the second intrinsic passivation layer constitute a first group of passivation layers;

[0026] a first doping layer located on a surface of the second intrinsic passivation layer;

[0027] a first transparent conductive layer located in the first doped layer;

[0028] a first electrode located on the first transparent conductive layer;

[0029] a third intrinsic passivation layer located on the second surface;

[0030] a fourth intrinsic passivation layer located on the surface of the third intrinsic passivation layer, wherein the third intrinsic passivation layer and the fourth intrinsic passivation layer constitute a second group of passivation layers;

[0031] a second doping layer located on the surface of the fourth intrinsic passivation layer;

[0032] a second transparent conductive layer located in the second doped layer;

[0033] A second electrode is located on the second transparent conductive layer.

[0034] In some embodiments, the thickness of the first intrinsic passivation layer is less than the thickness of the third intrinsic passivation layer.

[0035] The implementation of the technical solution of the present invention has at least the following beneficial effects:

[0036] In an embodiment of the present application, a method for preparing a heterojunction solar cell is provided, in which a first group of passivation layers is formed on a first surface of a silicon substrate, and a second group of passivation layers is formed on a second surface of the silicon substrate, wherein the first group of passivation layers includes a first intrinsic passivation layer close to the first surface and a second intrinsic passivation layer located on the first intrinsic passivation layer, and the second group of passivation layers includes a third intrinsic passivation layer close to the second surface and a fourth intrinsic passivation layer located on the third intrinsic passivation layer; the first intrinsic passivation layer and the third intrinsic passivation layer are prepared at low temperature and low speed, and the second intrinsic passivation layer and the fourth intrinsic passivation layer are prepared at high temperature and even lower speed. Therefore, by adopting a low-temperature and low-speed method to prepare the first intrinsic passivation layer and the third intrinsic passivation layer, although the poor film quality will increase the series resistance of the battery, it has a good anti-epitaxial effect at the a-Si:H / c-Si interface. In addition, when preparing the second intrinsic passivation layer and the fourth intrinsic passivation layer, high-temperature and lower-speed deposition are adopted, and the formed film quality is denser and has fewer defects, which can significantly improve the series resistance and open-circuit voltage of the heterojunction battery finally obtained, and can meet the passivation requirements of the heterojunction battery.

[0037] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a schematic flow chart of a method for preparing a heterojunction solar cell according to some exemplary embodiments of the present application;

[0039] FIG2 is a schematic structural diagram of a heterojunction solar cell provided by some exemplary embodiments of the present application;

[0040] FIG3 is a schematic diagram showing a comparison of battery parameters of intrinsic passivation layers of different film thicknesses provided by the present application;

[0041] FIG4 is an FTIR spectrum of different intrinsic passivation layers provided in some exemplary embodiments of the present application;

[0042] FIG5 is a schematic diagram showing a comparison of cell parameters for depositing an intrinsic amorphous silicon passivation layer at different temperatures as exemplified in the present application.

[0043] Description of reference numerals:

[0044] 10-silicon substrate;

[0045] 20-first group of passivation layers; 21-first intrinsic passivation layer; 22-second intrinsic passivation layer;

[0046] 30-second passivation layer; 31-third intrinsic passivation layer; 32-fourth intrinsic passivation layer;

[0047] 41-first doping layer; 42-second doping layer;

[0048] 51-first transparent conductive layer; 52-second transparent conductive layer;

[0049] 61-first electrode; 62-second electrode. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0051] Those skilled in the art will appreciate that, as discussed in the background, existing heterojunction solar cell fabrication methods still exhibit certain deficiencies. For example, the first sub-intrinsic passivation layer near the silicon substrate surface in existing heterojunction solar cells suffers from poor film quality, numerous defects, poor conductivity, and strong parasitic light absorption. This first sub-intrinsic passivation layer, deposited at high temperatures (typically >210°C) and at high speed, suffers from poor uniformity and is susceptible to yellowing due to temperature fluctuations. Specifically, to ensure excellent passivation and epitaxial growth prevention, existing heterojunction solar cell fabrication techniques require high-temperature and high-speed deposition of the first sub-intrinsic passivation layer near the silicon substrate surface to achieve a film with a high hydrogen content. For example, processes disclosed in related art require temperatures above 200°C for the preparation of the first sub-intrinsic passivation layer. However, this high-temperature, high-speed deposition of the first sub-intrinsic passivation layer exhibits poor film quality. FTIR and Raman spectroscopy analysis reveal that it contains numerous defects and voids, which severely impact the conductivity and light transmittance of the heterojunction solar cell, limiting further efficiency improvements. In addition, since the first sub-intrinsic passivation layer close to the surface of the silicon substrate and the second sub-intrinsic passivation layer located on the first sub-intrinsic passivation layer are both deposited using a high-temperature deposition process, the hydrogen content of the film layer is mainly controlled only by the deposition rate, which has strict requirements on temperature stability. The coating process window is narrow and yellow powder is easily generated.

[0052] Therefore, it is necessary to improve the preparation of heterojunction solar cells, thereby achieving better film quality and higher hydrogen content in the first sub-intrinsic layer. Compared with high-temperature, high-speed deposition, the first sub-intrinsic passivation layer can significantly improve the series resistance and open-circuit voltage when applied to heterojunction cells. The specific technical solution is described below.

[0053] As shown in FIG1 and FIG2 , in some embodiments, a method for preparing a heterojunction solar cell is provided, the method comprising:

[0054] A silicon substrate 10 is provided. The silicon substrate 10 includes a first surface and a second surface disposed opposite each other. The silicon substrate 10 includes two oppositely disposed surfaces, namely the first surface and the second surface, also known as the front and back surfaces. The front surface of the silicon substrate 10 is the surface facing the sun (i.e., the surface exposed to sunlight), and the back surface of the silicon substrate 10 is the surface facing away from the sun. Exemplarily, the first surface may be the front surface, also known as the light-receiving surface (N-type doped surface, referred to as the N-side); the second surface may be the back surface, also known as the backlight-receiving surface (P-type doped surface, referred to as the P-side). Of course, in other embodiments, the first surface may also be the back surface, also known as the backlight-receiving surface (P-type doped surface, referred to as the P-side); and the second surface may also be the front surface, also known as the light-receiving surface (N-type doped surface, referred to as the N-side).

[0055] Under the conditions of a first deposition temperature and a first deposition rate, a first intrinsic passivation layer 21 is deposited on the first surface of the silicon substrate 10, and under the conditions of a second deposition temperature and a second deposition rate, a second intrinsic passivation layer 22 is deposited on the first intrinsic passivation layer 21, that is, the first intrinsic passivation layer 21 is deposited on the first surface of the silicon substrate 10, and the second intrinsic passivation layer 22 is deposited on the first intrinsic passivation layer 21.

[0056] Then, under the conditions of a first deposition temperature and a first deposition rate, a third intrinsic passivation layer 31 is deposited on the second surface of the silicon substrate 10. Under the conditions of a second deposition temperature and a second deposition rate, a fourth intrinsic passivation layer 32 is deposited on the third intrinsic passivation layer 31. That is, the third intrinsic passivation layer 31 is deposited on the second surface of the silicon substrate 10, and the fourth intrinsic passivation layer 32 is deposited on the third intrinsic passivation layer 31. The first intrinsic passivation layer 21 and the second intrinsic passivation layer 22 constitute a first group of passivation layers 20, and the third intrinsic passivation layer 31 and the fourth intrinsic passivation layer 32 constitute a second group of passivation layers 30.

[0057] Among them, the high conversion efficiency of heterojunction solar cells is mainly due to its high opening voltage and excellent surface passivation, wherein the intrinsic passivation layer between the silicon wafer and the doped layer is the key to surface passivation. The inevitable epitaxial growth on the a-Si:H / c-Si interface during the intrinsic a-Si:H deposition process is detrimental to surface passivation. In order to avoid the occurrence of epitaxy, it is necessary to deposit a first intrinsic passivation layer with a higher hydrogen content on the a-Si:H / c-Si interface. The first intrinsic passivation layer deposited at low temperature and low speed (first deposition rate) has a poorer film quality than that deposited at high temperature and low speed, with more holes and defects. The higher hydrogen content corresponds to a larger band gap, but it can play a good anti-epitaxial effect. The second intrinsic passivation layer and the fourth intrinsic passivation layer deposited at high temperature serve as the main layer of passivation, and by adjusting the power and the reaction gas, a lower second deposition rate is obtained, the film quality is denser, the defects are fewer, and there is a good passivation effect. Therefore, preferably, the first deposition temperature is less than the second deposition temperature, and the second deposition rate is less than the first deposition rate, that is, the first deposition rate is greater than the second deposition rate.

[0058] It should be understood that the first and third intrinsic passivation layers 21 and 31 are prepared at a low temperature and low speed (a first deposition rate), which is considered to be low compared to existing or conventional deposition rates. The second and fourth intrinsic passivation layers 22 and 32 are prepared at a low temperature and even lower speed (a second deposition rate), which is lower than the first deposition rate. That is, the second deposition rate is considered to be even lower than the first deposition rate.

[0059] The above-mentioned first group of passivation layers 20 are formed on the first surface of the silicon substrate 10, and the second group of passivation layers 30 are formed on the second surface of the silicon substrate 10; the first group of passivation layers 20 include a first intrinsic passivation layer 21 close to the first surface of the silicon substrate 10, and a second intrinsic passivation layer 22 located on the first intrinsic passivation layer 21; the second group of passivation layers 30 include a third intrinsic passivation layer 31 close to the second surface of the silicon substrate 10, and a fourth intrinsic passivation layer 32 located on the third intrinsic passivation layer 31.

[0060] After the first set of passivation layers 20 and the second set of passivation layers 30 are prepared, the doping layers are prepared. For example, a first doping layer 41 is formed on the second intrinsic passivation layer 22, and a second doping layer 42 is formed on the fourth intrinsic passivation layer 32. The doping type of the second doping layer 42 is opposite to that of the first doping layer 41.

[0061] In some preferred embodiments, since the deposition temperature of the first process chamber used to deposit the first intrinsic passivation layer 21 and the third intrinsic passivation layer 31 does not exceed 180°C, and the deposition temperature of the second intrinsic passivation layer 22 and the fourth intrinsic passivation layer 32 must be higher than 200°C, according to the deposition temperature and the requirements of high production line cycle, the first intrinsic passivation layer 21 and the third intrinsic passivation layer 31 are prepared in the first process chamber, and the second intrinsic passivation layer 22 and the fourth intrinsic passivation layer 32 are prepared in the second process chamber; that is, the first intrinsic passivation layer 21 and the second intrinsic passivation layer 22 are prepared in different process chambers, and the third intrinsic passivation layer 31 and the fourth intrinsic passivation layer 32 are prepared in different process chambers.

[0062] In some preferred embodiments, the first deposition temperature is not more than 200°C, preferably not more than 180°C, and the second deposition temperature is not less than 200°C.

[0063] In some preferred embodiments, both the first deposition rate and the second deposition rate do not exceed 0.5 nm / s. Preferably, the first deposition rate is in the range of 0.2 to 0.5 nm / s, and the second deposition rate is in the range of 0.1 to 0.3 nm / s.

[0064] The technical solution of the method for preparing a heterojunction solar cell provided in this embodiment is adopted. The first intrinsic passivation layer 21 deposited by a low-temperature and low-speed process has fewer defects, better film quality, and a higher hydrogen content. For example, the first intrinsic passivation layer 21 and the second intrinsic passivation layer 22 are deposited in separate chambers. The first intrinsic passivation layer 21 adopts a low-temperature (e.g., less than 200°C, further 140-180°C) and low-speed deposition (e.g., less than 0.50 nm / s, further 0.2-0.50 nm / s) process. Compared with the existing first intrinsic passivation layer deposited at a high temperature (200-230°C) and high-speed deposition (0.6-0.9 nm / s), the low-temperature and low-speed first intrinsic passivation layer has better film quality, fewer defects, and a higher hydrogen content. When applied to the heterojunction cell terminal, the series resistance and open-circuit voltage of the first intrinsic passivation layer deposited at a high temperature and high speed are significantly improved. Furthermore, the low-temperature deposition of the first intrinsic passivation layer and the high-temperature deposition of the second intrinsic passivation layer utilize a separate chamber coating method, which facilitates control of the deposition temperature of each film layer, facilitates adjustment, is easy to implement, and has strong feasibility. Furthermore, the deposition process improvements for the third and fourth intrinsic passivation layers, and the resulting technical effects, are similar to those described above for the first and second intrinsic passivation layers and are not further described here.

[0065] At the same time, the heterojunction battery preparation method of the embodiment of the present invention has a simple process and is easy to implement. The prepared intrinsic passivation layer has good film quality and few defects. It can improve the series resistance, short-circuit current and open-circuit voltage of the heterojunction solar cell and has good application prospects.

[0066] It should be noted that the preparation method of this embodiment is not limited to the specific type of silicon substrate (silicon wafer). For example, it can be a single crystal silicon substrate, a polycrystalline silicon substrate, or a quasi-single crystal silicon substrate. The silicon substrate can be P-type doped or N-type doped. In other words, the silicon substrate can be an N-type silicon wafer or a P-type silicon wafer. Optionally, this embodiment uses an N-type single crystal silicon wafer as the silicon substrate.

[0067] In some specific embodiments, the method for preparing a heterojunction solar cell comprises the following steps:

[0068] S100: Provide a silicon substrate 10, comprising a first surface and a second surface disposed opposite to each other; wherein the first surface may be a light-receiving surface (N-surface), and the second surface may be a backlight surface (P-surface); and perform a texturing and cleaning process on the silicon substrate 10. Of course, the first surface may also be a backlight surface (P-surface), and the second surface may be both a backlight surface (P-surface) and a light-receiving surface (N-surface), which will not be further described herein.

[0069] It should be noted that the embodiments of the present application do not limit the specific operating methods and process conditions for the texturing and cleaning treatment of the silicon substrate, and can be selected and adjusted by those skilled in the art based on actual conditions. For example, conventional texturing and cleaning methods in related technologies can be used, and an alkaline texturing solution can be used for texturing treatment to form a textured surface structure on the clean surface of an N-type monocrystalline silicon wafer, such as a pyramid-shaped textured surface structure. This can enhance the light trapping effect, reduce the reflectivity of the silicon wafer, reduce carrier recombination centers, and increase the minority carrier lifetime, ultimately producing a solar cell with high conversion efficiency.

[0070] S200, forming a first group of passivation layers 20 on the first surface of the silicon substrate 10, and forming a second group of passivation layers 30 on the second surface of the silicon substrate 10; wherein the first group of passivation layers 20 includes a first intrinsic passivation layer 21 close to the first surface of the silicon substrate 10, and a second intrinsic passivation layer 22 located on the first intrinsic passivation layer 21; the second group of passivation layers 30 includes a third intrinsic passivation layer 31 close to the second surface of the silicon substrate 10, and a fourth intrinsic passivation layer 32 located on the third intrinsic passivation layer 31. In this embodiment, the first intrinsic passivation layer 21 and the third intrinsic passivation layer 31 are formed using a low-temperature and low-speed process, and the second intrinsic passivation layer 22 and the fourth intrinsic passivation layer 32 are formed using a high-temperature and lower-speed process. Specifically, step S200 includes:

[0071] S210, under the conditions of a first deposition temperature and a first deposition rate, a first intrinsic passivation layer 21 is deposited on the first surface of the silicon substrate 10, and then under the conditions of a second deposition temperature and a second deposition rate, a second intrinsic passivation layer 22 is deposited on the first intrinsic passivation layer 21 to form a second intrinsic passivation layer.

[0072] S220. Under the conditions of a first deposition temperature and a first deposition rate, a third intrinsic passivation layer 31 is deposited on the second surface of the silicon substrate 10. Then, under the conditions of a second deposition temperature and a second deposition rate, a fourth intrinsic passivation layer 32 is deposited on the third intrinsic passivation layer 31.

[0073] In this embodiment, the first deposition temperature is lower than the second deposition temperature, and the first deposition rate is higher than the second deposition rate. Optionally, the first deposition temperature is at least 20°C lower than the second deposition temperature, and both the first deposition rate and the second deposition rate are less than 0.5 nm / s. Furthermore, the first deposition temperature may be less than 200°C, and the second deposition temperature may be greater than or equal to 200°C. Compared to the existing first deposition temperature and the second deposition temperature both being above 200°C, this embodiment reduces the first deposition temperature for preparing the first intrinsic passivation layer 21 and the third intrinsic passivation layer 31, and takes into account the influence of the deposition rate, while reducing the first deposition rate.

[0074] In some preferred embodiments, the first deposition temperature ranges from 140 to 180°C, and the second deposition temperature ranges from 200 to 230°C; and by reducing the power and adjusting the process gas, the second deposition rate is less than the first deposition rate. Specifically, the first deposition rate ranges from 0.2 to 0.5 nm / s, and the second deposition rate ranges from 0.1 to 0.3 nm / s. Illustratively, the first deposition temperature may be 140°C, 150°C, 160°C, 170°C, 180°C, etc., and the second deposition temperature may be 200°C, 205°C, 210°C, 220°C, 230°C, etc.; the first deposition rate may be 0.2 nm / s, 0.25 nm / s, 0.3 nm / s, 0.35 nm / s, 0.4 nm / s, 0.45 nm / s, 0.5 nm / s, etc., and the second deposition rate may be 0.1 nm / s, 0.15 nm / s, 0.2 nm / s, 0.25 nm / s, 0.3 nm / s, etc.

[0075] In this embodiment, the hydrogen content in the first intrinsic passivation layer 21 is higher than the hydrogen content in the second intrinsic passivation layer 22; the hydrogen content in the third intrinsic passivation layer 31 is higher than the hydrogen content in the fourth intrinsic passivation layer 32; the electronic band gap of the first intrinsic passivation layer 21 is greater than the electronic band gap of the second intrinsic passivation layer 22; the electronic band gap of the third intrinsic passivation layer 31 is greater than the electronic band gap of the fourth intrinsic passivation layer 32.

[0076] Thus, using the above-mentioned low-temperature, low-speed process to prepare the first intrinsic passivation layer 21 and the third intrinsic passivation layer 31, particularly under the aforementioned low-temperature deposition temperature of 140-180°C and low-speed deposition rate of 0.2-0.5 nm / s, the hydrogen content of the prepared first intrinsic passivation layer 21 can be higher than that of the second intrinsic passivation layer 22 and the first intrinsic passivation layer 21 deposited using conventional high-temperature, high-speed deposition. Similarly, the hydrogen content of the prepared third intrinsic passivation layer 31 can be higher than that of the fourth intrinsic passivation layer 32 and the third intrinsic passivation layer 31 deposited using conventional high-temperature, high-speed deposition. This higher hydrogen content can improve the surface passivation effect of heterojunction solar cells. Furthermore, the first and third intrinsic passivation layers 21 and 31 with higher hydrogen content have larger electronic band gaps, resulting in better light transmittance. Furthermore, compared to conventional high-temperature, high-speed deposition, the first and third intrinsic passivation layers 21 and 31 deposited using low-temperature, low-speed deposition have fewer defects, which can lower the series resistance of the heterojunction solar cell.

[0077] According to this embodiment, the coating equipment used may be a plasma-phase chemical vapor deposition (PECVD) equipment or a catalytic chemical vapor deposition (CAT-CVD) equipment. For example, the coating equipment and method used may be RF-PECVD, VHF-PECVD, CAT-CVD, or other coating equipment and methods.

[0078] In some embodiments, when the first surface is a light-receiving surface and the second surface is a backlight surface, the thickness of the first intrinsic passivation layer 21 is less than the thickness of the third intrinsic passivation layer 31 .

[0079] Exemplarily, in some embodiments, the thickness of the first intrinsic passivation layer 21 can be 0.5nm~2nm, for example, it can be 0.5nm, 0.6nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 1.8nm, 2nm, etc.; the thickness of the third intrinsic passivation layer 31 can be 0.75nm~3nm, for example, it can be 0.75nm, 0.8nm, 4nm, 1nm, 1.2nm, 1.5nm, 1.8nm, 2nm, 2.5nm, 3nm, etc.; the thickness of the second intrinsic passivation layer 22 can be 3nm~6nm, for example, it can be 3nm, 3.5nm, 3.8nm, 4nm, 4.5nm, 5nm, 5.6nm, 6nm, etc.; the thickness of the fourth intrinsic passivation layer 32 can be 2nm~5nm, for example, it can be 2nm, 2.5nm, 3nm, 2.5nm, 4nm, 4.5nm, 5nm, etc.

[0080] When the first surface is the light-receiving surface and the second surface is the backlight surface, the first intrinsic passivation layer deposited at a low temperature at a first deposition rate has a higher hydrogen content, so it has a good anti-epitaxial effect at the a-Si:H / c-Si interface. However, the poor film quality leads to a larger short-wavelength light absorption coefficient and poor light transmittance. In addition, the poor film quality has poor conductivity, which will increase the series resistance of the battery. The second and fourth intrinsic passivation layers deposited at a higher temperature and a lower speed have denser films and fewer defects. In addition, the first intrinsic passivation layer on the light-receiving surface of the actual battery needs to be as thin as possible, and its thickness is less than the third intrinsic passivation layer on the backlight surface.

[0081] As shown in Figure 3, the embodiment of the present application adjusts the thickness of the intrinsic passivation layer on the light-receiving side or the backlight side respectively and prepares a complete battery, wherein the preferred thickness of the third intrinsic passivation layer of group A is 3nm, and the fourth intrinsic passivation layer is 5nm. The thickness of the first intrinsic passivation layer on the front is 3nm, and the second intrinsic passivation layer is 5nm. Its short-circuit current is 10.957A, the series resistance is 0.00273Ω, the open-circuit voltage is 0.748V, and the conversion efficiency is 25.52%. The thickness of the first intrinsic passivation layer of group B is 2nm, the thickness of the second intrinsic passivation layer is 5nm, the thickness of the third intrinsic passivation layer is 3nm, and the thickness of the fourth intrinsic passivation layer is 5nm. After thinning the first intrinsic passivation layer, the short-circuit current of the battery is 10.972A, the series resistance is 0.00269Ω, the open-circuit voltage is 0.748V, and the conversion efficiency is 25.60%. It can be seen that the thinner first intrinsic passivation layer improves the transmittance and conductivity of the front amorphous silicon layer, and the cell conversion efficiency is increased by 0.08%.

[0082] In some embodiments, the thickness of the first group of passivation layers 20 is 3nm to 8nm, that is, the total thickness of the first intrinsic passivation layer 21 and the second intrinsic passivation layer 22 is 3nm to 8nm, and can further be 5nm to 8nm; illustratively, the thickness of the first group of passivation layers 20 can be 3nm, 4nm, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 8nm, etc.

[0083] The thickness of the second group of passivation layers 30 is 2nm~8nm, that is, the total thickness of the third intrinsic passivation layer 31 and the fourth intrinsic passivation layer 32 is 2nm~8nm, and can further be 4nm~8nm; illustratively, the thickness of the second group of passivation layers 30 can be 2nm, 3nm, 4nm, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 8nm, etc.

[0084] In a specific implementation process, the thickness of each intrinsic passivation film layer can be controlled by controlling operating conditions such as the forming time of each intrinsic passivation film layer.

[0085] Therefore, using each intrinsic passivation layer within the above-mentioned thickness range or the total thickness of the passivation layer within the above-mentioned range is easier to implement and convenient to process and manufacture, and at the same time has better film quality and good use effect, which helps to improve the surface passivation effect of heterojunction solar cells.

[0086] It should be pointed out that in the process of preparing each intrinsic passivation film layer, while satisfying the conditions of preparing the first intrinsic passivation layer and the third intrinsic passivation layer at low temperature and low speed, and preparing the second intrinsic passivation layer and the fourth intrinsic passivation layer at high temperature and lower speed, other operating conditions such as reaction gas and gas pressure can be selected and adjusted according to actual conditions.

[0087] For example, in some embodiments, when preparing the first intrinsic passivation layer and the third intrinsic passivation layer, the flow ratio of hydrogen and silane in the reaction gas used is 0 to 50%. For example, the flow ratio of hydrogen and silane can be 0, 10%, 15%, 20%, 30%, 40%, 50%, etc.

[0088] S300: Prepare doping layers. Specifically, a first doping layer 41 is deposited on the second intrinsic passivation layer 22, and a second doping layer 42 is deposited on the fourth intrinsic passivation layer 32. The doping type of the second doping layer 42 is opposite to that of the first doping layer 41: one is N-type doped, such as phosphorus doping, and the other is P-type doped, such as boron doping. Optionally, the first doping layer 41 can be an N-type doped layer (such as an N-type phosphorus doped layer), and the second doping layer 42 can be a P-type doped layer (such as a P-type boron doped layer).

[0089] Optionally, the first doping layer 41 may be a P-type doping layer (such as a P-type phosphorus-doped layer), and the second doping layer 42 may be an N-type doping layer (such as an N-type boron-doped layer).

[0090] Optionally, the N-type doped layer may be an N-type amorphous silicon doped layer or an N-type microcrystalline silicon doped layer; and the P-type doped layer may be a P-type amorphous silicon doped layer or a P-type microcrystalline silicon doped layer.

[0091] In addition, for the preparation of the doping layer, optionally, after step S210, that is, after depositing the first intrinsic passivation layer 21 and the second intrinsic passivation layer 22, step S220 is first implemented, that is, depositing the third intrinsic passivation layer 31 and the fourth intrinsic passivation layer 32, and then depositing the second doping layer 42 on the fourth intrinsic passivation layer 32, and finally depositing the first doping layer 41 on the second intrinsic passivation layer 22. No further explanation is given here.

[0092] S400 , preparing a transparent conductive layer. Specifically, a first transparent conductive layer 51 is deposited on the first doping layer 41 , and a second transparent conductive layer 52 is deposited on the second doping layer 42 .

[0093] A transparent conductive layer (TCO) refers to a film layer of a transparent conductive oxide. TCO is a general term for a series of semiconductor materials that are both light-transmitting and conductive, mainly including ITO (indium tin oxide), IWO (tungsten-doped indium oxide), AZO (aluminum-doped zinc oxide), etc. This embodiment does not limit the specific material of the transparent conductive layer.

[0094] The equipment and methods for preparing the transparent conductive layer may include magnetron sputtering equipment (PVD) and reactive plasma deposition equipment (RPD).

[0095] S500 , preparing electrodes. Specifically, a first electrode 61 is formed on the first transparent conductive layer 51 , and a second electrode 62 is formed on the second transparent conductive layer 52 , thereby obtaining a heterojunction solar cell.

[0096] It should be pointed out here that in the preparation method of the heterojunction solar cell, the specific processes of preparing the doping layer, preparing the transparent conductive layer, preparing the electrode, etc. can refer to the existing technology and adopt conventional production process flow or operation mode. This embodiment does not limit this and will not be described in detail here.

[0097] Based on the same inventive concept, the present invention also provides a heterojunction solar cell, which can be manufactured using the aforementioned method for manufacturing a heterojunction solar cell. As shown in FIG2 , the heterojunction solar cell comprises:

[0098] The silicon substrate 10 includes a first surface and a second surface opposite to each other, wherein the first surface is a light-receiving surface and the second surface is a backlight surface;

[0099] a first intrinsic passivation layer 21 located on the first surface;

[0100] a second intrinsic passivation layer 22 located on the surface of the first intrinsic passivation layer 21 , wherein the first intrinsic passivation layer 21 and the second intrinsic passivation layer 22 constitute a first group of passivation layers 20 ;

[0101] A first doping layer 41 located on the surface of the second intrinsic passivation layer 22;

[0102] a first transparent conductive layer 51 located on the first doping layer 41;

[0103] A first electrode 61 located on the first transparent conductive layer 51;

[0104] a third intrinsic passivation layer 31 located on the second surface;

[0105] a fourth intrinsic passivation layer 32 located on the surface of the third intrinsic passivation layer 31 , wherein the third intrinsic passivation layer 31 and the fourth intrinsic passivation layer 32 constitute a second group of passivation layers 30 ;

[0106] a second doping layer 42 located on the surface of the fourth intrinsic passivation layer 32;

[0107] a second transparent conductive layer 52 located on the second doping layer 42;

[0108] The second electrode 62 is located on the second transparent conductive layer 52 .

[0109] In the heterojunction solar cell, the thickness of the first intrinsic passivation layer 21 is smaller than the thickness of the third intrinsic passivation layer 31 .

[0110] In some embodiments, the thickness of the first intrinsic passivation layer 21 is 0.5 nm to 2 nm, the thickness of the third intrinsic passivation layer 31 is 0.75 nm to 3 nm, the thickness of the second intrinsic passivation layer 22 is 3 nm to 6 nm, and the thickness of the fourth intrinsic passivation layer 32 is 2 nm to 5 nm. The thickness of the first group of passivation layers 20 is 3 nm to 8 nm. The thickness of the second group of passivation layers 30 is 2 nm to 8 nm.

[0111] It should be understood that the heterojunction solar cell of this embodiment and the aforementioned method for preparing a heterojunction solar cell are based on the same inventive concept, and thus have at least all the features and advantages of the method for preparing a heterojunction solar cell, which will not be described in detail here.

[0112] Therefore, based on the above configuration, compared to existing heterojunction solar cell intrinsic passivation layer preparation processes, the first intrinsic passivation layer, which is in direct contact with the silicon wafer, is typically deposited using a high-temperature deposition process (>200°C). The deposition temperature of the second intrinsic passivation layer is similar. High-temperature deposition ensures sufficient hydrogen content in the first intrinsic passivation layer, and high-speed deposition (0.6-0.9 nm / s) is required to achieve epitaxy prevention and good chemical passivation. However, high-speed deposited amorphous silicon thin films typically contain numerous defects and voids, and the poor film quality leads to extremely poor conductivity, severely limiting further efficiency improvements in heterojunction solar cells. The heterojunction solar cell and its preparation method provided in the present embodiment can effectively overcome the aforementioned drawbacks. The present embodiment deposits the first intrinsic passivation layer at a low temperature (140-180°C) and a low speed (0.2-0.50 nm / s). The first and second intrinsic passivation layers are deposited in separate chambers, allowing for independent control of the process temperatures of the two layers. Compared to high-temperature deposition, the lower deposition temperature (140-180°C) of the first intrinsic passivation layer significantly increases the hydrogen content of the film. Furthermore, low-refractive-index amorphous silicon films can be obtained at a relatively low deposition rate (0.25-0.50 nm / s), meeting the passivation requirements of heterojunction solar cells. Furthermore, low-temperature, low-rate deposition of the first intrinsic passivation layer results in fewer defects, higher-quality films, and reduced parasitic light absorption. Application to heterojunction solar cells can significantly improve series resistance, short-circuit current, and open-circuit voltage. Furthermore, low-temperature, low-rate deposition of the first intrinsic passivation layer offers a wider process window and is less sensitive to deposition temperature, mitigating the impact of equipment fluctuations on cell efficiency. Furthermore, low-rate deposition of the amorphous silicon layer reduces the generation of yellow powder, potentially reducing the frequency of RPS chamber cleaning in PECVD equipment and improving equipment utilization. The improved deposition process for the third intrinsic passivation layer and the resulting technical benefits are similar to those described above and will not be further elaborated here.

[0113] In order to verify the effect of the method for preparing a heterojunction solar cell provided by the embodiment of the present invention, the present invention also carried out some specific examples and comparative experiments.

[0114] As shown in Figure 4, Figure 4 shows the FTIR spectra of different intrinsic passivation layers. FTIR is a powerful tool for studying the microstructure of a-Si:H materials. The a-Si:H film grown by PECVD contains a large amount of hydrogen, most of which forms Si-H bonds with Si. The infrared absorption of the Si-H stretching vibration of the isolated Si-H bond occurs at 2000 cm -1 , while the infrared absorption of Si-H bonds associated with hydrogen clusters occurs at about 2100 cm -1Figure 4 shows a comparison of the FTIR spectra of the intrinsic passivation layer deposited at high temperature and high speed and at low temperature and low speed. It can be clearly seen that the absorption peak intensity related to the Si-H bond of the intrinsic passivation layer deposited at low temperature and low speed is significantly higher, indicating that the higher the hydrogen content in the film, the better the anti-epitaxial effect. At the same time, the film layer with a higher hydrogen content usually has a lower refractive index and lower light absorption. Using the formula R*=I 2100 cm-1 / (I 2000 cm-1 +I 2100 cm-1 ) can be used to calculate the structure factor R* of amorphous silicon films. A higher R* means a greater density of nanoscale voids in the a-Si:H film.

[0115] Table 1

[0116]

[0117] As shown in Table 1, Table 1 shows the structure factor R* of the intrinsic passivation layer deposited at different temperatures, showing a trend that the lower the temperature, the larger the structure factor R*. An intrinsic amorphous silicon passivation layer with a structure factor R* of 85.50% was obtained at 160°C.

[0118] In a specific embodiment, an intrinsic amorphous silicon passivation layer was deposited at three different temperatures at low speeds to prepare a complete solar cell structure, which was compared with the intrinsic passivation layer deposited at a conventional high temperature and high speed. As shown in Figure 5, the Voc of the intrinsic passivation layer deposited at 140°C, 160°C, and 180°C all showed advantages over the high temperature (220°C) and high speed deposition group. The lower the deposition temperature of the intrinsic passivation layer, the more obvious the Voc advantage. This corresponds to the structure factor R* measured by FTIR, that is, the higher the hydrogen content, the better the anti-epitaxial effect of the intrinsic amorphous silicon layer, and the better the overall passivation effect of the battery. However, a higher structure factor R* means more defects and voids in the intrinsic amorphous silicon passivation layer, resulting in a higher series resistance of the battery, which in turn affects the fill factor and conversion efficiency of the battery.

[0119] Table 2

[0120]

[0121] Table 2 summarizes the conversion efficiency of the resulting cell using intrinsic amorphous silicon passivation layers deposited at different temperatures. The process parameters for the other layers, including the second and fourth intrinsic passivation layers, the first and second doped layers, and the first and second electrodes, remained the same. The conversion efficiency of the intrinsic passivation layer deposited at a conventional high temperature (e.g., 220°C) and high speed was 25.66%, with an open-circuit voltage of 0.748V, a short-circuit current of 11.01A, and a series resistance of 0.0029Ω. By optimizing the temperature and film thickness, the intrinsic passivation layer deposited at a low temperature and low speed at 160°C achieved a conversion efficiency of 25.79%, a 0.13% improvement over the intrinsic passivation layer deposited at a higher temperature and high speed. The open-circuit voltage was 0.749V, and the series resistance was 0.0026Ω, both showing significant improvements.

[0122] Furthermore, the reaction gases used in the preparation of the first and third intrinsic passivation layers can be silane, or include silane and hydrogen, or include silane, hydrogen, and carbon dioxide. The deposition pressure is 10-800 Pa, the flow ratio of hydrogen to silane is 0-50%, and the deposition power is 150-650 W. The reaction gases used in the preparation of the second and fourth intrinsic passivation layers can include silane and hydrogen, or include silane, hydrogen, and carbon dioxide. The deposition pressure is 10-800 Pa, the flow ratio of hydrogen to silane is 50%-200%, and the deposition power is 100-500 W. Preferably, during the coating process of the first and third intrinsic passivation layers deposited at low temperature and low speed, some hydrogen can be introduced, with the hydrogen flow rate being 0-50% of the silane flow rate. Hydrogen aids in the decomposition of silane, improving the uniformity of the coating of the first and third intrinsic passivation layers and thereby enhancing conductivity. The lower deposition temperature also ensures the anti-epitaxial growth effect of the hydrogen-doped first and third intrinsic passivation layers. For comparison, cells with and without hydrogen in the first and third intrinsic passivation layers were fabricated at 160°C. The processes for the second and fourth intrinsic passivation layers, doping layer, and transparent conductive layer remained identical.

[0123] As shown in Table 3, each group of cells consists of 16 cells. Group C, in which no hydrogen was introduced into the first and third intrinsic passivation layers, achieved a median conversion efficiency of 25.54% with a standard deviation of 0.064. Group D, in which 40% hydrogen was introduced into the first and third intrinsic passivation layers, achieved a median conversion efficiency of 25.61% with a standard deviation of 0.040. The introduction of hydrogen improved the uniformity of the intrinsic passivation layer, resulting in a more convergent distribution of cell conversion efficiencies within the group.

[0124] Table 3

[0125]

[0126] Parts not described in detail in the specification of the present invention are well known to those skilled in the art.

[0127] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. It should be noted that the terms "and / or" or " / " used in this article are merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for preparing a heterojunction solar cell, characterized in that: The method comprises: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other; Depositing a first intrinsic passivation layer on a first surface of the silicon substrate at a first deposition temperature and a first deposition rate, and depositing a second intrinsic passivation layer on the first intrinsic passivation layer at a second deposition temperature and a second deposition rate; Depositing a third intrinsic passivation layer on the second surface of the silicon substrate at a first deposition temperature and a first deposition rate, and depositing a fourth intrinsic passivation layer on the third intrinsic passivation layer at a second deposition temperature and a second deposition rate; Wherein, the first deposition temperature is lower than the second deposition temperature, the first deposition rate is higher than the second deposition rate; the first intrinsic passivation layer and the second intrinsic passivation layer constitute a first group of passivation layers, and the third intrinsic passivation layer and the fourth intrinsic passivation layer constitute a second group of passivation layers; A first doping layer is formed on the second intrinsic passivation layer, and a second doping layer is formed on the fourth intrinsic passivation layer, wherein the doping type of the second doping layer is opposite to that of the first doping layer.

2. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The first deposition temperature is at least 20° C. lower than the second deposition temperature, and the first deposition rate and the second deposition rate are both less than 0.5 nm / s.

3. The method for preparing a heterojunction solar cell according to claim 2, characterized in that: The first deposition temperature is less than 200° C., and the second deposition temperature is greater than or equal to 200° C.; The first deposition rate ranges from 0.2 to 0.5 nm / s, and the second deposition rate ranges from 0.1 to 0.3 nm / s.

4. The method for preparing a heterojunction solar cell according to any one of claims 1 to 3, characterized in that: The first deposition temperature ranges from 140 to 180° C., and the second deposition temperature ranges from 200 to 230° C.

5. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The hydrogen content in the first intrinsic passivation layer is higher than the hydrogen content in the second intrinsic passivation layer; the hydrogen content in the third intrinsic passivation layer is higher than the hydrogen content in the fourth intrinsic passivation layer; and / or, The electronic band gap of the first intrinsic passivation layer is greater than the electronic band gap of the second intrinsic passivation layer; the electronic band gap of the third intrinsic passivation layer is greater than the electronic band gap of the fourth intrinsic passivation layer.

6. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: When the first surface is a light-receiving surface and the second surface is a backlight surface, the thickness of the first intrinsic passivation layer is less than the thickness of the third intrinsic passivation layer.

7. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The first intrinsic passivation layer and the second intrinsic passivation layer are respectively deposited and formed in different process chambers, and the third intrinsic passivation layer and the fourth intrinsic passivation layer are respectively deposited and formed in different process chambers.

8. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: After forming the first doping layer and the second doping layer, the method further includes: forming a first transparent conductive layer on the first doped layer, and forming a second transparent conductive layer on the second doped layer; A first electrode is formed on the first transparent conductive layer, and a second electrode is formed on the second transparent conductive layer.

9. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: In the reaction gas used when preparing the first intrinsic passivation layer and the third intrinsic passivation layer, the flow ratio of hydrogen to silane is 0-50%.

10. A heterojunction solar cell, characterized in that: The heterojunction solar cell is manufactured by the method for manufacturing a heterojunction solar cell according to any one of claims 1 to 9, and the heterojunction solar cell comprises: A silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the first surface being a light-receiving surface, and the second surface being a backlight surface; a first intrinsic passivation layer located on the first surface; a second intrinsic passivation layer located on the surface of the first intrinsic passivation layer, wherein the first intrinsic passivation layer and the second intrinsic passivation layer constitute a first group of passivation layers; a first doping layer located on the surface of the second intrinsic passivation layer; A first transparent conductive layer located on the first doped layer; A first electrode located on the first transparent conductive layer; a third intrinsic passivation layer located on the second surface; a fourth intrinsic passivation layer located on the surface of the third intrinsic passivation layer, wherein the third intrinsic passivation layer and the fourth intrinsic passivation layer constitute a second group of passivation layers; a second doping layer located on the surface of the fourth intrinsic passivation layer; a second transparent conductive layer located on the second doped layer; The second electrode is located on the second transparent conductive layer.

11. The heterojunction solar cell according to claim 10, characterized in that: The thickness of the first intrinsic passivation layer is smaller than the thickness of the third intrinsic passivation layer.

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