Driving circuit, driving method, pixel circuit, display panel, and display apparatus

Abstract

A driving circuit, a driving method, a pixel circuit, a display panel, and a display apparatus. The driving circuit comprises a first switch circuit (11) and a scanning signal generation circuit (SD). The first switch circuit (11) controls, under the control of a first gating control signal (SW1), a data signal provided by a data output end (S0) to be written to the scanning signal generation circuit (SD). The scanning signal generation circuit (SD) is used for generating a scanning signal according to the data signal and outputting the scanning signal by means of a scanning signal output end (SG). The driving circuit controls whether to refresh the data voltage of a corresponding pixel circuit, so that updating of a local picture of a screen may be implemented, thereby reducing power consumption.

Description

Driving circuit, driving method, pixel circuit, display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310717043.0 filed in China on June 16, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, a pixel circuit, a display panel, and a display device. Background Art

[0004] OLED (organic light-emitting diode) display technology has the advantages of high contrast, fast response, and low power consumption. In order to further reduce power consumption, the LTPO (low-temperature polycrystalline oxide) display technology achieved by combining LTPS (low-temperature polycrystalline silicon) + IGZO (indium gallium zinc oxide) can achieve low frame rate display, reducing driving power consumption by reducing the repeated refresh of static images. However, when updating the screen, existing OLED displays still need to initialize and write all pixel voltages within one frame. In some special screens, the voltages of most pixels on the entire screen do not need to be updated, that is, the original display brightness can be maintained by the low-leakage LTPO TFT (thin-film transistor). The repeated refresh of these pixels causes a waste of power consumption of the data lines.

[0005] Summary of the Invention

[0006] An embodiment of the present disclosure provides a driving circuit, comprising a first switching circuit and a scan signal generating circuit;

[0007] The first switch circuit is electrically connected to the first strobe control line, the data output terminal of the source driver and the scan signal generating circuit, and is used to control the writing of the data signal provided by the data output terminal into the scan signal generating circuit under the control of the first strobe control signal provided by the first strobe control line;

[0008] The scanning signal generating circuit is used to generate a scanning signal according to the data signal, and output the scanning signal through a scanning signal output terminal.

[0009] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a second switching circuit;

[0010] The second switch circuit is electrically connected to a second strobe control line, the data output terminal and a data line included in the display panel, and is used to control the connection or disconnection between the data output terminal and the data line under the control of a second strobe control signal provided by the second strobe control line;

[0011] The first gate control line and the second gate control line are the same gate control line, or the first gate control line and the second gate control line are different.

[0012] Optionally, the first switch circuit includes a first transistor and a first capacitor; the first switch circuit provides the data signal to the scan signal generating circuit through a control node;

[0013] The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the control node;

[0014] A first end of the first capacitor is electrically connected to the control node, and a second end of the first capacitor is electrically connected to a DC voltage end.

[0015] Optionally, the second switching circuit includes a second transistor;

[0016] A gate of the second transistor is electrically connected to the second selection control line, a first electrode of the second transistor is electrically connected to the data output terminal, and a second electrode of the second transistor is electrically connected to the data line.

[0017] Optionally, the scan signal generating circuit includes an output control circuit and an output circuit; the first switch circuit provides the data signal to the scan signal generating circuit through a control node;

[0018] The output control circuit is electrically connected to the control node, the first voltage terminal, the second voltage terminal, the output control terminal, and the scan output terminal, respectively, and is used to control the connection or disconnection between the output control terminal and the first voltage terminal under the control of the potential of the control node, and to control the connection or disconnection between the output control terminal and the second voltage terminal under the control of the signal provided by the scan output terminal;

[0019] The output circuit is electrically connected to the control end, the scan output end, the output control end, the first voltage end and the second voltage end, respectively, and is used to control the connection or disconnection between the scan output end and the first voltage end under the control of the control signal provided by the control end, and to control the connection or disconnection between the scan output end and the second voltage end under the control of the potential of the output control end.

[0020] Optionally, the scan output terminal is the scan signal output terminal; or,

[0021] The scanning signal generating circuit also includes an inverting circuit; the input end of the inverting circuit is electrically connected to the scanning output end, and the output end of the inverting circuit is electrically connected to the scanning signal output end. The inverting circuit is used to invert the voltage signal connected to its input end to obtain an inverted voltage signal, and output the inverted voltage signal through the output end of the inverting circuit.

[0022] Optionally, the output control circuit includes a third transistor and a fourth transistor;

[0023] The gate of the third transistor is electrically connected to the control node, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the output control terminal;

[0024] The gate of the fourth transistor is electrically connected to the scan output terminal, the first electrode of the fourth transistor is electrically connected to the output control terminal, and the second electrode of the fourth transistor is electrically connected to the second voltage terminal;

[0025] The output circuit includes a fifth transistor, a sixth transistor and a second capacitor;

[0026] The gate of the fifth transistor is electrically connected to the control terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the scan output terminal;

[0027] The gate of the sixth transistor is electrically connected to the output control terminal, the first electrode of the sixth transistor is electrically connected to the scan output terminal, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal;

[0028] A first end of the second capacitor is electrically connected to the control end, and a second end of the second capacitor is electrically connected to the second voltage end.

[0029] The embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned driving circuit, and is characterized in that the driving method comprises: during at least a portion of a blank period between two display frames,

[0030] The first switch circuit controls, under the control of the first selection control signal, to write the data signal provided by the data output terminal of the source driver into the scanning signal generating circuit;

[0031] The scanning signal generating circuit generates a scanning signal according to the data signal, and outputs the scanning signal to a corresponding column scanning line of the display panel through a scanning signal output terminal.

[0032] Optionally, the driving circuit further includes a second switching circuit; and the driving method further includes:

[0033] During a data writing period in a frame of display time, the second switch circuit controls the data output terminal of the source driver to be connected to the corresponding column data line of the display panel under the control of the second selection control signal.

[0034] The embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a light-emitting driving circuit, and a control circuit;

[0035] The light-emitting driving circuit is electrically connected to the first node and the first electrode of the light-emitting element, respectively, and is used to generate a driving current for driving the light-emitting element under the control of the potential of the first node; the second electrode of the light-emitting element is electrically connected to the third voltage terminal;

[0036] The control circuit is electrically connected to the first gate line, the scan line, the first node and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the first node and the first electrode of the light-emitting element under the control of a first gate drive signal provided by the first gate line and a scan signal provided by the scan line.

[0037] Optionally, the control circuit includes a first control circuit and a second control circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;

[0038] The first control circuit is electrically connected to the first gate line, the first node and the intermediate node respectively, and the first control circuit is used to control the connection or disconnection between the first node and the intermediate node under the control of a first gate driving signal provided by the first gate line;

[0039] The second control circuit is electrically connected to the scan line, the intermediate node and the third node respectively, and is used to control the connection or disconnection between the intermediate node and the third node under the control of the scan signal provided by the scan line.

[0040] Optionally, the control circuit includes a first control circuit and a second control circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;

[0041] The first control circuit is electrically connected to the first gate line, the third node and the intermediate node respectively, and is used to control the connection or disconnection between the third node and the intermediate node under the control of the first gate drive signal provided by the first gate line;

[0042] The second control circuit is electrically connected to the scan line, the intermediate node and the first node respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of a scan signal provided by the scan line.

[0043] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;

[0044] The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the second node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second node under the control of the first initial control signal provided by the first initial control terminal.

[0045] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;

[0046] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the third node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the third node under the control of the second initial control signal provided by the second initial control terminal.

[0047] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit, and an energy storage circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element, respectively;

[0048] The data writing circuit is electrically connected to the second gate line, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second gate driving signal provided by the second gate line;

[0049] The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control line;

[0050] The second light emitting control circuit is electrically connected to the light emitting control line, the third node, and the first electrode of the light emitting element, respectively, and is configured to control the third node to be electrically connected to the first electrode of the light emitting element under the control of the light emitting control signal;

[0051] The energy storage circuit is electrically connected to the first node and is used to store electrical energy.

[0052] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit;

[0053] The third initialization circuit is electrically connected to the first initial control terminal, the third initial voltage terminal and the first pole of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first pole of the light-emitting element under the control of the first initial control signal provided by the first initial control terminal.

[0054] Optionally, the first control circuit includes a first control transistor, and the second control circuit includes a second control transistor;

[0055] The gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the first node, and the second electrode of the first control transistor is electrically connected to the intermediate node;

[0056] A gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the intermediate node, and a second electrode of the second control transistor is electrically connected to the third node.

[0057] Optionally, the first control circuit includes a first control transistor, and the second control circuit includes a second control transistor;

[0058] The gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the intermediate node, and the second electrode of the first control transistor is electrically connected to the third node;

[0059] A gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the first node, and a second electrode of the second control transistor is electrically connected to the intermediate node.

[0060] Optionally, the first initialization circuit includes a first initialization transistor;

[0061] A gate of the first initialization transistor is electrically connected to the first initial control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the second node.

[0062] Optionally, the second initialization circuit includes a second initialization transistor;

[0063] A gate of the second initialization transistor is electrically connected to the second initial control terminal, a first electrode of the second initialization transistor is electrically connected to the second initial voltage terminal, and a second electrode of the second initialization transistor is electrically connected to the third node.

[0064] Optionally, the data writing circuit includes a writing transistor, the first light emitting control circuit includes a first light emitting control transistor, and the second light emitting control circuit includes a second light emitting control transistor; the light emitting driving circuit includes a driving transistor, and the energy storage circuit includes a storage capacitor;

[0065] The gate of the write transistor is electrically connected to the second gate line, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the second node;

[0066] The gate of the first light emitting control transistor is electrically connected to the light emitting control line, the first electrode of the first light emitting control transistor is electrically connected to the power supply voltage terminal, and the second electrode of the first light emitting control transistor is electrically connected to the second node;

[0067] The gate of the second light emitting control transistor is electrically connected to the light emitting control line, the first electrode of the second light emitting control transistor is electrically connected to the third node, and the second electrode of the second light emitting control transistor is electrically connected to the first electrode of the light emitting element;

[0068] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0069] A first terminal of the storage capacitor is electrically connected to the first node, and a second terminal of the storage capacitor is electrically connected to a power supply voltage terminal.

[0070] Optionally, the third initialization circuit includes a third initialization transistor;

[0071] The gate of the third initialization transistor is electrically connected to the first initial control terminal, the first electrode of the third initialization transistor is electrically connected to the third initial voltage terminal, and the second electrode of the third initialization transistor is electrically connected to the first electrode of the light emitting element.

[0072] An embodiment of the present disclosure provides a pixel driving method, which is applied to the above-mentioned pixel circuit. The pixel driving method includes:

[0073] The light emitting driving circuit generates a driving current for driving the light emitting element under the control of the potential of the first node;

[0074] The control circuit controls the connection or disconnection between the first node and the first electrode of the light emitting element under the control of a first gate driving signal and a scan signal.

[0075] Optionally, the pixel circuit includes a first initialization circuit, a first end of the light-emitting driving circuit is electrically connected to the second node, and a second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element, respectively; the display period includes a first initialization time period and a second initialization time period set successively; and the pixel driving method includes:

[0076] During the first initialization period, the control circuit controls the first node and the third node to be connected under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; and the light emitting drive circuit controls the second node and the third node to be connected under the control of the potential of the first node;

[0077] During the second initialization time period, the control circuit controls the disconnection between the first node and the third node under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; and the light-emitting drive circuit controls the connection between the second node and the third node under the control of the potential of the first node.

[0078] An embodiment of the present disclosure provides a display panel, comprising a source driver and the above-mentioned driving circuit;

[0079] The source driver includes a data output terminal.

[0080] Optionally, the display panel described in the embodiment of the present disclosure includes a plurality of columns of scan lines;

[0081] The scanning signal output terminal of the scanning signal generating circuit in the driving circuit is electrically connected to the scanning line.

[0082] Optionally, the display panel includes a plurality of columns of data lines;

[0083] The data output terminal is directly electrically connected to the data line; or the driving circuit includes a second switching circuit, and the second switching circuit controls the connection or disconnection between the data output terminal and the data line under the control of a second selection control signal.

[0084] Optionally, the source driver is disposed on a first side of the display panel, and the driving circuit is disposed on the first side of the display panel; or,

[0085] The source driver is disposed on a first side of the display panel, and the driving circuit is disposed on a second side of the display panel. The first side and the second side are opposite sides.

[0086] Optionally, the display panel described in at least one embodiment of the present disclosure further includes the above-mentioned pixel circuit.

[0087] An embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0089] FIG2 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0090] FIG3 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0091] FIG4 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0092] FIG5 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0093] FIG6A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0094] FIG6B is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0095] FIG7 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0096] FIG8 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0097] FIG9 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0098] FIG10 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0099] FIG11 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0100] FIG12 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG11 ;

[0101] FIG13 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0102] FIG14 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG13;

[0103] FIG15 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0104] FIG16 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0105] FIG17 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0106] FIG18 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0107] FIG19 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0108] FIG20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0109] FIG21A is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG20 ;

[0110] FIG21B is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG20 ;

[0111] FIG22 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0112] FIG23 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0113] FIG24 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0114] FIG25 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0115] FIG26 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0116] FIG. 27 is a structural diagram of a display panel according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0117] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0118] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0119] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0120] The driving circuit according to the embodiment of the present disclosure includes a first switching circuit and a scanning signal generating circuit;

[0121] The first switch circuit is electrically connected to the first strobe control line, the data output terminal of the source driver and the scan signal generating circuit, and is used to control the writing of the data signal provided by the data output terminal into the scan signal generating circuit under the control of the first strobe control signal provided by the first strobe control line;

[0122] The scanning signal generating circuit is used to generate a scanning signal according to the data signal, and output the scanning signal through a scanning signal output terminal.

[0123] In an embodiment of the present disclosure, the driving circuit may include a first switching circuit and a scan signal generating circuit. During at least part of the blank time period between two frames of display time, the first switching circuit, under the control of a first selection control signal, controls the writing of the data signal provided by the data output terminal into the scan signal generating circuit; the scan signal generating circuit generates a scan signal based on the data signal, and provides the scan signal to a column of scan lines included in the display panel, thereby controlling the transistor controlled by the column of scan lines to be turned on or off during the next frame of display time according to the scan signal.

[0124] In a specific implementation, when the transistor controlled by the column scan line is turned off during the next frame display time, the pixel circuit where the transistor is located does not perform data voltage writing, and the original display brightness can be maintained by the low-leakage transistor, thereby avoiding the waste of power consumption caused by repeated refresh of the pixel circuit;

[0125] When the transistor controlled by the column scan line is turned on during the next frame display time, the pixel circuit where the transistor is located writes the data voltage and refreshes the image normally.

[0126] When updating an image, OLED (organic light-emitting diode) displays must initialize and write data voltages to all pixel circuits within one frame. However, in certain special displays (such as AOD (all-day off display) displays, static displays, or displays that are rarely updated), the data voltages of most pixel circuits on the entire screen do not need to be updated, and the original display brightness can be maintained by low-leakage LTPO (low-temperature polycrystalline oxide) TFTs (thin-film transistors). Repeatedly refreshing these pixel circuits wastes power on the data lines.

[0127] Based on this, the embodiment of the present disclosure designs a driving circuit that can control the scanning signal on a column of scanning lines during at least part of the blank time period between two frames of display time, so as to control the transistor controlled by the scanning line to be turned on or off in the next frame of display time according to the scanning signal, thereby controlling whether to refresh the data voltage of the corresponding pixel circuit, thereby realizing the update of the partial screen picture, while the remaining pictures do not need to be charged and discharged multiple times, thereby further reducing the power consumption of the OLED display, or achieving ultra-low power consumption by partially updating the display picture.

[0128] As shown in FIG1 , the driving circuit according to the embodiment of the present disclosure includes a first switching circuit 11 and a scanning signal generating circuit SD;

[0129] The first switch circuit 11 is electrically connected to the first selection control line SW1, the data output terminal S0 of the source driver and the scan signal generation circuit SD, and is used to control the data signal provided by the data output terminal S0 to be written into the scan signal generation circuit SD under the control of the first selection control signal provided by the first selection control line SW1;

[0130] The scan signal generating circuit SD is used to generate a scan signal according to the data signal, and output the scan signal through the scan signal output terminal CG.

[0131] In at least one embodiment of the present disclosure, the first switch circuit 11 may be electrically connected to a data output terminal of the source driver.

[0132] Optionally, the first switch circuit includes a first transistor and a first capacitor; the first switch circuit provides the data signal to the scan signal generating circuit through a control node;

[0133] The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the control node;

[0134] A first end of the first capacitor is electrically connected to the control node, and a second end of the first capacitor is electrically connected to a DC voltage end.

[0135] In at least one embodiment of the present disclosure, the data output end may be directly electrically connected to a data line, and the scan signal output end may be electrically connected to a scan line, but the present invention is not limited thereto.

[0136] As shown in FIG2 , the pixel circuit labeled P11 is the first row and first column, the pixel circuit labeled P21 is the second row and first column, the pixel circuit labeled P31 is the third row and first column, and the pixel circuit labeled P41 is the fourth row and first column;

[0137] The line labeled DL is a data line, the line labeled CG is a scan line, the line labeled NG1 is the first gate line of the first row, the line labeled NG2 is the first gate line of the first row, the line labeled NG3 is the first gate line of the third row, and the line labeled NG4 is the first gate line of the fourth row;

[0138] The driving circuit according to at least one embodiment of the present disclosure includes a first switching circuit and a scan signal generating circuit SD;

[0139] The first switch circuit includes a first transistor T1;

[0140] The gate of the first transistor T1 is electrically connected to the first selection control line SW1, the source of the first transistor T1 is connected to the data line DL, and the second electrode of the first transistor is electrically connected to the scan signal generating circuit SD;

[0141] DL is electrically connected to the data output terminal S0 of the source driver;

[0142] The scan signal generating circuit SD is configured to generate a scan signal according to the data signal provided by the data output terminal S0 and provide the scan signal to the scan line CGL.

[0143] In at least one embodiment shown in FIG. 2 , T1 is a p-type transistor. Between two display frames, SW1 provides a low voltage signal to turn on T1 .

[0144] The difference between at least one embodiment shown in FIG. 3 and at least one embodiment shown in FIG. 2 is that T1 is an n-type transistor, and between two display frames, SW1 provides a high voltage signal to turn on T1.

[0145] The driving circuit according to at least one embodiment of the present disclosure further includes a second switching circuit;

[0146] The second switch circuit is electrically connected to a second strobe control line, the data output terminal and a data line included in the display panel, and is used to control the connection or disconnection between the data output terminal and the data line under the control of a second strobe control signal provided by the second strobe control line;

[0147] The first gate control line and the second gate control line are the same gate control line, or the first gate control line and the second gate control line are different.

[0148] In a specific implementation, the driving circuit may further include a second switch circuit. The second switch circuit controls the connection or disconnection between the data output terminal and the data line under the control of a second selection control signal.

[0149] Optionally, the second switching circuit includes a second transistor;

[0150] A gate of the second transistor is electrically connected to the second selection control line, a first electrode of the second transistor is electrically connected to the data output terminal, and a second electrode of the second transistor is electrically connected to the data line.

[0151] As shown in FIG4 , the pixel circuit labeled P11 is the first row and first column, the pixel circuit labeled P21 is the second row and first column, the pixel circuit labeled P31 is the third row and first column, and the pixel circuit labeled P41 is the fourth row and first column;

[0152] The line labeled DL is a data line, the line labeled CG is a scan line, the line labeled NG1 is the first gate line of the first row, the line labeled NG2 is the first gate line of the first row, the line labeled NG1 is the first gate line of the third row, and the line labeled NG4 is the first gate line of the fourth row;

[0153] The driving circuit according to at least one embodiment of the present disclosure includes a first switching circuit, a second switching circuit and a scan signal generating circuit SD;

[0154] The first switching circuit may include a first transistor T1;

[0155] The gate of T1 is electrically connected to the first selection control line SW1, the source of T1 is electrically connected to the data output terminal S0 of the source driver, and the drain of T1 is electrically connected to the scan signal generating circuit SD;

[0156] The second switch circuit 13 includes a second transistor T2;

[0157] The gate of T2 is electrically connected to the first selection control line SW1, the source of T2 is electrically connected to the data line DL, and the drain of T2 is electrically connected to the data output terminal S0 of the source driver;

[0158] The scan signal generating circuit SD is configured to generate a scan signal according to the data signal provided by the data output terminal S0 and provide the scan signal to the scan line CGL.

[0159] In at least one embodiment shown in FIG. 4 , T1 is a p-type transistor, and T2 is an n-type transistor.

[0160] In at least one embodiment of the present disclosure as shown in FIG4 , during operation, during at least a portion of a blank period between two display frames, SW1 provides a low voltage signal, T1 is turned on, and the data signal provided by the data output terminal S0 is written into the scan signal generating circuit SD. The scan signal generating circuit SD is configured to generate a scan signal based on the data signal provided by the data output terminal S0 and provide the scan signal to the scan line CGL.

[0161] During one frame display time, SW1 provides a high voltage signal and T2 is turned on to control the connection between the data output terminal S0 and the data line DL.

[0162] The difference between at least one embodiment shown in FIG. 5 and at least one embodiment shown in FIG. 4 is that T1 is an n-type transistor and T2 is a p-type transistor.

[0163] In at least one embodiment of the present disclosure as shown in FIG5 , during operation, during at least a portion of a blank period between two display frames, SW1 provides a high voltage signal, T1 is turned on, and the data signal provided by the data output terminal S0 is written into the scan signal generating circuit SD. The scan signal generating circuit SD is configured to generate a scan signal based on the data signal provided by the data output terminal S0, and provide the scan signal to the first column scan line CG1.

[0164] During one frame display time, SW1 provides a low voltage signal and T2 is turned on to control the connection between the data output terminal S0 and the data line DL.

[0165] In at least one embodiment shown in FIG. 4 and FIG. 5 , the first gate control line and the second gate control line are the same gate control line.

[0166] As shown in FIG6A , the pixel circuit labeled P11 is the first row and first column, the pixel circuit labeled P21 is the second row and first column, the pixel circuit labeled P31 is the third row and first column, and the pixel circuit labeled P41 is the fourth row and first column;

[0167] The line labeled DL is a data line, the line labeled CG is a scan line, the line labeled NG1 is the first gate line of the first row, the line labeled NG2 is the first gate line of the first row, the line labeled NG1 is the first gate line of the third row, and the line labeled NG4 is the first gate line of the fourth row;

[0168] The driving circuit according to at least one embodiment of the present disclosure includes a first switching circuit, a second switching circuit and a scan signal generating circuit SD;

[0169] The first switching circuit may include a first transistor T1;

[0170] The gate of T1 is electrically connected to the first selection control line SW1, the source of T1 is electrically connected to the data line DL, and the drain of T1 is electrically connected to the scan signal generating circuit SD;

[0171] The second switch circuit 13 includes a second transistor T2;

[0172] The gate of T2 is electrically connected to the second selection control line SW2, the source of T2 is electrically connected to the data line DL, and the drain of T2 is electrically connected to the data output terminal S0 of the source driver;

[0173] The scan signal generating circuit SD is configured to generate a scan signal according to a data signal provided by the data output terminal S0 and provide the scan signal to the scan line CGL.

[0174] In at least one embodiment shown in FIG. 6A , the first gate control line and the second gate control line are different gate control lines.

[0175] In at least one embodiment shown in FIG. 6A , T1 is a p-type transistor, and T2 is a p-type transistor.

[0176] In at least one embodiment of the present disclosure as shown in FIG6A , during operation, during at least a portion of a blank period between two display frames, SW1 provides a low voltage signal, SW2 provides a high voltage signal, and T1 is turned on to write the data signal provided by the data output terminal S0 into the scan signal generating circuit SD. The scan signal generating circuit SD is configured to generate a scan signal based on the data signal provided by the data output terminal S0 and provide the scan signal to the scan line CGL.

[0177] During one frame display time, SW2 provides a low voltage signal, SW1 provides a high voltage signal, and T2 is turned on to control the connection between the data output terminal S0 and the data line DL.

[0178] The difference between at least one embodiment shown in FIG. 6B and at least one embodiment shown in FIG. 6A is that T1 is an n-type transistor and T2 is an n-type transistor.

[0179] In at least one embodiment of the present disclosure as shown in FIG6B , during operation, during at least a portion of a blank period between two display frames, SW1 provides a high voltage signal, SW2 provides a low voltage signal, and T1 is turned on to write the data signal provided by the data output terminal S0 into the scan signal generating circuit SD. The scan signal generating circuit SD is configured to generate a scan signal based on the data signal provided by the data output terminal S0 and provide the scan signal to the scan line CGL.

[0180] During one frame display time, SW2 provides a high voltage signal, SW1 provides a low voltage signal, and T2 is turned on to control the connection between the data output terminal S0 and the data line DL.

[0181] In at least one embodiment shown in Figures 2 to 6B , the scan signal generating circuit and the source driver are disposed on the same side of the display panel. In actual operation, the scan signal generating circuit and the source driver may be disposed on opposite sides of the display panel.

[0182] The difference between at least one embodiment shown in FIG. 7 and at least one embodiment shown in FIG. 2 is that T1 is disposed on the upper side of the display panel where the scan signal generating circuit is disposed.

[0183] The difference between at least one embodiment shown in FIG. 8 and at least one embodiment shown in FIG. 3 is that T1 is disposed on the upper side of the display panel where the scan signal generating circuit is disposed.

[0184] In at least one embodiment of the present disclosure, the scan signal generating circuit includes an output control circuit and an output circuit; the first switch circuit provides the data signal to the scan signal generating circuit through a control node;

[0185] The output control circuit is electrically connected to the control node, the first voltage terminal, the second voltage terminal, the output control terminal, and the scan output terminal, respectively, and is used to control the connection or disconnection between the output control terminal and the first voltage terminal under the control of the potential of the control node, and to control the connection or disconnection between the output control terminal and the second voltage terminal under the control of the signal provided by the scan output terminal;

[0186] The output circuit is electrically connected to the control end, the scan output end, the output control end, the first voltage end and the second voltage end, respectively, and is used to control the connection or disconnection between the scan output end and the first voltage end under the control of the control signal provided by the control end, and to control the connection or disconnection between the scan output end and the second voltage end under the control of the potential of the output control end.

[0187] In a specific implementation, the scan signal generating circuit may include an output control circuit and an output circuit. The output control circuit controls the connection or disconnection between the output control terminal and the first voltage terminal under the control of the potential of the control node, and controls the connection or disconnection between the output control terminal and the second voltage terminal under the control of the signal provided by the scan output terminal; the output circuit controls the connection or disconnection between the scan output terminal and the first voltage terminal under the control of the control signal provided by the control terminal, and controls the connection or disconnection between the scan output terminal and the second voltage terminal under the control of the potential of the output control terminal.

[0188] Optionally, the scan output terminal is the scan signal output terminal; or,

[0189] The scanning signal generating circuit also includes an inverting circuit; the input end of the inverting circuit is electrically connected to the scanning output end, and the output end of the inverting circuit is electrically connected to the scanning signal output end. The inverting circuit is used to invert the voltage signal connected to its input end to obtain an inverted voltage signal, and output the inverted voltage signal through the output end of the inverting circuit.

[0190] As shown in FIG9 , the first switch circuit 11 is electrically connected to the first strobe control line SW1, the data output terminal S0 of the source driver, and the control node NC, respectively, and is configured to control the connection or disconnection between the data output terminal S0 and the control node NC under the control of the first strobe control signal provided by the first strobe control line SW1;

[0191] The scanning signal generating circuit includes an output control circuit 71 and an output circuit 72;

[0192] The output control circuit 71 is electrically connected to the control node NC, the first voltage terminal V1, the second voltage terminal V2, the output control terminal OE, and the scan signal output terminal CG, respectively, and is used to control the connection or disconnection between the output control terminal OE and the first voltage terminal V1 under the control of the potential of the control node NC, and to control the connection or disconnection between the output control terminal OE and the second voltage terminal V2 under the control of the signal provided by the scan signal output terminal CG;

[0193] The output circuit 72 is electrically connected to the control terminal VHRD, the output control terminal OE, the scan signal output terminal CG, the first voltage terminal V1 and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the scan signal output terminal CG and the first voltage terminal V1 under the control of the potential of the control signal provided by the control terminal VHRD, and to control the connection or disconnection between the scan signal output terminal CG and the second voltage terminal V2 under the control of the potential of the output control terminal OE.

[0194] In at least one embodiment of the scan signal generating circuit shown in FIG9 , the scan output terminal may be a scan signal output terminal CG, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal, but is not limited thereto.

[0195] As shown in FIG10 , the first switch circuit 11 is electrically connected to the first strobe control line SW1, the data output terminal S0 of the source driver, and the control node NC, respectively, and is configured to control the connection or disconnection between the data output terminal S0 and the control node NC under the control of the first strobe control signal provided by the first strobe control line SW1;

[0196] The scanning signal generating circuit includes an output control circuit 71 and an output circuit 72;

[0197] The output control circuit 71 is electrically connected to the control node NC, the first voltage terminal V1, the second voltage terminal V2, the output control terminal OE, and the scan output terminal OP, respectively, and is used to control the connection or disconnection between the output control terminal OE and the first voltage terminal V1 under the control of the potential of the control node NC1, and to control the connection or disconnection between the output control terminal OE and the second voltage terminal V2 under the control of the signal provided by the scan output terminal OP;

[0198] The output circuit 72 is electrically connected to the control terminal VHRD, the scan output terminal OP, the output control terminal OE, the first voltage terminal V1, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the scan output terminal OP and the first voltage terminal V1 under the control of the potential of the control terminal VHRD, and to control the connection or disconnection between the scan output terminal OP and the second voltage terminal V2 under the control of the potential of the output control terminal OE;

[0199] The scanning signal generating circuit further includes an inverting circuit 73;

[0200] The input end of the inverting circuit 73 is electrically connected to the scan output end OP, and the output end of the inverting circuit 73 is electrically connected to the scan signal output end CG. The inverting circuit 73 is used to invert the voltage signal connected to its input end to obtain an inverted voltage signal, and output the inverted voltage signal through the output end of the inverting circuit 73.

[0201] Optionally, the output control circuit includes a third transistor and a fourth transistor;

[0202] The gate of the third transistor is electrically connected to the control node, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the output control terminal;

[0203] The gate of the fourth transistor is electrically connected to the scan output terminal, the first electrode of the fourth transistor is electrically connected to the output control terminal, and the second electrode of the fourth transistor is electrically connected to the second voltage terminal;

[0204] The output circuit includes a fifth transistor, a sixth transistor and a second capacitor;

[0205] The gate of the fifth transistor is electrically connected to the control terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the scan output terminal;

[0206] The gate of the sixth transistor is electrically connected to the output control terminal, the first electrode of the sixth transistor is electrically connected to the scan output terminal, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal;

[0207] A first end of the second capacitor is electrically connected to the control end, and a second end of the second capacitor is electrically connected to the second voltage end.

[0208] As shown in FIG11 , based on at least one embodiment shown in FIG9 ,

[0209] The first switch circuit includes a first transistor T1 and a first capacitor C1;

[0210] The gate of the first transistor T1 is electrically connected to the first selection control line SW1, the source of the first transistor is electrically connected to the data output terminal S0, and the drain of the first transistor T1 is electrically connected to the control node NC;

[0211] A first end of the first capacitor C1 is electrically connected to the control node NC, and a second end of the first capacitor C1 is electrically connected to the low voltage terminal VGL;

[0212] The output control circuit includes a third transistor T3 and a fourth transistor T4;

[0213] The gate of the third transistor T3 is electrically connected to the control node NC, the source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and the drain of the third transistor T3 is electrically connected to the output control terminal OE;

[0214] The gate of the fourth transistor T4 is electrically connected to the scan signal output terminal CG, the source of the fourth transistor T4 is electrically connected to the output control terminal OE, and the drain of the fourth transistor T4 is electrically connected to the low voltage terminal VGL;

[0215] The output circuit includes a fifth transistor T5, a sixth transistor T6 and a second capacitor C2;

[0216] The gate of the fifth transistor T5 is electrically connected to the control terminal VHRD, the source of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the scan signal output terminal CG;

[0217] The gate of the sixth transistor T6 is electrically connected to the output control terminal OE, the source of the sixth transistor T6 is electrically connected to the scan signal output terminal CG, and the drain of the sixth transistor T6 is electrically connected to the low voltage terminal VGL;

[0218] A first end of the second capacitor C2 is electrically connected to the control end VHRD, and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.

[0219] In at least one embodiment of the scan signal generating circuit shown in FIG. 11 , the control voltage terminal is the second voltage terminal, the first voltage terminal is the high voltage terminal, and the second voltage terminal is the low voltage terminal, but the present invention is not limited thereto.

[0220] In at least one embodiment of the scan signal generating circuit shown in FIG. 11 , S0 may be electrically connected to the corresponding column data line DL.

[0221] In at least one embodiment shown in FIG. 11 , T1 is a p-type transistor, T3 is a p-type transistor, T4 is an n-type transistor, T5 is a p-type transistor, and T6 is an n-type transistor.

[0222] In at least one embodiment shown in FIG. 11 , the control terminal VHRD is used for a 3V voltage signal, the high voltage terminal VGH can be used to provide an 8V voltage signal, and the low voltage terminal VGL can be used to provide a −8V voltage signal.

[0223] In at least one embodiment of the present disclosure, the voltage value of the control signal provided by the control terminal VHRD can be greater than or equal to 3V and less than or equal to 4V, the voltage value of the high voltage signal provided by the high voltage terminal VGH can be greater than or equal to 7V and less than or equal to 9V, and the voltage value of the low voltage signal provided by the low voltage terminal VGL can be greater than or equal to -9V and less than or equal to -7V, but the present invention is not limited to this.

[0224] As shown in FIG12 , when at least one embodiment shown in FIG11 is working, the period labeled TB1 is the first blank period, the period labeled TB2 is the second control period, the period labeled TX1 is the first data writing period, and the period labeled TX2 is the second data writing period.

[0225] During part of the first blank period TB1, SW1 provides a low voltage signal, T1 is turned on, S0 provides a high voltage signal, the data line DL is connected to the high voltage signal, the potential of NC is high, T5 is turned on, CG is connected to VGH, the potential of CG is high, T4 is turned on, so that OE is connected to VGL, and OE outputs a low voltage signal;

[0226] In the first data writing period TX1, the potential of CG is maintained at a high voltage;

[0227] During part of the second blank period TB2, SW1 provides a low voltage signal, T1 is turned on, S0 provides a low voltage signal, DL receives the low voltage signal, the potential of NC is low, T3 is turned on, OE is connected to VGH, the potential of OE is high, T6 is turned on, and CG outputs a low voltage signal.

[0228] In the second data writing period TX2 , the potential of CG is maintained at a low voltage.

[0229] In at least one embodiment shown in FIG11 , during operation, during part of the first blank period TB1 , the voltage value of the high voltage signal connected to the DL may be 7V;

[0230] During part of the second blank period TB2, the voltage value of the low voltage signal connected to DL may be 0V;

[0231] But it is not limited to this.

[0232] During operation of at least one embodiment shown in FIG. 11 of the present disclosure, during a portion of the second blank period TB2 , the opening degree of T6 is higher than that of T5 , so CG outputs a low voltage signal.

[0233] As shown in FIG13, based on at least one embodiment shown in FIG10,

[0234] The first switch circuit includes a first transistor T1 and a first capacitor C1;

[0235] The gate of the first transistor T1 is electrically connected to the first selection control line SW1, the source of the first transistor is electrically connected to the data output terminal S0, and the drain of the first transistor T1 is electrically connected to the control node NC;

[0236] A first end of the first capacitor C1 is electrically connected to the control node NC, and a second end of the first capacitor C1 is electrically connected to the low voltage terminal VGL;

[0237] The output control circuit includes a third transistor T3 and a fourth transistor T4;

[0238] The gate of the third transistor T3 is electrically connected to the control node NC, the source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and the drain of the third transistor T3 is electrically connected to the output control terminal OE;

[0239] The gate of the fourth transistor T4 is electrically connected to the control node NC, the source of the fourth transistor T4 is electrically connected to the output control terminal OE, and the drain of the fourth transistor T4 is electrically connected to the low voltage terminal VGL;

[0240] The output circuit includes a fifth transistor T5 and a sixth transistor T6;

[0241] The gate of the fifth transistor T5 is electrically connected to the control terminal VHRD, the source of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the scan output terminal OP;

[0242] The gate of the sixth transistor T6 is electrically connected to the output control terminal OE, the source of the sixth transistor T6 is electrically connected to the scan output terminal OP, and the drain of the sixth transistor T6 is electrically connected to the low voltage terminal VGL;

[0243] The inverting circuit includes an inverter IV;

[0244] The input end of the inverter IV is electrically connected to the scan output end OP, and the output end of the inverter IV is electrically connected to the scan signal output end CG. The inverter IV is used to invert the voltage signal connected to its input end to obtain an inverted voltage signal, and output the inverted voltage signal through the output end of the inverter IV.

[0245] In at least one embodiment of the scan signal generating circuit shown in FIG. 13 , the first voltage end is a high voltage end, and the second voltage end is a low voltage end, but the present invention is not limited thereto.

[0246] In at least one embodiment of the scan signal generating circuit shown in FIG. 13 , S0 may be electrically connected to the data line DL.

[0247] In at least one embodiment shown in FIG. 13 , the control terminal VHRD is used for a 3V voltage signal, the high voltage terminal VGH can be used to provide an 8V voltage signal, and the low voltage terminal VGL can be used to provide a −8V voltage signal.

[0248] In at least one embodiment of the scanning signal generating circuit shown in FIG13 , when in operation, the first blank period, the first data writing period, the second blank period, and the second data writing period can be set sequentially;

[0249] During at least part of the first blank period, SW1 provides a low voltage signal, T1 is turned on, S0 provides a high voltage signal, DL is connected to the high voltage signal, the potential of NC is high, T5 is turned on, OP is connected to VGH, the potential of OP is high, T4 is turned on to connect OE to VGL, OE outputs a low voltage signal, and CG outputs a low voltage signal.

[0250] During the first data writing period, the potential of CG is maintained at a low voltage;

[0251] During at least part of the second blank period, SW1 provides a low voltage signal, T1 is turned on, S0 provides a low voltage signal, DL receives the low voltage signal, the potential of NC is low, T3 is turned on, OE is connected to VGH, the potential of OE is high, T6 is turned on, OP outputs a low voltage signal, and CG outputs a high voltage signal.

[0252] During the second data writing period, the potential of CG is maintained at a high voltage.

[0253] In at least one embodiment shown in FIG13 , during operation, during part of the first blank period, the voltage value of the high voltage signal connected to the DL may be 7V;

[0254] During part of the second blank period TB2, the voltage value of the low voltage signal connected to DL may be 0V;

[0255] But it is not limited to this.

[0256] During operation of at least one embodiment shown in FIG. 13 of the present disclosure, during a portion of the second blank period, the opening degree of T6 is higher than that of T5 , so OP outputs a low voltage signal.

[0257] FIG. 14 is a timing diagram illustrating a simulated operation of at least one embodiment of the scan signal generating circuit shown in FIG. 13 .

[0258] The driving method according to the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving method includes: during at least a portion of a blank period between two display frames,

[0259] The first switch circuit controls, under the control of the first selection control signal, to write the data signal provided by the data output terminal of the source driver into the scanning signal generating circuit;

[0260] The scanning signal generating circuit generates a scanning signal according to the data signal, and outputs the scanning signal to a corresponding column scanning line of the display panel through a scanning signal output terminal.

[0261] In the driving method described in the embodiment of the present invention, during at least part of the blank period between two frames of display time; the first switching circuit, under the control of a first selection control signal, controls the writing of the data signal provided by the data output end of the source driver into the scan signal generating circuit; the scan signal generating circuit generates a scan signal according to the data signal provided by the data output end, and outputs the scan signal to the corresponding column scan line of the display panel through the scan signal output end.

[0262] In at least one embodiment of the present disclosure, the driving circuit further includes a second switching circuit; and the driving method further includes:

[0263] During a data writing period in a frame of display time, the second switch circuit controls the data output terminal of the source driver to be connected to the corresponding column data line of the display panel under the control of a second selection control signal.

[0264] In a specific implementation, the driving circuit may further include a second switching circuit. During the data writing period in a frame display time, the second switching circuit, under the control of a second selection control signal, controls the data output end to be connected to the corresponding column data line of the display panel to provide a data voltage to the data line.

[0265] The pixel circuit described in the embodiment of the present disclosure includes a light-emitting element, a light-emitting driving circuit and a control circuit;

[0266] The light-emitting driving circuit is electrically connected to the first node and the first electrode of the light-emitting element, respectively, and is used to generate a driving current for driving the light-emitting element under the control of the potential of the first node; the second electrode of the light-emitting element is electrically connected to the third voltage terminal;

[0267] The control circuit is electrically connected to the first gate line, the scan line, the first node and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the first node and the first electrode of the light-emitting element under the control of a first gate drive signal provided by the first gate line and a scan signal provided by the scan line.

[0268] In a specific implementation, the pixel circuit may include a control circuit and a light-emitting driving circuit. The light-emitting driving circuit generates a driving current under the control of the potential of the first node. The control circuit controls the connection or disconnection between the first node and the first pole of the light-emitting element under the control of the first gate driving signal provided by the first gate line and the scanning signal provided by the scanning line. The driving current may be a current that drives the light-emitting element to emit light.

[0269] In at least one embodiment of the present disclosure, the third voltage terminal may be a low level terminal, but is not limited thereto.

[0270] Optionally, the light-emitting element is an organic light-emitting diode, the first electrode of the light-emitting element is an anode, and the second electrode of the light-emitting element is a cathode.

[0271] As shown in FIG15 , the pixel circuit may include a light emitting element E0, a control circuit 201 and a light emitting driving circuit 230;

[0272] The light-emitting driving circuit 230 is electrically connected to the first node N1 and the first electrode of the light-emitting element E0, respectively, and is configured to generate a driving current for driving the light-emitting element E0 under the control of the potential of the first node N1; the second electrode of the light-emitting element E0 is electrically connected to the third voltage terminal V3;

[0273] The control circuit 201 is electrically connected to the first gate line NG, the scan line CGL, the first node N1 and the first electrode of the light-emitting element E0, respectively, and is used to control the connection or disconnection between the first node N1 and the first electrode of the light-emitting element E0 under the control of a first gate drive signal provided by the first gate line NG and a scan signal provided by the scan line CGL.

[0274] In at least one embodiment of the present disclosure, the control circuit includes a first control circuit and a second control circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;

[0275] The first control circuit is electrically connected to the first gate line, the first node and the intermediate node respectively, and the first control circuit is used to control the connection or disconnection between the first node and the intermediate node under the control of a first gate driving signal provided by the first gate line;

[0276] The second control circuit is electrically connected to the scan line, the intermediate node and the third node respectively, and is used to control the connection or disconnection between the intermediate node and the third node under the control of the scan signal provided by the scan line.

[0277] In a specific implementation, the control circuit may include a first control circuit and a second control circuit. The first control circuit controls the connection or disconnection between the first node and the intermediate node under the control of a first gate drive signal provided by a first gate line, and the second control circuit controls the connection or disconnection between the intermediate node and the third node under the control of a scan signal provided by the scan line.

[0278] As shown in FIG16 , based on at least one embodiment of the pixel circuit shown in FIG15 , the control circuit includes a first control circuit 241 and a second control circuit 242; a first terminal of the light-emitting driving circuit 230 is electrically connected to the second node N2, and a second terminal of the light-emitting driving circuit 230 is electrically connected to the third node N3 and the first electrode of the light-emitting element E0, respectively;

[0279] The first control circuit 241 is electrically connected to the first gate line NG, the first node N1 and the intermediate node NZ respectively, and is used to control the connection or disconnection between the first node N1 and the intermediate node NZ under the control of the first gate driving signal provided by the first gate line NG;

[0280] The second control circuit 242 is electrically connected to the scan line CGL, the middle node NZ and the third node N3 respectively, and is used to control the connection or disconnection between the middle node NZ and the third node N3 under the control of the scan signal provided by the scan line CGL.

[0281] In at least one embodiment of the present disclosure, the control circuit includes a first control circuit and a second control circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;

[0282] The first control circuit is electrically connected to the first gate line, the third node and the intermediate node respectively, and is used to control the connection or disconnection between the third node and the intermediate node under the control of the first gate drive signal provided by the first gate line;

[0283] The second control circuit is electrically connected to the scan line, the intermediate node and the first node respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of a scan signal provided by the scan line.

[0284] In a specific implementation, the control circuit may include a first control circuit and a second control circuit, wherein the first control circuit controls the connection or disconnection between the third node and the intermediate node under the control of a first gate drive signal provided by the first gate line; and the second control circuit controls the connection or disconnection between the intermediate node and the first node under the control of a scan signal provided by the scan line.

[0285] As shown in FIG17 , based on at least one embodiment of the pixel circuit shown in FIG15 , the control circuit includes a first control circuit 241 and a second control circuit 242; a first terminal of the light-emitting driving circuit 230 is electrically connected to the second node N2, and a second terminal of the light-emitting driving circuit 230 is electrically connected to the third node N3 and the first electrode of the light-emitting element E0, respectively;

[0286] The first control circuit 241 is electrically connected to the first gate line NG, the third node N3 and the intermediate node NZ, respectively, and is used to control the connection or disconnection between the third node N3 and the intermediate node NZ under the control of the first gate driving signal provided by the first gate line NG;

[0287] The second control circuit 242 is electrically connected to the scan line CGL, the middle node NZ and the first node N1 respectively, and is used to control the connection or disconnection between the middle node NZ and the first node N1 under the control of the scan signal provided by the scan line CGL.

[0288] The pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;

[0289] The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the second node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second node under the control of the first initial control signal provided by the first initial control terminal.

[0290] In a specific implementation, the display period may include a first initialization time period and a second initialization time period set successively;

[0291] During the first initialization period, the control circuit controls the first node and the third node to be connected under the control of the first gate drive signal and the scan signal; the first initialization circuit writes a first initial voltage to the second node under the control of the first initial control signal; and the light emitting drive circuit controls the second node and the third node to be connected under the control of the potential of the first node;

[0292] During the second initialization time period, the control circuit controls the disconnection between the first node and the third node under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; and the light-emitting drive circuit controls the connection between the second node and the third node under the control of the potential of the first node.

[0293] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, in a first initialization time period, before data is written, the potentials of the first node, the second node, and the third node are initialized to reduce subsequent charging differences. In a second initialization time period, the first initialization circuit writes the first initial voltage to the second node, and the light-emitting drive circuit controls the connection between the second node and the third node so that the drive transistor included in the light-emitting drive circuit is in a bias state, which can improve the hysteresis phenomenon.

[0294] The pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;

[0295] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the third node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the third node under the control of the second initial control signal provided by the second initial control terminal.

[0296] In a specific implementation, the pixel circuit may further include a second initialization circuit;

[0297] In a third initialization time period set between the first initialization time period and the second initialization time period, before the data writing time period, the second initialization circuit writes the second initial voltage to the third node under the control of the second initial control signal, so that at the beginning of the data writing time period, the driving transistor included in the light-emitting driving circuit can be turned on, thereby facilitating data voltage writing and threshold voltage compensation.

[0298] In at least one embodiment of the present disclosure, the pixel circuit further includes a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit, and a storage circuit; a first end of the light-emitting driving circuit is electrically connected to the second node, and a second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element, respectively;

[0299] The data writing circuit is electrically connected to the second gate line, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second gate driving signal provided by the second gate line;

[0300] The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control line;

[0301] The second light emitting control circuit is electrically connected to the light emitting control line, the third node, and the first electrode of the light emitting element, respectively, and is configured to control the third node to be electrically connected to the first electrode of the light emitting element under the control of the light emitting control signal;

[0302] The energy storage circuit is electrically connected to the first node and is used to store electrical energy.

[0303] In a specific implementation, the pixel circuit may further include a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit and an energy storage circuit; the data writing circuit is used to write the data voltage into the second node, the first light-emitting control circuit and the second light-emitting control circuit are used to control the conduction light-emitting path, and the energy storage circuit is used to store electrical energy.

[0304] The pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit;

[0305] The third initialization circuit is electrically connected to the first initial control terminal, the third initial voltage terminal and the first pole of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first pole of the light-emitting element under the control of the first initial control signal provided by the first initial control terminal.

[0306] In a specific implementation, the pixel circuit may further include a third initialization circuit, which, under the control of the first initial control signal, writes a third initial voltage into the first electrode of the light-emitting element to control the light-emitting element not to emit light and clear the residual charge in the first electrode of the light-emitting element.

[0307] As shown in FIG18 , based on at least one embodiment of the pixel circuit shown in FIG16 , the pixel circuit according to at least one embodiment of the present disclosure may further include a first initialization circuit 231, a second initialization circuit 232, a data writing circuit 233, a first light-emitting control circuit 234, a second light-emitting control circuit 235, a storage circuit 236, and a third initialization circuit 237; the second electrode of the light-emitting element E0 is electrically connected to the low-level terminal ELVSS;

[0308] The first initialization circuit 231 is electrically connected to the first initial control terminal HR, the first initial voltage terminal I1, and the second node N2, respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2 under the control of the first initial control signal provided by the first initial control terminal HR;

[0309] The second initialization circuit 232 is electrically connected to the second initial control terminal PR, the second initial voltage terminal I2, and the third node N3, respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the third node N3 under the control of the second initial control signal provided by the second initial control terminal PR;

[0310] The data writing circuit 233 is electrically connected to the second gate line PG, the data line DT and the second node N2 respectively, and is used to write the data voltage Vdata provided by the data line DT into the second node N2 under the control of the second gate driving signal provided by the second gate line PG;

[0311] The first light emitting control circuit 234 is electrically connected to the light emitting control line E1, the power supply voltage terminal ELVDD, and the second node N2, respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control line E1;

[0312] The second light emitting control circuit 235 is electrically connected to the light emitting control line E1, the third node N3, and the first electrode of the light emitting element E0, respectively, and is configured to control the third node N3 to be electrically connected to the first electrode of the light emitting element E0 and the second electrode of the light emitting element E0 to be electrically connected to the third voltage terminal V3 under the control of the light emitting control signal;

[0313] The energy storage circuit 236 is electrically connected to the first node N1 and is used to store electrical energy;

[0314] The third initialization circuit 237 is electrically connected to the first initial control terminal HR, the third initial voltage terminal I3 and the first electrode of the light-emitting element E0, respectively, and is configured to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E0 under the control of the first initial control signal provided by the first initial control terminal HR.

[0315] In at least one embodiment of the pixel circuit shown in FIG. 18 , the third voltage terminal is a low level terminal ELVSS.

[0316] As shown in FIG19 , based on at least one embodiment of the pixel circuit shown in FIG17 , the pixel circuit according to at least one embodiment of the present disclosure may further include a first initialization circuit 231, a second initialization circuit 232, a data writing circuit 233, a first light-emitting control circuit 234, a second light-emitting control circuit 235, a storage circuit 236, and a third initialization circuit 237; the second electrode of the light-emitting element E0 is electrically connected to the low-level terminal ELVSS;

[0317] The first initialization circuit 231 is electrically connected to the first initial control terminal HR, the first initial voltage terminal I1, and the second node N2, respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2 under the control of the first initial control signal provided by the first initial control terminal HR;

[0318] The second initialization circuit 232 is electrically connected to the second initial control terminal PR, the second initial voltage terminal I2, and the third node N3, respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the third node N3 under the control of the second initial control signal provided by the second initial control terminal PR;

[0319] The data writing circuit 233 is electrically connected to the second gate line PG, the data line DT and the second node N2 respectively, and is used to write the data voltage Vdata provided by the data line DT into the second node N2 under the control of the second gate driving signal provided by the second gate line PG;

[0320] The first light emitting control circuit 234 is electrically connected to the light emitting control line E1, the power supply voltage terminal ELVDD, and the second node N2, respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control line E1;

[0321] The second light emitting control circuit 235 is electrically connected to the light emitting control line E1, the third node N3, and the first electrode of the light emitting element E0, respectively, and is configured to control the third node N3 to be electrically connected to the first electrode of the light emitting element E0 and the second electrode of the light emitting element E0 to be electrically connected to the third voltage terminal V3 under the control of the light emitting control signal;

[0322] The energy storage circuit 236 is electrically connected to the first node N1 and is used to store electrical energy;

[0323] The third initialization circuit 237 is electrically connected to the first initial control terminal HR, the third initial voltage terminal I3 and the first electrode of the light-emitting element E0, respectively, and is configured to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E0 under the control of the first initial control signal provided by the first initial control terminal HR.

[0324] In at least one embodiment of the pixel circuit shown in FIG. 19 , the third voltage terminal is a low level terminal ELVSS.

[0325] Optionally, the first control circuit includes a first control transistor, and the second control circuit includes a second control transistor;

[0326] The gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the first node, and the second electrode of the first control transistor is electrically connected to the intermediate node;

[0327] A gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the intermediate node, and a second electrode of the second control transistor is electrically connected to the third node.

[0328] Optionally, the first control circuit includes a first control transistor, and the second control circuit includes a second control transistor;

[0329] The gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the intermediate node, and the second electrode of the first control transistor is electrically connected to the third node;

[0330] A gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the first node, and a second electrode of the second control transistor is electrically connected to the intermediate node.

[0331] Optionally, the first initialization circuit includes a first initialization transistor;

[0332] A gate of the first initialization transistor is electrically connected to the first initial control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the second node.

[0333] Optionally, the second initialization circuit includes a second initialization transistor;

[0334] A gate of the second initialization transistor is electrically connected to the second initial control terminal, a first electrode of the second initialization transistor is electrically connected to the second initial voltage terminal, and a second electrode of the second initialization transistor is electrically connected to the third node.

[0335] Optionally, the data writing circuit includes a writing transistor, the first light emitting control circuit includes a first light emitting control transistor, and the second light emitting control circuit includes a second light emitting control transistor; the light emitting driving circuit includes a driving transistor, and the energy storage circuit includes a storage capacitor;

[0336] The gate of the write transistor is electrically connected to the second gate line, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the second node;

[0337] The gate of the first light emitting control transistor is electrically connected to the light emitting control line, the first electrode of the first light emitting control transistor is electrically connected to the power supply voltage terminal, and the second electrode of the first light emitting control transistor is electrically connected to the second node;

[0338] The gate of the second light emitting control transistor is electrically connected to the light emitting control line, the first electrode of the second light emitting control transistor is electrically connected to the third node, and the second electrode of the second light emitting control transistor is electrically connected to the first electrode of the light emitting element;

[0339] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0340] A first terminal of the storage capacitor is electrically connected to the first node, and a second terminal of the storage capacitor is electrically connected to a power supply voltage terminal.

[0341] Optionally, the third initialization circuit includes a third initialization transistor;

[0342] The gate of the third initialization transistor is electrically connected to the first initial control terminal, the first electrode of the third initialization transistor is electrically connected to the third initial voltage terminal, and the second electrode of the third initialization transistor is electrically connected to the first electrode of the light emitting element.

[0343] As shown in FIG20 , based on at least one embodiment of the pixel circuit shown in FIG18 , the first control circuit includes a first control transistor M1 , the second control circuit includes a second control transistor M2 , and the light emitting drive circuit includes a drive transistor M0 ;

[0344] The gate of the first control transistor M1 is electrically connected to the first gate line NG, the source of the first control transistor M1 is electrically connected to the first node N1, and the second electrode of the first control transistor M1 is electrically connected to the middle node NZ;

[0345] The gate of the second control transistor M2 is electrically connected to the scan line CGL, the source of the second control transistor M2 is electrically connected to the intermediate node NZ, and the drain of the second control transistor M2 is electrically connected to the third node N3;

[0346] The gate of the driving transistor M0 is electrically connected to the first node N1, the source of the driving transistor M0 is electrically connected to the second node N2, and the drain of the driving transistor M0 is electrically connected to the third node N3;

[0347] The first initialization circuit includes a first initialization transistor M3;

[0348] The gate of the first initialization transistor M3 is electrically connected to the first initial control terminal HR, the source of the first initialization transistor M3 is electrically connected to the first initial voltage terminal I1, and the drain of the first initialization transistor M3 is electrically connected to the second node N2; the first initial voltage terminal I1 is used to provide a first initial voltage Vinit1;

[0349] The second initialization circuit includes a second initialization transistor M4;

[0350] The gate of the second initialization transistor M4 is electrically connected to the second initial control terminal PR, the source of the second initialization transistor M4 is electrically connected to the second initial voltage terminal I2, and the drain of the second initialization transistor M4 is electrically connected to the third node N3; the second initial voltage terminal I2 is used to provide a second initial voltage Vinit2;

[0351] The data writing circuit includes a writing transistor M5, the first light emitting control circuit includes a first light emitting control transistor M6, and the second light emitting control circuit includes a second light emitting control transistor M7; the energy storage circuit includes a storage capacitor Cst; and the light emitting element is an organic light emitting diode O1;

[0352] The gate of the write transistor M5 is electrically connected to the second gate line PG, the source of the write transistor M5 is electrically connected to the data line DT, and the drain of the write transistor M5 is electrically connected to the second node N2;

[0353] The gate of the first light-emitting control transistor M6 is electrically connected to the light-emitting control line E1, the source of the first light-emitting control transistor M6 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the first light-emitting control transistor M6 is electrically connected to the second node N2;

[0354] a gate of the second light emitting control transistor M7 is electrically connected to the light emitting control line E1, a source of the second light emitting control transistor M7 is electrically connected to the third node N3, and a drain of the second light emitting control transistor M7 is electrically connected to the anode of the organic light emitting diode O1;

[0355] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD;

[0356] The third initialization circuit includes a third initialization transistor M8;

[0357] The gate of the third initialization transistor M8 is electrically connected to the first initial control terminal HR, the source of the third initialization transistor M8 is electrically connected to the third initial voltage terminal I3, and the drain of the third initialization transistor M8 is electrically connected to the anode of the organic light emitting diode O1;

[0358] The cathode of the organic light emitting diode O1 is electrically connected to the low level terminal ELVSS.

[0359] In at least one embodiment of the pixel circuit shown in FIG. 20 , M1 and M2 are n-type transistors, and the other transistors are p-type transistors, but the present invention is not limited thereto.

[0360] As shown in FIG21A , during operation of at least one embodiment of the pixel circuit shown in FIG20 of the present disclosure, a frame display time may include a first initialization time period TI1, a third initialization time period TI3, a data writing time period TX, a second initialization time period TI2, and a light-emitting time period TF, which are sequentially set. During this frame display time, CG may output a high voltage signal to control M2 to be turned on.

[0361] In the first initialization period TI1, the third initialization period TI3 ​​and the data writing period TX, NG outputs a high voltage signal to control M1 to be turned on;

[0362] In the first initialization period TI1, the third initialization period TI3, the data writing period TX and the second initialization period TI2, E1 provides a high voltage signal, and M6 and M7 are turned off;

[0363] In the second initialization period TI2 and the light-emitting period TF, NG outputs a low voltage signal to control M1 to turn off;

[0364] In the first initialization time period TI1, HR outputs a low voltage signal, PR and PG both output high voltage signals, M3 is turned on to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2, M0 is turned on to control the connection between N2 and N3, M1 and M2 are turned on to control the connection between N1 and N3, so as to initialize the potentials of the first node N1, the second node N2, and the third node N3, so as to reduce subsequent charging differences;

[0365] In the third initialization period TI3, PR outputs a low voltage signal, HR and PG both output high voltage signals, M4 is turned on to write the second initialization voltage Vinit2 provided by I2 into the third node N3, so that M0 can be turned on when the data writing period TX begins;

[0366] During the data writing period TX, HR and PR both output high voltage signals, PG outputs a low voltage signal, M5 is turned on, and DT provides the data voltage Vdata to N2;

[0367] At the beginning of the data writing period TX, M0 is turned on, Vdata charges Cst, until the potential of the first node N1 becomes Vdata+Vth, and M0 is turned off; wherein Vth is the threshold voltage of M0;

[0368] In the second initialization time period TI2, HR provides a low voltage signal, PR and PG both output high voltage signals, M3 is turned on to write Vinit1 to the second node N2, M0 is turned on to connect N2 and N3. At this time, the potential of N1 is a smaller positive voltage, the potential of N2 and the potential of N3 are higher positive voltages, M0 is in a bias state, and all driving transistors included in the display panel are in a bias state, which can improve the hysteresis phenomenon.

[0369] In at least one embodiment of the present disclosure, the voltage value of Vinit1 may be a positive value. For example, the voltage value of Vinit1 may be greater than or equal to 4V and less than or equal to 7V.

[0370] The voltage value of Vinit2 and the voltage value of Vinit3 may be negative values. For example, the voltage value of Vinit2 and the voltage value of Vinit3 may be greater than or equal to -5V and less than or equal to -3V.

[0371] But it is not limited to this.

[0372] When at least one embodiment of the pixel circuit shown in FIG. 20 of the present disclosure is in operation, in the first initialization time period, the potential of N1, the potential of N2, and the potential of N3 are all set to the reference voltage, so that in the data writing time period, the data voltage of the previous frame display time will not affect the writing of the data voltage of the current frame.

[0373] At least one embodiment of the pixel circuit shown in FIG20 is configured to control CG to output a low voltage signal during at least a portion of a blank period between two display frames when data voltage refresh of the pixel circuit is not required. CG continuously outputs the low voltage signal during the next display frame to control M2 to be turned off, thereby preventing data voltage writing and maintaining the display image without refreshing the image.

[0374] When the data voltage of the pixel circuit needs to be refreshed, it is necessary to control CG to output a high voltage signal for at least part of the blank time period between the two frames of display time, and continue to output a high voltage signal in the next frame of display time to control M2 to turn on, so as to write the data voltage in the data writing time period to refresh the screen.

[0375] In the operation timing diagram shown in FIG21A , one frame display time may be a refresh frame.

[0376] As shown in FIG21B , when at least one embodiment of the pixel circuit shown in FIG20 of the present disclosure is in operation, the holding frame may include a holding initial time period TBC and a holding light emitting time period TBF that are set successively;

[0377] During the initial maintenance period TBC, HR outputs a low voltage signal, NG outputs a low voltage signal, PR and PG both output high voltage signals, E1 provides a high voltage signal, M1 is turned off to control the disconnection between N1 and N3, M6 and M7 are turned off, and M5 is turned off; M3 and M8 are turned on, I1 provides a first initial voltage Vinit1 to the second node N2, driving transistor M0 to be turned on to control the connection between N2 and N3, initialize the potential of the second node N2 and the potential of the third node N3, and improve the hysteresis phenomenon; I3 provides a third initial voltage Vinit3 to the third node N3, and initializes the potential of the anode of O1, controls O1 not to emit light, and clears the residual charge on the anode of O1;

[0378] During the luminous period TBF, E1 provides a low voltage signal, HR provides a high voltage signal, NG outputs a low voltage signal, PR and PG both output high voltage signals, M1, M2, M3, M4, M5 and M8 are all turned off, M6 and M7 are turned on, and M0 drives O1 to emit light.

[0379] The difference between at least one embodiment of the pixel circuit shown in FIG. 22 and at least one embodiment of the pixel circuit shown in FIG. 20 is that M2 is a p-type transistor.

[0380] At least one embodiment of the pixel circuit shown in FIG22 is configured to control CG to output a high voltage signal during at least a portion of a blank period between two display frames when data voltage refresh is not required. CG continuously outputs a low voltage signal during the next display frame to control M2 to be turned off, thereby preventing data voltage writing and maintaining the display image without refreshing the image.

[0381] When the data voltage of the pixel circuit needs to be refreshed, it is necessary to control CG to output a low voltage signal for at least part of the blank time period between the two frames of display time, and to continuously output a high voltage signal during the next frame of display time to control M2 to turn on, so as to write the data voltage during the data writing time period to refresh the screen.

[0382] The difference between at least one embodiment of the pixel circuit shown in FIG23 and at least one embodiment of the pixel circuit shown in FIG20 is that:

[0383] The gate of the first control transistor M1 is electrically connected to the first gate line NG, the source of the first control transistor M1 is electrically connected to the intermediate node NZ, and the drain of the first control transistor M1 is electrically connected to the third node N3;

[0384] A gate of the second control transistor M2 is electrically connected to the scan line CGL, a source of the second control transistor M2 is electrically connected to the first node N1, and a drain of the second control transistor M2 is electrically connected to the intermediate node NZ.

[0385] In at least one embodiment of the pixel circuit shown in FIG. 23 , both M1 and M2 are n-type transistors.

[0386] At least one embodiment of the pixel circuit shown in FIG23 is configured to control CG to output a low voltage signal during at least a portion of a blank period between two display frames when data voltage refresh is not required. CG continuously outputs the low voltage signal during the next display frame to control M2 to be turned off, thereby preventing data voltage writing and maintaining the display image without refreshing the image.

[0387] When the data voltage of the pixel circuit needs to be refreshed, it is necessary to control CG to output a high voltage signal for at least part of the blank time period between the two frames of display time, and continue to output a high voltage signal in the next frame of display time to control M2 to turn on, so as to write the data voltage in the data writing time period to refresh the screen.

[0388] The difference between at least one embodiment of the pixel circuit shown in FIG. 24 and at least one embodiment of the pixel circuit shown in FIG. 23 is that M2 is a p-type transistor.

[0389] At least one embodiment of the pixel circuit shown in FIG24 is configured to control CG to output a high voltage signal during at least a portion of a blank period between two display frames when data voltage refresh is not required. CG continuously outputs a low voltage signal during the next display frame to control M2 to be turned off, thereby preventing data voltage writing and maintaining the display image without refreshing the image.

[0390] When the data voltage of the pixel circuit needs to be refreshed, it is necessary to control CG to output a low voltage signal for at least part of the blank time period between the two frames of display time, and to continuously output a high voltage signal during the next frame of display time to control M2 to turn on, so as to write the data voltage during the data writing time period to refresh the screen.

[0391] The pixel driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the pixel driving method includes:

[0392] The light emitting driving circuit generates a driving current for driving the light emitting element under the control of the potential of the first node;

[0393] The control circuit controls the connection or disconnection between the first node and the first electrode of the light emitting element under the control of a first gate driving signal and a scan signal.

[0394] In at least one embodiment of the present disclosure, the pixel circuit includes a first initialization circuit, a first terminal of a light-emitting driving circuit is electrically connected to a second node, and a second terminal of the light-emitting driving circuit is electrically connected to a third node and a first electrode of a light-emitting element, respectively; a display cycle includes a first initialization time period and a second initialization time period set sequentially; and the pixel driving method includes:

[0395] During the first initialization period, the control circuit controls the first node and the third node to be connected under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; and the light emitting drive circuit controls the second node and the third node to be connected under the control of the potential of the first node;

[0396] During the second initialization time period, the control circuit controls the disconnection between the first node and the third node under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; and the light-emitting drive circuit controls the connection between the second node and the third node under the control of the potential of the first node.

[0397] The display panel according to at least one embodiment of the present disclosure includes a source driver and the above-mentioned driving circuit;

[0398] The source driver includes a data output terminal.

[0399] The display panel according to at least one embodiment of the present disclosure includes a plurality of columns of scan lines;

[0400] The scanning signal output terminal of the scanning signal generating circuit in the driving circuit is electrically connected to the scanning line.

[0401] In a specific implementation, the display panel may include a plurality of scan lines, and the scan signal output end is electrically connected to the scan lines to provide scan signals to the scan lines.

[0402] Optionally, the display panel includes a plurality of columns of data lines;

[0403] The data output terminal is directly electrically connected to the data line; or,

[0404] The driving circuit includes a second switch circuit. The second switch circuit controls the connection or disconnection between the data output terminal and the data line under the control of a second selection control signal.

[0405] In at least one embodiment of the present disclosure, the source driver is disposed on a first side of the display panel, and the driving circuit is disposed on the first side of the display panel; or,

[0406] The source driver is disposed on a first side of the display panel, and the driving circuit is disposed on a second side of the display panel. The first side and the second side are opposite sides.

[0407] For example, the first side may be a lower side, and the second side may be an upper side, but the present invention is not limited thereto.

[0408] As shown in FIG25 , the area labeled A0 is the display area of ​​the display panel;

[0409] The first column of data lines is labeled DL1, the first column of scan lines is labeled CG1, the second column of data lines is labeled DL2, the second column of scan lines is labeled CG2, the third column of data lines is labeled DL3, the third column of scan lines is labeled CG3, the fourth column of data lines is labeled DL4, the fourth column of scan lines is labeled CG4; the mth column of data lines is labeled DLm, the mth column of scan lines is labeled CGm; the mth column of data lines is labeled DLM, the mth column of scan lines is labeled CGM;

[0410] Both m and M are positive integers; SI is the source driver;

[0411] The first data output terminal of the source driver S1 is labeled S1, the second data output terminal of the source driver S1 is labeled S2, the third data output terminal of the source driver S1 is labeled S3, the fourth data output terminal of the source driver S1 is labeled S4, the mth data output terminal is labeled Sm, the Mth data output terminal is labeled SM, the first first selection control line is labeled SW11, and the second first selection control line is labeled SW21;

[0412] The source driver SI is electrically connected to SW11 and SW21, and is used to provide a first first gating control signal to SW11 and a second first gating control signal to SW21;

[0413] In FIG25 , the first gating unit is labeled X1, the second gating unit is labeled X2, the third gating unit is labeled X3, the fourth gating unit is labeled X4, the mth gating unit is labeled Xm, and the Mth gating unit is labeled XM;

[0414] Each gating unit includes a first switching circuit and a scan signal generating circuit; or each gating unit includes a first switching circuit, a second switching circuit and a scan signal generating circuit.

[0415] As shown in FIG25 , the first gating unit X1 is electrically connected to DL1 and CG1, the second gating unit X2 is electrically connected to DL2 and CG2, the third gating unit X3 is electrically connected to DL3 and CG3, and the fourth gating unit X4 is electrically connected to DL4 and CG4; the mth gating unit Xm is electrically connected to DL and CGm, and the Mth gating unit XM is electrically connected to DLM and CGM.

[0416] The source driver SI is disposed below A0, and the first gating unit X1, the second gating unit X2, the third gating unit X3, the fourth gating unit X4, the mth gating unit Xm and the Mth gating unit XM are disposed below A0.

[0417] The difference between at least one embodiment of the display panel shown in Figure 26 and at least one embodiment of the display panel shown in Figure 25 is that the first selection unit X1, the second selection unit X2, the third selection unit X3, the fourth selection unit X4, the mth selection unit Xm and the Mth selection unit XM are arranged above A0.

[0418] The difference between at least one embodiment of the display panel shown in FIG27 and at least one embodiment of the display panel shown in FIG26 is that:

[0419] The data output terminals of the source driver SI are concentrated in the middle of the display panel to achieve a narrow bottom bezel. At least one embodiment of the display panel shown in FIG27 incorporates a FIP (Fanout In Pixel) embodiment. The display panel described in at least one embodiment of the present disclosure may further include multiple rows and columns of the aforementioned pixel circuits.

[0420] In at least one embodiment of the display panel shown in FIG. 25 to at least one embodiment of the display panel shown in FIG. 27 , each gating unit may be the driving circuit described in at least one embodiment of the present disclosure.

[0421] In at least one embodiment of the present disclosure, two columns of pixel circuits may be electrically connected to the same column of scan lines.

[0422] The embodiments of the present disclosure provide a driving scheme for an OLED display. The local refresh pixel circuit cooperates with the source driver circuit and the driving scheme. The HCT control signal (the HCT control signal can be a data signal provided by the source driver through its data output terminal during the blank period) can be used to update a part of the screen, while the remaining screen does not need to be charged and discharged multiple times, thereby further reducing the power consumption of the OLED display, or achieving ultra-low power consumption by partially updating the display screen.

[0423] In at least one embodiment of the present disclosure, for a display device, when it is necessary to update part of the screen, such as only the date and time parts need to be updated. In the row direction, the gate drive circuit can be controlled to output: in the row where the screen needs to be updated, the first gate drive signal is normally output to control the first control transistor in the pixel circuit in the display area to be normally turned on for data update; in the row where the screen does not need to be updated, the potential of the first gate drive signal is always maintained to turn off the first control transistor to ensure that the pixel brightness remains unchanged, thereby achieving local refresh in the row direction. In the column direction, it can be achieved by controlling whether the column scan line turns on the second control transistor in the pixel circuit: in the blank period between the two frames of display time, the source driver outputs HCT pulse (pulse) to write different scan signals to the column scan line. If the current column needs to be updated, the column scan line needs to ensure that the second control transistor is always turned on, so that the current column can be refreshed normally; if some columns do not need to be updated, the column scan line needs to ensure that the second control transistor in the pixel circuit of these columns is always turned off.

[0424] The display panel described in at least one embodiment of the present disclosure further includes the aforementioned pixel circuit.

[0425] The display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

[0426] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit, comprising a first switching circuit and a scanning signal generating circuit; The first switch circuit is electrically connected to the first selection control line, the data output terminal of the source driver and the scan signal generation circuit, and is used to control the data signal provided by the data output terminal to be written into the scan signal generation circuit under the control of the first selection control signal provided by the first selection control line; The scanning signal generating circuit is used to generate a scanning signal according to the data signal, and output the scanning signal through a scanning signal output terminal.

2. The driving circuit according to claim 1, wherein: Also comprising a second switching circuit; The second switch circuit is electrically connected to a second gate control line, the data output terminal and a data line included in the display panel, respectively, and is used to control the connection or disconnection between the data output terminal and the data line under the control of a second gate control signal provided by the second gate control line; The first gate control line and the second gate control line are the same gate control line, or the first gate control line and the second gate control line are different.

3. The driving circuit according to claim 1, wherein: The first switch circuit includes a first transistor and a first capacitor; the first switch circuit provides the data signal to the scan signal generating circuit through a control node; The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the control node; A first end of the first capacitor is electrically connected to the control node, and a second end of the first capacitor is electrically connected to a DC voltage end.

4. The driving circuit according to claim 2, wherein: The second switch circuit includes a second transistor; A gate of the second transistor is electrically connected to the second selection control line, a first electrode of the second transistor is electrically connected to the data output terminal, and a second electrode of the second transistor is electrically connected to the data line.

5. The driving circuit according to claim 1, wherein: The scanning signal generating circuit comprises an output control circuit and an output circuit; the first switch circuit provides the data signal to the scanning signal generating circuit through a control node; The output control circuit is electrically connected to the control node, the first voltage terminal, the second voltage terminal, the output control terminal and the scan output terminal respectively, and is used to control the connection or disconnection between the output control terminal and the first voltage terminal under the control of the potential of the control node, and control the connection or disconnection between the output control terminal and the second voltage terminal under the control of the signal provided by the scan output terminal; The output circuit is electrically connected to the control end, the scan output end, the output control end, the first voltage end and the second voltage end, respectively, and is used to control the connection or disconnection between the scan output end and the first voltage end under the control of the control signal provided by the control end, and to control the connection or disconnection between the scan output end and the second voltage end under the control of the potential of the output control end.

6. The driving circuit according to claim 5, wherein: The scan output terminal is the scan signal output terminal; or, The scanning signal generating circuit also includes an inverting circuit; the input end of the inverting circuit is electrically connected to the scanning output end, and the output end of the inverting circuit is electrically connected to the scanning signal output end. The inverting circuit is used to invert the voltage signal connected to its input end to obtain an inverted voltage signal, and output the inverted voltage signal through the output end of the inverting circuit.

7. The driving circuit according to claim 5, wherein: The output control circuit includes a third transistor and a fourth transistor; The gate of the third transistor is electrically connected to the control node, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the output control terminal; The gate of the fourth transistor is electrically connected to the scan output terminal, the first electrode of the fourth transistor is electrically connected to the output control terminal, and the second electrode of the fourth transistor is electrically connected to the second voltage terminal; The output circuit includes a fifth transistor, a sixth transistor and a second capacitor; The gate of the fifth transistor is electrically connected to the control terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the scan output terminal; The gate of the sixth transistor is electrically connected to the output control terminal, the first electrode of the sixth transistor is electrically connected to the scan output terminal, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal; The first end of the second capacitor is electrically connected to the control end, and the second end of the second capacitor is electrically connected to the second voltage end.

8. A driving method, applied to the driving circuit according to any one of claims 1 to 7, wherein: The driving method comprises: during at least a portion of a blank period between two display frames, The first switch circuit controls, under the control of the first selection control signal, to write the data signal provided by the data output terminal of the source driver into the scanning signal generating circuit; The scanning signal generating circuit generates a scanning signal according to the data signal, and outputs the scanning signal to a corresponding column scanning line of the display panel through a scanning signal output terminal.

9. The driving method according to claim 8, wherein: The driving circuit further includes a second switch circuit; and the driving method further includes: During a data writing period in a frame of display time, the second switch circuit controls the data output terminal of the source driver to be connected to the corresponding column data line of the display panel under the control of the second selection control signal.

10. A pixel circuit comprising a light emitting element, a light emitting driving circuit and a control circuit; The light-emitting driving circuit is electrically connected to the first node and the first electrode of the light-emitting element respectively, and is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node; the second electrode of the light-emitting element is electrically connected to the third voltage terminal; The control circuit is electrically connected to the first gate line, the scan line, the first node and the first pole of the light-emitting element, respectively, and is used to control the connection or disconnection between the first node and the first pole of the light-emitting element under the control of the first gate drive signal provided by the first gate line and the scan signal provided by the scan line.

11. The pixel circuit according to claim 10, wherein: The control circuit includes a first control circuit and a second control circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively; The first control circuit is electrically connected to the first gate line, the first node and the intermediate node respectively, and the first control circuit is used to control the connection or disconnection between the first node and the intermediate node under the control of the first gate driving signal provided by the first gate line; The second control circuit is electrically connected to the scan line, the intermediate node and the third node respectively, and is used to control the connection or disconnection between the intermediate node and the third node under the control of the scan signal provided by the scan line.

12. The pixel circuit according to claim 10, wherein: The control circuit includes a first control circuit and a second control circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively; The first control circuit is electrically connected to the first gate line, the third node and the intermediate node respectively, and is used to control the connection or disconnection between the third node and the intermediate node under the control of the first gate driving signal provided by the first gate line; The second control circuit is electrically connected to the scan line, the intermediate node and the first node respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of the scan signal provided by the scan line.

13. The pixel circuit according to claim 10, wherein: It also includes a first initialization circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively; The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the second node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second node under the control of the first initial control signal provided by the first initial control terminal.

14. The pixel circuit according to claim 10, wherein: It also includes a second initialization circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively; The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the third node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the third node under the control of the second initial control signal provided by the second initial control terminal.

15. The pixel circuit according to claim 10, wherein: It also includes a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit and an energy storage circuit; the first end of the light-emitting drive circuit is electrically connected to the second node, and the second end of the light-emitting drive circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively; The data writing circuit is electrically connected to the second gate line, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second gate driving signal provided by the second gate line; The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control line; The second light emitting control circuit is electrically connected to the light emitting control line, the third node and the first electrode of the light emitting element respectively, and is used to control the third node to be electrically connected to the first electrode of the light emitting element under the control of the light emitting control signal; The energy storage circuit is electrically connected to the first node and is used for storing electric energy.

16. The pixel circuit according to claim 15, wherein: Also comprising a third initialization circuit; The third initialization circuit is electrically connected to the first initial control terminal, the third initial voltage terminal and the first pole of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first pole of the light-emitting element under the control of the first initial control signal provided by the first initial control terminal.

17. The pixel circuit according to claim 11, wherein: The first control circuit includes a first control transistor, and the second control circuit includes a second control transistor; The gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the first node, and the second electrode of the first control transistor is electrically connected to the intermediate node; A gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the intermediate node, and a second electrode of the second control transistor is electrically connected to the third node.

18. The pixel circuit according to claim 12, wherein: The first control circuit includes a first control transistor, and the second control circuit includes a second control transistor; The gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the intermediate node, and the second electrode of the first control transistor is electrically connected to the third node; A gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the first node, and a second electrode of the second control transistor is electrically connected to the intermediate node.

19. The pixel circuit according to claim 13, wherein: The first initialization circuit includes a first initialization transistor; A gate of the first initialization transistor is electrically connected to the first initial control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the second node.

20. The pixel circuit according to claim 14, wherein: The second initialization circuit includes a second initialization transistor; A gate of the second initialization transistor is electrically connected to the second initial control terminal, a first electrode of the second initialization transistor is electrically connected to the second initial voltage terminal, and a second electrode of the second initialization transistor is electrically connected to the third node.

21. The pixel circuit according to claim 15, wherein: The data writing circuit includes a writing transistor, the first light emitting control circuit includes a first light emitting control transistor, and the second light emitting control circuit includes a second light emitting control transistor; the light emitting driving circuit includes a driving transistor, and the energy storage circuit includes a storage capacitor; The gate of the write transistor is electrically connected to the second gate line, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the second node; The gate of the first light emission control transistor is electrically connected to the light emission control line, the first electrode of the first light emission control transistor is electrically connected to the power supply voltage terminal, and the second electrode of the first light emission control transistor is electrically connected to the second node; The gate of the second light emission control transistor is electrically connected to the light emission control line, the first electrode of the second light emission control transistor is electrically connected to the third node, and the second electrode of the second light emission control transistor is electrically connected to the first electrode of the light emitting element; The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node; The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to a power supply voltage terminal.

22. The pixel circuit according to claim 16, wherein: The third initialization circuit includes a third initialization transistor; The gate of the third initialization transistor is electrically connected to the first initial control terminal, the first electrode of the third initialization transistor is electrically connected to the third initial voltage terminal, and the second electrode of the third initialization transistor is electrically connected to the first electrode of the light emitting element.

23. A pixel driving method, applied to the pixel circuit according to any one of claims 10 to 22, the pixel driving method comprising: The light-emitting driving circuit generates a driving current for driving the light-emitting element under the control of the potential of the first node; The control circuit controls the connection or disconnection between the first node and the first electrode of the light emitting element under the control of the first gate driving signal and the scanning signal.

24. The pixel driving method according to claim 23, wherein: The pixel circuit includes a first initialization circuit, a first end of the light-emitting driving circuit is electrically connected to a second node, and a second end of the light-emitting driving circuit is electrically connected to a third node and a first electrode of a light-emitting element, respectively; a display cycle includes a first initialization time period and a second initialization time period which are set successively; and the pixel driving method includes: In the first initialization time period, the control circuit controls the first node to be connected to the third node under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; the light emitting drive circuit controls the second node to be connected to the third node under the control of the potential of the first node; During the second initialization time period, the control circuit controls the first node and the third node to be disconnected under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; and the light-emitting drive circuit controls the second node and the third node to be connected under the control of the potential of the first node.

25. A display panel comprising a source driver and a driving circuit according to any one of claims 1 to 7; The source driver includes a data output terminal.

26. The display panel according to claim 25, wherein: including multiple columns of scan lines; A scan signal output terminal in a scan signal generating circuit in the driving circuit is electrically connected to the scan line.

27. The display panel according to claim 25, wherein: The display panel includes a plurality of columns of data lines; The data output terminal is directly electrically connected to the data line; or the driving circuit includes a second switch circuit, and the second switch circuit controls the connection or disconnection between the data output terminal and the data line under the control of a second selection control signal.

28. The display panel according to any one of claims 25 to 27, wherein: The source driver is disposed on a first side of the display panel, and the driving circuit is disposed on the first side of the display panel; or, The source driver is disposed on a first side of the display panel, and the driving circuit is disposed on a second side of the display panel. The first side and the second side are opposite sides.

29. The display panel according to any one of claims 25 to 27, wherein: Also comprises the pixel circuit as claimed in any one of claims 10 to 22.

30. A display device comprising the display panel according to any one of claims 25 to 29.

Images