Crystal laminate structure and semiconductor element

Abstract

The present invention aims to provide a crystal laminate structure. Schottky contact can be formed between the laminate structure and metal. On this basis, an SnO2 semiconductor element is manufactured, such that the development of an SnO2 material in the field of semiconductor elements can be promoted. The laminate structure comprises a base substrate and an SnO2 semiconductor layer which is directly arranged on or indirectly arranged on the base substrate by means of another layer; an SnO2 semiconductor thin film has a tetragonal rutile structure; and the SnO2 semiconductor layer uses, as a main plane, a (002) plane or a plane inclined at an angle not more than 6° with respect to the (002) plane.

Description

Crystal stacked structure and semiconductor device Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a crystal stacked structure and a semiconductor element. Background Art

[0002] The third-generation semiconductor materials have characteristics such as large bandgap width and high critical breakdown field strength, which make them suitable for the preparation of high-quality power devices. Materials such as SiC, GaN, Ga2O3, SnO2, etc. The power devices prepared still have excellent performance in high electric field, high power, strong radiation and other environments.

[0003] Currently, the main third-generation semiconductor materials commercialized in large quantities are SiC and GaN. SiC has a bandgap of approximately 3.26 eV, a breakdown field strength of approximately 3 MV / cm, and a Baliga quality factor of approximately 340; GaN has a bandgap of approximately 3.44 eV, a breakdown field strength of approximately 5 MV / cm, and a Baliga quality factor of approximately 870. In comparison, SnO2 has a bandgap of approximately 3.6 eV, a breakdown field strength of approximately 4.3 MV / cm, and a Baliga quality factor of approximately 626. These properties of SnO2 make it highly suitable for power devices such as diodes, MOS transistors, and IGBTs.

[0004] Compared with Si material (bandgap width of about 1.1eV, breakdown field strength of about 0.3MV / cm), the breakdown field strength of SnO2 material is about 14 times that of Si, and the Baliga quality factor is about 626 times that of Si. Therefore, when SnO2 material is used to make power devices, the thickness of the semiconductor film required to achieve the same voltage resistance effect is thinner, the device response rate is therefore faster, and the device conduction loss is therefore lower.

[0005] SiC is mainly prepared by the physical vapor transport (PVT) method, and the preparation temperature of SiC single crystals is in the range of 2100~2400℃. However, there are more than 200 isomers of SiC, and defects are prone to occur during the single crystal preparation process, affecting the quality of the single crystal. SnO2 can also be prepared by the physical vapor transport (PVT) method. The preparation temperature of SnO2 single crystals is in the range of 1650~1750℃. In addition, under high temperature and slightly negative pressure environment, there is only one isomer, namely SnO2 with tetragonal rutile structure, and there will be no crystal defects caused by isomer problems. Based on the above comparison, compared with SiC, the single crystal preparation cost of SnO2 is relatively lower and the defects are relatively smaller.

[0006] Previously, SnO2 materials were known to be used as transparent electrodes due to their excellent electrical conductivity. However, due to the large number of defects in the (200) surface of SnO2, it is difficult to form a good Schottky contact with metals, thus affecting the manufacturing and performance improvement of semiconductor devices. In order to use SnO2-based semiconductor thin films to form semiconductor devices, it is necessary to control the defects of SnO2-based semiconductor films. Summary of the Invention

[0007] In view of this, an object of the present invention is to provide a crystal stacked structure and a semiconductor element to solve the problem that the existing SnO2-based semiconductor film is difficult to form Schottky contact with metal.

[0008] In order to solve the above problems, the present invention provides the following technical solutions:

[0009] A first aspect of the present invention provides a crystalline stacked structure comprising:

[0010] A base substrate; and a SnO2-based semiconductor layer disposed on the base substrate directly or indirectly through other film layers, wherein the SnO2-based semiconductor layer has a tetragonal rutile structure, and the SnO2-based semiconductor layer has a (002) plane or a plane inclined at an angle within 6° relative to the (002) plane as a main surface.

[0011] Preferably, the surface roughness of the SnO2-based semiconductor layer is Ra≤0.1 um.

[0012] Preferably, the average dislocation density of the SnO2-based semiconductor layer is ≤1 x 10 5 / cm 2 .

[0013] Preferably, the thickness of the SnO2-based semiconductor layer is in the range of 0.5um to 50um.

[0014] Preferably, the bottom substrate is an m-plane sapphire substrate.

[0015] Preferably, the underlying substrate is a SnO2-based single crystal substrate having a (002) plane or a plane inclined within an angle range of 6° relative to the (002) plane as a main plane.

[0016] To achieve the above object, the present invention provides the following technical solutions:

[0017] A second aspect of the present invention provides a semiconductor element including the above-mentioned crystal stacked structure.

[0018] Preferably, the semiconductor element is a power device.

[0019] Preferably, the power device is a diode, a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT).

[0020] To achieve the above object, the present invention provides the following technical solutions:

[0021] A second aspect of the present invention provides a semiconductor element including the above-mentioned crystal stacked structure.

[0022] Preferably, the semiconductor element is a power device.

[0023] Preferably, the power device is a diode, a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT).

[0024] Preferably, the diode is a Schottky diode having an anode electrode and a cathode electrode, and the anode electrode is Ti, Mo, W, Ni, Au or Pt.

[0025] The beneficial effects of the present invention are as follows:

[0026] The crystal stacked structure of the present invention comprises an underlying substrate, and a SnO2-based semiconductor layer having a tetragonal rutile structure and having a (002) plane or a plane inclined at an angle within a range of 6° relative to the (002) plane as a main surface, which is directly or indirectly provided on the underlying substrate through other film layers. The SnO2-based semiconductor layer has few defects and a smooth surface, and can form a good Schottky contact with metal.

[0027] Furthermore, based on the fact that the SnO2-based semiconductor layer can form a good Schottky contact with metal, we can manufacture SnO2-based semiconductor components based on this and promote the use of SnO2 materials in the field of semiconductor components. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1a is a cross-sectional view of a SnO2-based semiconductor layer grown on an m-plane sapphire substrate according to one embodiment of the present invention;

[0029] FIG1b is a cross-sectional view of an m-plane sapphire substrate according to an embodiment of the present invention, wherein a SnO2-based semiconductor layer is indirectly grown by growing a buffer layer;

[0030] FIG2 is a perspective view of the crystal structure of a SnO2-based semiconductor layer grown on an m-plane sapphire substrate according to an embodiment of the present invention;

[0031] FIG3 is a SEM observation image of a SnO2-based first semiconductor layer and a SnO2-based second semiconductor layer with a (002) plane orientation grown on an m-plane sapphire substrate provided by one embodiment of the present invention;

[0032] FIG4 is a full XRD spectrum of a (002)-oriented SnO2-based first semiconductor layer and a SnO2-based second semiconductor layer grown on an m-plane sapphire substrate provided by one embodiment of the present invention;

[0033] 5 is a cross-sectional view of a SnO2-based semiconductor layer grown on a SnO2-based single crystal substrate according to one embodiment of the present invention;

[0034] FIG6 is a cross-sectional view of a pseudo-vertical SnO2 Schottky diode provided by one embodiment of the present invention;

[0035] FIG7 is a schematic diagram of a method for preparing a pseudo-vertical SnO2 Schottky diode provided by one embodiment of the present invention;

[0036] FIG8 is a current-voltage characteristic curve of a pseudo-vertical SnO2 Schottky diode provided by one embodiment of the present invention;

[0037] FIG9 a is a cross-sectional view of a vertical SnO 2 Schottky diode provided by one embodiment of the present invention;

[0038] FIG9 b is a cross-sectional view of a SnO 2 Schottky diode with a vertical field plate structure provided by one embodiment of the present invention;

[0039] FIG9 c is a cross-sectional view of a SnO 2 Schottky diode with a vertical field limiting ring structure provided by one embodiment of the present invention;

[0040] FIG10 is a cross-sectional view of a SnO2 Schottky MOSFET provided by one embodiment of the present invention;

[0041] FIG11 is a cross-sectional view of a SnO2 IGBT provided by one embodiment of the present invention;

[0042] The reference numerals are as follows:

[0043] 1. M-plane sapphire (bottom substrate)

[0044] 2. The first semiconductor layer (bottom substrate or n + -SnO2 semiconductor layer)

[0045] 3. The second semiconductor layer (n - -SnO2 semiconductor layer)

[0046] 4. Cathode electrode

[0047] 5. Anode electrode

[0048] 6. Buffer layer

[0049] 13. Dielectric layer

[0050] 14. p-type SnO2

[0051] 21. Source Part 1

[0052] 22. Source Part 2

[0053] 23. Drain

[0054] 24. Gate insulating film

[0055] 25. Gate

[0056] 31. The third semiconductor layer (p - type SnO2 semiconductor layer)

[0057] 32. The fourth semiconductor layer (n ＋ type SnO2 semiconductor layer)

[0058] 33. The fifth semiconductor layer (p ＋ type SnO2 semiconductor layer)

[0059] 36. Source DETAILED DESCRIPTION

[0060] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0061] The crystalline stacked structure of the present invention comprises an underlying substrate and a SnO2-based semiconductor layer disposed on the underlying substrate directly or indirectly via a film layer (e.g., a buffer layer), wherein the SnO2-based semiconductor layer has a tetragonal rutile structure, and the SnO2-based semiconductor layer has a (002) plane or a plane inclined at an angle within a range of 6° relative to the (002) plane as a primary surface. The surface roughness Ra of the SnO2-based semiconductor layer is not particularly limited as long as it is 0.1 μm or less. In the present invention, it is preferably 30 nm or less, and more preferably 10 nm or less.

[0062] The crystalline stacked structure comprises one or more crystalline layers and may also contain layers other than crystalline layers. The crystalline layers are preferably single crystalline layers, but may also be polycrystalline layers. The SnO2-based semiconductor layer may be annealed after film formation. The annealing process forms a good Schottky contact between the SnO2-based semiconductor layer and the Schottky electrode. The Schottky electrode is made of Ti, Mo, W, Ni, Au, or Pt.

[0063] The underlying substrate may be an m-plane sapphire having a corundum structure, or a SnO2-based single crystal having a (002) plane or a plane inclined within an angle range of 6° relative to the (002) plane as a primary plane, with a SnO2-based semiconductor layer disposed directly or indirectly via a film layer on the underlying substrate to form a stacked structure. The underlying substrate may be an n-type SnO2-based semiconductor layer or a p-type SnO2-based semiconductor layer, preferably an n-type SnO2-based semiconductor layer, and may be composed of an oxide having Sn as a primary component and added with one or more selected from Nb, In, Sb, Mg, Zn, and the like.

[0064] As for the crystalline thin film, the crystalline thin film is a SnO2-based single crystal thin film having a (002) plane or a plane inclined at an angle within a range of 6° relative to the (002) plane as a main plane, and the surface roughness Ra of the SnO2-based semiconductor layer is ≤ 0.1 μm. The surface roughness (Ra) is not particularly limited if it is 0.1 μm or less. In the present invention, it is preferably 30 nm or less, and more preferably 10 nm or less. The average dislocation density of the SnO2-based semiconductor layer is ≤ 1 x 10 5 / cm 2 The thickness of the SnO2-based semiconductor layer is in the range of 0.5um to 50um, and in the present invention is preferably less than 30um, and more preferably less than 20um.

[0065] First embodiment

[0066] The first embodiment of the present invention provides a specific stacked structure. FIG1a is a cross-sectional view of the crystalline stacked structure of the present invention. The embodiment of the crystalline stacked structure provided by the present invention includes:

[0067] The bottom substrate 1 includes an m-plane ( ) sapphire with corundum structure;

[0068] The first semiconductor layer 2 is n + -SnO2 semiconductor layer, formed on the underlying substrate 1, is a SnO2 single crystal having a (002) plane or a plane inclined at an angle within 6° relative to the (002) plane as a main plane;

[0069] The second semiconductor layer 3 is n - -SnO2 semiconductor layer, formed on the n + The SnO2 semiconductor layer 2 is a SnO2-based single crystal having a (002) plane or a plane tilted within an angle range of 6° relative to the (002) plane as a main plane.

[0070] In other embodiments, the SnO2-based semiconductor layer can be indirectly disposed on the underlying substrate 1 through a film layer 6 (which is a buffer layer 6), as shown in FIG1b . The crystal stacked structure shown in FIG1b grows the first semiconductor layer 2 by growing the buffer layer 6, which can reduce the stress between the underlying substrate 1 and the first semiconductor layer 2 and reduce the formation of defects.

[0071] As shown in Figure 2, the orientation axis of the crystal structure of rutile SnO2 is from the a-axis <100> , b-axis <010> , c-axis <001> The first semiconductor layer 2 and the second semiconductor layer 3 are plate-shaped with crystal plane indices defined by these three axes, namely, the (101) plane, the (001) plane, and the (010) plane, and the lattice constants are a = 4.738 Å, b = 4.738 Å, and c = 3.187 Å. One or more selected elements (such as Nb, In, Sb, Mg, and Zn) are doped to form an oxide crystal with Sn as the main component. The lattice constant, band gap, and conductivity type of the doped SnO2 crystal may change.

[0072] This embodiment uses the m-plane ( ) sapphire as the underlying substrate.

[0073] The first semiconductor layer 2 and the second semiconductor layer 3 may be prepared by physical vapor transport, spray thermal decomposition, chemical vapor deposition, magnetron sputtering, pulsed laser deposition, and the like.

[0074] In this embodiment, the radio frequency magnetron sputtering method is used to prepare the first semiconductor layer 2. The preparation process is as follows:

[0075] First, the target material is prepared by uniformly mixing the required doping elements (such as Sb), Sb2O5 with SnO2 in a certain stoichiometric ratio, sintering them at a certain temperature, and finally preparing an n-type SnO2 target material with a certain doping concentration.

[0076] Then, the m-plane sapphire substrate was ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for 15 minutes in sequence, and then blown dry with high-purity nitrogen to obtain a clean substrate and placed in the vacuum chamber of the magnetron sputtering system. The element-doped n-type SnO2 ceramic target material was placed in the RF sputtering target position, the working gas pressure was stabilized at 1 Pa, the working temperature was stabilized at 500 °C, and a suitable deposition time was used.

[0077] Finally, after the specified time has passed, the substrate is taken out and annealed at a certain time and temperature. After the SnO2 crystal is exposed with (002) as the main surface, the first semiconductor layer 2 is prepared.

[0078] The first semiconductor layer 2 is prepared by the above-mentioned RF magnetron sputtering method, and the second semiconductor layer 3 is epitaxially grown on the first semiconductor layer 2. Similarly, the second semiconductor layer 3 is prepared by the RF magnetron sputtering method. The concentration of the second semiconductor layer 3 is different from that of the first semiconductor layer 2. The required doping target material needs to be prepared. The operation steps are the same as those for the above-mentioned first layer of semiconductor, and the thickness of the semiconductor layer can be controlled by controlling the sputtering time.

[0079] FIG3 is a SEM observation image of the first semiconductor layer 2 and the second semiconductor layer 3 grown on the m-plane sapphire provided by the first embodiment of the present invention.

[0080] FIG4 is a full XRD spectrum of the first semiconductor layer 2 and the second semiconductor layer 3 grown on the m-plane sapphire provided by the first embodiment of the present invention. Both spectra contain the m-plane sapphire ( ) crystal plane diffraction peak and the (002) crystal plane diffraction peak of SnO2, and there are no other crystal plane diffraction peaks in the spectrum, indicating that the (002) plane oriented SnO2 epitaxial crystal was successfully prepared on the m-plane sapphire by radio frequency magnetron sputtering.

[0081] Second embodiment

[0082] The second embodiment of the present invention provides a specific stacked structure. FIG5 is a cross-sectional view of the crystalline stacked structure of the present invention. The embodiment of the crystalline stacked structure provided by the present invention includes:

[0083] The bottom substrate 2 is the first semiconductor layer, which is n + -SnO2 semiconductor layer, the underlying substrate 2 is a SnO2 single crystal substrate with a (002) plane or a plane inclined at an angle within 6° relative to the (002) plane as the main surface; the second semiconductor layer 3 is formed on the underlying substrate 2, and is n - The SnO2 semiconductor layer is a SnO2-based semiconductor layer having a (002) plane or a plane inclined at an angle within 6° relative to the (002) plane as a main plane.

[0084] The preparation methods of the bottom substrate 2 in the second embodiment include physical vapor transport (PVT), chemical vapor deposition, and the like.

[0085] This embodiment uses the PVT method to prepare the bottom substrate 2, and a growth process is provided as follows:

[0086] (1) Vacuuming: Use a mechanical pump to pump the air pressure in the furnace cavity to below 10Pa;

[0087] (2) Remove impurity gases: slowly raise the temperature to a certain temperature, keep the pump running, and keep the gas pressure in the furnace cavity below 10Pa. The main purpose of this step is to remove the impurity gases adsorbed by the tin oxide powder source;

[0088] (3) Rapid heating - pressure reduction and constant temperature: During the rapid heating process, high-purity CO2 gas is filled into the furnace cavity, and the temperature is kept constant when it reaches 1650℃~1750℃. During the heating process, the gas pressure needs to be reduced to control the gas pressure within a certain range.

[0089] (4) Crystal growth: The growth environment of SnO2 crystal is constant temperature and pressure, and the temperature gradient difference between the bottom of the crucible and the seed crystal is maintained between 100K and 200K. During the growth of SnO2 crystal, the height of the seed crystal rod can be slowly and dynamically adjusted to keep the temperature gradient stable. The reactions involved in this process are as follows:

[0090] SnO2(s) = SnO(g) + 0.5O2(g)

[0091] SnO (g) + CO2 (g) = SnO2 (single crystal) + CO (g)

[0092] SnO (g) + 0.5O2 (g) = SnO2 (single crystal)

[0093] (5) Stopping Growth: When a growth process is completed, heating is stopped, ending the growth of the SnO2 single crystal. The single crystal obtained above is cut into a SnO2 crystal block with the (002) plane as the main surface. The SnO2 crystal is then cleaned to remove organic and inorganic matter on the surface, leaving it in a state where epitaxial growth of Sn-containing oxide is possible.

[0094] The second semiconductor layer 3 may be prepared by MOCVD, sol-gel, spray pyrolysis, chemical vapor deposition, molecular beam epitaxy, magnetron sputtering, pulsed laser deposition, ion beam plating, and the like.

[0095] In this embodiment, when the second semiconductor layer 3 is prepared by magnetron sputtering, the growth method is the same as that described in the first embodiment.

[0096] When the MOCVD method is used to prepare the second semiconductor layer 3, a preparation process is provided as follows:

[0097] (1) The reaction chamber of the MOCVD equipment is evacuated to a vacuum state, and the first semiconductor layer is placed in the reaction chamber and heated to the desired growth temperature;

[0098] (2) Turn on the nitrogen gas and purge the chamber with a large flow rate, then turn on the oxygen gas and keep it for a period of time, and finally introduce the organic metal Sn source. By adjusting the nitrogen gas flow rate, reaction temperature, pressure in the reaction chamber and growth time, the second semiconductor layer is grown;

[0099] After the crystal grows to the required thickness, the growth is stopped, and samples are taken after cooling to room temperature to complete the growth of the second semiconductor layer.

[0100] Third embodiment

[0101] A third embodiment of the present invention provides a semiconductor device including a specific implementation of any one of the crystal stacked structures according to the first embodiment.

[0102] Furthermore, the semiconductor component is a Schottky diode, and the Schottky diode further includes:

[0103] a Schottky electrode, located on the upper surface of the second semiconductor layer 3;

[0104] The ohmic electrodes are located on the upper surface of the first semiconductor layer 2 and on both sides of the second semiconductor layer 3 and are separated from the second semiconductor layer 3 .

[0105] FIG6 is a cross-sectional view of a Schottky barrier diode according to a third embodiment of the present invention. The Schottky barrier diode is a pseudo-vertical Schottky diode, comprising:

[0106] Bottom substrate 1, m-plane ( ) sapphires;

[0107] A first semiconductor layer 2 is located on the upper surface of the bottom substrate 1;

[0108] The second semiconductor layer 3 is located on the upper surface of the first semiconductor layer 2;

[0109] The cathode electrode 4 is located on the upper surface of the first semiconductor layer 2 , and forms an ohmic contact with the upper surface of the first semiconductor layer 2 .

[0110] The anode electrode 5 is located on the upper surface of the second semiconductor layer 3 , and forms a Schottky contact with the upper surface of the second semiconductor layer 3 .

[0111] This embodiment also provides a method for preparing a SnO2 Schottky diode. FIG7 is a schematic diagram of a Schottky diode manufacturing process. The method includes the following steps:

[0112] S1. Select m-plane sapphire as the substrate and clean it using the standard cleaning process;

[0113] S2, depositing a first semiconductor layer 2 on the sapphire substrate using a magnetron sputtering process;

[0114] S3, depositing a second semiconductor layer 3 on the first semiconductor layer 2 using a magnetron sputtering process;

[0115] S4, using a photolithography process to prepare a photoresist mask layer of a preset shape on the second semiconductor layer 3;

[0116] S5. Etching the photoresist mask layer using a dry etching process to transfer the pattern to the second semiconductor layer 3, exposing the first semiconductor layer 2, and completing the production of the mesa of the second semiconductor layer 3;

[0117] S6 and S7, preparing a photolithography mask layer in a preset area of ​​the first semiconductor layer 2 and depositing an ohmic contact metal layer using a photolithography process and a metal plating technology;

[0118] S8 and S9, preparing a photolithography mask layer in the mesa region of the second semiconductor layer 3 and depositing a Schottky contact metal layer using a photolithography process and a metal coating technique;

[0119] In this embodiment, carriers flow from the anode vertically through the second semiconductor layer 3 and then horizontally through the first semiconductor layer 2 to the cathode, forming a pseudo-vertical SnO2 Schottky diode with excellent performance and reliability.

[0120] Furthermore, the ohmic contact electrode used in this experiment is indium.

[0121] Furthermore, the Schottky electrode can be made of high work function metals such as tungsten, nickel, molybdenum, gold, platinum, and titanium. The anode metal used in this experiment is tungsten.

[0122] FIG8 is an IV characteristic curve of a pseudo-vertical SnO2 Schottky diode provided by an embodiment of the present invention. As can be seen from the figure, the Schottky diode prepared by the stacked structure has an IV curve showing good Schottky contact characteristics.

[0123] Fourth embodiment

[0124] Furthermore, the semiconductor device is a vertical structure Schottky diode. Figure 9a is a cross-sectional view of a Schottky diode. The Schottky diode has a stacked first semiconductor layer 2 and a second semiconductor layer 3. The anode electrode 5 is located on the upper surface of the second semiconductor layer 3 and forms a Schottky contact therewith. The cathode electrode 4 is located on the lower surface of the first semiconductor layer 2 and forms an ohmic contact therewith.

[0125] In the Schottky barrier diode, by applying a forward voltage between the anode electrode 5 and the cathode electrode 4 (positive potential on the anode electrode 5 side), the interface barrier between the anode electrode 5 and the second semiconductor layer 3 is lowered, and current flows from the anode electrode 5 to the cathode electrode 4 .

[0126] A fourth embodiment of the present invention provides a semiconductor device including a specific implementation of the crystal stacked structure according to the second embodiment.

[0127] In the Schottky barrier diode, by applying a reverse voltage between the anode electrode 5 and the cathode electrode 4 (negative potential on the anode electrode 5 side), a depletion layer expands from the interface between the anode electrode 5 and the second semiconductor layer 3 , thereby achieving a withstand voltage.

[0128] In reverse bias, the spatial electric field distribution is not uniform, and the electric field is denser near the Schottky junction, causing avalanche breakdown to occur earlier, thereby improving its withstand voltage characteristics.

[0129] Figure 9b is a Schottky diode with a field plate structure. Compared with the Schottky diode shown in Figure 9a, the second semiconductor layer 3 not only forms a Schottky contact with the anode electrode 5 but also covers the dielectric layer 13. Part of the anode electrode extends above the dielectric layer 13 to form a field plate. The field plate structure can reduce the electric field strength at the contact edge of the anode electrode 5 and the second semiconductor layer 3, thereby improving the withstand voltage of the device.

[0130] Figure 9c is a Schottky diode with a field-limiting ring structure. Compared with the Schottky diode shown in Figure 9a, multiple p-type SnO2 regions 14 are formed in the second semiconductor layer 3 by ion implantation. The p-type SnO2 regions 14 form a pn junction with the second semiconductor layer 3. During the application of reverse withstand voltage, a depletion region can be quickly formed, thereby improving the withstand voltage of the device.

[0131] Fifth embodiment

[0132] A fifth embodiment of the present invention provides a semiconductor device including a specific implementation of the crystal stacked structure in the second embodiment.

[0133] Furthermore, the semiconductor device is a vertical structure Schottky junction MOSFET. Figure 10 is a cross-sectional view of a Schottky junction MOSFET. The Schottky junction MOSFET has a stacked first semiconductor layer 2 and a second semiconductor layer 3. The source electrode is located on the upper surface of the second semiconductor layer 3. The source electrode is divided into a first source part 21 and a second source part 22. The first source part 21 extends into the interior of the second semiconductor layer 3. There is a Schottky barrier between the first source part 21 and the second semiconductor layer 3. The second source part 22 forms an ohmic contact with the second semiconductor layer 3. The second source part 22 is closer to the gate insulating film 24 than the first source part 21. The gate 25 is wrapped by the gate insulating film 24 and is located in the groove of the second semiconductor layer 3.

[0134] In the Schottky junction MOSFET, by applying a forward voltage between the drain 23 and the source electrode (the drain 23 side is a positive potential), when a positive voltage is applied to the gate 25, the Schottky junction MOSFET is forward-conducted, and the conduction current flows out from the second part 22 of the source. When no voltage is applied to the gate 25, the depletion layer formed by the Schottky contact between the first part 21 of the source and the second semiconductor layer 3 cuts off the current between the drain 23 and the second part of the source 22. The depletion layer formed by the Schottky contact expands in the second semiconductor 3, and the voltage is mainly borne by the second semiconductor layer 3.

[0135] Sixth embodiment

[0136] A sixth embodiment of the present invention provides a semiconductor device including a specific implementation of the crystal stacked structure in the second embodiment.

[0137] Furthermore, the semiconductor device is a vertical structure IGBT. As shown in FIG11 , which is a cross-sectional view of the IGBT, the IGBT has a stacked structure of a first semiconductor layer 2, a second semiconductor layer 3, a third semiconductor layer 31, a fourth semiconductor layer 32, and a fifth semiconductor layer 33. The third semiconductor layer 31 is p - type SnO2 semiconductor layer, the fourth semiconductor layer 32 is n + type SnO2 semiconductor layer, the fifth semiconductor layer 33 is p ＋ type SnO2 semiconductor layer, the fourth semiconductor layer 32 is located above the third semiconductor layer 31, the source 36 extends through the fourth semiconductor layer 32 and contacts the third semiconductor layer 31, the groove passes through the fourth semiconductor layer 32 and the third semiconductor layer 31, and stays in the second semiconductor layer 3, the inner surface of the groove is covered by an insulating film, and the insulating film is a gate insulating film 34, and the conductive material is filled in the groove to form a gate 35.

[0138] In an IGBT, by applying a forward voltage between the drain 23 and the source 36 (the drain 23 side is at a positive potential), when a positive voltage is applied to the gate, the gate insulating film 34 forms a channel region, and current flows from the drain to the source through the channel. When no voltage is applied to the gate, the device enters the off state, and the withstand voltage is mainly achieved by the expansion of the depletion layer in the second semiconductor layer 3. Compared with ordinary MOSFETs, the IGBT has a much greater current conduction capability than a MOSFET because the fifth semiconductor layer 33 provides a large number of holes to participate in conduction when it is turned on.

[0139] While preferred embodiments of the present invention have been described above, the present invention is not limited to the aforementioned embodiments. Various modifications may be made without departing from the spirit of the present invention, and such modifications are naturally encompassed within the scope of the present invention. The method for forming each layer of the semiconductor element according to the present invention is not particularly limited, and may be a known method, as long as it does not hinder the purpose of the present invention.

Claims

1. A crystal stacked structure, It is characterized in that include: underlying substrate; and SnO 2 The SnO 2 The semiconductor layer is directly or indirectly arranged on the bottom substrate through a film layer, and the SnO 2 The semiconductor layer has a tetragonal rutile structure, and the SnO 2 The semiconductor layer has a (002) plane or a plane inclined within an angle range of 6° with respect to the (002) plane as a main plane.

2. The crystal stacked structure according to claim 1, It is characterized in that The SnO 2 The surface roughness of the semiconductor layer is Ra≤0.1um.

3. The crystal stacked structure according to claim 1, It is characterized in that The SnO 2 The average dislocation density of the semiconductor layer is ≤1 x 10 5 / cm 2 .

4. The crystal stacked structure according to claim 1, It is characterized in that The SnO 2 The thickness of the semiconductor layer is in the range of 0.5um~50um.

5. The crystal stacked structure according to any one of claims 1 to 4, It is characterized in that The bottom substrate is an m-plane sapphire substrate.

6. The crystal stacked structure according to any one of claims 1 to 4, It is characterized in that The underlying substrate is a SnO substrate having a (002) plane as a main surface or a plane inclined at an angle within a range of 6° relative to the (002) plane. 2 It is a single crystal substrate.

7. A semiconductor element, It is characterized in that A crystal stacking structure comprising any one of claims 1 to 6.

8. The semiconductor device according to claim 7, It is characterized in that The semiconductor element is a power device.

9. The semiconductor device according to claim 8, It is characterized in that The power device is a diode, a metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

10. The semiconductor device according to claim 9, It is characterized in that The diode is a Schottky diode having an anode electrode and a cathode electrode, and the anode electrode is Ti, Mo, W, Ni, Au or Pt.

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