PLC programming device and program

Abstract

[PROBLEM] To perform high-speed processing by extracting, from a sequence program, processes sequentially executed and processes capable of being executed in parallel. [SOLUTION] A PLC programming device according to one aspect of the present disclosure comprises: a program acquisition unit that acquires a sequence program to be executed by a PLC device; an extraction unit that extracts, from the acquired sequence program, sequential processes including sequential instructions to be sequentially executed and parallel processes including parallel instructions that can be executed in parallel; a sequential process compiling unit that compiles the extracted sequential processes into a sequential instruction execution format that can be executed by the PLC device; and a parallel process compiling unit that compiles the extracted parallel processes into a parallel instruction execution format that can be executed by the PLC device.

Description

PLC programming device and program

[0001] The present disclosure relates to a PLC (Programmable Logic Controller) programming device and program.

[0002] In recent years, software PLC devices that perform sequence control of controlled devices by processing programs rather than using dedicated hardware have become increasingly common. A von Neumann-type central processing unit (CPU)—such as a complex instruction set computer (CISC) type manufactured by Intel and AMD, or a reduced instruction set computer (RISC) type manufactured by ARM—basically executes processing sequentially. Therefore, when a PLC device using such a sequential processing CPU controls a large number of input / output (I / O) signals, the scan time (sequence program processing cycle) becomes longer, potentially resulting in reduced responsiveness of the I / O signal control.

[0003] Meanwhile, a technique for generating parallel processes that can be executed at high speed from at least some of the processes included in a program executed by a computer that can be executed in parallel is known (see, for example, Patent Document 1). By applying a parallel arithmetic device capable of executing parallel processes at high speed, such as a general-purpose computing on graphics processing unit (GPGPU) or a graphics processing unit (GPU), to a PLC device, I / O signal control can be executed at high speed. However, the sequence programs executed by the PLC device for I / O signal control often include complex processes that cannot be processed by a parallel arithmetic device alone and can only be realized by executing the processes sequentially.

[0004] Therefore, if a PLC device is equipped with both a serial processing type arithmetic device such as a CPU that executes processes sequentially and a parallel processing type arithmetic device such as a GPU, the execution of I / O signal control can be accelerated and the scan time can be shortened.Furthermore, in such a PLC device, if the serial processing of the sequence program that is executed sequentially is executed by the serial processing type arithmetic device and the parallel processing that can be executed in parallel is executed by the parallel processing type arithmetic device, the execution of I / O signal control can be further accelerated and the scan time can be further shortened.

[0005] Japanese Patent Application Laid-Open No. 2022-027536

[0006] In light of the above-mentioned background, it is desirable to extract processes that are executed sequentially and processes that can be executed in parallel from a sequence program and execute them at high speed in a PLC device.

[0007] One aspect of the PLC programming device of the present disclosure includes a program acquisition unit that acquires a sequence program to be executed by a PLC device, an extraction unit that extracts, from the acquired sequence program, sequential processes including sequential instructions that are executed sequentially and parallel processes including parallel instructions that can be executed in parallel, a sequential processing compilation unit that compiles the extracted sequential processes into a sequential instruction execution format that can be executed by the PLC device, and a parallel processing compilation unit that compiles the extracted parallel processes into a parallel instruction execution format that can be executed by the PLC device.

[0008] According to the present disclosure, processes that are executed sequentially and processes that can be executed in parallel can be extracted from a sequence program and executed at high speed in a PLC device.

[0009] FIG. 1 is a block diagram illustrating a configuration of a first PLC programming device 2 according to the present disclosure. FIG. 2A is a diagram illustrating a sequence program 10 written in the form of a ladder diagram. FIG. 2B is a diagram illustrating conversion of instructions included in NET1 of the sequence program 10 into instructions written in the IL language. FIG. 2C is a diagram illustrating parallel instructions shown in the GPU-executable instruction list 204 shown in FIG. 1. FIG. 3 is a flowchart illustrating the processing of the program acquisition unit 200 and the extraction unit 202 of the PLC programming device 2 (FIG. 1) according to the present disclosure. FIG. 4 is a diagram illustrating an example of the execution timing of instructions corresponding to NET1 to NET3. FIG. 5 is a block diagram illustrating a configuration of a second PLC programming device 5 according to the present disclosure. FIG. 6A is a diagram illustrating an example of a UI image used by a user to operate settings for the extraction unit 202. FIG. 6B is a diagram illustrating another example of a UI image used by a user to operate settings for the extraction unit 202. FIG. 6C is a block diagram illustrating a configuration for verifying the safety of the sequence program 10. FIG. 7A is a flowchart showing the processing of the PLC programming device 2 that is capable of arbitrating the execution timing of the GPU instruction execution format 30 and the CPU instruction execution format 32. FIG. 7B is a diagram illustrating the execution timing of the GPU instruction execution format 30 and the CPU instruction execution format 32, whose execution timing has been arbitrated by the processing shown in FIG. 7A. FIG. 8A is a flowchart showing the processing of the second instruction type determination processing (S24). FIG. 8B is a diagram illustrating the manner in which parallel instructions included in the GPU instruction execution format 30 and instructions included in the CPU instruction execution format 32 are executed alternately. FIG. 8C is a diagram illustrating the execution timing of instructions included in the GPU instruction execution format 30 and the CPU instruction execution format 32, whose execution timing has been arbitrated.

[0010] First Embodiment First, a first embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. Note that common components and processes in the drawings are denoted by the same reference numerals. In the following, no distinction will be made between a GPGPU and a GPU for image processing.

[0011] First, the configuration of a first PLC programming device 2 according to the present disclosure will be described. Fig. 1 is a block diagram showing the configuration of the first PLC programming device 2 according to the present disclosure. The PLC programming device 2 includes a program acquisition unit 200, an extraction unit 202, an executable instruction list 204 (hereinafter referred to as "GPU executable instruction list 204"), a GPU compilation unit 212, and a CPU compilation unit 222 that generates the GPU executable instruction list 204.

[0012] The program acquisition unit 200 of the PLC programming device 2 acquires a sequence program 10, which describes the control of a device to be controlled by the PLC device (neither of which is shown in FIG. 1 ), from a storage device such as a solid state drive (SSD) or hard disk drive (HDD), not shown, or via a communication network. The program acquisition unit 200 outputs the acquired sequence program 10 to the extraction unit 202.

[0013] As will be described later with reference to Figure 2C, the GPU-executable instruction list 204 shows instructions that are independent of other instructions and that can be executed in parallel (hereinafter referred to as "parallel instructions") rather than instructions that must be executed sequentially. The parallel instructions shown in the GPU-executable instruction list 204 will be described in further detail with reference to Figure 2C.

[0014] The extraction unit 202 compares the sequence program 10 with the parallel instructions listed in the GPU-executable instruction list 204. Furthermore, the extraction unit 202 performs syntax analysis on the sequence program 10 input from the program acquisition unit 200 based on the result of this comparison.

[0015] As a result of this syntax analysis, the extraction unit 202 extracts, from the processing included in the sequence program 10, parallel processing 210 (hereinafter referred to as "GPU processing 210") that can be executed in parallel in the PLC device, and sequential processing 220 (hereinafter referred to as "CPU processing 220") that is executed sequentially in the PLC device.

[0016] The extraction unit 202 outputs the extracted GPU processing 210 to a GPU compilation unit 212. The extraction unit 202 also outputs the extracted CPU processing 220 to a CPU compilation unit 222. Note that processing such as syntax analysis by the extraction unit 202 will be described in further detail with reference to FIG. 2B and the like.

[0017] The GPU compiler unit 212 compiles the GPU processing 210 input from the extraction unit 202. As a result of this compilation, the GPU compiler unit 212 generates a parallel instruction execution format 30 (hereinafter referred to as the "GPU instruction execution format 30") that can be directly executed by the PLC device to control the controlled device. Specifically, the GPU instruction execution format 30 is, for example, hexadecimal data that is input as a set of instruction codes to the GPU of the PLC device.

[0018] Meanwhile, the CPU compilation unit 222 compiles the CPU processing 220 input from the extraction unit 202. As a result of this compilation, the CPU compilation unit 222 generates a sequential instruction execution format 32 (hereinafter referred to as the "CPU instruction execution format 32") that can be directly executed by the PLC device to control the controlled device. Specifically, the CPU instruction execution format 32 is, for example, hexadecimal data that is input to the CPU of the PLC device as a set of instruction codes.

[0019] 1 , the PLC programming device 2 generates a sequence program execution format 3 that includes both a GPU instruction execution format 30 and a CPU instruction execution format 32. Alternatively, when the sequence program 10 does not include a parallel instruction, the PLC programming device 2 generates a sequence program execution format 3 that includes only the CPU instruction execution format 32. The PLC programming device 2 outputs the generated sequence program execution format 3 to the PLC device.

[0020] Next, the sequence program 10 to be processed by the PLC programming device 2 and the processing of the extraction unit 202 will be described in detail with reference to Figures 2A to 2C. First, the sequence program 10 will be described using a specific example. Figure 2A is a diagram illustrating an example of the sequence program 10 written in the form of a ladder diagram. As shown in Figure 2A, the sequence program 10 is written, for example, in LD language (hereinafter referred to as "ladder diagram").

[0021] Note that ladder diagrams conform to the IEC 61131-3 standard and correspond to high-level languages ​​in the computer field. Hereinafter, in ladder diagrams, a combination of instructions connected by multiple horizontal lines will be referred to as NET. In addition to ladder diagrams, the sequence program 10 can also be written in ST language, which conforms to the same standard and corresponds to high-level languages ​​in the computer field. Alternatively, the sequence program 10 can also be written in IL language, which conforms to the same standard and corresponds to assembly language in the computer field.

[0022] 2A, the sequence program 10 includes, for example, NET1 to NET3. However, the sequence program 10 may include more NETs than NET1 to NET3, that is, NET4 and subsequent NETs.

[0023] NET1 to NET3 each include instructions indicated by normally open switches R1, R2, R5, R6, and R7 whose contacts are closed when a specific output assumes a predetermined logical value, and NET1 to NET3 also include instructions indicated by normally closed switch R3 whose contacts are open when a specific output assumes a predetermined logical value.

[0024] NET1 to NET3 also include commands indicated by outputs R4, R6, and R8 to coils that drive relays, etc. Hereinafter, "commands indicated by switches R1, R2, R5, R6, and R7" will be described as "switches R1, R2, R5, R6, and R7," and "commands indicated by outputs R4, R6, and R8" will be described as "outputs R4, R6, and R8."

[0025] Each command of switches R1 to R3, R5, R6, and R7 is executed in response to a user operation of the PLC device or the logical value of some output result. Note that hereinafter, the "logical value of the execution result of the command" will be referred to as the "execution result" or "result." In particular, switch R6 included in NET3 is either executed or not executed depending on the execution result of output R6 included in NET2.

[0026] Furthermore, NET2 includes a macro instruction "FILEOPEN" that includes instructions that cannot be executed in parallel and must be executed sequentially (hereinafter, such instructions will be referred to as "sequential instructions"). The macro instruction "FILEOPEN" is a combination of instructions for opening a specific file stored in a PLC device. However, not all macro instructions include sequential instructions, and there may be macro instructions that do not include sequential instructions.

[0027] Next, we will explain the syntax analysis of the sequence program 10 by the extraction unit 202 shown in Figure 1. The result of output R4 included in NET1 is not related to the execution of any of switches R1 to R3, R5, R6, and R7 included in NET1 to NET3. However, the result of output R4 may affect the execution of switches included in NET4 and later. Furthermore, switches R1 to R3 may affect the results of instructions included in NET4 and later, or may be affected by these instructions. However, for the sake of concreteness and clarity of explanation, such possibilities will not be taken into consideration below.

[0028] Furthermore, switches R1 to R3 included in NET1 are not affected by the results of outputs R6 and R8 included in other NETs 2 and 3. NET1 also does not include macro instructions that include sequential instructions. In other words, instructions included in NET1 can be executed regardless of the results of instructions included in other NETs 2 and 3. Therefore, all instructions included in NET1 are parallel instructions.

[0029] NET2 of the sequence program 10 includes a macro instruction "FILEOPEN" which includes a sequential instruction in addition to the switch R5 and the output R6. Therefore, the instructions included in NET2 cannot be executed in parallel and must be executed sequentially.

[0030] NET3 of sequence program 10 includes switches R6 and R7 and output R8. As indicated by the dotted line in the figure, switch R6 is executed or not depending on the result of output 6 included in NET2. In other words, instructions included in NET3 cannot be executed independently of instructions included in NET2. Therefore, instructions included in NET2 and NET3 cannot be considered to be instructions that can be executed in parallel unless there is arbitration of the timing of the execution of these instructions.

[0031] On the other hand, the switches R7 and output R8 other than switch R6 included in NET3 can be executed in parallel as long as the result of output 6 included in NET2 is determined. In other words, as long as the execution timing of the instructions included in NET2 and NET3 is adjusted, the instructions included in NET3 can be executed in parallel.

[0032] As explained above, of the instructions contained in NET1 to NET3 shown in Figure 2A, only the instructions contained in NET1 can be executed in parallel unless there is arbitration for the timing of instruction execution. On the other hand, since NET2 contains the macro instruction "FILEOPEN" which includes a sequential instruction, the instructions contained in NET2 cannot be executed in parallel. Furthermore, the instructions contained in NET3 cannot be executed in parallel either.

[0033] 2A, among the NETs that include only parallel instructions, there are NETs that include only instructions that do not depend on the results of instructions included in other NETs as conditions for execution, and the instructions included in such NETs can be executed in parallel. Therefore, in the sequence program 10, such NETs include combinations of only parallel instructions and can be included in the GPU processing 210.

[0034] On the other hand, in the sequence program 10, instructions included in a NET that includes even one sequential instruction cannot be included in the GPU processing 210. Such instructions must be included in the CPU processing 220. Also, even if there is no sequential instruction, there are NETs that include even one instruction whose execution condition is the result of an instruction included in another NET. A combination of instructions included in such a NET cannot be included in the GPU processing 210 and must be included in the CPU processing 220 unless there is arbitration for the execution timing.

[0035] As described above, the syntactic analysis by the extraction unit 202 is performed. Through such syntactic analysis, the extraction unit 202 can determine whether a combination of instructions included in each NET of the sequence program 10 can be included in the GPU processing 210 or whether it must be included in the CPU processing 220.

[0036] Note that CPU processing 220 includes all of the instructions included in NET2 and NET3, but instructions such as switch R5 can also be considered parallel instructions that can be executed independently of the results of instructions in other NETs. Therefore, CPU processing 220 can include not only sequential instructions but also parallel instructions shown in GPU-executable instruction list 204. Therefore, the parallel instructions and sequential instructions included in CPU processing 220 will hereinafter be collectively referred to as "instructions."

[0037] 2B is a diagram illustrating an example of converting instructions included in NET1 of the sequence program 10 into instructions written in the IL language. As shown in FIG. 2B , in the sequence program 10, instructions included in each NET included in the ladder diagram can be converted into instructions written in the IL language. For example, the extraction unit 202 can convert the instructions included in NET1 of the sequence program 10 into a combination of instructions written in the IL language: "RD R1 STK1," "OR R2 STK1 STK2," "NOT R5 STK3," "AND STK2 STK3 STK4," and "WRT STK4 R4." However, due to factors such as differences in IL language between manufacturers of PLC devices, it is not always possible to obtain instructions written in the same IL language from each NET of the same sequence program 10.

[0038] The IL language instruction "RD R1 STK1" shown in FIG. 2B is a read instruction that reads the state of switch R1 into stack STK1. For example, the state of switch R1 is represented by a logical value "0" when the contacts of switch R1 are open, and by a logical value "1" when the contacts of switch R1 are closed. Furthermore, "OR R2 STK1 STK2" indicates that the result of a logical sum operation (OR) of the logical values ​​of stacks STK1 and STK2 is to be set as the state of switch R2.

[0039] Furthermore, "NOT R3 STK3" indicates that the result of a logical negation operation (NOT) of the logical values ​​of stack STK3 is to be set as the state of switch R3. Furthermore, "AND STK2 STK3 STK4" indicates that the result of a logical negation operation (NOT) of the logical values ​​of stacks STK2 to STK4 is to be set as the state of switch R3. Furthermore, "WRT STK4 R4" indicates that the logical value of stack STK4 is to be written as the state of switch R4.

[0040] 2C is a diagram illustrating parallel instructions shown in the GPU-executable instruction list 204 shown in FIG. 1. The instructions written in the IL language shown in FIG. 2A include sequential instructions and parallel instructions. The GPU-executable instruction list 204 shown in FIG. 1 shows parallel instructions as shown in FIG. 2C. The GPU-executable instruction list 204 shows, as parallel instructions, instructions "RD", "WRT", "COMPARE", "AND", "OR", "NOT", "SET", "RESET", "ADD-SINT", "SUB-SINT", "MUL-SINT", and "DIV-SINT".

[0041] 2C, more parallel instructions may be shown in the GPU-executable instruction list 204. Macro-instructions that include only parallel instructions may also be shown in the GPU-executable instruction list 204.

[0042] Of the instructions shown in the GPU executable instruction list 204, "COMPARE" indicates a comparison. "SET" indicates setting a logical value indicating the state of a switch or the like to "1". "RESET" indicates resetting a logical value indicating the state of a switch or the like to "0". "ADD-SINT" indicates 8-bit (1 byte) addition. "SUB-SINT" indicates 8-bit subtraction. "MUL-SINT" indicates 8-bit multiplication. "DIV-SINT" indicates 8-bit division.

[0043] A combination of instructions included in a specific NET of the sequence program 10 written in the IL language may include a sequential instruction that is not listed in the GPU-executable instruction list 204. In such a case, the extraction unit 202 determines that the combination of instructions included in this specific NET cannot be executed in parallel and must be executed sequentially.

[0044] Conversely, all of the processes included in a specific NET may be parallel instructions listed in the GPU-executable instruction list 204. In this case, the extraction unit 202 determines that the combination of processes included in this specific NET may be executed in parallel. By performing the above-described syntax analysis on the combination of instructions included in the specific NET that has been determined to be executed in parallel, the extraction unit 202 determines whether the combination of processes included in this specific NET may be executed in parallel.

[0045] The processing of the PLC programming device 2 will be described below. Fig. 3 is a flowchart showing the processing of the program acquisition unit 200 and the extraction unit 202 of the PLC programming device 2 (Fig. 1) according to the present disclosure. The program acquisition unit 200 acquires the sequence program 10 shown in Fig. 2A from outside the PLC programming device 2 via removable media. Alternatively, the program acquisition unit 200 acquires the sequence program 10 from another computer via a communication network. The program acquisition unit 200 outputs the acquired sequence program 10 to the extraction unit 202 (S100).

[0046] The extraction unit 202 converts the sequence program 10 written in the ladder diagram shown in Figure 2A into an IL-format language, and as described with reference to Figure 2C, compares it with the parallel instructions shown in the GPU-executable instruction list 204 and further performs syntax analysis (S102). Based on the results of the processing in S102, the extraction unit 202 determines whether combinations of instructions included in each NET of the sequence program 10 can be executed in parallel (S104).

[0047] The extraction unit 202 extracts combinations of instructions included in NETs that are determined to be executable in parallel (Y) in the processing of S102, from among the NETs included in the sequence program 10. The extraction unit 202 includes the extracted combinations of instructions in the GPU processing 210. After completing generation of the GPU processing 210, the extraction unit 202 outputs the GPU processing 210 to the GPU compilation unit 212 (S106).

[0048] On the other hand, the extraction unit 202 includes a combination of processes included in the NET that is determined as not being able to be executed in parallel (N) as a result of the processing in S102 in the CPU processing 220. After finishing generating the CPU processing 220, the extraction unit 202 outputs the CPU processing 220 to the CPU compilation unit 222 (S108).

[0049] In the PLC programming device 2, the GPU compiler 212 compiles the GPU processing 210 input from the extractor 202 into a format that can be directly executed in the PLC device, and generates a GPU instruction execution format 30. The CPU compiler 222 compiles the CPU processing 220 input from the extractor 202 into a format that can be directly executed in the PLC device, and generates a CPU instruction execution format 32.

[0050] When both the GPU instruction execution format 30 and the CPU instruction execution format 32 are generated, the PLC programming device 2 generates a sequence program execution format 3 including the GPU instruction execution format 30 and the CPU instruction execution format 32. Alternatively, when the GPU instruction execution format 30 is not generated and only the CPU instruction execution format 32 is generated, the PLC programming device 2 generates a sequence program execution format 3 including only the CPU instruction execution format 32. The PLC programming device 2 outputs the generated sequence program execution format 3 to the PLC device, causes it to execute the PLC device, and causes it to control the controlled device.

[0051] 4 is a diagram illustrating the timing of execution of instructions corresponding to NET1 to NET3 included in sequence program execution format 3 generated from sequence program 10 shown in FIG. 1 etc. As described above, the combination of instructions included in NET1 of sequence program 10 can be executed in parallel, and therefore is included in GPU instruction execution format 30. On the other hand, as described above, the processes included in NET2 and NET3 of sequence program 10 cannot be executed in parallel and must be executed sequentially, and therefore the instructions included in these two NET2 and NET3 are included in CPU instruction execution format 32.

[0052] 4, first, the parallel instructions included in the GPU instruction execution format 30 and corresponding to NET1 are executed by the GPU (not shown) of the PLC device. Next, the sequential instructions corresponding to NET2 and NET3 are executed by the CPU (not shown) of the PLC device. Note that when the sequence program 10 includes processing included in NET4 and subsequent NETs, ​​after the sequential instruction corresponding to NET3 is completed, the instructions corresponding to NET4 and subsequent NETs are executed.

[0053] 4, according to the PLC programming device 2, a combination of instructions that can be executed in parallel, among combinations of instructions included in each NET of the sequence program 10, can be set as a GPU process 210. The GPU process 210 compiled by the GPU compiler 212 is executed at high speed by the GPU of the PLC device.

[0054] It is generally known that approximately 80% of the instructions included in the sequence program execution format 3 executed by a PLC device are parallel instructions, such as bit operations. Therefore, when the PLC device executes the GPU instruction execution format 30 and the CPU instruction execution format 32 generated from the sequence program 10, the execution speed of the sequence program 10 is significantly increased (for example, by 1000 times or more) compared to when only the CPU instruction execution format 32 is executed.

[0055] Therefore, in a PLC device that executes the GPU instruction execution format 30 and the CPU instruction execution format 32, the execution speed of the sequence program 10 can be equal to or faster than the execution speed of the sequence program 10 using dedicated hardware. In a PLC device that executes the GPU instruction execution format 30 and the CPU instruction execution format 32, the increased speed of the execution of the sequence program 10 also significantly reduces the scan time of the sequence program 10.

[0056] In some cases, a GPU instruction execution format 30 and a CPU instruction execution format 32 are generated using the PLC programming device 2 and executed by the PLC device to simulate control of a device to be processed. In such cases, if the PLC programming device 2 generates a sequence program execution format 3 including the GPU instruction execution format 30 and the CPU instruction execution format 32 and executes it on the PLC device, the simulation is sped up and its accuracy is improved.

[0057] Second Embodiment Next, a second embodiment of the present disclosure will be described in detail. First, the configuration of a PLC programming device 5 will be described. Fig. 5 is a block diagram showing the configuration of a second PLC programming device 5 according to the present disclosure. As shown in Fig. 5, the second PLC programming device 5 according to the present disclosure has a configuration in which an executable format input unit 500 is added to the first PLC programming device 2 shown in Fig. 1.

[0058] Next, a description will be given of the operation of the PLC programming device 5. In the PLC programming device 5, an execution format input unit 500 is connected to the extraction unit 202. The execution format input unit 500 accepts settings input by a user of the PLC programming device 5. The settings input by the user indicate whether the extraction unit 202 is to generate both the GPU processing 210 and the CPU processing 220 from the sequence program 10, or whether the extraction unit 202 is to generate only the CPU processing 220.

[0059] There are times when the user sets the executable format input unit 500 to generate both the GPU processing 210 and the CPU processing 220. In this case, the executable format input unit 500 controls the extraction unit 202 to generate both the GPU processing 210 and the CPU processing 220 from the sequence program 10.

[0060] Furthermore, the GPU compiler unit 212 compiles the GPU processing 210 to generate a GPU instruction execution format 30. Furthermore, the CPU compiler unit 222 compiles the CPU processing 220 to generate a CPU instruction execution format 32. The PLC programming device 2 outputs a sequence program execution format 3 that includes both the GPU instruction execution format 30 and the CPU instruction execution format 32.

[0061] On the other hand, there are times when the user sets the execution format input unit 500 to generate only the CPU processing 220. In this case, the execution format input unit 500 controls the extraction unit 202 to generate only the CPU processing 220 from the sequence program 10.

[0062] Furthermore, the CPU compiling unit 222 compiles the CPU processing 220 to generate a CPU instruction execution format 32. The PLC programming device 2 outputs a sequence program execution format 3 including only the CPU instruction execution format 32.

[0063] A user interface (UI) image used for user settings for the executable format input unit 500 will now be described. Fig. 6A is a diagram showing an example of a UI image used for a user setting whether to generate only the GPU processing 210 or to generate both the GPU processing 210 and the CPU processing 220 for the extraction unit 202 of the PLC programming device 5. As shown in Fig. 6A, this UI image is displayed on a display (not shown) of the PLC programming device 5 or the like. This UI image includes a check box that can be checked by a user operation and an OK box for the user to confirm such operation.

[0064] A user may wish to generate a sequence program execution format 3 that includes both a GPU instruction execution format 30 and a CPU instruction execution format 32. As described above, this sequence program execution format 3 is used to simulate the sequence program 10. Alternatively, this sequence program execution format 3 is generated to be executed by a PLC device equipped with a GPU. In such a case, the user checks the checkbox in the UI image shown in FIG. 6A and presses the OK button.

[0065] By this operation, the execution format input unit 500 in the PLC programming device 5 accepts the user's setting to generate both the GPU processing 210 and the CPU processing 220. In response to this user's setting, the PLC programming device 5 outputs a sequence program execution format 3 including both the GPU instruction execution format 30 and the CPU instruction execution format 32.

[0066] 6A , the user presses the OK button without checking the checkbox. When this operation is performed, the execution format input unit 500 in the PLC programming device 5 accepts the user's setting to generate only the CPU processing 220. In response to this user setting, the PLC programming device 5 outputs a sequence program execution format 3 that includes only the CPU instruction execution format 32.

[0067] As described above, the PLC programming device 5 can have two operation modes when using the UI image shown in Fig. 6A. One of the two operation modes is an operation mode for outputting a sequence program execution format 3 that includes both the GPU instruction execution format 30 and the CPU instruction execution format 32.

[0068] The other of the two operation modes is an operation mode that outputs a sequence program execution format 3 that includes only a CPU instruction execution format 32. A user can sell a PLC programming device 5 that is capable of using both of these two operation modes at a higher price than a PLC programming device 5 that is capable of using only the other of the two operation modes.

[0069] Furthermore, the user can be charged separately for the PLC programming device 5 that allows the use of both of the two operation modes from the PLC programming device 5 that allows the use of only one of the other two operation modes, which brings about business benefits for the user in the manufacture and sale of the PLC programming device 5.

[0070] 6B is a diagram showing another example of a UI image used for an operation in which the user sets whether to generate only the GPU processing 210 or to generate both the GPU processing 210 and the CPU processing 220 for the extraction unit 202 of the PLC programming device 5. In FIG. 6B , "main sequence," "PLC4," and "PLC5" respectively represent multiple sequence programs 10 processed in the PLC programming device 5.

[0071] Level 1 indicates an operation mode in which the PLC programming device 5 outputs a sequence program execution format 3 including only the CPU instruction execution format 32. On the other hand, level 2 indicates an operation mode in which the PLC programming device 5 outputs a sequence program execution format 3 including the GPU instruction execution format 30 and the CPU instruction execution format 32. Furthermore, "GPU enabled" indicates that the user has selected the level 2 operation mode out of these two operation modes.

[0072] The user operates the UI image shown in Fig. 6B using a mouse pointer or the like. In response to this operation, the PLC programming device 5 receives a setting from each of the plurality of sequence programs 10 as to whether to generate a sequence program execution format 3 generated in the level 1 operation mode or the second mode.

[0073] The following describes the technical effects of the PLC programming device 5. The PLC programming device 5 can provide a sequence program execution format 3 including only the CPU instruction execution format 32 for a PLC device that does not have a GPU. Furthermore, the PLC programming device 5 can provide a sequence program execution format 3 including both the GPU instruction execution format 30 and the CPU instruction execution format 32 for a PLC device that has a GPU and a CPU. Furthermore, as described above, the PLC programming device 5 allows users to enjoy advantages in the manufacturing and sales business and allows them to set different operation modes for each of multiple sequence programs 10.

[0074] The technical effects of the PLC programming devices 2 and 5 will be further described with reference to Fig. 6C. Fig. 6C is a block diagram showing a configuration for verifying the safety of the sequence program 10. As shown in Fig. 6C, the configuration for verifying the safety of the sequence program 10 includes the PLC programming devices 2 and 5, PLC devices 60-1 and 60-2, control target devices 62-1 and 62-2, and a comparison device 64.

[0075] The PLC programming devices 2 and 5 are connected to the PLC devices 60-1 and 60-2, respectively. The PLC devices 60-1 and 60-2 are connected to the control target devices 62-1 and 62-2, respectively. The control target devices 62-1 and 62-2 are connected to the comparison device 64.

[0076] The PLC device 60-1 is configured to be able to execute a sequence program execution format 3 that includes both the GPU instruction execution format 30 and the CPU instruction execution format 32. The PLC device 60-2 is configured to be able to execute a sequence program execution format 3 that includes at least the CPU instruction execution format 32.

[0077] The control target devices 62-1 and 62-2 have the same configuration and are configured to perform the same operation under the control of the PLC devices 60-1 and 60-2. The comparison device 64 is configured to be able to compare the operation of common relays, switches, etc. included in the information from the control target devices 62-1 and 62-2.

[0078] 6C will be described below. The PLC programming device 2 generates a sequence program execution format 3 including a GPU instruction execution format 30 and a CPU instruction execution format 32 from the sequence program 10, and provides the generated sequence program execution format 3 to the PLC device 60-1. The PLC device 60-1 executes the sequence program execution format 3 provided by the PLC programming device 2, and controls the controlled device 62-1. The controlled device 62-1 operates under the control of the PLC device 60-1, and outputs information indicating the details of the operation to the comparison device 64.

[0079] The PLC programming device 5 is set to generate a sequence program execution format 3 including only the CPU instruction execution format 32. The PLC programming device 5 generates the sequence program execution format 3 including only the CPU instruction execution format 32 from the sequence program 10 and provides it to the PLC device 60-2.

[0080] The PLC device 60-2 executes the sequence program execution format 3 provided by the PLC programming device 5 and controls the controlled device 62-2. The controlled device 62-2 operates according to the control of the PLC device 60-2 and outputs information indicating the details of the operation to the comparison device 64.

[0081] The comparison device 64 compares the information input from the control target device 62-1 with the information input from the control target device 62-2 to verify the safety of the sequence program 10. In other words, the comparison device 64 determines that the sequence program 10 is safe when the operation indicated by the information input from the control target device 62-1 matches the operation indicated by the information input from the control target device 62-2. On the other hand, the comparison device 64 determines that there is a problem with the sequence program 10 when these operations do not match.

[0082] 6C generates two types of sequence program execution formats 3 for performing the same processing with different content from one sequence program 10, and executes them in two types of PLC devices 60-1 and 60-2, respectively, to create diversity. Furthermore, the configuration shown in FIG. 6C causes the two types of PLC devices 60-1 and 60-2 that have created diversity to control controlled devices 62-1 and 62-2 with the same configuration, respectively, and a comparison device 64 cross-checks the operations of the controlled devices 62-1 and 62-2.

[0083] 6C, it is possible to verify the safety of the sequence program 10 in accordance with ISO 13849-1. Furthermore, with such a configuration, it is possible to dual-systemize the control of the control target devices 62-1 and 62-2, thereby enabling safer control of the control target devices 62-1 and 62-2.

[0084] [Third Embodiment] Next, a third embodiment of the present disclosure will be described in detail. According to the third embodiment of the present disclosure, the processing of the PLC programming device 2 shown in Fig. 1 is changed so that the execution timing of the GPU instruction execution format 30 and the CPU instruction execution format 32 can be arbitrated multiple times within one scan time.

[0085] Fig. 7A is a flowchart showing the processing of the PLC programming device 2 that is capable of arbitrating the execution timing of the GPU instruction execution format 30 and the CPU instruction execution format 32. Fig. 7B is a diagram illustrating the execution timing of the GPU instruction execution format 30 and the CPU instruction execution format 32, the execution timing of which has been arbitrated by the processing shown in Fig. 7A.

[0086] As shown in Fig. 7A, the program acquisition unit 200 of the PLC programming device 2 acquires the sequence program 10 written in the ladder diagram format shown in Fig. 3A (S200). In the first command type determination process (S22), the extraction unit 202 performs the syntax analysis described above with reference to Figs. 2A to 2C on the NET that is closest to the beginning of the sequence program 10 and has not yet reached the process of S22 among the sequence programs 10 acquired in the process of S200 (S220).

[0087] The extraction unit 202 determines whether the combination of instructions included in the NET that was the target of the processing in S220 can be executed in parallel (S222). If the combination of instructions included in this NET can be executed in parallel (Y), the extraction unit 202 determines whether the processing result of a parallel instruction included in another NET or the processing result of a sequential instruction included in another NET is input to the processing included in this NET (S224).

[0088] When the result of a parallel instruction is input to an instruction included in this NET, the extraction unit 202 includes the instruction included in this NET as a parallel instruction in the GPU processing 210 (S226). When the instruction included in this NET cannot be executed in parallel (N in S222), or when the result of a sequential instruction is input to an instruction included in this NET, the extraction unit 202 includes the instruction included in this NET in the CPU processing 220 (S228).

[0089] The extraction unit 202 determines whether the process of S22 has been executed for the last (terminal) NET of the sequence program 10 acquired in S200 (S230). If the process of S22 has been executed for the terminal NET (Y), the process of S22 ends and the process proceeds to S202. On the other hand, if the process of S22 has not been executed for the terminal NET (N), the extraction unit 202 returns to the process of S220.

[0090] The GPU compiler 212 compiles the GPU process 210 generated by the process of S22 into a format that can be directly executed by the PLC device, and generates a GPU instruction execution format 30 (S202). The CPU compiler 222 compiles the CPU process 220 generated by the process of S22 into a format that can be directly executed by the PLC device, and generates a CPU instruction execution format 32 (S202).

[0091] Through the above processing, the PLC programming device 2 generates a sequence program execution format 3 in which the execution timing is adjusted between the parallel instructions included in the GPU instruction execution format 30 and the instructions included in the CPU instruction execution format 32. The PLC programming device 2 outputs the generated sequence program execution format 3 to the PLC device.

[0092] The process shown in Fig. 7A realizes arbitration between the execution timing of the parallel instruction included in GPU instruction execution format 30 and the execution timing of the instruction included in CPU instruction execution format 32. In other words, as shown in Fig. 7B, the parallel instruction included in GPU instruction execution format 30 and corresponding to NET1 shown in Fig. 2A is started simultaneously with the instruction included in CPU instruction execution format 32 and corresponding to NET2 due to arbitration of the execution timing.

[0093] On the other hand, execution of the instruction included in GPU instruction execution format 30 and corresponding to NET3 requires the result of NET2. Therefore, due to arbitration of execution timing, the instruction included in GPU instruction execution format 30 and corresponding to NET3 is treated as a parallel instruction included in GPU instruction execution format 30 that starts after execution of the instruction corresponding to NET2.

[0094] The processes included in each of the other NETs included in the sequence program 10 are also treated as parallel instructions included in the GPU instruction execution format 30 and instructions included in the CPU instruction execution format 32, which are executed simultaneously. Alternatively, such instructions are treated as parallel instructions included in the GPU instruction execution format 30, which are executed after the execution of the instructions included in the CPU instruction execution format 32.

[0095] A modified example of the third embodiment of the present disclosure will be described below. Fig. 8A is a flowchart illustrating a second instruction type determination process (S24) that is executed instead of the first instruction type determination process (S22) in the process of the PLC programming device 2 shown in Fig. 7A.

[0096] Fig. 8B is a diagram illustrating an example of how the parallel instructions included in the GPU instruction execution format 30 and the instructions included in the CPU instruction execution format 32 are executed alternately by the process shown in Fig. 8A. Fig. 8C is a diagram illustrating the timing of execution of the parallel instructions included in the GPU instruction execution format 30 and the instructions included in the CPU instruction execution format 32, the execution timings of which have been adjusted by the process shown in Fig. 8A.

[0097] After the processing of S200, S220 and S224 shown in FIG. 7A, as shown in FIG. 8A, the extraction unit 202 determines whether the instructions contained in the NET that was the target of the processing of S24 can be executed in parallel (S240).

[0098] When instructions included in the NET being processed can be executed in parallel (Y), the extraction unit 202 determines whether the result of a parallel instruction included in another NET is input to the parallel instruction included in this NET, or whether the result of a sequential instruction included in another NET is input (S242).When the result of a sequential instruction included in another NET is input to the parallel processing included in this NET (A), the extraction unit 202 sets the parallel instruction included in this NET as a parallel instruction included in GPU processing 210 that is executed after GPU processing 220 that includes a sequential instruction that provides a result as input to this NET (S244).

[0099] When no results of instructions contained in other NETs are input to the instructions contained in this NET, or when the results of parallel instructions contained in other NETs are input (B), the extraction unit 202 includes the processing contained in this NET as a parallel instruction in the GPU processing 210 (S246).

[0100] When the instructions included in the NET being processed cannot be executed in parallel (N in S240), the extraction unit 202 determines whether the results of parallel instructions or sequential instructions are input to the instructions included in this NET (S248). When the results of parallel instructions are input to the instructions included in this NET (C), the extraction unit 202 includes the instructions included in this NET in the CPU processing 220 following the GPS processing 210 that includes parallel instructions that provide the results as input to this NET (S250).

[0101] When the result of a parallel instruction included in another NET is input to an instruction included in this NET, or when no result of an instruction included in another NET is input (D), the extraction unit 202 includes the instruction included in this NET in the CPU processing 220 (S252).

[0102] After the above-described processing, the PLC programming device 2 performs the processing of S202, S204, and S230 shown in Fig. 7A. As a result of this processing, the execution timing of the parallel instruction included in the GPU instruction execution format 30 and the execution timing of the sequential instruction included in the CPU instruction execution format 32 are arbitrated.

[0103] According to the process shown in FIG. 8A, as shown in FIG. 8B, the parallel instructions included in the GPU instruction execution format 30 and the instructions included in the CPU instruction execution format 32 are executed alternately during one scan time by arbitrating the timing of the execution of these instructions.

[0104] 8A, the instruction included in GPU instruction execution format 30 and corresponding to NET2 shown in FIG. 2A becomes an instruction that starts after the parallel instruction included in GPU instruction execution format 30 and corresponding to NET1 is completed. On the other hand, the instruction included in GPU instruction execution format 30 and corresponding to NET3 becomes a parallel instruction that starts after the execution of the instruction corresponding to NET2.

[0105] Note that the processes included in each of the other NETs included in the sequence program 10 also become parallel instructions included in the GPU instruction execution format 30 that is started after execution of the CPU instruction execution format 32. Alternatively, the processes included in each of the other NETs included in the sequence program 10 also become instructions included in the CPU instruction execution format 32 that is started after execution of the GPU instruction execution format 30.

[0106] 7A and 8A, more instructions included in the sequence program 10 are parallelized than in the process shown in Fig. 3. Therefore, according to the process shown in Fig. 7A, the PLC programming device 2 can generate a sequence program execution format 3 from the sequence program 10 that is faster and has a shorter scan time.

[0107] [Implementation of Processing of the PLC Programming Device by Software, etc.] The processing of the PLC programming device according to the present disclosure can be implemented by software. When this processing is implemented by software, the program constituting this software is installed and executed on a user's computer. Such a program can be distributed and installed on the user's computer via removable media, or can be distributed and installed on the user's computer from another computer over a network. Furthermore, the program constituting this software does not necessarily have to be distributed to the user's computer; for example, it can be provided to the user's computer as a web service.

[0108] Although the present disclosure has been described in detail, the present disclosure is not limited to the individual embodiments described above. Various additions, substitutions, modifications, partial deletions, etc. may be made to these embodiments without departing from the gist of the present disclosure or the spirit of the present disclosure derived from the content of the claims and their equivalents. Furthermore, these embodiments may be implemented in combination. For example, in the above-described embodiments, the order of each operation and the order of each process are shown as examples and are not limited to these. The same applies when numerical values ​​or mathematical expressions are used to describe the above-described embodiments.

[0109] The following supplementary notes are further disclosed regarding the above-described embodiments and modifications. (Supplementary Note 1) A PLC programming device (2) according to the present disclosure includes a program acquisition unit (200) that acquires a sequence program (10) to be executed by a PLC device (60), an extraction unit (202) that extracts, from the acquired sequence program (10), sequential processing (220) including sequential instructions to be executed sequentially and parallel processing (210) including parallel instructions that can be executed in parallel, a sequential processing compilation unit (222) that compiles the extracted sequential processing (220) into a sequential instruction execution format (32) that can be executed by the PLC device (60), and a parallel processing compilation unit (212) that compiles the extracted parallel processing (210) into a parallel instruction execution format (30) that can be executed by the PLC device (60). (Supplementary Note 2) In the PLC programming device (2) according to the present disclosure, the extraction unit (202) extracts the sequential processing (220) or the sequential processing (220) and the parallel processing (210) based on a parallel executable instruction list (204) indicating the parallel instructions. (Supplementary Note 3) The PLC programming device (2) according to the present disclosure further includes an executable format input unit (500) that accepts input in an executable format indicating that the sequence program (10) is to be executed in parallel, and the extraction unit (202) extracts the sequential processing (220) and the parallel processing (210) from the sequence program (10) when the executable format input unit (500) accepts input indicating that the sequence program (10) is to be executed in parallel. (Supplementary Note 4) The extraction unit (202) of the PLC programming device (2) according to the present disclosure acquires the portion (NET) of the received sequence program (10), analyzes the syntax of the acquired portion (NET) of the sequence program (10), and, when it determines as a result of the analysis that the acquired portion (NET) of the sequence program (10) can be executed in parallel, adds the acquired portion (NET) of the sequence program (10) to the parallel processing (210), and adds the acquired portion (NET) of the sequence program (10) to the sequential processing (220) when it is not determined that the acquired portion (NET) of the sequence program (10) can be executed in parallel.(Supplementary Note 5) The extraction unit (202) of the PLC programming device (2) according to the present disclosure acquires a portion (NET) of the received sequence program (10), analyzes the syntax of the acquired portion (NET) of the sequence program (10), and as a result of the analysis, the acquired portion (NET) of the sequence program (10) can be executed in parallel. When the output of the sequential processing (220) is used, the acquired portion (NET) of the sequence program (10) is added to the parallel processing (210) that is processed after the sequential processing (220). (Supplementary Note 6) The extraction unit (202) of the PLC programming device (2) of (Supplementary Note 5) adds the acquired part (NET) of the sequence program (10) to the parallel processing (210) except when the acquired part (NET) of the sequence program (10) can be executed in parallel and the output of the parallel processing (220) is used or the output of the sequential processing (220) or the parallel processing (210) is used. (Supplementary Note 7) The extraction unit (202) of the PLC programming device (2) according to the present disclosure acquires a portion (NET) of the accepted sequence program (10), parses the acquired portion (NET) of the sequence program (10), and, as a result of the parsing, adds the acquired portion (NET) of the sequence program (10) to the sequential processing (220) that is processed after the parallel processing (210) when an output of the parallel processing (210) is used, except when the acquired portion (NET) of the sequence program (10) can be executed in parallel. (Supplementary Note 8) The extraction unit (202) of the PLC programming device (2) of (Supplementary Note 7) adds the acquired portion (NET) of the sequence program (10) to the sequential processing (220) when an output of the sequential processing (220) or the parallel processing (210) is used, except when the acquired portion (NET) of the sequence program (10) can be executed in parallel.(Supplementary Note 9) The program according to the embodiment causes a computer to execute a program acquisition step (S100, S200) of acquiring a sequence program (10) to be executed by a PLC device (60), an extraction step (S22, S24) of extracting, from the acquired sequence program (10), a sequential process (220) including sequential instructions to be executed sequentially and a parallel process (210) including parallel instructions that can be executed in parallel, a sequential process compilation step (S204) of compiling the extracted sequential process (220) into a sequential instruction execution format executable by the PLC device (60), and a parallel process compilation step (S202) of compiling the extracted parallel process into a parallel instruction execution format executable by the PLC device (60).

[0110] 10 Sequence program 2, 5 PLC programming device 200 Program acquisition unit 202 Extraction unit 204 GPU executable command list 210 Parallel processing 212 GPU compilation unit 220 Sequential processing 222 CPU compilation unit 3 Sequence program execution format 30 GPU command execution format 32 CPU command execution format 500 Execution format input unit 60 PLC device 62 Control target device 64 Comparison device

Claims

1. A PLC programming device comprising: a program acquisition unit that acquires a sequence program to be executed by a PLC device; an extraction unit that extracts, from the acquired sequence program, sequential processes including sequential instructions that are executed sequentially and parallel processes including parallel instructions that can be executed in parallel; a sequential processing compilation unit that compiles the extracted sequential processes into a sequential instruction execution format executable by the PLC device; and a parallel processing compilation unit that compiles the extracted parallel processes into a parallel instruction execution format executable by the PLC device.

2. The PLC programming device according to claim 1, wherein the extraction unit extracts the sequential processing, or the sequential processing and the parallel processing, based on a list of parallel executable instructions indicating the parallel instructions.

3. The PLC programming device of claim 1, further comprising: an executable format input unit that accepts an input in an executable format indicating that the sequence program is to be executed in parallel; and wherein the extraction unit extracts the sequential processing and the parallel processing from the sequence program when the executable format input unit accepts an input indicating that the sequence program is to be executed in parallel.

4. The PLC programming device of claim 1, wherein the extraction unit acquires a portion of the accepted sequence program, analyzes the syntax of the acquired portion of the sequence program, and when it is determined as a result of the analysis that the acquired portion of the sequence program can be executed in parallel, adds the acquired portion of the sequence program to the parallel processing, and when it is not determined that the acquired portion of the sequence program can be executed in parallel, adds the acquired portion of the sequence program to the sequential processing.

5. The PLC programming device according to claim 1, wherein the extraction unit acquires a portion of the accepted sequence program, parses the syntax of the acquired portion of the sequence program, and, as a result of the syntax analysis, the acquired portion of the sequence program can be executed in parallel, and when the output of the sequential processing is used, adds the acquired portion of the sequence program to the parallel processing which is processed after the sequential processing.

6. The PLC programming device according to claim 5, wherein the extraction unit adds a portion of the acquired sequence program to the parallel processing when a portion of the acquired sequence program can be executed in parallel and the output of the parallel processing is used or when an output of the sequential processing or the parallel processing is used.

7. The PLC programming device according to claim 1, wherein the extraction unit acquires a portion of the accepted sequence program, performs syntax analysis on the acquired portion of the sequence program, and, when the result of the syntax analysis indicates that the acquired portion of the sequence program can be executed in parallel except when the output of the parallel processing is to be used, adds the acquired portion of the sequence program to the sequential processing which is processed after the parallel processing.

8. The PLC programming device according to claim 7, wherein the extraction unit adds the acquired part of the sequence program to the sequential processing when the output of the sequential processing or the parallel processing is to be used except when the acquired part of the sequence program can be executed in parallel.

9. A program that causes a computer to execute the following steps: a program acquisition step for acquiring a sequence program to be executed by a PLC device; an extraction step for extracting, from the acquired sequence program, sequential processing including sequential instructions that are executed sequentially and parallel processing including parallel instructions that can be executed in parallel; a sequential processing compilation step for compiling the extracted sequential processing into a sequential instruction execution format that can be executed by the PLC device; and a parallel processing compilation step for compiling the extracted parallel processing into a parallel instruction execution format that can be executed by the PLC device.

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