Monolithic interconnected modules (MIMS) thin-film photovoltaic (PV) cells

Abstract

A monolithic interconnected module photovoltaic device can include a plurality of photovoltaic modules arranged in a MIM configuration, each of the photovoltaic modules comprising an epitaxial semiconductor photovoltaic absorber (103) having a bandgap, a back metallization layer (105) comprising an electrically conductive material, and a lateral conduction layer (111), wherein the lateral conduction layer comprises an electrically and thermally conductive material. The back metallization layer (105) can have high reflectivity for wavelengths below the bandgap of the absorber. The high sub-bandgap reflectivity of the back metallization layer (105) and the high thermal conductivity of the lateral conduction layer (111) can facilitate use in high temperature applications, such as thermophotovoltaic applications using a thermophotovoltaic absorber.

Description

MONOLITHIC INTERCONNECTED MODULES (MIMS) THIN-FILM PHOTOVOLTAIC (PV) CELLSRELATED APPLICATION

[0001] This application claims priority to U.S. Provisional Application No. 63 / 507,660, filed June 12, 2023, the entire contents of which is incorporated herein by reference.TECHNICAL FIELD

[0002] Aspects of the present disclosure relate to the field of photovoltaic (PV) and other solar devices. More specifically, embodiments set forth below describe methods of manufacturing monolithic interconnected modules (MIM) involving thin-film photovoltaic (PV) cells.BACKGROUND OF INVENTION

[0003] Conventional methods of manufacturing thin-film photovoltaic (PV) cells typically involve many-step processes, including dicing, and picking and placing, of cells for module assembly. The monolithic interconnected module (MIM) concept generally relies on a thick, heavily-doped lateral conduction layer (LCL). which is typically incompatible with devices having extremely high sub-bandgap reflectivity requirements, such as some applications of PVs. However, MIMs can have substantial benefits for increasing voltages and reducing currents. Thus, methods for applying MIM to thin-film photovoltaic (PV) cells are desirable.SUMMARY

[0004] Some aspects of this disclosure are related to monolithic interconnected modules (MIMs) comprising a plurality of photovoltaic modules arranged in a MIM configuration. In some examples, each of the photovoltaic modules include an epitaxial semiconductor photovoltaic absorber having a bandgap, a back metallization layer comprising an electrically conductive materials, and a lateral conduction layer. The lateral conduction layer can include an electrically and thermally conductive materials.

[0005] The photovoltaic absorber can include a thermophotovoltaic absorber including, for example InGaAs and / or InP.

[0006] In some embodiments, the back metallization layer comprises a material that reflects light having energy below the bandgap of the epitaxial semiconductor photovoltaic absorber, for example, reflecting at least 80% or 90% of such light. This can help reflect energy not absorbed by the photovoltaic absorber. Additionally or alternatively, in some examples, thedevice includes a substrate that supports the plurality of photovoltaic modules, and the substrate can have a suitably high thermal conductivity to allow the device to dissipate heat through the substrate to maintain suitable device operation temperatures. In some cases, a lateral conduction layer separate from the substrate can provide electrical conductivity. In some embodiments, the back metallization layer can provide lateral conduction. In some examples, a high sub-bandgap reflectivity (e.g., in the back metallization layer) and a thermally conductive substrate material operate in conjunction to reduce heating of the device, such as in thermophotovoltaic applications using thermophotovoltaic absorbers.

[0007] Various fabrication techniques, such as a liftoff or other technique, can facilitate growth of high quality epitaxial layer(s) on a growth substrate and subsequent placement of the epitaxial layer(s) onto a suitable substrate which may otherwise make epitaxial growth difficult or impossible. A MIM technique can simplify processing by eliminating the need for dicing and pick and placing of cells for module assembly.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various non-limiting and non-exhaustive aspects and features of the present disclosure are described hereinbelow with references to the drawings, wherein:

[0009] FIGS. 1 A-1F are flow diagrams showing exemplary methods for manufacturing thin- film photovoltaic (PV) cells using monolithic interconnected module (MIM) techniques, in accordance with one or more embodiments.

[0010] FIG. 2 is a top view of the resulting PV cell in FIG. IB, in accordance with one or more embodiments.

[0011] FIG. 3 is a top view7of the PV cells in the process steps in FIG. 1C, respectively, in accordance with one or more embodiments.

[0012] FIG. 4 is a top view of the resulting PV cell in FIG. ID, in accordance with one or more embodiments.

[0013] FIG. 5A-C are flow' diagrams show ing another method for manufacturing thin-film PV cells using MIM techniques, in accordance with one or more embodiments.

[0014] Like reference numbers and designations in the various drawings indicate like elements. Skilled artisans will appreciate that elements in the Figures are illustrated for simplicity' and clarity, and have not necessarily been drawn to scale, for example, with the dimensions of some of the elements in the figures exaggerated relative to other elements to help to improve understanding of various embodiments. Common, well-understood elementsthat are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments.DETAILED DESCRIPTION

[0015] The invention is directed to methods for manufacturing thin-film photovoltaic cells using monolithic interconnected modules techniques. The Figures and the following description describe certain embodiments by way of illustration only. One of ordinary skill in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein. Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying figures.

[0016] The systems and methods described herein disclose techniques for applying MIM techniques in the manufacturing of thin-film photovoltaic (PV) cells (e.g., thermophotovoltaic (TPV), concentrator photovoltaic (CPV), and the like). The monolithic interconnected module (MIM) concept is a lateral multi-junction approach that allows many sub-cells to be interconnected in series in a single sample. This has the benefit of increased voltages and reduced currents. Thin-film cells, including thin-film III-V PV cells (e.g., GaAs or InGaAs absorbers) with highly reflective back contacts have been shown to be capable of very high sub-bandgap reflectivity (Rbbg) and very high efficiency. By taking a thin film architecture having a high Rbbg and bonding the architecture to a thermally suitable substrate, such as a direct bond copper (DBC) or direct plated copper (DPC) board, and patterning the MIM structure by incorporating the DBC or DPC into the process flow, high Rbbg can be maintained while taking advantage of the features of the MIM approach and, in some embodiments, including material properties advantageous for thermophotovoltaic applications. For example, a thermally suitable substrate can provide thermal conduction from a thermophotovoltaic device while the high Rbbg of the device (e.g., via a suitable reflective back contact) can be maintained. Example substrates can include copper (e.g., DBC or DPC), sapphire, and semi-insulating silicon, though other materials are possible. In some cases, a high quality photovoltaic device with high Rbbg is not easily constructed on such substrates. For instance, in an example embodiments, a high quality monocrystalline thermophotovoltaic absorber (e.g., an epitaxial absorber) with a high Rbbg cannot easily be made directly on a substrate having suitable thermal properties for high temperatures encountered in a thermophotovoltaic application. For instance, in some such applications, a substrate having a high thermal conductivity allows the device to dissipate heat through itssubstrate to maintain suitable device operation temperatures. Additionally or alternatively, a high sub-bandgap reflectivity allows energy to be reflected back out from the device and not absorbed into the substrate. In an example thermophotovoltaic application, a high temperature source, such as a heated carbon block or other thermal storage medium radiates energy toward a device with a high sub-bandgap reflectivity (e.g., greater than 80% reflectivity or greater than 90% reflectivity for photons having sub-bandgap energy). Subbandgap photons can be reflected back from the device into its environment and toward the source of the radiation. In some embodiments, the source can absorb the reflected radiation and prolong its ability to emit useful radiation to be absorbed by the device.

[0017] In other examples, such as some non-thermophotovoltaic applications, thermal conductivity is not as important for high efficiency operation, at least partially since the temperature of the operating environment of the device is generally not as high as in thermophotovoltaic applications. In some such examples, a PCB-like substrate can be used in conjunction with a MIM photovoltaic structure. In some examples, a substrate can be used to receive a structure (e.g., an epitaxial photovoltaic structure) such as described herein and patterned into electrically conductive and electrically insulating regions to provide a MIM configuration of photovoltaic modules.

[0018] In an example, applying MIM techniques to a thin-film III / V cell architecture for a TPV module can simplify processing by eliminating the need for dicing and pick and placing of cells for module assembly. In a TPV application, heat conduction out the bottom and back of the TPV devices is important due to the high heat load on the devices, often quantified by thermal insulance (e.g., R-value). A substrate thermal insulance of less than approximately 0.5 K * cm2 / W is preferable for a TPV module. Examples of substrates that meet this criteria include DBC and DPC. Copper (Cu) has a thermal conductivity of approximately 398 lV / (m * If), therefore a 200 pm layer of Copper has a thermal insulance of -0.005 K * cm2 / W. Sapphire (AI2O3) has a thermal conductivity of -25 W / (m * K) therefore a 1 mm thick sapphire wafer has a thermal insulance of -0.4 K * cm2 / W. Silicon (Si) has a thermal conductivity of -150 W / (m * K) at 300 K. therefore a 1 mm thick Si wafer has a thermal insulance of -0.07 K * cm2 / W. Alternatives to sapphire or silicon include Aluminum nitride (AIN), Silicon dioxide (SiCh), Silicon nitride (SisNft, and the like.

[0019] FIGS. 1 A-1E are flow diagrams showing exemplary' methods for manufacturing thin- film photovoltaic (PV) cells using monolithic interconnected module (MIM) techniques, in accordance with one or more embodiments. In FIG. 1A, process flow 100 may begin with growing an epitaxial structure 103 (e.g., an epitaxial layer, device, etc.) onto growth substrate101, forming an epi -wafer. Various techniques for growing the epitaxial structure 103 can be used, including, but not limited to metalorganic vapor phase epitaxy (MOVPE) (also known as metalorganic chemical vapor deposition (MOCVD)), liquid phase epitaxy (LPE), hydride vapor phase epitaxy (HVPE), and molecular beam epitaxy (MBE). In some examples, the epitaxial structure 103 comprises a plurality of epitaxial layers, such as in the form of a junction or other structure.

[0020] Back metallization layer 105 may be deposited onto epitaxial structure 103 afterward. Example techniques for depositing the back metallization layer include sputtering, thermal evaporation, electron beam evaporation, electroplating, and electroless plating. The epitaxial structure 103 may be separated from the growth substrate and resulting intermediate device 107. Such separation may be achieved using substrate etching or dissolution, epitaxial liftoff (ELO), laser liftoff (LLO), sonic liftoff, mechanical fracturing or spalling, and the like. In some examples, the resulting intermediate device 107 comprises an unprocessed device foil, comprising an epitaxially grown device having a metallization layer.

[0021] The MIMS PV cell manufacturing process continues in FIG. IB with process flow102, wherein intermediate device 107 is bonded to a substrate (e.g., DBC, DPC, etc.) comprising a dielectric (e.g., AI2O3, AIN, SiCh, Si.ftS ) layer 113 between two copper layers 111 and 115. In some examples, bonding may be achieved using a die-attach layer 109 comprising die-attach film (DAF) or other die attachment (e.g., solder). In other examples, metallization layer 105 may be bonded metal -to-metal to copper layer 111 without die attach layer 109. Front side cell processing may then be performed, including one or a combination of front metallization, isolation etching, contact etching, and the like, resulting in the addition of front metal contacts 106a- 106c and isolation etching of epitaxial structure 103, back metallization 105, die-attach layer 109, and copper layer 111 into a plurality of rows. The patterned elements in process flow 102 correspond to similarly paterned elements in process flow 100.

[0022] In an example embodiment, one of such a plurality' of rows can include epitaxial structure 103a with a front metal contact 106a and a back metallization layer 105a, and is atached to a copper layer 11 la by a die-atach layer 109a. Similarly, another row can include epitaxial structure 103b having a front metal contact 106b and a back metallization layer 105c, and atached to a copper layer 11 lb by a die-atach layer 109b, and another row can include epitaxial structure 103c having a front metal contact 106c and a back metallization layer 105c. and atached to a copper layer 111c by a die-atach layer 109c. In some examples, the copper layer 111 (e.g., I l la) can provide a lateral conduction layer for such rows, forexample, during operation of a device formed by a corresponding epitaxial structure (e.g., 103a). Additionally or alternatively, back metallization layer (e.g., 105a) can provide high sub-bandgap reflectivity (e.g., greater than 80% or greater than 90%) relative to a bandgap of the epitaxial structure (e.g., for photons having lower energy than a bandgap energy of the epitaxial structure). In some embodiments, a reflectivity percentage corresponds to multiplying a reflectivity curve of the structure with the spectrum of the source of radiation incident on the structure and integrating across all wavelengths of energy lower than the bandgap. In some such examples, the resulting calculated reflectivity is greater than 80%, and in some examples, is greater than 90%. In some embodiments, the bandgap energy used for determining the sub-bandgap reflectivity of the epitaxial structure is a bandgap of an absorber layer of the epitaxial structure. For example, in some embodiments, the epitaxial structure comprises a plurality of layers, and the plurality of layers includes an absorber layer. In some such embodiments, the bandgap of the absorber layer is the relevant bandgap energy for determining the sub-bandgap reflectivity of the epitaxial structure.

[0023] FIG. 2 is a top view of the resulting PV cell in FIG. IB, in accordance with one or more embodiments. The patterned elements in view 200 correspond to similarly patterned elements shown in process flows 101-102. In some examples, a MIM structure is designed such that the left-to-right direction in the top-dow n view' of FIG. 2 corresponds to an into-the- page direction in FIGS. 1A and IB such that epitaxial structures 103a, 103b, and 103c of FIG. IB are aligned as shown in FIG. 2.

[0024] The MIMS PV cell manufacturing process continues in FIG. 1 C with process flow 110, wherein lanes or streets are etched through to dielectric layer 113 (e.g., by photolithography and wet etch, laser ablation, and the like). Interconnects 112a- 112b and insulation 114a- 114b may then be added, insulation 114a- 114b as shown in the streets and interconnects 1 12a-l 12b over insulation 114a-l 14b. In some examples, interconnects 112a- 112b and insulation 114a-l 14b may be deposited by photolithography, deposition, and liftoff. In other examples, interconnects 112a-l 12b and insulation 114a-l 14b may be added by deposition, lithography, and etch. In still other examples, other methods may be used, including direct printing (e.g., inkjetting or screenprinting) of insulation followed by printing of the interconnects.

[0025] Interconnects can include an electrically conductive material, such as copper, silver, or gold, and in various examples, can include metal pastes or inks, such as a silver paste or ink. In some examples, such a paste or ink can comprise an electrically conductive metal with other additives. In some embodiments, insulation 114a-b can include an insulating material,such as, for example, AI2O3, AIN, S1O2, SisN4, SU-8, benzocyclobutene (BCB), polyimide, or other insulating materials, including, for example, printable dielectric materials. Once deposited, insulation 114-114b separates individual epitaxial structures, e.g., 103a and 103b, while interconnects 112a-l 12b provide a series connection between such layer. For example, in the illustrated embodiment, interconnect 112a connects back metallization 105a of epitaxial structure 103a to a front metal contact 106b of epitaxial structure 103b. Such an interconnect places epitaxial structures 103a and 103b in series.

[0026] In some examples, copper layers I l la, 111b, 111c provide electrically conductive lateral conduction layers for the structures in series, while back metallization layers 105a, 105b, 105c provide high sub-bandgap reflectivity.

[0027] FIG. 3 shows top views of the PV cells in the process steps in FIG. 1C, respectively, in accordance with one or more embodiments. View 300 shows the PV cell before adding interconnects 112a-l 12b and insulation 114a-l 14b. View 302 shows the PV cell with interconnects 112a-112b and insulation 114a-114b. The patterned elements in view 300 correspond to similarly patterned elements shown in process flows 101-102 and 110. as well as top view- 200.

[0028] FIG. ID is a flow' diagram illustrating an alternative process for MIMS PV cell manufacturing, in accordance with one or more embodiments. Process flow' 120 continues from process flow 100, and shows an electrically insulating, thermally-conductive substrate 121 (e.g.. AI2O3. Si, etc.) being bonded to device 107. In some examples, bonding may be achieved using a die-attach layer 109 comprising die-attach fdm (DAF) or other die attachment (e.g., solder). In other examples, metallization layer 105 may be bonded to layer 121 without die attach layer 109. Front side cell processing, street etching to substrate layer 121, and addition of insulation 114a-b and interconnects 112a-b, may then be performed as described above.

[0029] FIG. 4 is a top view of the resulting PV cell in FIG. ID, in accordance with one or more embodiments. The patterned elements in view 400 correspond to similarly patterned elements shown in process flows 101-102, 110 and 120, as well as top views 200 and 300- 302. Top view 400 may be the same or similar to top view 302.

[0030] FIG. IE- IF are flow diagrams illustrating another alternative process for MIMS PV cell manufacturing, in accordance with one or more embodiments. Process flow' 130 continues from process flow 100, and shows processing PV device 107, comprising epitaxial structure 103 and metallization layer 105, with a temporary handle (e.g., temporary bond 109 and temporary substrate 131) prior to permanent bonding (e.g., with bond 133 and permanentsubstrate 135). This variant may be useful where permanent bond 133 and / or permanent (i.e., final) substrate 135 are incompatible with a device process flow. In this example, temporary bond 109 (e.g., BrewerBOND® and other temporary bond solutions) may be used to bond to atemporary substrate 131 (e.g., AhOs, Si, etc.) to PV device 107. Front side cell processing may be performed, as described herein, to etch epitaxial structure 103 and add front metal contacts 106a- 106c. Temporary bond 109 and temporary substrate 131 may then be removed and resulting device 107 cleaned in preparation for bonding with a final substrate 135. Permanent substrate 135 may be bonded to resulting device 107 by permanent bond 133 using one or more of the bonding methods described above.

[0031] In FIG. IF, process flow 140 continues from process flow 130, and shows street etching to permanent substrate layer 135, as well as addition of insulation 114a-b and interconnects 1 12a-b, which may be performed as described above. A top view of the resulting PV device would be the same or similar to top views 302 and 400. In some examples, because of electrical characteristics of the substrate 135 and / or bond 133 (e.g., poor electrical conductivity), back metallization layer 105a. 105b, 105c provide electrically conductive lateral conduction layers for epitaxial structures 103a. 103b, 103c and a resulting device with such structures in series.

[0032] FIG. 5A-5C are flow diagrams illustrating another alternative process for MIMS PV cell manufacturing, in accordance with one or more embodiments. The process flow 500 in FIG. 5A may begin with adding (e.g., by depositing, growing, or otherwise forming or placing) a sacrificial layer 202 onto growth substrate 201 which can be performed using various methods. The sacrificial layer 202 may comprise various compounds including, but not limited to, aluminum arsenide, graphene, sodium chloride, porous silicon, silicon dioxide, germanium oxide, or a photoresist. In some examples, the sacrificial layer can be deposited using a technique suitable for depositing an epitaxial layer (e.g., using metalorganic vapor phase epitaxy (MOVPE) (also known as metalorganic chemical vapor deposition (MOCVD)), liquid phase epitaxy (LPE), hydride vapor phase epitaxy (HVPE), and molecular beam epitaxy (MBE)). In some examples, the sacrificial layer can be deposited using the same technique as is used to deposit a subsequent epitaxial layer, such as using the same system. In other examples, ex -situ deposition of graphene, sodium chloride, porous silicon, silicon dioxide, germanium oxide, or a photoresist can form the sacrificial layer.

[0033] Process flow may then continue with growing an epitaxial structure 203 onto sacrificial layer 202 on the growth substrate 201, for example, using epitaxial grow th techniques referenced elsewhere herein. In some examples, the epitaxial structure 203comprises a photovoltaic device, such as a thermophotovoltaic device. Back metallization layer 205 may be deposited onto epitaxial structure 203 afterward, forming an intermediate device 208. As illustrated in FIG. 5A, the intermediate device 208 may be flipped before flow continues to FIG. 5B.

[0034] In FIG. 5B, process flow 520 continues from process flow 500. Process flow 520 starts with bonding an electrically insulating, thermally-conductive module substrate 221 (e.g.. AI2O3, Si, etc.) to the intermediate device 208. In some examples, bonding may be achieved using a bonding layer 209, which can include, for example, a spin-on layer. In various embodiments, bonding layer 209 can include, for example, a die-attach film (DAF), BrewerBOND®, or other die attachment (e.g., solder). In some embodiments, a carbon nanotube- or boron nitride-enhanced benzocyclobutene (BCB) can be used as a die attach polymer in the bonding layer 209. BCB can be an effective dielectric polymer, but with poor thermal conductivity. In some cases, the incorporation of carbon nanotubes or boron nitride into BCB enhances the thermal conductivity of the BCB (in some cases up to 70% compared to typical BCB). In other examples, metallization layer 205 may be bonded to substrate 221 without bonding 209. In some embodiments, the intermediate device 208 is bonded to a substrate (e.g., DBC, DPC, etc.) comprising a dielectric (e.g., AI2O3, AIN, SiCh, Si3N4) layer between two Copper layers (e.g., as illustrated in FIG. IB).

[0035] Process flow 520 may then continue with epitaxial liftoff whereby the grow th substrate 201 is removed from the intermediate device 208. In epitaxial liftoff, the sacrificial layer 202 is chemically removed via selective etching. In an example embodiment, a heated hydrofluoric acid and water mixture (e.g., HF:H2O) to dissolve an aluminum-rich sacrificial layer, such as AlAs. With the sacrificial layer 202 dissolved / etched away, the device comprising the epitaxial structure 203. the back metallization layer 205, the bonding layer 209, and the substrate 221 can be separated from the growth substrate 201. In some examples, using epitaxial liftoff can enable the growth substrate 201 to be re-used. For instance, the growth substrate 201 may be used for creating additional epitaxial layers or devices, such thin-film PV cells following the epitaxial liftoff.

[0036] Process flow 520 may further continue with etching lanes or streets through the epitaxial structure 203 and the back metallization layer 205 to the bonding layer 209 (e.g., by photolithography and w et etching, laser ablation, and the like such as described elsewhere herein). The etching lanes / streets through to the bonding layer 209 separates the epitaxial structure 203 into individual epitaxial structures 203a, 203b, 203c and 203d along with the corresponding individual back metallization layers 205a, 205b, 205c, and 205d. In theillustrated embodiment, the epitaxial structures 203a-203c and the back metallization layers 205a-205c may comprise individual thin-film PV cells with a back metal contact and epitaxial structure 203d and corresponding back metallization layer 205d may comprise a bypass diode. In some examples, multiple rounds of etching are performed such that an epitaxial structure (e.g., 203a) is etched to extend laterally less than a corresponding back metallization layer (e.g., 205a). Such etching may facilitate electrical connection between back metallization layers (e.g.. 205a-205c) and adjacent epitaxial structure (e.g., 203b-203d), for example, to connect several devices in series such as described elsewhere herein. Flow 520 then continues with process flow 540 of FIG. 5C.

[0037] In FIG. 5C. process flow 540 continues with selective etching of the epitaxial structure 203d (e.g., that comprises part of a bypass diode). In some examples, the amount of selective etching, and the resulting thickness and shape of the epitaxial structure 203d can be selected for suitable device characteristics. For example, a tapered profile of layer 203d with an appropriate thickness of insulation or dielectric can be used to make sure there is no break, crack, etc. in the deposited metal layer making contact between isolated cells. Such tapering can be included in one or more of epitaxial structures 203a-c.

[0038] Process flow 540 further continues with adding insulation 214a, 214b, 214c in the streets / lanes between the separated epitaxial and / or back metallization layers. In the illustrated embodiment, the insulation does not entirely cover the individual back metallization layers in the streets / lanes such that at least a portion of the back metallization layer(s) (e g., 205a, 205b, 205c) are accessible for subsequent contact.

[0039] Process flow 540 continues with adding front metal contacts 206a, 206b, 206c on top of the insulation 214a-214c and portions of the epitaxial structures 203b-203d. The front metal contacts 206a-206c may contact back metallization layers 205a-205c to provide a series connection between a back metallization layer of one row with an epitaxial structure of another row. For example, in the illustrated embodiment, front metal contact 206a connects back metallization 205a of epitaxial structure 203a to the top of epitaxial structure 203b. Such a connection places epitaxial structures 203a and 203b in series. In some embodiments, such as shown in FIG. 5C, front metal contacts 206a-c can also act as interconnects connecting the back metal of one row and a front side of an epitaxial structure of an adjacent row.

[0040] In some optional examples, the process flow 540 may further continue with depositing an anti-reflective coating 219 on top of various layers of the monolithic interconnected module (MIM). For instance, in an example embodiment, the anti-reflective coating 219 may be deposited on top of epitaxial structures 203a-203c comprisingphotovoltaic devices (e.g., TPV devices), but not on a bypass diode comprising epitaxial structure 203d. In some examples, the anti-reflective coating also covers, either partially or entirely, epitaxial structure 203d, for example, comprising a bypass diode. In some embodiments, the anti -reflective coating 219 covers every part of the device, including areas of back metallization layer 205 not otherwise covered by insulation 214 or contacts 206. Various anti-reflective coatings can be used. In some embodiments, any dielectric material with low absorption in visible and infrared wavelengths can be used as an anti-reflective coating, including, for example, SiO2, TiO2, Si3N4, SiNx, SiOxNy (silicon oxynitride), MgF2, ZnS, A12O3, ITO, HfO2, YF3, BaF2, LaB6, Nb2O5, Ta2O5, Na3AlF6, ZrO2, TiN, TaN, SignalSeal, Parylene, Parylene-C, silicones, and others.

[0041] The process of performing epitaxial liftoff (ELO). as outlined in FIG. 5A-5C. may provide certain advantages. For instance, ELO can provide a cost-effective w ay to defray the cost of the growth substrate. The back metallization layer 205 may be used in connecting epitaxial structure (e g., 203a-203c) in series (e.g., by electrically connecting to front metal contacts 206 providing electrical communication with an adjacent epitaxial structure), as well as function as lateral conduction layers. For instance, in some examples, after an ELO process and after the intermediate device 208 is attached to the substrate 221 (e.g., via bonding layer 209), the substrate 221 and / or bonding layer 209 is not suitable for serving as a lateral conduction layer (e.g., due to insufficient electrical conductivity). In some such examples, back metallization layer 205 can provide lateral conduction for epitaxial structures 203a-c supported by substrate 221 .

[0042] Various example processes and devices are described. In some examples, steps described herein can be used to construct a high quality photovoltaic MIM device on a substrate suitable for the desired application of the MIM device, even if the substrate is not itself conducive to having a high quality photovoltaic device grown directly thereon. For example, in some embodiments, an epitaxial thermophotovoltaic absorber can be positioned on a substrate including a copper layer that provides desired thermal, optical, and / or electrical characteristics, even if the epitaxial thermophotovoltaic absorber could not be easily grown directly on the copper layer. For example, in some cases, a high temperature substrate is required for growing a high quality epitaxial semiconductor structure. How ever, if growing directly on a copper or other metallic substrate, such a high temperature could cause the metal to diffuse during deposition of the semiconductor, w hich can lead to impurities in the semiconductor structure and / or an amorphous or polycrystalline semiconductor structure having lower efficiency in photovoltaic applications compared to high quality crystallinestructures. In addition, to achieve high quality epitaxial semiconductor device structures, it is often advantageous to grow on a single crystalline substrate such that the grown layers can inherit the same crystal lattice structure as the growth substrate. For example, single crystal Ino.53Gao.47As is often grown on InP substrates. However, while in some cases, such substrates are useful for growing high quality devices, the substrate may prove unsuitable for some use applications of the device. Techniques described herein can provide high quality MIM PV devices on suitable substrates for the desired PV application (e.g., TPV applications).

[0043] To facilitate an understanding of the subject matter described herein, many aspects are described in terms of sequences of actions. The description herein of any sequence of actions is not intended to imply that the specific order described for performing that sequence must be followed. All methods described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context.

[0044] The use of the terms “a” and “an” and “the” and similar references in the context of describing the subject matter (particularly in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The use of the term “at least one” followed by a list of one or more items (for example, “at least one of A and B”) is to be construed to mean one item selected from the listed items (A or B) or any combination of two or more of the listed items (A and B), unless otherwise indicated herein or clearly contradicted by context. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation, as the scope of protection sought is defined by the claims as set forth hereinafter together with any equivalents thereof. The use of any and all examples, or exemplary- language (e.g., “such as”) provided herein, is intended merely to better illustrate the subject matter and does not pose a limitation on the scope of the subject matter unless otherwise claimed. The use of the term “based on” and other like phrases indicating a condition for bringing about a result, both in the claims and in the w ritten description, is not intended to foreclose any other conditions that bring about that result. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention as claimed.

[0045] While specific examples have been provided above, it is understood that the present invention can be applied with a wide variety of inputs, thresholds, ranges, and other factors, depending on the application. For example, the time frames and ranges provided above areillustrative, but one of ordinary skill in the art would understand that these time frames and ranges may be varied or even be dynamic and variable, depending on the implementation.

[0046] As those skilled in the art will understand, a number of variations may be made in the disclosed embodiments, all without departing from the scope of the invention, which is defined solely by the appended claims. It should be noted that although the features and elements are described in particular combinations, each feature or element can be used alone without other features and elements or in various combinations with or without other features and elements. The methods or flow charts provided may be implemented in a computer program, software, or firmware tangibly embodied in a computer-readable storage medium for execution by a general-purpose computer or processor.

Claims

CLAIMS1. A monolithic interconnected module (MIM) photovoltaic device comprising: a plurality of photovoltaic modules arranged in a MIM configuration, each of the photovoltaic modules comprising: an epitaxial semiconductor photovoltaic absorber having a bandgap; a back metallization layer comprising an electrically conductive material; and a lateral conduction layer, wherein the lateral conduction layer comprises an electrically and thermally conductive material.

2. The device of claim 1, wherein the photovoltaic absorber comprises a thermophotovoltaic absorber and each of the plurality of photovoltaic modules comprises a thermophotovoltaic module.

3. The device of claim 2, wherein the epitaxial semiconductor thermophotovoltaic absorber comprises InGaAs and / or InP.

4. The device of either of claims 1 or 2, further comprising a substrate configured to support the plurality of photovoltaic modules.

5. The device of claim 4, wherein the lateral conduction layer comprises at least a portion of the substrate.

6. The device of claim 5, wherein the substrate comprises at least one copper layer and at least one dielectric, and wherein the at least one copper layer is etched to include a plurality of rows, each row supporting one of the plurality of photovoltaic modules and providing a lateral conduction layer therefor.

7. The device of claim 4, wherein the lateral conduction layer does not comprise part of the substrate.

8. The device of claim 7, wherein the back metallization layer forms the lateral conduction layer.

9. The device of claim 4, wherein the substrate comprises sapphire.

10. The device of claim 4, wherein the substrate comprises silicon.

11. The device of either of claims 1 or 2, wherein the lateral conduction layer has a thermal insulance of less than 0.5 Kcm2 / W.

12. The device of either of claims 1 or 2, wherein the back metallization layer comprises a material that reflects at least 80% of light having energy below the bandgap of the epitaxial semiconductor photovoltaic absorber.

13. The device of claim 12, wherein the back metallization layer comprises a material that reflects at least 90% of light having energy below the bandgap of the epitaxial semiconductor photovoltaic absorber.

14. The device of either of claims 12 or 13 wherein the epitaxial photovoltaic absorber forms an absorber layer of a multi-layer epitaxial structure.

15. The device of either of claims 1 or 2, wherein the back metallization layer of at least one photovoltaic module is coupled to the lateral conduction layer of the at least one photovoltaic module.

16. The device of claim 15, wherein the at least one photovoltaic module is coupled to the lateral conduction layer via an attachment layer.

17. The device of either of claims 1 or 2 , further comprising an anti-reflective coating deposited on top of at least a portion of the epitaxial semiconductor photovoltaic absorber.

18. The device of either of claims 1 or 2, wherein: the plurality of photovoltaic modules comprises a first photovoltaic module and a second photovoltaic module; andthe second photovoltaic module comprises a front contact electrically separated from the back metallization layer of the first photovoltaic module; and wherein the device further comprises: an interconnect made from an electrically conductive material and providing electrical communication between the back metallization layer of the first photovoltaic module and the front contact of the second photovoltaic module such that the first photovoltaic module and the second photovoltaic module are connected in series.

19. The device of claim 18, wherein the first photovoltaic module and the second photovoltaic module are separated by an insulative material.

20. The device of claim 18, wherein the plurality of photovoltaic modules comprises at least three photovoltaic modules connected in series.

21. The device of either of claims 1 or 2, wherein the lateral conduction layer of at least one of the plurality of photovoltaic modules comprises a metal.

22. The device of claim 21, wherein the lateral conduction layer of at least one of the plurality of photovoltaic modules comprises copper.

23. The device of claim 22, wherein: the plurality of photovoltaic modules comprises a first photovoltaic module and a second photovoltaic module connected in series; the lateral conduction layer of each of the first photovoltaic module and the second photovoltaic module comprises a first copper layer, a dielectric layer, and a second copper layer, the dielectric layer being positioned between and separating the first copper layer and the second copper layer, each of the first and second photovoltaic modules being coupled to the first copper layer of the lateral conduction layer; the dielectric layer is continuous between the first and second photovoltaic module; and the first copper layer is not continuous between the first and second photovoltaic module.

24. The device of either of claims 1 or 2, wherein the epitaxial semiconductor photovoltaic absorber of each of the plurality of photovoltaic modules comprises the same material;the back metallization layer of each of the plurality of photovoltaic modules comprises the same material.

25. The device of either of claims 1 or 2, wherein the plurality of photovoltaic modules comprises a first photovoltaic module and a second photovoltaic module, the second photovoltaic module comprising a second epitaxial semiconductor photovoltaic absorber; and wherein the device further comprises: a front contact comprising an electrically conductive material electrically connecting the back metallization layer of the first photovoltaic module and the second epitaxial semiconductor photovoltaic absorber such that the first photovoltaic module and the second photovoltaic module are connected in series.

26. The device of either of claims 1 or 2, wherein the epitaxial semiconductor photovoltaic absorber is a monocrystalline absorber.

27. A method for manufacturing monolithic interconnected module (MIM) thin-film photovoltaic (PV) cells, comprising: growing an epitaxial photovoltaic absorber on a growth substrate; adding a back metallization layer onto the epitaxial photovoltaic absorber; separating the epitaxial photovoltaic absorber from the growth substrate, thereby leaving an intermediate device comprising the epitaxial photovoltaic absorber and the back metallization layer; bonding the intermediate device to a substrate such that the back metallization layer is bonded to the substrate; etching the epitaxial photovoltaic absorber into a plurality of rows to form a corresponding plurality of epitaxial photovoltaic modules; adding one or more front metal contacts, including at least one front metal contact for each of the plurality of rows; etching one or more lanes through the back metallization layer between the plurality of rows; adding insulation in the one or more lanes; and adding interconnects over the insulation, the interconnects providing an electrical communication between a front metal contact of a first row of the plurality of rows and a back metallization layer of a second row of the plurality of rows such that theepitaxial photovoltaic module corresponding to the first row and epitaxial photovoltaic module corresponding to the second row are connected in series.

28. The method of claim 27, wherein: the substrate comprises a first copper layer, a second copper layer, and a dielectric layer positioned between the first copper layer and the second copper layer; and bonding the device to the substrate comprises bonding the device to the first copper layer of the substrate.

29. The method of claim 28, fiirther comprising etching one or more lanes through the first copper layer aligned with the one or more lanes etched through the back metallization layer.

30. The method of claim 29, wherein etching one or more lanes through the back metallization layer and etching the one or more lanes through the first copper layer aligned with the one or more lanes etched through the back metallization layer are performed via the same etching process.

31. The method of claim 27, wherein: bonding the intermediate device to the substrate comprises bonding the intermediate device to a temporary substrate; wherein the etching the epitaxial photovoltaic absorber is performed after bonding the intermediate device to the temporary substrate; and the method further comprises removing the temporary substrate after etching the epitaxial photovoltaic absorber but before etching the back metallization layer; and attaching the back metallization layer to a permanent substrate.

32. The method of claim 31, wherein the etching the one or more lanes through the back metallization layer and the adding the insulation in the one or more lanes are each performed after attaching the back metallization layer to the permanent substrate.

33. The method of claim 32, wherein the adding the one or more front metal contacts is performed before removing the temporary substrate.

34. The method of claim 27, wherein: the epitaxial photovoltaic absorber comprises a semiconductor material having a bandgap; and the back metallization layer comprises a material that reflects at least 90% of light having energy below the bandgap of the epitaxial photovoltaic absorber.

35. The method of claim 34, wherein the epitaxial photovoltaic absorber comprises InGaAs and / or InP.

36. The method of any of claims 27 - 35, wherein the epitaxial photovoltaic absorber comprises an epitaxial thermophotovoltaic absorber such that the plurality of epitaxial photovoltaic modules comprises a plurality of epitaxial thermophotovoltaic devices.

37. The method of claim 27 further comprising adding an anti-reflective coating over at least a portion of the epitaxial photovoltaic modules.

38. A method for manufacturing monolithic interconnected module (MIM) thin-film photovoltaic (PV) cells, comprising: depositing a sacrificial layer on a growth substrate; growing an epitaxial photovoltaic absorber on the sacrificial layer; adding a back metallization layer onto the epitaxial photovoltaic absorber, thereby leaving an intermediate device comprising the growth substrate, the sacrificial layer, the epitaxial photovoltaic absorber, and the back metallization layer attached to the growth substrate via the sacrificial layer; bonding the intermediate device to a module substrate such that the back metallization layer is bonded to the module substrate; after bonding the intermediate device to the module substrate, separating the epitaxial photovoltaic absorber from the growth substrate by etching the sacrificial layer; after etching the sacrificial layer to separate the epitaxial photovoltaic absorber from the growth substrate, etching the epitaxial photovoltaic absorber into a plurality of rows to form a corresponding plurality of epitaxial photovoltaic modules; etching one or more lanes through the back metallization layer between the plurality of rows; adding insulation in the one or more lanes; andadding contacts over the insulation, the contacts providing an electrical communication between a back metallization layer of a first row of the plurality of rows and an epitaxial photovoltaic absorber layer of a second row of the plurality of rows such that the epitaxial photovoltaic module corresponding to the first row and epitaxial photovoltaic module corresponding to the second row are connected in series.

39. The method of claim 38, further comprising adding an anti-reflective coating over one or more of the contacts and at least a portion of the epitaxial photovoltaic modules.

40. The method of claim 38, wherein growing the epitaxial photovoltaic absorber on the sacrificial layer comprises growing an epitaxial thermophotovoltaic absorber on the sacrificial layer.

41. The method of claim 40, wherein the back metallization layer comprises a material that reflects at least 80% of light having energy below a bandgap of the epitaxial thermophotovoltaic absorber.

42. The method of claim 41, wherein the back metallization layer comprises a material that reflects at least 90% of light having energy below the bandgap of the epitaxial thermophotovoltaic absorber.

43. The method of claim 38, further comprising adding a bonding layer to the module substrate and wherein bonding the intermediate device to the module substrate such that the back metallization layer is bonded to the module substrate comprises attaching the back metallization layer to the bonding layer.

44. The method of claim 43, wherein the bonding layer comprises carbon nanotube- or boron nitride-enhanced benzocyclobutene (BCB).

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