Display substrate and display apparatus

Abstract

A display substrate, comprising: a substrate, multiple first pixel circuits, multiple second pixel circuits, multiple third pixel circuits and multiple fourth pixel circuits, and further comprising multiple first reset connecting lines, multiple second reset connecting lines and multiple third reset connecting lines, the reset connecting lines being electrically connected to the pixel circuits, respectively; reset signal voltages inputted on the first reset connecting lines and the second reset connecting lines are lower than a reset signal voltage inputted on the third reset connecting lines; the difference between the reset signal voltages inputted on the first reset connecting lines and the second reset connecting lines is smaller than a set value; orthographic projections of the first reset connecting lines and the second reset connecting lines onto the substrate are located in different repeating units between orthographic projections of the first pixel circuits and the second pixel circuits onto the substrate; and orthographic projections of the third reset connecting lines onto the substrate are located in repeating units between orthographic projections of the third pixel circuits and the fourth pixel circuits onto the substrate.

Description

Display substrate and display device Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and particularly relate to a display substrate and a display device. Background Art

[0002] Currently, electroluminescent display products are becoming increasingly important in the display industry, especially OLED (Organic Light-Emitting Diode) displays, which have been widely promoted and applied in recent years due to their advantages such as high color gamut, bendability, and fast response time.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising: a base,

[0005] A plurality of first pixel circuits, a plurality of second pixel circuits, a plurality of third pixel circuits, and a plurality of fourth pixel circuits are located on one side of the substrate and arranged in an array;

[0006] The first pixel circuit, the second pixel circuit, and the third pixel circuit are respectively configured to drive sub-pixels of different colors, and the second pixel circuit and the fourth pixel circuit are respectively configured to drive sub-pixels of the same color.

[0007] The first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit are arranged in sequence along a first direction and form a repeating unit.

[0008] A plurality of the repeating units are arranged sequentially along the first direction;

[0009] It also includes a plurality of first reset connection lines, a plurality of second reset connection lines and a plurality of third reset connection lines,

[0010] The first reset connection line, the second reset connection line, and the third reset connection line are electrically connected to any one of the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit, respectively.

[0011] The first reset connection line, the second reset connection line, and the third reset connection line extend along a second direction respectively, and the first direction intersects the second direction.

[0012] The reset signal voltages inputted to the first reset connection line and the second reset connection line are smaller than the reset signal voltage inputted to the third reset connection line.

[0013] The difference between the reset signal voltages inputted on the first reset connection line and the reset signal voltage inputted on the second reset connection line is smaller than a set value.

[0014] The orthographic projections of the first reset connection line and the second reset connection line on the substrate are located between the orthographic projections of the first pixel circuit and the second pixel circuit on the substrate in different repeating units.

[0015] The orthographic projection of the third reset connection line on the substrate is located between the orthographic projections of the third pixel circuit and the fourth pixel circuit on the substrate in the repeating unit.

[0016] In some embodiments, the first pixel circuit and the second pixel circuit in the repeating unit are mirror-symmetrical with the first reset connection line as the symmetry axis.

[0017] And / or, the first pixel circuit and the second pixel circuit in the repeating unit are mirror-symmetrical with the second reset connection line as the symmetry axis,

[0018] And / or, the third pixel circuit and the fourth pixel circuit in the repeating unit are mirror-symmetrical with the third reset connection line as the axis of symmetry.

[0019] In some embodiments, in any two adjacent repeating units, the first reset connection line, the third reset connection line, the second reset connection line, and the third reset connection line are sequentially arranged along the first direction.

[0020] In some embodiments, in any two adjacent repeating units, the third reset connection line, the first reset connection line, the third reset connection line, and the second reset connection line are arranged in sequence along the first direction.

[0021] In some embodiments, in any two adjacent repeating units, the third reset connection line, the second reset connection line, the third reset connection line, and the first reset connection line are arranged in sequence along the first direction.

[0022] In some embodiments, in any two adjacent repeating units, the second reset connection line, the third reset connection line, the first reset connection line, and the third reset connection line are arranged in sequence along the first direction.

[0023] In some embodiments, the repeating unit comprises a first repeating unit, a second repeating unit, and a third repeating unit,

[0024] The first repeating unit, the third repeating unit and the second repeating unit are arranged in sequence along the first direction,

[0025] The third reset connection line and the first reset connection line in the first repeating unit are arranged in sequence along the first direction,

[0026] The third reset connection line and the second reset connection line in the second repeating unit are arranged in sequence along the first direction,

[0027] In the third repeating unit, the first reset connection line, the second reset connection line and the third reset connection line are not distributed,

[0028] There is at least one third repeating unit between the first repeating unit and the second repeating unit.

[0029] In some embodiments, the repeating unit comprises a first repeating unit, a second repeating unit, and a third repeating unit,

[0030] The first repeating unit, the third repeating unit and the second repeating unit are arranged in sequence along the first direction,

[0031] The third reset connection line and the second reset connection line in the first repeating unit are arranged in sequence along the first direction,

[0032] The third reset connection line and the first reset connection line in the second repeating unit are arranged in sequence along the first direction,

[0033] In the third repeating unit, the first reset connection line, the second reset connection line and the third reset connection line are not distributed,

[0034] There is at least one third repeating unit between the first repeating unit and the second repeating unit.

[0035] In some embodiments, the repeating unit comprises a first repeating unit, a second repeating unit, and a third repeating unit,

[0036] The first repeating unit, the third repeating unit and the second repeating unit are arranged in sequence along the first direction,

[0037] The first reset connection line and the third reset connection line in the first repeating unit are arranged in sequence along the first direction,

[0038] The second reset connection line and the third reset connection line in the second repeating unit are arranged in sequence along the first direction,

[0039] In the third repeating unit, the first reset connection line, the second reset connection line and the third reset connection line are not distributed,

[0040] There is at least one third repeating unit between the first repeating unit and the second repeating unit.

[0041] In some embodiments, the repeating unit comprises a first repeating unit, a second repeating unit, and a third repeating unit,

[0042] The first repeating unit, the third repeating unit and the second repeating unit are arranged in sequence along the first direction,

[0043] The second reset connection line and the third reset connection line in the first repeating unit are arranged in sequence along the first direction,

[0044] The first reset connection line and the third reset connection line in the second repeating unit are arranged in sequence along the first direction,

[0045] In the third repeating unit, the first reset connection line, the second reset connection line and the third reset connection line are not distributed,

[0046] There is at least one third repeating unit between the first repeating unit and the second repeating unit.

[0047] In some embodiments, the system further includes a plurality of first reset signal lines, a plurality of second reset signal lines, and a plurality of third reset signal lines.

[0048] The first reset signal line, the second reset signal line and the third reset signal line extend along the first direction respectively.

[0049] The plurality of first reset signal lines are arranged in sequence along the second direction,

[0050] The plurality of second reset signal lines are arranged sequentially along the second direction,

[0051] The plurality of third reset signal lines are arranged sequentially along the second direction,

[0052] The orthographic projections of the first reset signal line, the second reset signal line, and the third reset signal line on the substrate do not overlap,

[0053] The first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit located in the same row are electrically connected to one first reset signal line, one second reset signal line, and one third reset signal line respectively;

[0054] The plurality of first reset signal lines intersect with the orthographic projections of the plurality of first reset connection lines on the substrate and are electrically connected at the intersection position.

[0055] The plurality of second reset signal lines intersect with the orthographic projections of the plurality of second reset connection lines on the substrate and are electrically connected at the intersection position.

[0056] The plurality of third reset signal lines intersect with orthographic projections of the plurality of third reset connection lines on the substrate, and are electrically connected at the intersection positions.

[0057] In some embodiments, the plurality of first reset signal lines are located on the same layer.

[0058] The plurality of second reset signal lines are located on the same layer,

[0059] The plurality of third reset signal lines are located on the same layer,

[0060] The plurality of first reset connection lines, the plurality of second reset connection lines, and the plurality of third reset connection lines are located in the same layer, and are different from the first reset signal line, the second reset signal line, and the third reset signal line.

[0061] In some embodiments, the plurality of first reset signal lines spatially intersect with the plurality of first reset connection lines, and are electrically connected at the spatial intersection position through a first via hole provided in the insulating layer between the two.

[0062] The plurality of second reset signal lines spatially intersect with the plurality of second reset connection lines, and are electrically connected at the spatial intersection position through a second via hole provided in the insulating layer between the two.

[0063] The plurality of third reset signal lines spatially intersect with the plurality of third reset connection lines, and are electrically connected at the spatial intersection position through a third via hole opened in the insulation layer between the two.

[0064] In some embodiments, at least two of the first reset signal line, the second reset signal line, and the third reset signal line are located in different layers.

[0065] In some embodiments, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are further included.

[0066] The first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are stacked in sequence away from the substrate,

[0067] The fourth conductive layer includes patterns of the first reset connection line, the second reset connection line, and the third reset connection line.

[0068] The third conductive layer includes a pattern of the third reset signal line;

[0069] The second conductive layer includes a pattern of the second reset signal line;

[0070] The first conductive layer includes a pattern of the first reset signal line.

[0071] In some embodiments, the substrate further includes a camera hole, wherein the orthographic projection of the camera hole on the substrate is located in the display area.

[0072] Part of the first reset signal line, part of the second reset signal line and part of the third reset signal line extending through the camera hole are disconnected at the camera hole position, and the orthographic projection of part of the first reset signal line, part of the second reset signal line and part of the third reset signal line extending through the camera hole on the substrate does not overlap with the orthographic projection of the camera hole on the substrate.

[0073] In some embodiments, part of the first reset connection line, part of the second reset connection line and part of the third reset connection line extending through the camera hole are disconnected at the camera hole position, and the orthographic projection of part of the first reset connection line, part of the second reset connection line and part of the third reset connection line extending through the camera hole on the substrate does not overlap with the orthographic projection of the camera hole on the substrate.

[0074] In some embodiments, the first reset signal line, the second reset signal line, and the third reset signal line extend from the display area to the first side frame area and the second side frame area, respectively.

[0075] The first side frame area and the second side frame area are opposite to each other and arranged along the first direction;

[0076] The display substrate further includes a first reset signal source, a second reset signal source, and a third reset signal source, all of which are located in the first side frame area and the second side frame area;

[0077] The two ends of the first reset signal line located in the first side frame area and the second side frame area are electrically connected to the first reset signal source respectively.

[0078] The two ends of the second reset signal line located in the first side frame area and the second side frame area are electrically connected to the second reset signal source respectively.

[0079] Two ends of the third reset signal line located in the first side frame area and the second side frame area are electrically connected to the third reset signal source respectively.

[0080] In some embodiments, the first reset connection line, the second reset connection line, and the third reset connection line extend from the display area to the third side frame area and / or the fourth side frame area, respectively.

[0081] The third side frame area and the fourth side frame area are opposite to each other and arranged along the second direction;

[0082] The display substrate further includes a first reset signal source, a second reset signal source and a third reset signal source, all of which are located in the third side frame area and / or the fourth side frame area;

[0083] One end of the first reset connection line located in the third side frame area and / or the fourth side frame area is electrically connected to the first reset signal source,

[0084] One end of the second reset connection line located in the third side frame area and / or the fourth side frame area is electrically connected to the second reset signal source,

[0085] One end of the third reset connection line located in the third side frame area and / or the fourth side frame area is electrically connected to the third reset signal source.

[0086] In some embodiments, the first pixel circuit is configured to drive a red sub-pixel or a blue sub-pixel.

[0087] The second pixel circuit and the fourth pixel circuit are configured to drive a green sub-pixel,

[0088] The third pixel circuit is configured to drive a blue sub-pixel or a red sub-pixel.

[0089] In a second aspect, an embodiment of the present disclosure further provides a display device, which includes the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0091] FIG. 1 a is a circuit diagram of a pixel driving circuit of an OLED display panel in the related art.

[0092] FIG1 b is a top view schematic diagram of the distribution of the Vinit3 reset signal line in the display panel in the related art.

[0093] FIG. 1 c is a schematic diagram showing a luminous hole Mura defect in a display panel in the related art.

[0094] FIG1d is a schematic diagram showing a gradual change in the luminous brightness of a light-emitting element in an extension area of ​​a reset signal line Vinit3 that is disconnected on the right side of a camera hole in the related art.

[0095] FIG. 1e is a schematic diagram of a dark hole Mura defect occurring in a display panel in the related art.

[0096] FIG. 1f is a diagram showing the brightness of the display area of ​​the OLED display panel driven by the pixel driving circuit in FIG. 1a .

[0097] FIG. 2 a is a schematic top view of the structure of a display substrate according to an embodiment of the present disclosure.

[0098] FIG2b is an enlarged view of portion A in FIG2a.

[0099] FIG. 2 c is a schematic top view of another structure of a display substrate according to an embodiment of the present disclosure.

[0100] FIG. 2 d is a schematic top view of the structure of another display substrate in an embodiment of the present disclosure.

[0101] FIG. 2e is a schematic top view of the structure of another display substrate according to an embodiment of the present disclosure.

[0102] FIG3 a is a schematic cross-sectional view of the structure at the sub-pixel position in a display substrate according to an embodiment of the present disclosure.

[0103] FIG3 b is a schematic top view showing the active layer pattern in the substrate according to an embodiment of the present disclosure.

[0104] FIG. 3 c is a schematic top view showing a first conductive layer pattern in a substrate according to an embodiment of the present disclosure.

[0105] FIG. 3 d is a schematic top view showing a second conductive layer pattern in a substrate according to an embodiment of the present disclosure.

[0106] FIG. 3 e is a schematic top view showing a third conductive layer pattern in a substrate according to an embodiment of the present disclosure.

[0107] FIG. 3 f is a schematic top view showing a fourth conductive layer pattern in a substrate according to an embodiment of the present disclosure.

[0108] FIG. 3 g is a schematic top view of a fifth conductive layer pattern in a substrate according to an embodiment of the present disclosure.

[0109] FIG3h is a schematic top view showing the fourth conductive layer and anode patterns in the substrate according to an embodiment of the present disclosure.

[0110] FIG. 4 a is a schematic top view of the structure of another display substrate according to an embodiment of the present disclosure.

[0111] FIG4 b is a schematic top view of the structure of another display substrate in an embodiment of the present disclosure.

[0112] FIG. 4 c is a schematic top view of the structure of another display substrate according to an embodiment of the present disclosure.

[0113] FIG4 d is a schematic top view of the structure of another display substrate in an embodiment of the present disclosure.

[0114] FIG5 is a schematic top view of the structure of another display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0115] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a display substrate and a display device provided by the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific implementation plans.

[0116] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully enable those skilled in the art to understand the scope of this disclosure.

[0117] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions, but are not intended to be limiting.

[0118] In order to better achieve flicker-free refresh rate switching of OLED (Organic Light-Emitting Diode) display panels and enhance the end-user experience of using OLED panels, referring to FIG1a, there is a circuit diagram of a pixel driving circuit of an OLED display panel in the related art. The 8T1C pixel driving circuit in FIG1a is an LTPO (Low Temperature Polycrystalline Oxide) circuit. LTPO technology combines the advantages of traditional LTPS TFT and oxide TFT technologies, and has the advantages of high mobility, low leakage current, and excellent reliability. Its minimum refresh rate can reach 1Hz, and it is highly adaptable.

[0119] The 8T1C (8 transistors and one capacitor) pixel driver circuit in Figure 1a adds a transistor (T8) to the 7T1C (7 transistors and one capacitor) pixel driver circuit. Furthermore, the 8T1C pixel driver circuit in Figure 1a adds a reset function for the anode of light-emitting element D, effectively reducing flickering during display panel switching. The 8T1C pixel driver circuit has three sets of Vinit reset voltages. Vinit1 is a negative voltage used to reset the gate of driver transistor T3; Vinit2 is a negative voltage used to reset the anode of light-emitting element D; and Vinit3 is a positive voltage used to reset the gate of driver transistor T3 and node N3. These three Vinit reset voltages are provided to the display panel by a reset power supply IC.

[0120] Referring to Figure 1b, a top view schematically illustrates the distribution of the Vinit3 reset signal line in a display panel according to related art. A camera hole 21 (i.e., a camera mounting hole) is provided in the display panel. Because camera hole 21 is cut into a through hole, no pixels are located in the area where camera hole 21 is located. The portion of the Vinit3 reset signal line that extends past camera hole 21 is disconnected there. In this way, the pixels near the camera hole 21 are at the end of the Vinit3 reset signal line, and the Vinit3 reset signal line near the camera hole 21 is far away from the Vinit3 reset power chip (IC) and is driven by a single-sided reset power supply instead of a double-sided reset power supply. As a result, the Vinit3 reset signal on the Vinit3 reset signal line near the camera hole 21 is easily affected by other voltage jumps. The Vinit3 reset signal line that does not extend through the camera hole 21 is not disconnected, so the Vinit3 reset signal line that does not extend through the camera hole 21 is still driven by a double-sided reset power supply. The Vinit3 reset signal on this part of the Vinit3 reset signal line is not easily affected by other voltage jumps, resulting in an increase in the display brightness at the camera hole 21 on the display panel, resulting in a bright hole Mura defect. Referring to Figure 1c, it is a schematic diagram of a bright hole Mura defect occurring on a display panel in the related art.

[0121] In related art, referring to Figure 1a, the change in the Vinit3 reset signal on the Vinit3 reset signal line near the camera aperture is believed to be driven by the voltage of the reset signal Reset H in the gate shift register circuit (i.e., the GOA circuit) during the shutdown process. The reset signal Reset H momentarily pulls the Vinit3 reset signal high during the shutdown process. The pulled-up Vinit3 reset signal writes a higher voltage to the N2 and N3 nodes during the shutdown process of transistor T8. During the activation of the lighting control signal EM, the charge stored in the N3 node flows to the N4 node. The higher the voltage at the N3 node, the higher the voltage at the N4 node in its initial state when the lighting control signal EM is activated, and the faster the lighting process of the light-emitting element D (i.e., the pixel) is.

[0122] In addition, referring to FIG1b and FIG1c, when the camera hole 21 is an offset hole (ie, the camera mounting hole is not in the middle of the display area), the length of the disconnected Vinit3 reset signal line extending to the right of the camera hole 21 is longer, and the load of the Vinit3 reset signal line itself is greater. During the H shutdown process, the voltage is pulled higher, so the light-emitting elements (i.e., pixels) in the extended area of ​​the disconnected Vinit3 reset signal line on the right side of the camera aperture 21 emit relatively bright light. Furthermore, the closer to the right edge of the display area, the smaller the difference in load between the disconnected Vinit3 reset signal line on the right side of the camera aperture 21 and the Vinit3 reset signal line in other areas of the display area. Therefore, the light-emitting elements (i.e., pixels) in the extended area of ​​the disconnected Vinit3 reset signal line on the right side of the camera aperture 21 exhibit a gradual change in brightness. The brightness of the light-emitting elements gradually decreases from the Vinit3 disconnection point to the right edge of the display area. The significant difference in load between the Vinit3 reset signal line in the camera aperture 21 and the Vinit3 reset signal line in other areas of the display area results in a significant difference in the turn-on speed of the light-emitting elements (i.e., pixels). Refer to Figures 1c and 1d. Figure 1d is a schematic diagram illustrating the gradual change in brightness of the light-emitting elements in the extended area of ​​the disconnected Vinit3 reset signal line on the right side of the camera aperture in the related art. This uneven brightness of the camera aperture mura is difficult to resolve using algorithmic compensation in the driver circuit.

[0123] In the related art, in order to solve the bright hole Mura defect at the camera mounting hole position on the display panel, the various Vinit reset signal lines extending through the camera hole position are no longer disconnected. Instead, the various Vinit reset signal lines extending through the camera hole position are connected together through a circle of metal traces surrounding the camera hole. However, this arrangement also causes dark hole Mura defect at the camera hole position. Referring to Figure 1e, there is a schematic diagram of dark hole Mura defect occurring in the display panel in the related art.

[0124] In addition, in the related art, referring to FIG1f, there is shown an effect diagram of the display brightness of the display area of ​​the OLED display panel driven by the pixel driving circuit in FIG1a; it can be seen that the display brightness of the left and right edge areas BB1 of the display area BB of the display panel (i.e., the opposite sides of the display area arranged in sequence along the extension direction of the Vinit reset signal line) is significantly lower than the display brightness of the middle area BB2 of the display area, and this is particularly obvious in the low grayscale state. For example, at 2nitL32 (i.e., 32 grayscale brightness under 2nit display brightness), the display brightness of the left and right edge areas BB1 of the display area is significantly lower than the display brightness of the middle area BB2 of the display area. The phenomenon is more obvious; its occurrence mechanism is consistent with the occurrence mechanism of hole Mura: that is, the luminous area is in the middle area BB2 of the display area, and the Vinit3 reset signal line of the left and right edge areas BB1 of the display area is further away from its reset power chip (IC), so that the Vinit3 reset signal on the Vinit3 reset signal line in the middle area BB2 of the display area is more easily affected by the reset signal Reset in the gate shift register circuit (i.e., GOA circuit). During the shutdown process, the voltage of H increases, causing the light-emitting elements (i.e., pixels) in the center area BB2 of the display area to illuminate, while the light-emitting elements in the left and right edge areas BB1 of the display area appear relatively dim. Furthermore, the brightness of the light-emitting elements gradually decreases from the center area BB2 to the left and right edge areas BB1 of the display area. This uneven brightness between the center and edge areas of the display area cannot be corrected by using the algorithm in the driver circuit to compensate.

[0125] In order to solve the problem of uneven display brightness in different areas of a display area existing in the related art, an embodiment of the present disclosure provides a display substrate. Referring to Figures 2a and 2b, Figure 2a is a schematic top view of the structure of a display substrate in an embodiment of the present disclosure; Figure 2b is an enlarged view of part A in Figure 2a; wherein, the display substrate includes: a substrate, a plurality of first pixel circuits 1, a plurality of second pixel circuits 2, a plurality of third pixel circuits 3 and a plurality of fourth pixel circuits 4, which are located on one side of the substrate and arranged in an array; the first pixel circuit 1, the second pixel circuit 2 and the third pixel circuit 3 are respectively configured to drive sub-pixels of different colors, and the second pixel circuit 2 and the fourth pixel circuit 4 are respectively configured to drive sub-pixels of the same color, and the first pixel circuit 1, the second pixel circuit 2, the third pixel circuit 3 and the fourth pixel circuit 4 are arranged in sequence along a first direction X and constitute a repeating unit 100, and the plurality of repeating units 100 are arranged in sequence along the first direction X.

[0126] The display substrate also includes a plurality of first reset connection lines V1, a plurality of second reset connection lines V2, and a plurality of third reset connection lines V3. The first reset connection lines V1, the second reset connection lines V2, and the third reset connection lines V3 are electrically connected to any one of the first pixel circuit 1, the second pixel circuit 2, the third pixel circuit 3, and the fourth pixel circuit 4, respectively. The first reset connection lines V1, the second reset connection lines V2, and the third reset connection lines V3 extend along the second direction Y, respectively. The first direction X intersects the second direction Y. The reset signal voltage input to the first reset connection line V1 and the second reset connection line V2 is less than the reset signal voltage input to the third reset connection line V3. The difference between the reset signal voltages input to the first reset connection line V1 and the second reset connection line V2 is less than a set value.

[0127] The orthographic projections of the first reset connection line V1 and the second reset connection line V2 on the substrate are located between the orthographic projections of the first pixel circuit 1 and the second pixel circuit 2 on the substrate in different repeating units 100, and the orthographic projection of the third reset connection line V3 on the substrate is located between the orthographic projections of the third pixel circuit 3 and the fourth pixel circuit 4 on the substrate in the repeating unit 100.

[0128] In some embodiments, referring to FIG. 3 a , a schematic cross-sectional view of a sub-pixel structure of a display substrate in an embodiment of the present disclosure is shown; sub-pixel 5 is an organic electroluminescent element (i.e., an OLED element). The organic electroluminescent element includes an anode 51 , a light-emitting functional layer 52 , and a cathode 53 stacked in a direction away from a substrate 6 . 3a, 3b, 3c, 3d, 3e, 3f and 3g, FIG3b is a schematic top view of an active layer pattern in a display substrate according to an embodiment of the present disclosure; FIG3c is a schematic top view of a first conductive layer pattern in a display substrate according to an embodiment of the present disclosure; FIG3d is a schematic top view of a second conductive layer pattern in a display substrate according to an embodiment of the present disclosure; FIG3e is a schematic top view of a third conductive layer pattern in a display substrate according to an embodiment of the present disclosure; FIG3f is a schematic top view of a fourth conductive layer pattern in a display substrate according to an embodiment of the present disclosure; FIG3g is a schematic top view of a fifth conductive layer pattern in a display substrate according to an embodiment of the present disclosure; the display substrate further comprises an active layer 7, a first conductive layer 8, a second conductive layer 9, a third conductive layer 10, a fourth conductive layer 11 and a second conductive layer 12 located between the substrate 6 and the anode 51 and stacked in sequence in a direction away from the substrate 6. A buffer layer 13 is further provided between the active layer 7 and the substrate 6, a first gate insulating layer 14 is provided between the active layer 7 and the first conductive layer 8, a second gate insulating layer 15 is provided between the first conductive layer 8 and the second conductive layer 9, a third gate insulating layer 16 is provided between the second conductive layer 9 and the third conductive layer 10, an intermediate dielectric layer 17 is provided between the third conductive layer 10 and the fourth conductive layer 11, a first flat layer 18 is provided between the fourth conductive layer 11 and the fifth conductive layer 12, a second flat layer 19 is provided between the fifth conductive layer 12 and the anode 51, and a pixel defining layer 20 is further provided on the side of the anode 51 facing away from the substrate 6, an opening is provided in the pixel defining layer 20, the anode 51 is exposed at the opening, and the light-emitting functional layer 52 and the cathode 53 are at least partially located in the opening.

[0129] In some embodiments, referring to Figures 3b, 3c, 3d, 3e, 3f and 3g, the first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit are circuits formed by connecting transistors and capacitors. The active layer 7 includes active layer patterns of transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit; the first conductive layer 8 includes patterns of gates, gate lines and gate lines of some transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit, as well as patterns of the lower plate of the capacitor; the second conductive layer 9 includes patterns of gates, gate lines and gate lines of some transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit, as well as patterns of the upper plate of the capacitor; the third conductive layer 10 includes patterns of gates, gate lines and gate lines of some transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit; the fourth conductive layer 11 includes patterns of sources, drains and some vias of transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit; the fifth conductive layer 12 includes patterns of data lines Data and some power lines (such as VDD, VSS, Vgh, Vgl, etc.) that are electrically connected to the first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit respectively.

[0130] In some embodiments, referring to FIG3h , which is a top view schematic diagram of a fourth conductive layer and anode patterns in a display substrate according to an embodiment of the present disclosure; the first pixel circuit 1 is configured to drive a red sub-pixel 501 or a blue sub-pixel 503, the third pixel circuit 3 is configured to drive a blue sub-pixel 503 or a red sub-pixel 501, and the second pixel circuit 2 and the fourth pixel circuit 4 are both configured to drive a green sub-pixel 502. Referring to FIG3h , FIG2a , and FIG2b , in an array formed by a plurality of first pixel circuits 1, a plurality of second pixel circuits 2, a plurality of third pixel circuits 3, and a plurality of fourth pixel circuits 4, a pixel unit 500 is formed by one red sub-pixel 501, one blue sub-pixel 503, and two green sub-pixels 502 driven by one first pixel circuit 1, one second pixel circuit 2, one third pixel circuit 3, and one fourth pixel circuit 4 adjacent in the row direction (i.e., the first direction X) and also adjacent in the column direction (i.e., the second direction Y).

[0131] In some embodiments, the reset signal voltages input to the first reset connection line V1 and the second reset connection line V2 are both negative voltages, and the reset signal voltages input to the first reset connection line V1 and the second reset connection line V2 are close to -3V±1v; the difference between the reset signal voltages input to the first reset connection line V1 and the second reset connection line V2 is less than 2V; the difference between the reset signal voltages input to the first reset connection line V1 and the second reset connection line V2 can be 0V; the reset signal voltage input to the third reset connection line V3 is +7V.

[0132] In this embodiment, by positioning the orthographic projections of the first reset connection line V1 and the second reset connection line V2 on the substrate between the orthographic projections of the first pixel circuit 1 and the second pixel circuit 2 in different repeating units 100, and positioning the orthographic projection of the third reset connection line V3 on the substrate between the orthographic projections of the third pixel circuit 3 and the fourth pixel circuit 4 in the repeating unit 100 on the substrate, it is possible to ensure uniformity of the loads of the first pixel circuit 1 and the second pixel circuit 2 within the repeating unit 100, and simultaneously ensure uniformity of the loads of the third pixel circuit 3 and the fourth pixel circuit 4 within the repeating unit 100. This ensures uniformity of the loads of the first pixel circuit 1 and the second pixel circuit 2 within the same row of repeating units 100 arranged along the first direction X, and ensures uniformity of the loads of the third pixel circuit 3 and the fourth pixel circuit 4 within the same row of repeating units 100 arranged along the first direction X, thereby ensuring uniformity of display brightness of the display substrate and improving the display effect of the display substrate.

[0133] In some embodiments, referring to Figures 2a and 2b, the first pixel circuit 1 and the second pixel circuit 2 in the repeating unit 100 are mirror-symmetrical with the first reset connection line V1 as the symmetry axis, and / or, the first pixel circuit 1 and the second pixel circuit 2 in the repeating unit 100 are mirror-symmetrical with the second reset connection line V2 as the symmetry axis, and / or, the third pixel circuit 3 and the fourth pixel circuit 4 in the repeating unit 100 are mirror-symmetrical with the third reset connection line V3 as the symmetry axis.

[0134] Such an arrangement can ensure the symmetry of the loads of the first pixel circuit 1 and the second pixel circuit 2 within the repeating unit 100, while also ensuring the symmetry of the loads of the third pixel circuit 3 and the fourth pixel circuit 4 within the repeating unit 100, thereby ensuring the uniformity of the loads of the first pixel circuit 1 and the second pixel circuit 2 within the same row of repeating units 100 arranged along the first direction X, and ensuring the uniformity of the loads of the third pixel circuit 3 and the fourth pixel circuit 4 within the same row of repeating units 100 arranged along the first direction X. This avoids the occurrence of vertical stripes during display in an array of sub-pixels 5 composed of sub-pixels 5 of different colors driven by different pixel circuits in a pixel circuit array formed by a plurality of first pixel circuits 1, a plurality of second pixel circuits 2, a plurality of third pixel circuits 3, and a plurality of fourth pixel circuits 4, thereby ensuring the uniformity of the display brightness of the display substrate and improving the display effect of the display substrate.

[0135] In some embodiments, referring to FIG. 2 a , in any two adjacent repeating units 100 , the first reset connection line V1 , the third reset connection line V3 , the second reset connection line V2 , and the third reset connection line V3 are sequentially arranged along the first direction X. That is, along the first direction X, the first reset connection line V1 , the second reset connection line V2 , and the third reset connection line V3 are arranged in a periodicity of V1 - V3 - V2 - V3 .

[0136] In some embodiments, referring to FIG. 2 c , which is a schematic top view of another display substrate structure in an embodiment of the present disclosure, in any two adjacent repeating units 100 , the third reset connection line V3 , the first reset connection line V1 , the third reset connection line V3 , and the second reset connection line V2 are sequentially arranged along the first direction X. That is, along the first direction X, the arrangement period of the first reset connection line V1 , the second reset connection line V2 , and the third reset connection line V3 is V3 - V1 - V3 - V2 .

[0137] In some embodiments, referring to FIG. 2 d , which is a schematic top view of another display substrate structure in an embodiment of the present disclosure, in any two adjacent repeating units 100 , the third reset connection line V3 , the second reset connection line V2 , the third reset connection line V3 , and the first reset connection line V1 are sequentially arranged along the first direction X. That is, along the first direction X, the arrangement period of the first reset connection line V1 , the second reset connection line V2 , and the third reset connection line V3 is V3 - V2 - V3 - V1 .

[0138] In some embodiments, referring to FIG. 2e , which is a schematic top view of another display substrate structure in an embodiment of the present disclosure, in any two adjacent repeating units 100 , the second reset connection line V2 , the third reset connection line V3 , the first reset connection line V1 , and the third reset connection line V3 are sequentially arranged along the first direction X. That is, along the first direction X, the arrangement period of the first reset connection line V1 , the second reset connection line V2 , and the third reset connection line V3 is V2 - V3 - V1 - V3.

[0139] In some embodiments, referring to Figure 4a, a schematic top view of the structure of another display substrate in an embodiment of the present disclosure is shown; the repeating unit 100 includes a first repeating unit 101, a second repeating unit 102, and a third repeating unit 103. The first repeating unit 101, the third repeating unit 103, and the second repeating unit 102 are arranged in sequence along the first direction X. The third reset connection line V3 and the first reset connection line V1 in the first repeating unit 101 are arranged in sequence along the first direction X. The third reset connection line V3 and the second reset connection line V2 in the second repeating unit 102 are arranged in sequence along the first direction X. In the third repeating unit 103, the first reset connection line, the second reset connection line, and the third reset connection line are not distributed. There is at least one third repeating unit 103 between the first repeating unit 101 and the second repeating unit 102.

[0140] In some embodiments, referring to FIG. 4 a , a third repeating unit 103 is spaced between the first repeating unit 101 and the second repeating unit 102 , that is, along the first direction X, the arrangement period of the first reset connection line V1 , the second reset connection line V2 , and the third reset connection line V3 is V3 - V1 - none - none - V3 - V2 .

[0141] In some embodiments, referring to Figure 4b, which is a schematic top view of the structure of another display substrate in an embodiment of the present disclosure; the repeating unit 100 includes a first repeating unit 101, a second repeating unit 102, and a third repeating unit 103. The first repeating unit 101, the third repeating unit 103, and the second repeating unit 102 are arranged in sequence along the first direction X. The third reset connection line V3 and the second reset connection line V2 in the first repeating unit 101 are arranged in sequence along the first direction X. The third reset connection line V3 and the first reset connection line V1 in the second repeating unit 102 are arranged in sequence along the first direction X. In the third repeating unit 103, the first reset connection line, the second reset connection line, and the third reset connection line are not distributed. There is at least one third repeating unit 103 between the first repeating unit 101 and the second repeating unit 102.

[0142] In some embodiments, referring to FIG. 4 b , a third repeating unit 103 is spaced between the first repeating unit 101 and the second repeating unit 102 , that is, along the first direction X, the arrangement period of the first reset connection line V1 , the second reset connection line V2 , and the third reset connection line V3 is V3 - V2 - none - none - V3 - V1 .

[0143] In some embodiments, referring to Figure 4c, which is a schematic top view of the structure of another display substrate in an embodiment of the present disclosure; the repeating unit 100 includes a first repeating unit 101, a second repeating unit 102, and a third repeating unit 103. The first repeating unit 101, the third repeating unit 103, and the second repeating unit 102 are arranged in sequence along the first direction X. The first reset connection line V1 and the third reset connection line V3 in the first repeating unit 101 are arranged in sequence along the first direction X, the second reset connection line V2 and the third reset connection line V3 in the second repeating unit 102 are arranged in sequence along the first direction X, and the first reset connection line, the second reset connection line, and the third reset connection line in the third repeating unit 103 are not distributed. There is at least one third repeating unit 103 between the first repeating unit 101 and the second repeating unit 102.

[0144] In some embodiments, referring to FIG. 4 c , a third repeating unit 103 is spaced between the first repeating unit 101 and the second repeating unit 102 , that is, along the first direction X, the arrangement period of the first reset connection line V1 , the second reset connection line V2 , and the third reset connection line V3 is V1 - V3 - none - none - V2 - V3 .

[0145] In some embodiments, referring to Figure 4d, a schematic top view of the structure of another display substrate in an embodiment of the present disclosure is shown; the repeating unit 100 includes a first repeating unit 101, a second repeating unit 102, and a third repeating unit 103. The first repeating unit 101, the third repeating unit 103, and the second repeating unit 102 are arranged in sequence along the first direction X. The second reset connection line V2 and the third reset connection line V3 in the first repeating unit 101 are arranged in sequence along the first direction X. The first reset connection line V1 and the third reset connection line V3 in the second repeating unit 102 are arranged in sequence along the first direction X. In the third repeating unit 103, the first reset connection line, the second reset connection line, and the third reset connection line are not distributed. There is at least one third repeating unit 103 between the first repeating unit 101 and the second repeating unit 102.

[0146] In some embodiments, referring to FIG. 4 d , a third repeating unit 103 is spaced between the first repeating unit 101 and the second repeating unit 102 , that is, along the first direction X, the arrangement period of the first reset connection line V1 , the second reset connection line V2 , and the third reset connection line V3 is V2 - V3 - none - none - V1 - V3 .

[0147] In some embodiments, referring to Figures 2a to 2e and Figures 4a to 4d, the display substrate further includes a plurality of first reset signal lines V1', a plurality of second reset signal lines V2', and a plurality of third reset signal lines V3'. The first reset signal lines V1', the second reset signal lines V2, and the third reset signal lines V3' extend respectively along the first direction X. The plurality of first reset signal lines V1' are sequentially arranged along the second direction Y, the plurality of second reset signal lines V2' are sequentially arranged along the second direction Y, and the plurality of third reset signal lines V3' are sequentially arranged along the second direction Y. The orthographic projections of the first reset signal lines V1', the second reset signal lines V2', and the third reset signal lines V3' on the substrate do not overlap.

[0148] The first pixel circuit 1, the second pixel circuit 2, the third pixel circuit 3 and the fourth pixel circuit 4 located in the same row are electrically connected to a first reset signal line V1', a second reset signal line V2' and a third reset signal line V3' respectively; the multiple first reset signal lines V1' intersect with the orthographic projections of the multiple first reset connection lines V1 on the substrate and are electrically connected at the intersection position, the multiple second reset signal lines V2' intersect with the orthographic projections of the multiple second reset connection lines V2 on the substrate and are electrically connected at the intersection position, and the multiple third reset signal lines V3' intersect with the orthographic projections of the multiple third reset connection lines V3 on the substrate and are electrically connected at the intersection position.

[0149] In some embodiments, multiple first reset signal lines V1' are located on the same layer, multiple second reset signal lines V2' are located on the same layer, multiple third reset signal lines V3' are located on the same layer, multiple first reset connection lines V1, multiple second reset connection lines V2 and multiple third reset connection lines V3 are located on the same layer and are on a different layer from the first reset signal lines V1', the second reset signal lines V2' and the third reset signal lines V3'.

[0150] In some embodiments, referring to Figures 2a to 2e, 3h and 4a to 4d, multiple first reset signal lines V1' spatially intersect with multiple first reset connection lines V1, and are electrically connected at the spatial intersection position through a first via P1 provided in the insulating layer between the two; multiple second reset signal lines V2' spatially intersect with multiple second reset connection lines V2, and are electrically connected at the spatial intersection position through a second via P2 provided in the insulating layer between the two; multiple third reset signal lines V3' spatially intersect with multiple third reset connection lines V3, and are electrically connected at the spatial intersection position through a third via P3 provided in the insulating layer between the two.

[0151] Through the above-mentioned arrangement, multiple first reset signal lines V1' are connected to multiple first reset connection lines V1 to form a mesh; multiple second reset signal lines V2' are connected to multiple second reset connection lines V2 to form a mesh; multiple third reset signal lines V3' are connected to multiple third reset connection lines V3 to form a mesh. With such an arrangement, the reset signal on any reset signal line or reset connection line at any position in the display area of ​​the display substrate becomes more uniform, thereby improving or avoiding the reset signal on any reset signal line or reset connection line at any position in the display area of ​​the display substrate being affected by the pulling effect of other jump voltage signals, that is, the uniformity of the pull-resistance of any reset signal line or reset connection line at any position in the display area of ​​the display substrate can be improved, thereby improving the uniformity of the luminous brightness at different positions in the display area of ​​the display substrate, and improving the display effect of the display substrate.

[0152] In some embodiments, the plurality of first reset connection lines V1, the plurality of second reset connection lines V2, and the plurality of third reset connection lines V3 may also be located on different layers. In some embodiments, the first reset connection line V1 and the first reset signal line V1' may be located on the same layer, the second reset connection line V2 and the second reset signal line V2' may be located on the same layer, and the third reset connection line V3 and the third reset signal line V3' may be located on the same layer.

[0153] In some embodiments, at least two of the first reset signal line V1 ′, the second reset signal line V2 ′, and the third reset signal line V3 ′ are located in different layers.

[0154] In some embodiments, referring to Figures 3c, 3d, 3e, 3f and 3h, the display substrate further includes a first conductive layer 8, a second conductive layer 9, a third conductive layer 10 and a fourth conductive layer 11. The first conductive layer 8, the second conductive layer 9, the third conductive layer 10 and the fourth conductive layer 11 are stacked in sequence away from the substrate 6. The fourth conductive layer 11 includes patterns of the first reset connection line V1, the second reset connection line V2 and the third reset connection line V3. The third conductive layer 10 includes a pattern of the third reset signal line V3'; the second conductive layer 9 includes a pattern of the second reset signal line V2'; and the first conductive layer 8 includes a pattern of the first reset signal line V1'.

[0155] In some embodiments, the second conductive layer 9 includes patterns of a second reset signal line V2 ′ and a first reset signal line V1 ′ (not shown).

[0156] In some embodiments, refer to Figure 5, which is a schematic top view of the structure of another display substrate in an embodiment of the present disclosure; the display substrate also includes a camera hole 21, and the orthographic projection of the camera hole 21 on the substrate is located in the display area BB, and part of the first reset signal line V1', part of the second reset signal line V2' and part of the third reset signal line V3' extending through the camera hole 21 are disconnected at the position of the camera hole 21, and the orthographic projection of the part of the first reset signal line V1', part of the second reset signal line V2' and part of the third reset signal line V3' extending through the camera hole 21 on the substrate does not overlap with the orthographic projection of the camera hole 21 on the substrate.

[0157] In some embodiments, the camera hole 21 is used to install a camera, and the camera hole 21 runs through the entire display substrate. No sub-pixels are set in the camera hole 21 area, so part of the first reset signal line V1', part of the second reset signal line V2' and part of the third reset signal line V3' extending through the camera hole 21 are disconnected at the camera hole 21 position.

[0158] In some embodiments, referring to Figure 5, part of the first reset connection line V1, part of the second reset connection line V2 and part of the third reset connection line V3 extending through the camera hole 21 are disconnected at the camera hole 21, and the orthographic projection of the part of the first reset connection line V1, part of the second reset connection line V2 and part of the third reset connection line V3 extending through the camera hole 21 on the substrate does not overlap with the orthographic projection of the camera hole 21 on the substrate.

[0159] In this embodiment, multiple first reset signal lines V1' are connected to multiple first reset connection lines V1 to form a mesh; multiple second reset signal lines V2' are connected to multiple second reset connection lines V2 to form a mesh; and multiple third reset signal lines V3' are connected to multiple third reset connection lines V3 to form a mesh. This allows the reset signal line or reset connection line disconnected at the camera hole 21 within the display area BB of the display substrate to be affected by the pull of other jump voltage signals and dispersed to the entire mesh of reset signal lines and reset connection lines. This makes the reset signal on any reset signal line or reset connection line at any position within the display area BB of the display substrate more uniform, thereby improving or preventing the reset signal on any reset signal line or reset connection line at any position within the display area of ​​the display substrate from being affected by the pull of other jump voltage signals. This improves the uniformity of the pull resistance of any reset signal line or reset connection line at any position within the display area of ​​the display substrate, ultimately improving the uniformity of the luminous brightness at different positions within the display area of ​​the display substrate and improving the display effect of the display substrate.

[0160] In some embodiments, referring to Figure 5, the first reset signal line V1', the second reset signal line V2' and the third reset signal line V3' extend from the display area BB to the first side frame area BK1 and the second side frame area BK2 respectively, and the first side frame area BK1 and the second side frame area BK2 are opposite to each other and arranged along the first direction X; the display substrate also includes a first reset signal source 22, a second reset signal source 23 and a third reset signal source 24, all of which are located in the first side frame area BK1 and the second side frame area BK2; the two ends of the first reset signal line V1' located in the first side frame area BK1 and the second side frame area BK2 are respectively electrically connected to the first reset signal source 22, the two ends of the second reset signal line V2' located in the first side frame area BK1 and the second side frame area BK2 are respectively electrically connected to the second reset signal source 23, and the two ends of the third reset signal line V3' located in the first side frame area BK1 and the second side frame area BK2 are respectively electrically connected to the third reset signal source 24.

[0161] In some embodiments, referring to Figure 5, the first reset connection line V1, the second reset connection line V2 and the third reset connection line V3 extend from the display area BB to the third side frame area BK3 and / or the fourth side frame area BK4 respectively, and the third side frame area BK3 and the fourth side frame area BK4 are opposite to each other and arranged along the second direction Y; the display substrate also includes a first reset signal source 22, a second reset signal source 23 and a third reset signal source 24, all of which are located in the third side frame area BK3 and / or the fourth side frame area BK4; one end of the first reset connection line V1 located in the third side frame area BK3 and / or the fourth side frame area BK4 is electrically connected to the first reset signal source 22, one end of the second reset connection line V2 located in the third side frame area BK3 and / or the fourth side frame area BK4 is electrically connected to the second reset signal source 23, and one end of the third reset connection line V3 located in the third side frame area BK3 and / or the fourth side frame area BK4 is electrically connected to the third reset signal source 24.

[0162] In this embodiment, by electrically connecting each reset signal line and reset connection line to different reset signal sources located in the first side frame area BK1, the second side frame area BK2, the third side frame area BK3 and the fourth side frame area BK4, respectively, the reset signal source can be provided to each reset signal line and reset connection line from the surrounding frame areas at the same time, so that the load difference between the reset signal line or reset connection line disconnected at the camera hole 21 and the load difference between the reset signal line or reset connection line in other areas of the display area BB is greatly reduced, thereby improving or eliminating the difference in the luminous brightness of the light-emitting element at the camera hole 21 and the luminous brightness of the light-emitting element in other areas of the display area BB, and at the same time improving or eliminating the difference in the luminous brightness of the light-emitting element in the middle area and the edge area of ​​the display area BB, thereby improving the uniformity of the luminous brightness at different positions in the display area BB of the display substrate, and improving the display effect of the display substrate.

[0163] In some embodiments, each reset signal source can be distributed only in the first side frame area BK1 and the second side frame area BK2, thereby increasing the wiring space of the third side frame area BK3 and the fourth side frame area BK4, or reducing the width of the third side frame area BK3 and the fourth side frame area BK4.

[0164] In some embodiments, each reset signal source may be distributed only in the third side frame area BK3 or the fourth side frame area BK4 , thereby increasing the wiring space of the other three side frame areas or reducing the width of the other three side frame areas.

[0165] The display substrate provided by the embodiments of the present disclosure ensures uniformity of the loads of the first pixel circuits 1 and the second pixel circuits 2 within the repeating unit 100, and also ensures uniformity of the loads of the third pixel circuits 3 and the fourth pixel circuits 4 within the repeating unit 100, by positioning the orthographic projections of the first reset connection line V1 and the second reset connection line V2 on the substrate between the orthographic projections of the first pixel circuits 1 and the second pixel circuits 2 within different repeating units 100, and positioning the orthographic projection of the third reset connection line V3 on the substrate between the orthographic projections of the third pixel circuits 3 and the fourth pixel circuits 4 within the repeating unit 100. This ensures uniformity of the loads of the first pixel circuits 1 and the second pixel circuits 2 within the repeating unit 100, and also ensures uniformity of the loads of the third pixel circuits 3 and the fourth pixel circuits 4 within the repeating unit 100. This ensures uniformity of the display brightness of the display substrate, thereby improving the display effect of the display substrate.

[0166] An embodiment of the present disclosure further provides a display device, comprising the display substrate in the above embodiment.

[0167] By adopting the display substrate in the above embodiment, it is possible to ensure the uniformity of the load of the first pixel circuit and the second pixel circuit in the same row of repeating units arranged along the first direction, and to ensure the uniformity of the load of the third pixel circuit and the fourth pixel circuit in the same row of repeating units arranged along the first direction, thereby ensuring the uniformity of the display brightness of the display device and improving the display effect of the display device.

[0168] The display panel provided in the embodiments of the present disclosure may be any product or component with a display function, such as an OLED panel, an OLED TV, an OLED billboard, a display, a mobile phone, or a navigation device.

[0169] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, wherein: include: Base, A plurality of first pixel circuits, a plurality of second pixel circuits, a plurality of third pixel circuits and a plurality of fourth pixel circuits are located on one side of the substrate and arranged in an array; The first pixel circuit, the second pixel circuit and the third pixel circuit are respectively configured to drive sub-pixels of different colors, and the second pixel circuit and the fourth pixel circuit are respectively configured to drive sub-pixels of the same color. The first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit are arranged in sequence along a first direction and constitute a repeating unit. A plurality of the repeating units are arranged in sequence along the first direction; Also includes a plurality of first reset connection lines, a plurality of second reset connection lines and a plurality of third reset connection lines, The first reset connection line, the second reset connection line and the third reset connection line are electrically connected to any one of the first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit, respectively. The first reset connection line, the second reset connection line and the third reset connection line extend along a second direction respectively, and the first direction intersects the second direction. The reset signal voltages input to the first reset connection line and the second reset connection line are smaller than the reset signal voltage input to the third reset connection line. The difference between the reset signal voltages inputted to the first reset connection line and the reset signal voltage inputted to the second reset connection line is smaller than a set value. The orthographic projections of the first reset connection line and the second reset connection line on the substrate are located between the orthographic projections of the first pixel circuit and the second pixel circuit on the substrate in different repeating units. The orthographic projection of the third reset connection line on the substrate is located between the orthographic projections of the third pixel circuit and the fourth pixel circuit on the substrate in the repeating unit.

2. The display substrate according to claim 1, wherein: The first pixel circuit and the second pixel circuit in the repeating unit are mirror-symmetrical with the first reset connection line as the symmetry axis. and / or, the first pixel circuit and the second pixel circuit in the repeating unit are mirror-symmetric with the second reset connection line as a symmetry axis, And / or, the third pixel circuit and the fourth pixel circuit in the repeating unit are mirror-symmetric with the third reset connection line as a symmetry axis.

3. The display substrate according to claim 1, wherein: In any two adjacent repeating units, the first reset connection line, the third reset connection line, the second reset connection line and the third reset connection line are arranged in sequence along the first direction.

4. The display substrate according to claim 1, wherein: In any two adjacent repeating units, the third reset connection line, the first reset connection line, the third reset connection line and the second reset connection line are arranged in sequence along the first direction.

5. The display substrate according to claim 1, wherein: In any two adjacent repeating units, the third reset connection line, the second reset connection line, the third reset connection line and the first reset connection line are arranged in sequence along the first direction.

6. The display substrate according to claim 1, wherein: In any two adjacent repeating units, the second reset connection line, the third reset connection line, the first reset connection line and the third reset connection line are arranged in sequence along the first direction.

7. The display substrate according to claim 1, wherein: The repeating unit comprises a first repeating unit, a second repeating unit and a third repeating unit, The first repeating unit, the third repeating unit and the second repeating unit are arranged in sequence along the first direction, The third reset connection line and the first reset connection line in the first repeating unit are arranged in sequence along the first direction, The third reset connection line and the second reset connection line in the second repeating unit are arranged in sequence along the first direction, In the third repeating unit, the first reset connection line, the second reset connection line and the third reset connection line are not distributed, At least one third repeating unit is spaced between the first repeating unit and the second repeating unit.

8. The display substrate according to claim 1, wherein: The repeating unit comprises a first repeating unit, a second repeating unit and a third repeating unit, The first repeating unit, the third repeating unit and the second repeating unit are arranged in sequence along the first direction, The third reset connection line and the second reset connection line in the first repeating unit are arranged in sequence along the first direction, The third reset connection line and the first reset connection line in the second repeating unit are arranged in sequence along the first direction, In the third repeating unit, the first reset connection line, the second reset connection line and the third reset connection line are not distributed, At least one third repeating unit is spaced between the first repeating unit and the second repeating unit.

9. The display substrate according to claim 1, wherein: The repeating unit comprises a first repeating unit, a second repeating unit and a third repeating unit, The first repeating unit, the third repeating unit and the second repeating unit are arranged in sequence along the first direction, The first reset connection line and the third reset connection line in the first repeating unit are arranged in sequence along the first direction, The second reset connection line and the third reset connection line in the second repeating unit are arranged in sequence along the first direction, In the third repeating unit, the first reset connection line, the second reset connection line and the third reset connection line are not distributed, At least one third repeating unit is spaced between the first repeating unit and the second repeating unit.

10. The display substrate according to claim 1, wherein: The repeating unit comprises a first repeating unit, a second repeating unit and a third repeating unit, The first repeating unit, the third repeating unit and the second repeating unit are arranged in sequence along the first direction, The second reset connection line and the third reset connection line in the first repeating unit are arranged in sequence along the first direction, The first reset connection line and the third reset connection line in the second repeating unit are arranged in sequence along the first direction, In the third repeating unit, the first reset connection line, the second reset connection line and the third reset connection line are not distributed, At least one third repeating unit is spaced between the first repeating unit and the second repeating unit.

11. The display substrate according to any one of claims 1 to 10, wherein: Also includes a plurality of first reset signal lines, a plurality of second reset signal lines and a plurality of third reset signal lines, The first reset signal line, the second reset signal line and the third reset signal line extend along the first direction respectively. The plurality of first reset signal lines are arranged in sequence along the second direction, The plurality of second reset signal lines are arranged in sequence along the second direction, The plurality of third reset signal lines are arranged in sequence along the second direction, The orthographic projections of the first reset signal line, the second reset signal line and the third reset signal line on the substrate do not overlap, The first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit located in the same row are electrically connected to one first reset signal line, one second reset signal line and one third reset signal line respectively; The plurality of first reset signal lines intersect with the orthographic projections of the plurality of first reset connection lines on the substrate and are electrically connected at the intersection position, The plurality of second reset signal lines intersect with the orthographic projections of the plurality of second reset connection lines on the substrate and are electrically connected at the intersection position, The plurality of third reset signal lines intersect with orthographic projections of the plurality of third reset connection lines on the substrate, and are electrically connected at the intersection positions.

12. The display substrate according to claim 11, wherein: The plurality of first reset signal lines are located in the same layer, The plurality of second reset signal lines are located in the same layer, The plurality of third reset signal lines are located on the same layer, The plurality of first reset connection lines, the plurality of second reset connection lines, and the plurality of third reset connection lines are located in the same layer, and are different from the first reset signal line, the second reset signal line, and the third reset signal line.

13. The display substrate according to claim 12, wherein: The plurality of first reset signal lines spatially intersect with the plurality of first reset connection lines, and are electrically connected at the spatial intersection position through a first via hole opened in the insulating layer between the two. The plurality of second reset signal lines spatially intersect with the plurality of second reset connection lines, and are electrically connected at the spatial intersection position through a second via hole opened in the insulating layer between the two. The plurality of third reset signal lines spatially intersect with the plurality of third reset connection lines, and are electrically connected at the spatial intersection position through a third via hole opened in the insulating layer between the two.

14. The display substrate according to claim 12, wherein: At least two of the first reset signal line, the second reset signal line, and the third reset signal line are located in different layers.

15. The display substrate according to claim 14, wherein: Also includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, The first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are stacked in sequence away from the substrate, The fourth conductive layer includes patterns of the first reset connection line, the second reset connection line and the third reset connection line, The third conductive layer includes a pattern of the third reset signal line; The second conductive layer includes a pattern of the second reset signal line; The first conductive layer includes a pattern of the first reset signal line.

16. The display substrate according to claim 11, wherein: It also includes a camera hole, the orthographic projection of the camera hole on the substrate is located in the display area, Part of the first reset signal line, part of the second reset signal line and part of the third reset signal line extending through the camera hole are disconnected at the camera hole position, and the orthographic projections of part of the first reset signal line, part of the second reset signal line and part of the third reset signal line extending through the camera hole on the substrate do not overlap with the orthographic projection of the camera hole on the substrate.

17. The display substrate according to claim 16, wherein: Part of the first reset connection line, part of the second reset connection line and part of the third reset connection line extending through the camera hole are disconnected at the camera hole position, and the orthographic projection of part of the first reset connection line, part of the second reset connection line and part of the third reset connection line extending through the camera hole on the substrate does not overlap with the orthographic projection of the camera hole on the substrate.

18. The display substrate according to any one of claims 16 to 17, wherein: The first reset signal line, the second reset signal line and the third reset signal line extend from the display area to the first side frame area and the second side frame area respectively. The first side frame area and the second side frame area are opposite to each other and arranged along the first direction; The display substrate further includes a first reset signal source, a second reset signal source and a third reset signal source, all of which are located in the first side frame area and the second side frame area; Two ends of the first reset signal line located in the first side frame area and the second side frame area are electrically connected to the first reset signal source respectively. Two ends of the second reset signal line located in the first side frame area and the second side frame area are electrically connected to the second reset signal source respectively. Two ends of the third reset signal line located in the first side frame area and the second side frame area are electrically connected to the third reset signal source respectively.

19. The display substrate according to any one of claims 16 to 17, wherein: The first reset connection line, the second reset connection line and the third reset connection line extend from the display area to the third side frame area and / or the fourth side frame area respectively. The third side frame area and the fourth side frame area are opposite to each other and arranged along the second direction; The display substrate further comprises a first reset signal source, a second reset signal source and a third reset signal source, all of which are located in the third side frame area and / or the fourth side frame area; One end of the first reset connection line located in the third side frame area and / or the fourth side frame area is electrically connected to the first reset signal source, One end of the second reset connection line located in the third side frame area and / or the fourth side frame area is electrically connected to the second reset signal source, One end of the third reset connection line located in the third side frame area and / or the fourth side frame area is electrically connected to the third reset signal source.

20. The display substrate according to claim 1, wherein: The first pixel circuit is configured to drive a red sub-pixel or a blue sub-pixel, The second pixel circuit and the fourth pixel circuit are configured to drive a green sub-pixel, The third pixel circuit is configured to drive a blue sub-pixel or a red sub-pixel.

21. A display device, wherein: A display substrate comprising any one of claims 1-20.

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