Diamond semiconductor element, electromechanical instrument, and method for manufacturing diamond semiconductor element

Abstract

The purpose of the present invention is to provide a diamond semiconductor element, an electromechanical instrument, and a method for manufacturing a diamond semiconductor element that are capable of contributing to obtaining desired characteristics with respect to electrical characteristics, high-frequency characteristics, and the like while ensuring yield, reliability, and adhesion between gold and a diamond semiconductor even when the diamond semiconductor element is miniaturized. This diamond semiconductor element is provided, on a part of a diamond semiconductor layer, with an electrode structure in which an Au electrode that is formed of Au and has a thickness of less than 100 nm is disposed so as to be in ohmic contact with the diamond semiconductor layer (Fig. 8).

Description

Diamond semiconductor element, electrical machinery and equipment, and method for manufacturing diamond semiconductor element

[0001] [Description of Related Applications] The present invention is based on Japanese Patent Application No. 2023-100169 (filed June 19, 2023), the entire contents of which are incorporated herein by reference. The present invention relates to a diamond semiconductor element, an electrical machine or device, and a method for manufacturing a diamond semiconductor element.

[0002] With the recent development of diamond CVD (Chemical Vapor Deposition) technology, the purity of CVD diamond has been improved, and it has become possible to obtain diamond single crystals with high electron mobility and hole mobility, and it is expected that these will be used in diamond semiconductor elements (e.g., field effect transistors (FETs), diodes, inverters, converters, frequency conversion, regulators, etc.) that have excellent element performance such as electrical properties and high frequency properties.

[0003] One method for manufacturing a diamond semiconductor element is the following self-alignment method (see, for example, Non-Patent Documents 1 and 2). First, a diamond semiconductor layer (e.g., a hydrogen-terminated diamond layer) is formed on the (001) of a diamond single crystal, gold is evaporated onto the surface of the diamond semiconductor layer, a first resist is formed in the element region on the gold, and using the first resist as a mask, the gold is wet-etched until the diamond semiconductor layer is exposed, and the first resist is removed. Next, a second resist having openings for forming a gate electrode and a source electrode / drain electrode is formed, and the gold exposed from the openings of the second resist is wet-etched to form source electrode / drain electrode made of gold, widely separated from the openings. Next, using the second resist as a mask, a gate electrode is formed by metal evaporation on the diamond semiconductor layer exposed from the openings of the second resist, and then the second resist and the metal film thereon are lifted off. This completes a MESFET (Metal Semiconductor Field Effect Transistor) type diamond semiconductor element.

[0004] According to the self-alignment method, compared with the non-self-alignment method (for example, see Patent Document 1, Non-Patent Document 3) that uses separate resists to form gate electrode and source electrode / drain electrode, the number of times that the channel of device region is exposed to wet etching agent and resist stripping agent or oxygen plasma for resist ashing can be reduced, so that the damage to channel can be reduced, and the yield and reliability of device can be improved.In addition, according to the self-alignment method, after forming diamond semiconductor layer and before forming the gold for source electrode / drain electrode, diamond semiconductor layer is not exposed to wet etching agent etc., so compared with the non-self-alignment method that is exposed to them, the adhesion between source electrode / drain electrode and diamond semiconductor layer can be improved.

[0005] JP 2018-078254 A

[0006] Carrier transport properties in diamond and its application to high-frequency FETs, Kawarada et al., Applied Physics, 73, 339-345, 2004-03-10, Japan Society of Applied Physics; Gate-metal interface of hydrogen-terminated diamond FETs, Kakazu et al., Surface Science, Vol. 29, No. 3, pp. 159-163, 2008; Special feature "The forefront of diamond surface and interface research" (https: / / www.jstage.jst.go.jp / article / jsssj / 29 / 3 / 29_3_159 / _pdf / -char / ja); "A High Frequency Hydrogen-Terminated Diamond MISFET With fT / fmax of 70 / 80 GHz", X. Yu et al., IEEE Electron Device Letters, vol. 39, no. 9, pp. 1373-1376, Sept. 2018, doi: 10.1109 / LED.2018.2862158.

[0007] The following analysis is provided by the present inventors.

[0008] In the self-alignment method described in Non-Patent Documents 1 and 2, the gold for the source electrode / drain electrode is isotropically etched by wet etching, so that sharp bird's beaks are formed on the end faces of the etched source electrode / drain electrode near the diamond semiconductor layer. Furthermore, when the thickness of the source electrode / drain electrode is set in consideration of durability during bonding, the source electrode / drain electrode becomes thicker and the bird's beak becomes larger. If there is a large bird's beak, it becomes difficult to align the end faces of the source electrode / drain electrode to the desired position due to the shape of the bird's beak and parasitic resistance, etc., making it difficult to obtain desired device performance characteristics such as electrical characteristics and high-frequency characteristics. This becomes more pronounced as the device region becomes smaller, and the same applies not only to diamond FETs but also to other types of diamond semiconductor devices in which the position of the electrode end face is critical.

[0009] The main object of the present invention is to provide a diamond semiconductor element, an electrical machine and device, and a method for manufacturing a diamond semiconductor element, which can contribute to obtaining desired characteristics such as electrical characteristics and high frequency characteristics while ensuring yield, reliability, and adhesion between gold and the diamond semiconductor even when miniaturized.

[0010] The diamond semiconductor element according to the first aspect comprises an electrode structure in which an Au electrode made of Au and having a thickness of less than 100 nm is disposed on a part of a diamond semiconductor layer so as to be in ohmic contact with the diamond semiconductor layer.

[0011] An electrical device according to a second aspect comprises the diamond semiconductor element according to the first aspect.

[0012] The manufacturing method of the diamond semiconductor element according to the third aspect includes the steps of forming an Au film made of Au and having a thickness of less than 100 nm on a diamond semiconductor layer, forming a resist on a part of the Au film, and wet-etching the Au film using the resist as a mask to form an Au electrode.

[0013] According to the first to third aspects, even when miniaturized, it is possible to contribute to obtaining desired characteristics such as electrical characteristics and high frequency characteristics while ensuring yield, reliability, and adhesion between gold and the diamond semiconductor layer.

[0014] 1 is a partial cross-sectional view schematically showing an example of the configuration of a diamond semiconductor element according to Form 1. FIG. 2 is a partial cross-sectional view schematically showing a first modified example of the configuration of a diamond semiconductor element according to Form 1. FIG. 3 is a partial cross-sectional view schematically showing a second modified example of the configuration of a diamond semiconductor element according to Form 1. FIG. 4 is a process cross-sectional view schematically showing an example of the manufacturing method of a diamond semiconductor element according to Form 1. FIG. 5 is a process cross-sectional view schematically showing an example of the manufacturing method of a diamond semiconductor element according to Form 1. FIG. 6 is an enlarged cross-sectional view of the drain electrode portion during drain electrode formation of a diamond semiconductor element, (A) being Form 1 and (B) being a comparative example. FIG. 7 is a graph schematically showing the relationship between extension length Lext and cutoff frequency for each predetermined surface resistivity. FIG. 8 is a cross-sectional view schematically showing the configuration of a sample used in measuring electrical properties and testing durability. FIG. 9 is a graph showing the electrical properties of the sample. FIG. 10 is a cross-sectional view schematically showing an example of the configuration of a diamond semiconductor element according to Form 2.

[0015] The present disclosure will be described below with reference to the drawings. Note that when reference numerals are used in this application, they are intended solely to aid understanding and are not intended to limit the present invention to the illustrated embodiments. Furthermore, the following embodiments are merely examples and do not limit the present invention.

[0016] [Form 1] A diamond semiconductor element according to Form 1 will be described with reference to the drawings. Fig. 1 is a partial cross-sectional view showing a schematic example of the configuration of a diamond semiconductor element according to Form 1. Fig. 2 is a partial cross-sectional view showing a schematic first modified example of the configuration of a diamond semiconductor element according to Form 1. Fig. 3 is a partial cross-sectional view showing a schematic second modified example of the configuration of a diamond semiconductor element according to Form 1.

[0017] The diamond semiconductor element 1 is a semiconductor element having an electrode structure in which electrodes made of Au (gold) (source electrode 12a, drain electrode 12b in FIG. 1) are arranged on a diamond semiconductor layer 11 (hydrogen termination portion 11a in FIG. 1) so as to be in ohmic contact with the diamond semiconductor layer 11. The electrode structure of the diamond semiconductor element 1 can be applied to FETs. Furthermore, the electrode structure of the diamond semiconductor element 1 may be applied to diodes, inverters, converters, frequency conversion, regulators, etc., in addition to FETs. The diamond semiconductor element 1 can be incorporated into electrical machinery and equipment such as semiconductor devices, power electronics devices, high-frequency devices, communication equipment, sensing equipment, automobiles, power transmission and distribution equipment, devices for harsh environments, equipment for high-temperature environments, equipment for radiation environments, space equipment, and nuclear reactor equipment.

[0018] When the diamond semiconductor element 1 is applied to a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a gate insulating film 14a as shown in FIG. 1, it can have the following configuration.

[0019] In the diamond semiconductor element 1 of Figure 1, a diamond semiconductor layer 11 is formed on a diamond substrate 10, with the upper surface ((001) plane) being a hydrogen-terminated portion 11a. In Figure 1, the hydrogen-terminated portion 11a is present in the element region 2, and is configured not to be present outside the element region 2. A gate electrode 15a is formed near the center of the hydrogen-terminated portion 11a, with a gate insulating film 14a interposed therebetween. On both sides of the gate electrode 15a on the hydrogen-terminated portion 11a, a source electrode 12a and a drain electrode 12b are disposed so as to be in ohmic contact with the hydrogen-terminated portion 11a. The source electrode 12a and the drain electrode 12b are disposed at a distance from the gate electrode 15a. Upper electrode layers 17a and 17b are formed on parts of the source electrode 12a and the drain electrode 12b, with intermediate electrode layers 16a and 16b interposed therebetween. The source electrode 12a and the drain electrode 12b have extending portions 13a, 13b that extend (protrude) toward the gate electrode 15a side from the end face of the intermediate electrode layer 16a, 16b and the upper electrode layer 17a, 17b on the gate electrode 15a side.The intermediate electrode layer 16a, 16b and the upper electrode layer 17a, 17b are not present on the extending portions 13a, 13b.In addition to the MISFET shown in Figure 1, the diamond semiconductor element 1 can also be applied to a MESFET (Metal Semiconductor Field Effect Transistor) shown in Figure 2 that does not have a gate insulating film and is arranged so that the gate electrode 15a contacts the hydrogen termination portion 11a.

[0020] Here, the diamond substrate 10 is a substrate made of a diamond single crystal (see FIG. 1). As the diamond substrate 10, for example, a high-temperature, high-pressure synthetic diamond single crystal substrate can be used.

[0021] The diamond semiconductor layer 11 is a layer that includes diamond and has a portion that functions as a semiconductor (see FIG. 1). The diamond semiconductor layer 11 can be formed, for example, by chemical vapor deposition of diamond crystals (epitaxial diamond crystals) on the diamond substrate 10 using hydrogen and methane gas as raw materials using a microwave plasma CVD (Chemical Vapor Deposition) device. The diamond semiconductor layer 11 thus formed has a hydrogen termination 11a on the (001) plane (upper surface). The hydrogen termination 11a has a hole channel formed therein and exhibits p-type conduction. By subjecting the region of the hydrogen termination 11a other than the element region 2 to ozone treatment to remove hydrogen, it is possible to configure the hydrogen termination 11a so that it is present in the element region 2 and not present in any region other than the element region 2. Note that the diamond semiconductor layer 11 is not limited to having the hydrogen termination 11a, but may also have a portion containing (doped or implanted into) impurities (e.g., boron, phosphorus, etc.) in diamond. Furthermore, instead of having a diamond semiconductor layer 11 on a diamond substrate 10, a free-standing diamond film may be used, for example, by using a microwave plasma CVD apparatus to grow diamond crystals on a seed substrate using hydrogen and methane gas as raw materials, followed by removing the seed substrate.

[0022] The source electrode 12a and the drain electrode 12b are electrodes (Au electrodes) made of Au (gold) (see FIG. 1). The source electrode 12a and the drain electrode 12b are formed on the diamond semiconductor layer 11. In order to ensure adhesion with the diamond semiconductor layer 11, the source electrode 12a and the drain electrode 12b are preferably formed on the diamond semiconductor layer 11 in a state that has not been exposed to an etching agent, a resist remover, or oxygen plasma for resist ashing. The source electrode 12a and the drain electrode 12b are arranged so as to be in direct contact (ohmic contact) with the hydrogen termination part 11a of the diamond semiconductor layer 11. The source electrode 12a and the drain electrode 12b can be formed, for example, by forming an Au film on the diamond semiconductor layer 11 (for example, by vapor deposition or sputtering), forming a resist for forming the source electrode / drain electrode on the Au film, etching using the resist as a mask, and removing the resist. The source-drain distance L, which is the distance between the source electrode 12a and the drain electrode 12b, is ＳＤ In consideration of operation in a high frequency band (for example, a cutoff frequency of 50 to 100 GHz), it is preferable that the thickness is less than 100 nm.

[0023] The thickness of the source electrode 12a and the drain electrode 12b is preferably less than 100 nm when operating in a high frequency band, preferably less than 50 nm when obtaining desired RF (Radio Frequency) characteristics, and preferably less than 25 nm when operating in an even higher frequency band (e.g., a cutoff frequency of over 100 GHz). The lower limit of the thickness of the source electrode 12a and the drain electrode 12b is the critical film thickness (the same applies to other thicknesses for which no lower limit is specified). A detailed description of the thickness of the source electrode 12a and the drain electrode 12b will be given later (see FIG. 7).

[0024] The gate insulating film 14a is made of, for example, Al ２ O ３ , SiO ２ , CaF ２ , HfO ２ , AlN, BN, Si ３ N ４, SiON, Ta ２ O ５ , TiO ２ , W.O. ３ , LaF ３ , and MgF ２ The gate electrode 15a can be formed by forming a single layer structure of any of Al, Au, Ti, Mo, Cr, Ru, Cu, Pb, Zn, Pt or a laminate structure of any combination thereof. The gate insulating film 14a and the gate electrode 15a can be formed, for example, by forming a resist for gate electrode formation on the diamond semiconductor layer 11, and using the resist as a mask, forming an insulating film for the gate insulating film 14a by a CVD method using a predetermined raw material gas by a self-alignment method, and then forming a metal film for the gate electrode 15a on the gate insulating film 14a (for example, by evaporation or sputtering), and then lifting off the resist and the insulating film and metal film thereon.

[0025] The intermediate electrode layers 16a and 16b can be made of a metal different from the Au of the source electrode 12a and the drain electrode 12b, such as a metal electrode layer made of any of Ru, Al, Ti, Mo, Cu, Cr, Pb, Zn, and Pt. The upper electrode layers 17a and 17b can be made of a metal different from the intermediate electrode layers 16a and 16b, such as a metal electrode layer selected from Au, Ru, Al, Ti, Mo, Cu, Cr, Pb, Zn, and Pt. The intermediate electrode layers 16a and 16b in FIG. 1 can be omitted as shown in FIG. 3. In this case, the upper electrode layers 17a and 17b can be made of a metal different from the Au of the source electrode 12a and the drain electrode 12b, such as a metal electrode layer made of any of Ru, Al, Ti, Mo, Cu, Cr, Pb, Zn, and Pt. The thickness of the upper electrode layer 17a, 17b alone, or the total thickness of the intermediate electrode layer 16a, 16b and the upper electrode layer 17a, 17b, is preferably 300 nm or more in order to enhance the durability of the source electrode 12a and the drain electrode 12b, and it is preferable to increase the thickness as the current flow increases.In addition, considering that the upper electrode layer 17a, 17b and the intermediate electrode layer 16a, 16b have weak adhesion to the diamond semiconductor layer 11 that has been exposed to etching agents, etc., it is preferable that they do not protrude from the area of ​​the upper surface of the source electrode 12a and the drain electrode 12b.The upper surface of the upper electrode layer 17a, 17b is the surface where the contact of the measurement needle or bonding etc. is performed.It is preferable that the upper electrode layer 17a, 17b is made of the same metal (e.g., Cu, Au) as that used for bonding wires, bumps, balls, etc.The intermediate electrode layers 16a, 16b and the upper electrode layers 17a, 17b can be formed, for example, by forming a resist having openings for forming the intermediate electrode layer and the upper electrode layer on the diamond semiconductor layer 11 including the gate electrode 15a, the source electrode 12a and the drain electrode 12b, depositing (for example, by vapor deposition, sputtering) a metal layer for the intermediate electrode layers 16a, 16b on the source electrode 12a and the drain electrode 12b including the resist 22, subsequently depositing (for example, by vapor deposition, sputtering) a metal layer for the upper electrode layers 17a, 17b on the metal layer for the intermediate electrode layers 16a, 16b, and lifting off the resist and the metal layer for the intermediate electrode layers 16a, 16b and the metal layer for the upper electrode layers 17a, 17b that are located thereon.

[0026] The purpose of adding the upper electrode layers 17a, 17b and the intermediate electrode layers 16a, 16b to the source electrode 12a and the drain electrode 12b is as follows: If the thickness of the source electrode 12a and the drain electrode 12b were less than 100 nm in consideration of operation in the high frequency band, it would be possible to align the end faces of the source electrode 12a and the drain electrode 12b to the desired positions, but this would reduce the durability of the source electrode 12a and the drain electrode 12b. Therefore, the upper electrode layers 17a, 17b and the intermediate electrode layers 16a, 16b were added to ensure the durability of the source electrode 12a and the drain electrode 12b. This ensures the durability of the source electrode 12a and the drain electrode 12b even when they are contacted by a measurement needle or subjected to physical effects (heat, ultrasound, etc.) during bonding.

[0027] The reason for adding the intermediate electrode layers 16a, 16b between the source electrode 12a / drain electrode 12b and the upper electrode layers 17a, 17b is as follows: If the same type of metal film is used for the source electrode 12a / drain electrode 12b and the upper electrode layers 17a, 17b, the source electrode 12a / drain electrode 12b will be exposed to a resist remover or the like after the source electrode 12a / drain electrode 12b is formed, and the surfaces of the source electrode 12a / drain electrode 12b will be damaged or poisoned (penetration or adsorption of inhibitory components, etc.), which may make it impossible to ensure adhesion between the source electrode 12a / drain electrode 12b and the upper electrode layers 17a, 17b. By adding intermediate electrode layers 16a, 16b made of a metal film different from the metal films of source electrode 12a / drain electrode 12b and upper electrode layers 17a, 17b between source electrode 12a / drain electrode 12b and upper electrode layers 17a, 17b, it is possible to ensure adhesion between source electrode 12a / drain electrode 12b and upper electrode layers 17a, 17b. This ensures adhesion between source electrode 12a / drain electrode 12b and upper electrode layers 17a, 17b even when there is contact with a measurement needle or physical effects (heat, ultrasound, etc.) during bonding.

[0028] The source electrode 12a and the drain electrode 12b have extensions 13a and 13b that extend (protrude) toward the gate electrode 15a beyond the end faces of the upper electrode layers 17a and 17b and the intermediate electrode layers 16a and 16b on the gate electrode 15a side. ｅｘｔ The length L of the extensions 13a and 13b (from the end faces of the upper electrode layers 17a and 17b and the intermediate electrode layers 16a and 16b on the gate electrode 15a side to the tip faces of the extensions 13a and 13b) is preferably less than 200 nm in consideration of operation in the high frequency band, and is preferably less than 100 nm in consideration of the balance with the thickness of the source electrode 12a and the drain electrode 12b when operating in the high frequency band, and is preferably less than 50 nm in consideration of obtaining desired RF characteristics. The length of the extensions 13a and 13b may be 0 nm (the extensions 13a and 13b may not be present). ｅｘｔ A detailed description of this will be given later (see FIG. 8).

[0029] Next, the method for manufacturing a diamond semiconductor element according to embodiment 1 will be described with reference to the drawings. Figures 4 to 6 are cross-sectional views of steps that schematically show an example of the method for manufacturing a diamond semiconductor element according to embodiment 1.

[0030] First, a diamond semiconductor layer 11 is formed on a diamond substrate 10 (see FIG. 4(A)). The diamond semiconductor layer 11 can be formed by chemical vapor deposition of diamond crystals on the diamond substrate 10 using hydrogen and methane gas as raw materials, for example, using a microwave plasma CVD device. The diamond semiconductor layer 11 thus formed has a hydrogen termination 11a on the (001) plane (upper surface).

[0031] Next, the Au film 12 is formed on the diamond semiconductor layer 11 (see FIG. 4(B)). The Au film 12 can be formed by depositing gold on the diamond semiconductor layer 11 by, for example, vapor deposition.

[0032] Next, a resist 20 is formed to cover the element region 2 on the Au film 12, and the Au film 12 is etched using the resist 20 as a mask until the diamond semiconductor layer 11 is exposed (see FIG. 4(C)). The resist 20 can be formed by, for example, lithography. The Au film 12 can be etched using, for example, a wet etching agent.

[0033] Next, using the resist 20 as a mask, ozone treatment is performed to eliminate the hydrogen termination portion 11a in the region other than the element region 2 in the diamond semiconductor layer 11 (see FIG. 4(D)). As a result, the region other than the element region 2 in the diamond semiconductor layer 11 becomes highly resistive, and the elements can be electrically insulated from each other.

[0034] Next, the resist (20 in FIG. 4D) on the Au film 12 is removed (see FIG. 5A). The resist 20 can be removed, for example, with a resist remover or by ashing. After the resist 20 is removed, cleaning is performed.

[0035] Next, a resist 21 having openings 21a for forming a gate electrode and a source electrode / drain electrode is formed on the diamond semiconductor layer 11 including the Au film 12 (see FIG. 5(B)). The resist 21 can be formed by, for example, a lithography method.

[0036] Next, using the resist 21 as a mask, the Au film (12 in FIG. 5B) exposed from the opening 21a is etched, and the Au film 12 is separated into the source electrode 12a and the drain electrode 12b by under-etching, and then the distance between the end faces of the source electrode 12a and the drain electrode 12b is made wider than the width of the opening 21a by side-etching (see FIG. 5C). The Au film 12 can be etched using, for example, a wet etching agent.

[0037] Next, on the diamond semiconductor layer 11 including resist 21, insulating layer 14 and gate insulating film 14a are formed, and then on insulating layer 14 and gate insulating film 14a, metal layer 15 and gate electrode 15a are formed (see Fig. 6 (A)).In other words, by self-alignment process, gate electrode 15a is formed via gate insulating film 14a on the diamond semiconductor layer 11 in the region of opening 21a of resist 21.Insulating layer 14 and gate insulating film 14a can be formed by, for example, CVD method.Metal layer 15 and gate electrode 15a can be formed by, for example, evaporation.

[0038] Next, the resist (21 in FIG. 6A), as well as the insulating layer (14 in FIG. 6A) and the metal layer (15 in FIG. 6A) thereon are removed (see FIG. 6B). The resist 21, as well as the insulating layer 14 and the metal layer 15 thereon, can be removed by lifting them off using a resist remover, for example. After the resist 21 is removed, cleaning is performed.

[0039] Next, a resist 22 having openings 22a and 22b for forming an intermediate electrode layer and an upper electrode layer is formed on the diamond semiconductor layer 11 including the source electrode 12a, a part of the drain electrode 12b, and the gate electrode 15a. A metal layer 16 and an intermediate electrode layer 16a and 16b are formed on the source electrode 12a and the drain electrode 12b including the resist 22. Then, a metal layer 17 and an upper electrode layer 17a and 17b are formed on the metal layer 16 and the intermediate electrode layer 16a and 16b (see FIG. 6(C)). As a result, the upper electrode layers 17a and 17b can be formed on the source electrode 12a and the drain electrode 12b in the openings 22a and 22b of the resist 22 via the intermediate electrode layers 16a and 16b. The resist 22 can be formed, for example, by lithography. The metal layer 16 and the intermediate electrode layers 16a and 16b can be formed, for example, by vapor deposition. The metal layer 17 and the upper electrode layers 17a and 17b can be formed by, for example, vapor deposition.

[0040] Finally, the resist (22 in FIG. 6C), and the metal layer (16 in FIG. 6C) and the metal layer (17 in FIG. 6C) thereon are removed (see FIG. 1). The resist 22, and the metal layer 16 and the metal layer 17 thereon can be removed by lifting them off using a resist remover, for example. After the resist 22 is removed, cleaning is performed.

[0041] Next, the thickness of the source electrode 12a and the drain electrode 12b will be explained using the drawings. Figure 7 is an enlarged cross-sectional view of the drain electrode portion of the diamond semiconductor element when the drain electrode is formed, (A) is form 1, and (B) is a comparative example.

[0042] The reason why the thickness of each of the source electrode (12a in FIG. 1) and the drain electrode 12b is set to less than 100 nm is as follows. When forming the source electrode 12a and the drain electrode 12b, the Au layer (12 in FIG. 5(A)) is under-etched to separate the source electrode 12a and the drain electrode 12b, and then the end faces of the source electrode 12a and the drain electrode 12b are side-etched. When the end faces of the source electrode 12a and the drain electrode 12b are isotropically etched by wet etching, sharp bird's beaks 12c are formed on the etched end faces of the source electrode 12a and the drain electrode 12b in the region close to the diamond semiconductor layer 11. The bird's beak 12c becomes a parasitic resistance. When the thickness T of the source electrode 12a and the drain electrode 12b is 100 nm or more, the bird's beak 12c becomes large as shown in FIG. 7(B). If there is parasitic resistance due to a large bird's beak, desired device performance characteristics such as electrical characteristics and high-frequency characteristics cannot be obtained. Furthermore, when forming the source electrode 12a and the drain electrode 12b, the tip of the bird's beak 12c needs to be spaced to a certain extent from the region where the gate electrode 15a is formed. In this case, the base of the bird's beak 12c is located farther from the region where the gate electrode 15a is formed than the tip of the bird's beak 12c. The thicker the source electrode 12a and the drain electrode 12b, the farther the base of the bird's beak 12c is located from the region where the gate electrode 15a is formed. Therefore, in order to minimize the influence of the bird's beak (parasitic resistance, shape, size, etc.) even when the device configuration is miniaturized, in embodiment 1, the thickness T of the source electrode 12a and the drain electrode 12b is set to less than 100 nm, as shown in FIG. 7A . Furthermore, by setting the thickness of the source electrode 12a and the drain electrode 12b to less than 100 nm, the positions of the end faces of the source electrode 12a and the drain electrode 12b can be precisely controlled. Furthermore, by setting the thickness T of the source electrode 12a and the drain electrode 12b to less than 50 nm, carrier movement becomes smoother, enabling high-speed switching operations, thereby improving frequency characteristics.Furthermore, when the diamond semiconductor element 1 is used as a sensor, noise can be suppressed by setting the thickness T of the source electrode 12a and the drain electrode 12b to less than 50 nm. This enables detection of weak signals and highly sensitive measurements, which is advantageous in sensing fields such as medical diagnosis and environmental monitoring. Furthermore, setting the thickness T of the source electrode 12a and the drain electrode 12b to less than 50 nm shortens the etching time, reduces damage to the channel, and improves electrical characteristics. Furthermore, setting the thickness T of the source electrode 12a and the drain electrode 12b to less than 50 nm improves the resistance to bending of the diamond semiconductor element 1. This enables the development of advanced devices, such as diamond semiconductor elements with curved surfaces. Furthermore, setting the thickness T of the source electrode 12a and the drain electrode 12b to less than 50 nm allows heat to be dissipated more efficiently from the source electrode 12a and the drain electrode 12b, thereby improving energy efficiency. Furthermore, by setting the thickness T of the source electrode 12a and the drain electrode 12b to less than 50 nm, the manufacturing cost and the time required for manufacturing can be reduced.

[0043] Here, the cutoff frequency f T is generally expressed as transconductance g m And the actually observed transconductance g m is the gate length L G However, if the intrinsic transconductance is g m０ The transconductance g m and the source-gate resistance R S As can be seen from the relationship (see equation 1 below), as miniaturization progresses, the source-gate resistance R S The influence of the source-gate resistance R becomes increasingly difficult to ignore and eventually reaches a plateau. S Therefore, it is important to minimize the source-gate distance L SG , source-drain distance L SDIn order to prevent an increase in the thickness, it is preferable that the thickness of the source electrode 12a and the drain electrode 12b be less than 50 nm.

[0044]

[0045] Next, the length L of the extensions 13a and 13b ｅｘｔ 8 shows the relationship between the extension length L and the surface resistivity. ｅｘｔ 10 is a graph schematically showing the relationship between the cutoff frequency and the power consumption.

[0046] To improve the characteristics of FETs, including high frequency characteristics, it is necessary to reduce the source resistance. SG It is necessary to shorten the length of the source electrode 12a and the drain electrode 12b, and when a self-alignment process is used, it is necessary to ensure the accuracy of the position of the end faces of the source electrode 12a and the drain electrode 12b (see FIG. 1). To achieve this, it is necessary to thin the thickness of each of the source electrode 12a and the drain electrode 12b. However, when the thickness of the source electrode 12a and the drain electrode 12b made of Au is thinned, the resistivity component increases, and the resistivity may reach a maximum of 40 mΩcm. This is 16,000 times the bulk resistivity. For example, when the thickness of the Au is set to 50 nm, a huge parasitic resistance of 8 kΩ / sq in sheet resistance occurs. If the sheet resistance increases due to factors such as these, it is necessary to thin the Au film etched in the self-alignment process while simultaneously increasing the length L of the extensions 13a and 13b. ｅｘｔ As shown in the graph of FIG. G Even if the length L of the extensions 13a and 13b is reduced, in order to achieve high performance, ｅｘｔ It is also essential to miniaturize the cutoff frequency f T In order to manufacture a high frequency device with a frequency of less than 50 GHz, the length L of the extensions 13a and 13b is ｅｘｔ It is important to make the length L of the extensions 13a and 13b less than 200 nm, and considering that there may be other factors that inhibit performance, ｅｘｔ Furthermore, in order to suppress the adverse effect on high frequency characteristics due to thinning of the Au film to about 20% of the source resistance that was 1 / 10, the length L of the extensions 13a and 13b isｅｘｔ It is necessary to make the thickness less than 50 nm.

[0047] Next, the measurement of the electrical characteristics of the sample of the diamond semiconductor element according to embodiment 1 and the test of durability will be explained with reference to the drawings. Figure 9 is the cross-sectional view that shows the structure of the sample that is used for the measurement of electrical characteristics and the test of durability. Figure 10 is the graph that shows the electrical characteristics of sample.

[0048] The sample of the electrode structure of the diamond semiconductor element according to embodiment 1 (see Fig. 9) was obtained as follows.First, on a diamond substrate 10 (4mm x 4mm x 0.5mm), a diamond semiconductor layer 11 (thickness 100nm) having hydrogen termination 11a was formed (CVD method).Next, an Au film (thickness 90nm) was formed on the hydrogen termination 11a (electron beam vacuum deposition apparatus: Eiko Engineering Co., Ltd. NPF023 used, deposition temperature 100 ° C or less), and a resist (200 μm square) for forming an Au electrode was formed on the Au film, and the resist for forming an Au electrode was used as a mask to etch the Au film, and the resist for forming an Au electrode was removed to form an Au electrode 12d. Next, a resist having openings (180 μm square) for forming the intermediate electrode layer and the upper electrode layer was formed on the hydrogen termination portion 11 a including the Au electrode 12 d. A metal layer (Ti, 20 nm thick) for the intermediate electrode layer 16 a was formed on the Au electrode 12 d including the resist (using an electron beam vacuum evaporation apparatus: NPF023 manufactured by Eiko Engineering Co., Ltd., at a deposition temperature of 100° C. or less). Subsequently, a metal layer (Au, 300 nm thick) for the upper electrode layer 17 a was formed on the metal layer for the intermediate electrode layer 16 a (using an electron beam vacuum evaporation apparatus: NPF023 manufactured by Eiko Engineering Co., Ltd., at a deposition temperature of 100° C. or less). The resist and the metal layer for the intermediate electrode layer 16 a and the metal layer for the upper electrode layer 17 a located thereon were lifted off to form the intermediate electrode layer 16 a and the upper electrode layer 17 a, thereby obtaining a sample. The thickness and length were measured using a scanning electron microscope (Hitachi High-Technologies Corporation: S-4800), and supplementary measurements were made using a stylus step profiler (KLA-Tencor Corporation: Alpha-Step IQ). Electrical properties were measured using a prober (Hybridge Corporation: Ultra-high vacuum microprober: HUMP-100) and a semiconductor parameter analyzer (Agilent Corporation: B1505A).

[0049] In measuring the electrical characteristics, a short circuit was measured with two probe needles in contact with the upper electrode layer 17a, and the resistance value was measured. The resistance value, including the tendency of the measurement system, was less than 6 Ω.

[0050] In the durability test, the above electrical characteristics were measured more than 10 times, and the probe core was reapplied each time to confirm that the electrodes did not peel off (confirmed using the above scanning electron microscope) and that the electrical characteristics did not deteriorate (the deviation from the initial values ​​of the above electrical characteristics was within 10%).No peeling of the electrodes was observed, and no deterioration of the electrical characteristics occurred.

[0051] As described above, it was confirmed that the electrode structure actually fabricated has excellent electrical characteristics and durability, and is also suitable for use as an electrode for FETs.

[0052] According to form 1, the thickness of the electrodes (source electrode 12a and drain electrode 12b in Fig. 1) made of Au (gold) which are in ohmic contact on the diamond semiconductor layer 11 is set to less than 100 nm, so that it is possible to minimize the influence of bird's beaks (12c in Fig. 7) which are generated at the ends of the electrodes by etching, and even if miniaturized, it is possible to ensure yield, reliability, and adhesion between the gold and the diamond semiconductor layer, while contributing to obtaining desired characteristics in terms of electrical characteristics, high frequency characteristics, etc.

[0053] Furthermore, according to the first embodiment, by making the thickness of the source electrode 12a and the drain electrode 12b less than 100 nm, the size can be precisely controlled, and desired performance can be obtained.

[0054] Furthermore, according to the first embodiment, by forming the upper electrode layers 17a and 17b on the source electrode 12a and the drain electrode 12b, the source electrode 12a and the drain electrode 12b can be protected and peeling of the electrodes can be prevented.

[0055] Furthermore, according to form 1, by interposing intermediate electrode layers 16a and 16b between source electrode 12a, drain electrode 12b and upper electrode layers 17a and 17b, it is possible to improve the adhesion between source electrode 12a, drain electrode 12b and upper electrode layers 17a and 17b.

[0056] Furthermore, according to form 1, the upper electrode layers 17a and 17b are thicker than the source electrode 12a and the drain electrode 12b, so that peeling of the source electrode 12a and the drain electrode 12b due to physical influences (heat, ultrasonic waves) during bonding can be prevented.

[0057] Furthermore, according to form 1, even if the diamond substrate 10 is small and difficult to handle, the self-alignment process can ensure yield, reliability, and adhesion between the gold and the diamond semiconductor layer, while providing a high-performance element that operates stably even in harsh environments such as a high-temperature environment of 400°C, a high-voltage environment of 500V, or a radiation environment.

[0058] [Embodiment 2] The diamond semiconductor element according to embodiment 2 will be described with reference to the drawings. Figure 11 is a cross-sectional view showing a schematic example of the configuration of the diamond semiconductor element according to embodiment 2.

[0059] The diamond semiconductor element 1 has an electrode structure in which an Au electrode 12 d made of Au and having a thickness of less than 100 nm is disposed on a part of the diamond semiconductor layer 11 so as to be in ohmic contact with the diamond semiconductor layer 11 .

[0060] According to form 2, the thickness of the Au electrode 12d that makes ohmic contact on the diamond semiconductor layer 11 is set to less than 100 nm, so that it is possible to minimize the influence of bird's beaks that occur at the end of the electrode due to etching, and even when miniaturized, it is possible to ensure yield, reliability, and adhesion between gold and the diamond semiconductor layer, while contributing to obtaining desired characteristics in terms of electrical characteristics, high frequency characteristics, etc.

[0061] Some or all of the above embodiments may be described as, but are not limited to, the following supplementary notes.

[0062] [Appendix 1] A diamond semiconductor element comprising an electrode structure in which an Au electrode made of Au and having a thickness of less than 100 nm is arranged on a part of a diamond semiconductor layer so as to be in ohmic contact with the diamond semiconductor layer. [Appendix 2] A diamond semiconductor element according to appendix 1, in which the thickness of the Au electrode is less than 50 nm. [Appendix 3] A diamond semiconductor element according to appendix 1 or 2, in which the end face of the Au electrode is a surface formed by wet etching. [Appendix 4] A diamond semiconductor element according to any one of appendices 1 to 3, in which the diamond semiconductor layer is made of hydrogen-terminated diamond. [Appendix 5] A diamond semiconductor element according to any one of appendices 1 to 4, in which a metal electrode layer made of a metal and having a thickness of 300 nm or more is arranged on a part of the Au electrode so as to be in contact with the Au electrode. [Appendix 6] The diamond semiconductor element according to Appendix 5, wherein the metal electrode layer has a configuration in which an intermediate electrode layer and an upper electrode layer are laminated in this order from the Au electrode side, the upper electrode layer is made of any of Au, Ru, Al, Ti, Mo, Cu, Cr, Pb, Zn, and Pt, and the intermediate electrode layer is made of a metal different from the Au electrode and the upper electrode layer from among Ru, Al, Ti, Mo, Cu, Cr, Pb, Zn, and Pt. [Appendix 7] The diamond semiconductor element according to Appendix 5, wherein the metal electrode layer is made of any of Ru, Al, Ti, Mo, Cu, Cr, Pb, Zn, and Pt. [Appendix 8] The diamond semiconductor element according to Appendix 5, wherein the Au electrode has an extension portion that extends beyond the end face of the metal electrode layer, and the length of the extension portion from the end face of the metal electrode layer to the end face of the extension portion is less than 200 nm. [Appendix 9] The diamond semiconductor element according to appendix 8, wherein the length from the end face of the metal electrode layer to the end face of the extension is less than 100 nm. [Appendix 10] The diamond semiconductor element according to appendix 9, wherein the length from the end face of the metal electrode layer to the end face of the extension is less than 50 nm. [Appendix 11] The diamond semiconductor element according to appendix 4, wherein the hydrogen-terminated diamond has an element region including the Au electrode, and is configured to have a hydrogen termination in the element region and not have a hydrogen termination in regions other than the element region.[Appendix 12] The diamond semiconductor element according to appendix 5, wherein the metal electrode layer is configured so as not to protrude from the upper surface of the Au electrode. [Appendix 13] The diamond semiconductor element according to any one of appendices 1 to 12, wherein the Au electrodes are source and drain electrodes, and the diamond semiconductor element is configured such that a gate electrode is disposed spaced apart from the source and drain electrodes on a part of the diamond semiconductor layer between the source and drain electrodes. [Appendix 14] The diamond semiconductor element according to appendix 13, wherein the gate electrode is disposed via a gate insulating film on a part of the diamond semiconductor layer between the source and drain electrodes. [Appendix 15] The gate insulating film is Al. ２ O ３ , SiO ２ , CaF ２ , HfO ２ , AlN, BN, Si ３ N ４ , SiON, Ta ２ O ５ , TiO ２ , W.O. ３ , LaF ３ , and MgF ２a diamond semiconductor element according to appendix 14, which has a single layer structure of any one of the above or a laminated structure of any combination thereof. [Appendix 16] A diamond semiconductor element according to appendix 13, wherein the gate electrode is in ohmic contact with the diamond semiconductor layer. [Appendix 17] A diamond semiconductor element according to appendix 13, wherein the distance between the source electrode and the drain electrode is less than 100 nm. [Appendix 18] An electrical appliance comprising the diamond semiconductor element according to any one of appendices 1 to 17. [Appendix 19] A method for manufacturing a diamond semiconductor element, comprising the steps of: forming an Au film made of Au and having a thickness of less than 100 nm on a diamond semiconductor layer; and forming an Au electrode by forming a resist on a part of the Au film and wet-etching the Au film using the resist as a mask. [Appendix 20] A method for manufacturing a diamond semiconductor element according to appendix 19, which includes the step of forming the diamond semiconductor layer on a diamond substrate, wherein etching is not performed after forming the diamond semiconductor layer and before forming the Au film.

[0063] The disclosures of the above-mentioned patent and non-patent documents are incorporated herein by reference and may be used as the basis or part of the present invention, as necessary. Modifications and adjustments of the embodiments and examples are possible within the scope of the entire disclosure of the present invention (including the claims and drawings), and further based on the basic technical concepts thereof. Furthermore, various combinations and selections (or non-selections, as necessary) of the various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible within the scope of the entire disclosure of the present invention. In other words, the present invention naturally includes various modifications and alterations that would be possible by a person skilled in the art in accordance with the entire disclosure and technical concepts, including the claims and drawings. Furthermore, with regard to the numerical values ​​and numerical ranges described in this application, any intermediate values, lower values, and smaller ranges are deemed to be included, even if not explicitly stated. Furthermore, the disclosures of the above-cited documents, when used in part or in whole in combination with the disclosures herein as part of the disclosure of the present invention, are also deemed to be included in (belong to) the disclosures of this application, in accordance with the spirit of the present invention.

[0064] REFERENCE SIGNS LIST 1 Diamond semiconductor element 2 Element region 10 Diamond substrate 11 Diamond semiconductor layer 11a Hydrogen termination portion 12 Au layer 12a Source electrode (Au electrode) 12b Drain electrode (Au electrode) 12c Bird's beak 12d Au electrode 13a, 13b Extension portion 14 Insulating layer 14a Gate insulating film 15 Metal layer 15a Gate electrode 16 Metal layers 16a, 16b Intermediate electrode layer (metal electrode layer) 17 Metal layers 17a, 17b Upper electrode layer (metal electrode layer) 20, 21, 22 Resist 21a, 22a, 22b Opening

Claims

1. A diamond semiconductor element comprising an electrode structure in which an Au electrode made of Au and having a thickness of less than 100 nm is disposed on a portion of a diamond semiconductor layer so as to be in ohmic contact with the diamond semiconductor layer.

2. The diamond semiconductor element according to claim 1, wherein the thickness of the Au electrode is less than 50 nm.

3. A diamond semiconductor element according to claim 1 or 2, wherein the end face of the Au electrode is a surface formed by wet etching.

4. A diamond semiconductor element according to any one of claims 1 to 3, wherein the diamond semiconductor layer is made of hydrogen-terminated diamond.

5. A diamond semiconductor element according to any one of claims 1 to 4, wherein a metal electrode layer made of a metal having a thickness of 300 nm or more is disposed on a portion of the Au electrode so as to be in contact with the Au electrode.

6. The diamond semiconductor element according to claim 5, wherein the metal electrode layer is configured by stacking an intermediate electrode layer and an upper electrode layer in this order from the Au electrode side, the upper electrode layer being made of any one of Au, Ru, Al, Ti, Mo, Cu, Cr, Pb, Zn, and Pt, and the intermediate electrode layer being made of a metal different from the Au electrode and the upper electrode layer from among Ru, Al, Ti, Mo, Cu, Cr, Pb, Zn, and Pt.

7. The diamond semiconductor element according to claim 5, wherein the metal electrode layer is made of any one of Ru, Al, Ti, Mo, Cu, Cr, Pb, Zn, and Pt.

8. A diamond semiconductor element as described in claim 5, wherein the Au electrode has an extension portion extending beyond the end face of the metal electrode layer, and the length of the extension portion from the end face of the metal electrode layer to the end face of the extension portion is less than 200 nm.

9. A diamond semiconductor element according to claim 8, wherein the length from an end face of the metal electrode layer to an end face of the extension is less than 100 nm.

10. A diamond semiconductor element according to claim 9, wherein the length from an end face of the metal electrode layer to an end face of the extension is less than 50 nm.

11. A diamond semiconductor element as described in claim 4, wherein the hydrogen-terminated diamond has an element region including the Au electrode, and is configured to have a hydrogen termination portion in the element region and not have a hydrogen termination portion in any region other than the element region.

12. A diamond semiconductor element according to claim 5, wherein the metal electrode layer is configured so as not to protrude from the upper surface of the Au electrode.

13. A diamond semiconductor element according to any one of claims 1 to 12, wherein the Au electrodes are a source electrode and a drain electrode, and the diamond semiconductor element is configured such that a gate electrode is disposed spaced apart from the source electrode and the drain electrode on a portion of the diamond semiconductor layer between the source electrode and the drain electrode.

14. A diamond semiconductor element according to claim 13, wherein the gate electrode is disposed on a portion of the diamond semiconductor layer between the source electrode and the drain electrode via a gate insulating film.

15. The gate insulating film is Al ２ O ３ , SiO ２ , CaF ２ , HfO ２ , AlN, BN, Si ３ N ４ , SiON, Ta ２ O ５ , TiO ２ , W.O. ３ , LaF ３ , and MgF ２ 15. The diamond semiconductor element according to claim 14, which has a single layer structure or a laminate structure of any combination of the above.

16. The diamond semiconductor element according to claim 13, wherein the gate electrode is in ohmic contact with the diamond semiconductor layer.

17. A diamond semiconductor element according to claim 13, wherein the distance between the source electrode and the drain electrode is less than 100 nm.

18. An electrical machine or device comprising a diamond semiconductor element according to any one of claims 1 to 17.

19. A method for manufacturing a diamond semiconductor element, comprising: a step of forming an Au film having a thickness of less than 100 nm on a diamond semiconductor layer; and a step of forming a resist on a portion of the Au film, and wet-etching the Au film using the resist as a mask to form an Au electrode.

20. A method for producing a diamond semiconductor element according to claim 19, comprising the step of forming the diamond semiconductor layer on a diamond substrate, wherein no etching is performed after the diamond semiconductor layer is formed and before the Au film is formed.

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