Refresh control circuit and memory

Abstract

Provided in the present disclosure are a refresh control circuit and a memory. The refresh control circuit comprises a self-refresh control signal generation module and a self-refresh signal generation module, wherein the self-refresh control signal generation module is configured to receive a self-refresh mode signal, output a self-refresh control signal of a first level when the self-refresh mode signal indicates that a memory enters a self-refresh mode, and output a self-refresh control signal of a second level when the self-refresh mode signal indicates that the memory exits the self-refresh mode; and the self-refresh signal generation module is configured to receive the self-refresh control signal, output a self-refresh signal, generate a shielding signal on the basis of the self-refresh control signal, and shield the self-refresh control signal for a preset duration on the basis of the shielding signal and then output the self-refresh control signal.

Description

Refresh control circuit and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 27, 2023, with application number 202310776149.8 and application name “Refresh Control Circuit and Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a refresh control circuit and a memory. Background Art

[0003] At present, the refresh mode of the memory can be divided into automatic refresh mode and self-refresh mode. In automatic refresh mode, the refresh command is issued periodically by the controller, and the memory is responsible for executing the refresh command; in self-refresh mode, the controller is responsible for sending commands to enter and exit the self-refresh mode. During the self-refresh mode process, the refresh command is generated periodically by the memory itself.

[0004] After receiving a command to enter self-refresh mode, the memory usually first executes the command as a refresh command in automatic refresh mode. After execution, it then periodically generates refresh commands. However, it takes a certain amount of time for the memory to execute a refresh command, and each refresh command execution is accompanied by a relocking of the delay locked loop (DLL). In actual operation of the storage system, the memory may receive short-term commands to enter and exit self-refresh mode. As a result, the memory may not complete an initial refresh after the self-refresh mode process has ended. In this case, the DLL will be locked at a lower operating voltage during the refresh process, but the next read and write operation of the memory will be at the normal operating voltage. This will inevitably cause a series of problems and affect the performance of the memory.

[0005] Summary of the Invention

[0006] The present disclosure provides a refresh control circuit and a memory, which can effectively improve the performance of the memory.

[0007] In a first aspect, an embodiment of the present disclosure provides a refresh control circuit applied to a memory, wherein the refresh control circuit includes: a self-refresh control signal generation module and a self-refresh signal generation module, wherein:

[0008] The self-refresh control signal generation module includes at least one input terminal and a first output terminal, wherein the at least one input terminal is used to receive a self-refresh mode signal; the self-refresh control signal generation module is configured to: when the self-refresh mode signal received by the at least one input terminal indicates that the memory enters the self-refresh mode, output a self-refresh control signal of a first level at the first output terminal; when the self-refresh mode signal received by the at least one input terminal indicates that the memory exits the self-refresh mode, output a self-refresh control signal of a second level at the first output terminal;

[0009] The self-refresh signal generation module includes a first input terminal and a second output terminal, the first input terminal is connected to the first output terminal and is used to receive the self-refresh control signal, and the second output terminal is used to output a self-refresh signal, and the self-refresh signal is used to instruct the memory to enter a self-refresh operation; the self-refresh signal generation module is configured to: generate a shielding signal based on the self-refresh control signal, and shield the self-refresh control signal for a preset period of time based on the shielding signal before outputting it.

[0010] In a second aspect, an embodiment of the present disclosure provides a memory comprising the refresh control circuit provided in the first aspect.

[0011] The refresh control circuit provided by the embodiment of the present disclosure has a self-refresh control signal generation module that receives a self-refresh mode signal and converts the self-refresh mode signal into a self-refresh control signal, and uses the level state of the self-refresh control signal to instruct the memory to enter the self-refresh mode or to exit the self-refresh mode; the self-refresh signal generation module shields the self-refresh control signal for a preset period of time through a shielding signal and then outputs it, so that the memory does not perform a refresh operation after initially receiving the command to enter the self-refresh mode, but outputs it after shielding the self-refresh control signal for a preset period of time. Under the premise of ensuring that the memory can perform normal refresh operations, it can avoid the situation where the self-refresh process has ended but the memory has not completed a refresh process when the memory receives a short-term command to enter / exit the self-refresh mode, thereby causing the DLL to be locked at a lower operating voltage during the refresh process, but the next read and write of the memory is at a normal operating voltage, thereby causing a series of problems such as timing matching, thereby improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a structural diagram 1 of a refresh control circuit provided in an embodiment of the present disclosure;

[0013] FIG2 is a first structural diagram of a self-refresh signal generating module 200 provided in an embodiment of the present disclosure;

[0014] FIG3 is a second structural diagram of a self-refresh signal generating module 200 provided in an embodiment of the present disclosure;

[0015] FIG4 is a first structural diagram of a self-refresh control signal generating module 100 provided in an embodiment of the present disclosure;

[0016] FIG5 is a second structural diagram of a self-refresh control signal generating module 100 provided in an embodiment of the present disclosure;

[0017] FIG6 is a second structural diagram of a refresh control circuit provided in an embodiment of the present disclosure;

[0018] FIG7 is a third structural diagram of a self-refresh control signal generating module 100 provided in an embodiment of the present disclosure;

[0019] FIG8 is a third structural diagram of a refresh control circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. In addition, although the disclosure in the present disclosure is introduced according to one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method separately.

[0021] It should be noted that the brief descriptions of terms in this disclosure are only for the purpose of facilitating the understanding of the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise specified, these terms should be understood according to their ordinary and usual meanings.

[0022] In the specification and claims of this disclosure, as well as in the accompanying drawings, the terms "first," "second," "third," and the like are used to distinguish similar or similar objects or entities and are not necessarily intended to define a particular order or precedence, unless otherwise noted. It should be understood that the terms used in this manner are interchangeable where appropriate, e.g., embodiments of the disclosure can be implemented in an order other than that shown or described in the drawings.

[0023] In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0024] It should be understood that when an element is referred to as being “connected” or “electrically connected” to other elements in an embodiment of the present disclosure, the element may be directly connected or electrically connected to the other elements; or there may be several intermediate elements, and the element may be connected or electrically connected to the other elements through the several intermediate elements.

[0025] The term "module" used in the embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that can perform the functions associated with the element.

[0026] The embodiments of the present disclosure relate to the field of semiconductor memory technology and can optionally be applied to the design of dynamic random access memory (DRAM) chips, including controlling the refresh mode of DRAM. It should be noted that the refresh control circuit provided in the embodiments of the present disclosure can be applied to DRAM as well as other memories with refresh operations, such as NAND Flash or NOR Flash, and is not limited in the embodiments of the present disclosure.

[0027] It can be understood that a memory generally includes a plurality of bit lines (BL), a plurality of word lines (WL), and a plurality of memory cells, wherein each memory cell is connected to a corresponding WL and a corresponding BL.

[0028] In some embodiments, each memory cell includes a transistor and a capacitor. The transistor's gate is connected to WL, and one of the transistor's source / drain is connected to BL, while the other is connected to the capacitor. When the signal on WL turns on the transistor, BL can write a high-level signal "1" to the capacitor. When the signal on WL turns off the transistor, the charge on the capacitor slowly leaks away over time. The time between the capacitor leaking from a high-level signal "1" to a low-level signal "0" is the data retention time of the capacitor.

[0029] To prevent data loss in the capacitors, the memory needs to continuously refresh all stored data within a limited timeframe. During the refresh process, the memory first reads the original data, compares the voltage level on the capacitors with a reference voltage, determines the data's 1 / 0 value, and then writes the original data back. The write-back process fully charges the capacitors (if the data is 1), like a recharge operation.

[0030] In some embodiments, the refresh mode of the memory can be divided into automatic refresh mode and self-refresh mode. In automatic refresh mode, the refresh command is issued periodically by the controller, and the memory is responsible for executing the refresh command; in self-refresh mode, the controller is only responsible for sending commands to enter and exit the self-refresh mode. During the self-refresh mode process, the refresh command is generated periodically by the memory itself.

[0031] After receiving a command to enter self-refresh mode, the memory typically first executes the command as a refresh command in automatic refresh mode. After execution is complete, it then periodically generates refresh commands. However, in the actual operation of a storage system, there are a large number of short-term commands to enter and exit self-refresh mode. In this case, the performance of the memory can be easily affected. For example, after receiving a command to enter self-refresh mode, the memory will first use the command as a refresh command in automatic refresh mode to refresh the memory. Executing a refresh command takes a certain amount of time, during which the DLL is re-locked. However, in actual operation, the memory may repeatedly receive commands to enter and exit self-refresh mode in a short period of time. This may result in the memory not completing an automatic refresh process after the self-refresh process has ended. In this case, the DLL will be locked at a lower operating voltage during the refresh process, but the next read and write operation of the memory will be at a normal operating voltage. This will inevitably cause a series of problems and affect the performance of the memory.

[0032] In response to the above technical problems, the present disclosure provides a refresh control circuit, including a self-refresh control signal generation module and a self-refresh signal generation module, wherein the self-refresh control signal generation module receives a self-refresh mode signal and converts the self-refresh mode signal into a self-refresh control signal, and uses the level state of the self-refresh control signal to instruct the memory to enter the self-refresh mode or to exit the self-refresh mode; the self-refresh signal generation module shields the self-refresh control signal for a preset time period through a shielding signal and then outputs it, so that the memory does not perform a refresh operation after initially receiving a command to enter the self-refresh mode, but outputs the self-refresh control signal after shielding the self-refresh control signal for a preset time period. Under the premise of ensuring that the memory can perform normal refresh operations, it can avoid the situation where the self-refresh process has ended but the memory has not yet completed a refresh process when the memory receives a short-term command to enter / exit the self-refresh mode, thereby causing the DLL to be locked at a lower operating voltage during the refresh process, but the next read and write of the memory is at a normal operating voltage, thereby causing a series of problems such as timing matching, thereby improving the performance of the memory. The detailed technical solution can be referred to the following embodiments.

[0033] Refer to FIG. 1 , which is a structural diagram 1 of a refresh control circuit provided in an embodiment of the present disclosure.

[0034] In some embodiments of the present disclosure, the refresh control circuit includes a self-refresh control signal generating module 100 and a self-refresh signal generating module 200 .

[0035] In some embodiments, the self-refresh control signal generating module 100 includes at least one input terminal and a first output terminal, where the at least one input terminal is configured to receive the self-refresh mode signal S1 .

[0036] In some embodiments, the self-refresh mode signal S1 may be a signal sent by a controller corresponding to the memory, received by the memory, and generated after being decoded by a decoder in the memory.

[0037] The self-refresh mode signal S1 may be used to instruct the memory to enter the self-refresh mode or to instruct the memory to exit the self-refresh mode.

[0038] In some embodiments, the self-refresh control signal generation module 100 is configured to: when the self-refresh mode signal S1 received by the above-mentioned at least one input terminal indicates that the memory enters the self-refresh mode, output a first-level self-refresh control signal S2 at the above-mentioned first output terminal; when the self-refresh mode signal S1 received by the above-mentioned at least one input terminal indicates that the memory exits the self-refresh mode, output a second-level self-refresh control signal S2 at the above-mentioned first output terminal.

[0039] Optionally, the first level may be a high level, and the second level may be a low level. However, the present invention is not limited thereto, and the first level may also be a low level, and the second level may also be a high level.

[0040] In some embodiments, the self-refresh mode signal S1 may include multiple signals.

[0041] For example, for storage media of large-capacity memory, synchronous dynamic random access memory (SDRAM) is usually used, such as double data rate synchronous dynamic random access memory (DDR SDRAM, DDR for short). Among them, the fifth generation DDR (hereinafter referred to as DDR5) will have a separate self-refresh mode entry command signal (hereinafter referred to as SRE CMD signal) and self-refresh mode exit command signal (hereinafter referred to as SRX CMD signal). The SRE CMD signal is used to control the memory to enter the self-refresh mode, and the SRX CMD signal is used to control the memory to exit the self-refresh mode. The fourth generation DDR (hereinafter referred to as DDR4) uses the refresh command signal (hereinafter referred to as REF CMD signal) and the clock enable signal (hereinafter referred to as CKE signal) to work together to control the memory to enter the self-refresh mode or control the memory to exit the self-refresh mode.

[0042] In some embodiments, when the memory is DDR5, the self-refresh mode signal S1 includes an SRE CMD signal and an SRX CMD signal; when the memory is DDR4, the self-refresh mode signal S1 includes a REF CMD signal and a CKE signal.

[0043] It can be understood that in the embodiment of the present disclosure, the self-refresh control signal generation module 100 can be used to convert the multiple signals contained in the self-refresh mode signal S1 into a self-refresh control signal S2, and the level state of the self-refresh control signal S2 is used to indicate that the memory enters the self-refresh mode or indicates that the memory exits the self-refresh mode.

[0044] Exemplarily, when the self-refresh control signal S2 is at a high level, the self-refresh control signal S2 instructs the memory to enter the self-refresh mode; when the self-refresh control signal S2 is at a low level, the self-refresh control signal S2 instructs the memory to exit the self-refresh mode.

[0045] In some embodiments, the self-refresh signal generation module 200 includes a first input terminal and a second output terminal. The first input terminal is connected to the first output terminal of the self-refresh control signal generation module 100 for receiving the self-refresh control signal S2, and the second output terminal is used to output a self-refresh signal S3, which is used to instruct the memory to enter a self-refresh operation.

[0046] In some embodiments, the self-refresh signal generation module 200 is configured to generate a shielding signal based on the self-refresh control signal S2, and shield the self-refresh control signal S2 for a preset time period based on the shielding signal before outputting the signal.

[0047] In some embodiments, when the self-refresh control signal S2 received by the self-refresh signal generation module 200 flips from a low level to a high level, the self-refresh signal generation module 200 generates a shielding signal and, based on the shielding signal, shields the self-refresh control signal S2 for a preset time and then outputs it.

[0048] It is understandable that after the memory receives the command signal to enter the self-refresh mode, the normal operation will first use the command signal as an automatic refresh command to perform the automatic refresh operation, and then start the internal self-refresh command generation circuit after the execution is completed to generate a self-refresh command regularly. However, in the case of a large number of short-term commands to enter / exit the self-refresh mode, the memory will be caused to repeatedly perform the automatic refresh operation, resulting in a series of problems that affect the performance of the memory. In the embodiment of the present disclosure, by generating a self-refresh control signal S2, the self-refresh control signal S2 can be used to accurately characterize the state of the self-refresh mode process (specifically, when the self-refresh control signal S2 is high, the memory is in the self-refresh mode process, and when the self-refresh control signal S2 is low, the memory is not in the self-refresh mode process). The self-refresh signal generation module 200 generates a shielding signal based on the self-refresh control signal S2, and based on the shielding signal, the self-refresh control signal S2 is shielded for a preset period of time and then output. Through the shielding signal, the initial refresh operation after the memory enters the self-refresh mode can be shielded, thereby improving the impact of the short-term command to enter / exit the self-refresh mode.

[0049] Furthermore, the preset duration can be set according to actual application requirements. For example, the preset duration can be set to the running time of the first automatic refresh operation after entering the self-refresh operation. This can solve a series of problems such as the DLL repeatedly locking at low voltage due to short-term commands to enter / exit the self-refresh mode.

[0050] In some embodiments, the preset time duration is the time interval between two consecutive refresh commands received by the memory, that is, tREFI. The refresh commands include automatic refresh commands and self-refresh commands.

[0051] In some implementations, the preset time duration may also be greater than tREFI.

[0052] In some embodiments, when the self-refresh control signal S2 output after shielding for a preset time is at a high level, the self-refresh signal generation module 200 can periodically output a self-refresh signal S3 at the second output terminal, and the memory performs a self-refresh operation based on the self-refresh signal S3.

[0053] Optionally, the self-refresh signal S3 may be active at a high level, that is, when the self-refresh signal S3 is at a high level, the memory performs a self-refresh operation.

[0054] It can be understood that after the above-mentioned self-refresh control signal S2 is flipped from a low level to a high level, the self-refresh control signal S2 is shielded by a shielding signal, thereby preventing the memory from performing a refresh operation after initially receiving a command to enter the self-refresh mode, and outputting the self-refresh control signal S2 after shielding it for a preset period of time. This can ensure that the memory can perform normal refresh operations while avoiding the situation where the self-refresh process has ended but the memory has not yet completed a refresh process when the memory receives a large number of short-term commands to enter / exit the self-refresh mode. This can prevent the DLL from being repeatedly locked at a lower operating voltage, while the memory is read and written at a normal operating voltage, thereby improving the performance of the memory.

[0055] Referring to Figure 2, Figure 2 is a schematic diagram illustrating the structure of a self-refresh signal generation module 200 provided in some embodiments of the present disclosure. In some embodiments of the present disclosure, the self-refresh signal generation module 200 includes a shielding signal generation unit 201 and a shielding unit 202. The shielding signal generation unit 201 is connected to the first output terminal of the self-refresh control signal generation module and is configured to receive the self-refresh control signal S2 outputted by the first output terminal.

[0056] In some embodiments, the shielding signal generating unit 201 is configured to generate the shielding signal S4 based on the received self-refresh control signal S2 .

[0057] The shielding signal S4 is a clock signal whose initial level is the second level.

[0058] In some embodiments, the initial level of the shielding signal S4 may also be a clock signal that is inversely proportional to the level of the self-refresh control signal when the memory enters the self-refresh mode. For example, when the self-refresh control signal is at a high level, indicating that the memory enters the self-refresh mode, the initial level of the shielding signal S4 is low; and when the self-refresh control signal is at a low level, indicating that the memory enters the self-refresh mode, the initial level of the shielding signal S4 is high.

[0059] In some embodiments, the shielding unit 202 is connected to the first output terminal and the shielding signal generating unit 201 , respectively, and is configured to receive the self-refresh control signal S2 and the shielding signal S4 .

[0060] In some embodiments, the shielding unit 202 is configured to shield the self-refresh control signal S2 for a preset time period based on the shielding signal S4 and then output the signal.

[0061] In the embodiment of the present disclosure, since the starting level of the above-mentioned shielding signal S4 is a clock signal that is inverted with the level of the self-refresh control signal when instructing the memory to enter the self-refresh mode, the self-refresh control signal can be shielded by the above-mentioned shielding signal S4 when the self-refresh control signal first instructs the memory to enter the self-refresh mode, so that the memory will not perform a refresh operation after it first receives the command to enter the self-refresh mode, thereby avoiding the situation where the self-refresh process has ended but the memory has not yet completed a refresh process when the memory receives a short-term command to enter / exit the self-refresh mode.

[0062] 3 , which is a second structural diagram of a self-refresh signal generating module 200 provided in an embodiment of the present disclosure.

[0063] In some embodiments, the shielding signal generating unit 201 includes an oscillator 2011 , a frequency divider 2012 , and a first inverter NOT1 ; and the shielding unit 202 includes a first AND gate AND1 .

[0064] Among them, the oscillator 2011 is used to output a clock signal CLK with a specific frequency, and the output end of the oscillator 2011 is connected to the input end of the divider 2012; the divider 2012 is used to divide the input clock signal CLK and output a divided clock signal CLK-DIV with a preset frequency, and the output end of the divider 2012 is connected to an input end of the first AND gate AND1; the input end of the first inverter NOT1 is connected to the first output end of the above-mentioned self-refresh control signal generation module, and is used to receive the self-refresh control signal S2 output by the above-mentioned first output end; the output end of the first inverter NOT1 is connected to the reset end R of the divider 2012; the other input end of the first AND gate AND1 is also connected to the above-mentioned first output end, and is used to receive the self-refresh control signal S2 output by the above-mentioned first output end. The output end of the first AND gate AND1 is the second output end of the self-refresh signal generation module 200, and is used to output the self-refresh signal S3.

[0065] The oscillator 2011 can generate a sine wave or other repetitive waveform of desired amplitude and frequency at the output without an external excitation signal. In the disclosed embodiment, the oscillator 2011 can be used to generate a clock signal CLK having a specific frequency and oscillating between a high level and a low level.

[0066] Frequency divider 2012 is an electronic circuit that generates an output signal with an integer fraction of the input signal frequency. In the disclosed embodiment, the input signal of frequency divider 2012 is the aforementioned clock signal CLK, and the output signal is the divided clock signal CLK-DIV. In some embodiments, upon receiving a reset signal at its reset terminal R, frequency divider 2012 divides the frequency of the aforementioned clock signal CLK and outputs the divided clock signal CLK-DIV.

[0067] Optionally, the frequency divider 2012 may divide the frequency of the clock signal CLK by two, four, or eight, which is not limited in the embodiments of the present disclosure.

[0068] An AND gate, also known as an "AND circuit," a logical "product," or a logical "AND" circuit, is a basic logic gate circuit that performs an AND operation. In the disclosed embodiment, the first AND gate AND1 has two input terminals and one output terminal. Its output terminal outputs a high level only when both input terminals of the first AND gate AND1 are simultaneously high (logical 1). Otherwise, its output terminal outputs a low level (logical 0).

[0069] In some embodiments, the self-refresh signal S3 is active at a high level, that is, the memory performs a refresh operation only when the self-refresh signal S3 is at a high level, and does not perform a refresh operation when the self-refresh signal S3 is at a low level.

[0070] In some implementations, the divided clock signal CLK-DIV can be used as the shielding signal S4, wherein the divided clock signal CLK-DIV is a clock signal with a low initial level.

[0071] In some embodiments, by setting the frequency of the divided clock signal CLK-DIV, the duration during which the initial level of the divided clock signal CLK-DIV remains low can be set to the preset duration. For example, by setting the frequency of the divided clock signal CLK-DIV, half a cycle of the divided clock signal CLK-DIV can be set to be greater than or equal to the preset duration.

[0072] In some embodiments, the frequency of the divided clock signal CLK-DIV matches the refresh frequency of the memory.

[0073] For example, assuming that the time interval tREFI between two consecutive refresh commands received by the memory is a (ns), the frequency of the divided clock signal CLK-DIV can match the refresh frequency, and the divided clock signal CLK-DIV initially has a low level for a (ns). For a short-term command to enter the self-refresh mode (high level), the presence of the first AND gate AND1 can make the output self-refresh signal S3 low. That is, during the period when the divided clock signal CLK-DIV is still at a low level, regardless of whether the self-refresh control signal S2 is at a low level or a high level, the self-refresh signal S3 is always low. That is, the low level of the divided clock signal CLK-DIV can intercept the brief high level of the self-refresh control signal S2.

[0074] In some embodiments, the first inverter NOT1 may also be a NOT gate circuit, which can change the output level to a level opposite to the input level.

[0075] It can be understood that when the self-refresh mode signal S1 instructs the memory to enter the self-refresh mode, the self-refresh control signal S2 will be flipped from a low level to a high level. After the self-refresh control signal S2 is flipped from a low level to a high level, the self-refresh control signal S2 will be inverted by the first inverter NOT1, and a low level signal will be applied to the reset terminal R of the divider 2012 as the reset signal of the divider 2012, and the divider 2012 will start working (previously, when the self-refresh control signal S2 is at a low level, the reset terminal R of the divider 2012 is at a high level, and the divider 2012 is disabled), and the divided clock signal CLK-DIV is output.

[0076] Since the starting level of the divided clock signal CLK-DIV is a low level and the duration of the low level is equal to the above-mentioned preset duration, one input end of the first AND gate AND1 will continue to receive a low level within the above-mentioned preset duration. Therefore, within the above-mentioned preset duration, even if the self-refresh control signal S2 received by the other receiving end of the first AND gate AND1 is a high level, the self-refresh signal S3 outputted by the output end of the first AND gate AND1 is still a low level, and the memory does not perform a refresh operation.

[0077] It can be understood that for a short-term command to enter the self-refresh mode, that is, when the time for the self-refresh control signal S2 to maintain a high level is less than the above-mentioned preset time length, due to the existence of the above-mentioned divided clock signal CLK-DIV, the self-refresh signal S3 output from the output end of the first AND gate AND1 will remain at a low level unchanged, that is, the first AND gate AND1 can use the above-mentioned divided clock signal CLK-DIV to shield the self-refresh control signal S2 within the above-mentioned preset time length.

[0078] In some embodiments, when the self-refresh control signal S2 maintains a high level for a time greater than the above-mentioned preset time length, the output end of the first AND gate AND1 will output a high-level self-refresh signal S3 at the end of the above-mentioned preset time length. At this time, the memory itself will periodically generate a refresh command and perform a refresh operation according to the generated refresh command.

[0079] In the refresh control circuit provided by the disclosed embodiments, the self-refresh signal generation module shields the self-refresh control signal for a preset period of time through a shielding signal and then outputs it. This allows the memory to not perform a refresh operation after initially receiving a command to enter the self-refresh mode, but to output the self-refresh control signal after shielding it for a preset period of time. This can prevent the memory from performing normal refresh operations while ensuring that the memory can perform normal refresh operations. This can also prevent the memory from having a self-refresh process terminated but not yet completed when receiving a short-term command to enter / exit the self-refresh mode. This also avoids a series of problems, such as timing matching, caused by the DLL being locked at a low operating voltage during the refresh process while the memory is read or written at a normal operating voltage the next time. This improves memory performance.

[0080] Based on the description in the above embodiments, in some embodiments of the present disclosure, the self-refresh mode signal S1 received by the above memory includes a self-refresh entry signal and a self-refresh exit signal. The self-refresh control signal generation module 100 is configured to: receive the above self-refresh entry signal and the self-refresh exit signal, and generate a self-refresh control signal S2 based on the transition edges of the above self-refresh entry signal and the self-refresh exit signal, wherein the active level of the self-refresh control signal S2 starts at the transition edge of the above self-refresh entry signal and ends at the transition edge of the above self-refresh exit signal.

[0081] For example, taking the memory as DDR5 as an example, the self-refresh entry signal may be an SRE CMD (Self Refresh Entry Command) signal, and the self-refresh exit signal may be an SRX CMD (Self Refresh Exit Command) signal.

[0082] Referring to Figure 4, Figure 4 is a first structural diagram of a self-refresh control signal generation module 100 provided in an embodiment of the present disclosure. In some embodiments of the present disclosure, the self-refresh control signal generation module 100 includes a second inverter NOT2, a first NOR gate NOR1, and a first latch 101; wherein the first latch 101 includes a first NAND gate NAND1 and a second NAND gate NAND2.

[0083] In some embodiments, a receiving end of the second inverter NOT2 is used to receive the SRE CMD signal, and an output end of the second inverter NOT2 is connected to an input end of the first NAND gate NAND1; another input end of the first NAND gate NAND1 is connected to the output end of the second NAND gate NAND2, and the output end of the first NAND gate NAND1 is connected to an input end of the second NAND gate NAND2; another input end of the second NAND gate NAND2 is connected to the output end of the first NOR gate NOR1, one input end of the first NOR gate NOR1 is used to receive the SRX CMD signal, and the other input end of the first NOR gate NOR1 is used to receive the start reset signal PWR Reset; the output end of the first NAND gate NAND1 is the first output end of the self-refresh control signal generation module 100, which is used to output the self-refresh control signal S2.

[0084] In some embodiments, the first NOR gate NOR1 can also be replaced by a NOT gate, whose input terminal is used to receive the SRX CMD signal, and whose output terminal is connected to an input terminal of the second NAND gate NAND2. That is, in some embodiments, the reset signal PWR Reset may not be required.

[0085] Among them, the NOR gate can realize the logical NOR function. The NOR gate has two input terminals and one output terminal. Only when both input terminals receive a low level (logic 0) will the output terminal output a high level (logic 1). It can also be understood that if any input is a high level (logic 1), the output is a low level (logic 0).

[0086] The NAND gate has two inputs and one output. If both inputs receive a high level (logic 1), the output outputs a low level (logic 0); if at least one of the two inputs receives a low level (logic 0), the output output is a high level (logic 1).

[0087] In some implementations, PWR Reset remains low after the memory system is powered on.

[0088] PWR Reset resets the memory system when it is powered on, ensuring the initial state of the latches in the circuit. When needed, PWR Reset switches to a high level to restart the circuit and exit self-refresh mode.

[0089] In some embodiments, the SRE CMD signal and the SRX CMD signal are both valid at high levels, that is, when the SRE CMD signal is high and the SRX CMD signal is low, the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is high; when the SRE CMD signal is low and the SRX CMD signal is high, the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is low.

[0090] Referring to Figure 5, Figure 5 is a second structural diagram of a self-refresh control signal generation module 100 provided in some embodiments of the present disclosure. In some embodiments of the present disclosure, the self-refresh control signal generation module 100 includes a fourth inverter NOT4 and a third latch 103; wherein the third latch 103 includes a third NOR gate NOR3 and a fourth NOR gate NOR4.

[0091] In some embodiments, one input end of the third NOR gate NOR3 is used to receive the SRE CMD signal, the other input end of the third NOR gate NOR3 is connected to the output end of the fourth NOR gate NOR4, the output end of the third NOR gate NOR3 is connected to one input end of the fourth NOR gate NOR4, and the other input end of the fourth NOR gate NOR4 is used to receive the SRX CMD signal; the input end of the fourth inverter NOT4 is connected to the output end of the third NOR gate NOR3, and the output end of the fourth NOR gate NOR4 is the first output end of the self-refresh control signal generation module 100, which is used to output the self-refresh control signal S2.

[0092] In some embodiments, the SRE CMD signal and the SRX CMD signal are both valid at high levels, that is, when the SRE CMD signal is high and the SRX CMD signal is low, the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is high; when the SRE CMD signal is low and the SRX CMD signal is high, the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is low.

[0093] The self-refresh control signal generation module provided in the embodiment of the present disclosure can convert the received self-refresh entry signal and self-refresh exit signal into a self-refresh control signal, and use the level state of the self-refresh control signal to instruct the memory to enter the self-refresh mode or instruct the memory to exit the self-refresh mode; thereby, it is beneficial to subsequently shield short-term commands to enter / exit the self-refresh mode, thereby improving the performance of the memory.

[0094] 6 is a second structural diagram of a refresh control circuit provided in some embodiments of the present disclosure. In some embodiments of the present disclosure, the refresh control circuit includes a self-refresh control signal generation module 100, a self-refresh signal generation module 200, a refresh operation module 300, and a decoder 400.

[0095] In some embodiments, the self-refresh control signal generation module 100 can be the self-refresh control signal generation module 100 shown in Figure 4 or Figure 5, and the self-refresh signal generation module 200 can be the self-refresh signal generation module 200 shown in Figure 2 or Figure 3. The detailed structure can refer to the description in the above embodiment, and this embodiment will not be repeated here.

[0096] In some embodiments, the refresh operation module 300 includes a first OR gate OR; one input end of the first OR gate OR is used to receive an automatic refresh signal, and the other input end of the first OR gate OR is connected to the second output end of the self-refresh signal generation module 200, for receiving a self-refresh signal S3, and the output end of the first OR gate OR is used to output a refresh signal S5, which is used to instruct the memory to perform a refresh operation.

[0097] In some embodiments of the present disclosure, the automatic refresh signal is an automatic refresh command AREF CMD signal sent by a controller corresponding to the memory.

[0098] The AREF CMD signal is a refresh signal periodically sent by the controller when the memory is in an automatic refresh mode.

[0099] Among them, the OR gate is also called the OR circuit, the logic and circuit. The above-mentioned OR gate has two input terminals and one output terminal. As long as one of the two input terminals is at a high level (logic 1), the output terminal output is a high level (logic 1); only when the inputs of the two input terminals are all at a low level (logic 0), the output terminal output is a low level (logic 0).

[0100] In some embodiments, the decoder 400 is configured to receive a signal S output by a controller corresponding to the memory, decode the signal S, and then output the aforementioned SRE CMD signal, SRX CMD signal, and AREF CMD signal.

[0101] In some embodiments of the present disclosure, the self-refresh mode signal S1 received by the memory includes a first mode signal and a second mode signal. The self-refresh control signal generation module 100 is configured to receive the first mode signal and the second mode signal and, when the first mode signal is at an active level, generate a signal that is inverted from the second mode signal as the self-refresh control signal S2.

[0102] For example, taking the above-mentioned memory as DDR4 as an example, the above-mentioned first mode signal can be a refresh command signal (hereinafter referred to as REF CMD signal) sent by the controller corresponding to the memory, and the second mode signal can be an externally input clock enable signal (hereinafter referred to as CKE signal).

[0103] The refresh control circuit provided in the embodiment of the present disclosure utilizes a refresh operation module to enable the memory to execute an automatic refresh signal periodically issued by the controller in automatic refresh mode, and to execute a self-refresh signal periodically generated by the memory itself in self-refresh mode, thereby ensuring that the data stored in the memory is not lost.

[0104] Referring to FIG. 7 , FIG. 7 is a third structural diagram of a self-refresh control signal generation module 100 provided in an embodiment of the present disclosure. In some embodiments of the present disclosure, the self-refresh control signal generation module 100 includes a third inverter NOT3, a second NOR gate NOR2, a third NAND gate NAND3, and a second latch 102. The second latch 102 includes a fourth NAND gate NAND4 and a fifth NAND gate NAND5; wherein:

[0105] In some embodiments, a receiving end of the third inverter NOT3 is used to receive a CKE signal, an output end of the third inverter NOT3 is connected to an input end of the third NAND gate NAND3, another input end of the third NAND gate NAND3 is used to receive a REF CMD signal, an output end of the third NAND gate NAND3 is connected to an input end of a fourth NAND gate NAND4; another input end of the fourth NAND gate NAND4 is connected to an output end of a fifth NAND gate NAND5, an output end of the fourth NAND gate NAND4 is connected to an input end of a fifth NAND gate NAND5; another input end of the fifth NAND gate NAND5 is connected to an output end of the second NOR gate NOR2, one input end of the second NOR gate NOR2 is used to receive a CKE signal, and another input end of the second NOR gate NOR2 is used to receive a start reset signal PWR Reset; an output end of the fourth NAND gate NAND4 is a first output end of the self-refresh control signal generation module 100, used to output a self-refresh control signal S2.

[0106] In some implementations, PWR Reset remains low after the memory system is powered on.

[0107] In some embodiments, the REF CMD signal is active high. When the REF CMD signal is high, the memory enters refresh mode. During the period when the REF CMD signal is high, if the CKE signal is low, the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is high, and the memory enters self-refresh mode. If the CKE signal is high, the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is low, and the memory enters auto-refresh mode. When the REF CMD signal is low, the memory exits refresh mode, and the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is low.

[0108] The self-refresh control signal generation module provided in the embodiment of the present disclosure can convert the received refresh command signal and clock enable signal into a self-refresh control signal, and use the level state of the self-refresh control signal to instruct the memory to enter the self-refresh mode or to instruct the memory to exit the self-refresh mode; thereby, it can be beneficial to subsequently shield short-term commands to enter / exit the self-refresh mode, thereby improving the performance of the memory.

[0109] Referring to Figure 8, Figure 8 is a third structural diagram of a refresh control circuit provided in some embodiments of the present disclosure. In some embodiments of the present disclosure, the refresh control circuit includes a self-refresh control signal generation module 100, a self-refresh signal generation module 200, a refresh operation module 300, a decoder 400, and a second AND gate AND2.

[0110] In some embodiments, the self-refresh control signal generation module 100 can be the self-refresh control signal generation module 100 shown in Figure 7, and the self-refresh signal generation module 200 can be the self-refresh signal generation module 200 shown in Figure 2 or Figure 3. The detailed structure can refer to the description in the above embodiment, and this embodiment will not be repeated here.

[0111] In some embodiments, the refresh operation module 300 includes a first OR gate OR; a second AND gate AND2 having one input terminal configured to receive the REF CMD signal, another input terminal configured to receive the CKE signal, and an output terminal of the second AND gate AND2 connected to one input terminal of the first OR gate OR for outputting the AREF CMD signal. Another input terminal of the first OR gate OR is connected to a second output terminal of the self-refresh signal generation module 200 for receiving the self-refresh signal S3, and an output terminal of the first OR gate OR for outputting a refresh signal S5, which is used to instruct the memory to perform a refresh operation.

[0112] In some embodiments, the REF CMD signal is active high. When the REF CMD signal is high, the memory enters refresh mode. During the period when the REF CMD signal is high, if the CKE signal is high, the AREF CMD signal is high; if the CKE signal is low, the AREF CMD signal is low. The AREF CMD signal is active high. When the AREF CMD signal is high, the memory performs a refresh operation in auto-refresh mode.

[0113] In some implementations, the decoder 400 is configured to receive a signal S output by a controller corresponding to the memory, decode the signal S, and then output the aforementioned REF CMD signal and CKE signal.

[0114] The refresh control circuit provided in the embodiment of the present disclosure utilizes a refresh operation module to enable the memory to execute an automatic refresh signal periodically issued by the controller in automatic refresh mode, and to execute a self-refresh signal periodically generated by the memory itself in self-refresh mode, thereby ensuring that the data stored in the memory is not lost.

[0115] Based on the contents described in the above embodiments, a memory is further disclosed in the embodiments of the present disclosure. The memory includes a refresh control circuit as described in the above embodiments, which will not be described in detail in the embodiments of the present disclosure.

[0116] In the several embodiments provided herein, it should be understood that the module divisions described are merely logical functional divisions. In actual implementation, other divisions may be employed, such as combining or integrating multiple modules into another system, or omitting or disabling certain features. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections via interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0117] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network elements. Some or all of the modules may be selected to achieve the purpose of the solution of this embodiment according to actual needs.

[0118] In addition, the functional modules in the various embodiments of the present disclosure may be integrated into a single processing unit, each module may exist physically separately, or two or more modules may be integrated into a single unit. The aforementioned module integration unit may be implemented in the form of hardware or hardware plus software functional units.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A refresh control circuit, applied to a memory, the refresh control circuit comprising: A self-refresh control signal generating module (100) and a self-refresh signal generating module (200), wherein: The self-refresh control signal generation module (100) comprises at least one input terminal and a first output terminal, wherein the at least one input terminal is used to receive a self-refresh mode signal (S1); the self-refresh control signal generation module (100) is configured to: when the self-refresh mode signal (S1) received by the at least one input terminal indicates that the memory enters a self-refresh mode, output a self-refresh control signal (S2) of a first level at the first output terminal; when the self-refresh mode signal (S1) received by the at least one input terminal indicates that the memory exits a self-refresh mode, output a self-refresh control signal (S2) of a second level at the first output terminal; The self-refresh signal generating module (200) comprises a first input terminal and a second output terminal, wherein the first input terminal is connected to the first output terminal and is used to receive the self-refresh control signal (S2), and the second output terminal is used to output a self-refresh signal (S3), wherein the self-refresh signal (S3) is used to instruct the memory to enter a self-refresh operation; the self-refresh signal generating module (200) is configured to: generate a shielding signal based on the self-refresh control signal (S2), and output the self-refresh control signal (S2) after shielding it for a preset time period based on the shielding signal.

2. The refresh control circuit according to claim 1, wherein: The preset time length is the time interval between two refresh commands received consecutively by the memory.

3. The refresh control circuit according to claim 1 or 2, wherein: The shielding signal is a clock signal whose starting level is the second level.

4. The refresh control circuit according to claim 3, wherein: The self-refresh signal generating module (200) comprises a shielding signal generating unit (201) and a shielding unit (202); The shielding signal generating unit (201) is connected to the first output terminal and is used to receive the self-refresh control signal (S2) outputted by the first output terminal; the shielding signal generating unit (201) is configured to: generate the shielding signal (S4) based on the received self-refresh control signal (S2); The shielding unit (202) is connected to the first output terminal and the shielding signal generating unit (201) respectively, and is used to receive the self-refresh control signal (S2) and the shielding signal (S4); the shielding unit (202) is configured to: based on the shielding signal (S4), shield the self-refresh control signal (S2) for a preset time period and then output it.

5. The refresh control circuit according to claim 4, wherein: The shielding signal generating unit (201) comprises an oscillator (2011), a frequency divider (2012) and a first inverter (NOT1); the shielding unit (202) comprises a first AND gate (AND1); The output end of the oscillator (2011) is connected to the input end of the frequency divider (2012), the output end of the frequency divider (2012) is connected to an input end of the first AND gate (AND1), the input end of the first inverter (NOT1) is connected to the first output end, the output end of the first inverter (NOT1) is connected to a reset end (R) of the frequency divider (2012); the other input end of the first AND gate (AND1) is connected to the first output end; and the output end of the first AND gate (AND1) is the second output end.

6. The refresh control circuit according to any one of claims 1 to 5, wherein: The self-refresh mode signal (S1) includes a self-refresh entry signal and a self-refresh exit signal; The self-refresh control signal generating module (100) is configured to: receive the self-refresh entry signal and the self-refresh exit signal, and generate the self-refresh control signal (S2) based on the transition edge of the self-refresh entry signal and the transition edge of the self-refresh exit signal, wherein the effective level of the self-refresh control signal (S2) starts at the transition edge of the self-refresh entry signal and ends at the transition edge of the self-refresh exit signal.

7. The refresh control circuit according to claim 6, wherein: The self-refresh control signal generating module (100) comprises a second inverter (NOT2), a first NOR gate (NOR1) and a first latch (101), wherein the first latch (101) comprises a first NAND gate (NAND1) and a second NAND gate (NAND2); wherein: The receiving end of the second inverter (NOT2) is used to receive the self-refresh entry signal, and the output end of the second inverter (NOT2) is connected to an input end of the first NAND gate (NAND1); the other input end of the first NAND gate (NAND1) is connected to the output end of the second NAND gate (NAND2), and the output end of the first NAND gate (NAND1) is connected to an input end of the second NAND gate (NAND2); the other input end of the second NAND gate (NAND2) is connected to the output end of the first NOR gate (NOR1), one input end of the first NOR gate (NOR1) is used to receive the self-refresh exit signal, and the other input end of the first NOR gate (NOR1) is used to receive a start reset signal (PWR Reset); the output end of the first NAND gate (NAND1) is the first output end.

8. The refresh control circuit according to claim 6 or 7, wherein: The self-refresh entry signal is a self-refresh mode entry command signal (SRE CMD); the self-refresh exit signal is a self-refresh mode exit command signal (SRX CMD).

9. The refresh control circuit according to any one of claims 1 to 5, wherein: The self-refresh mode signal (S1) includes a first mode signal and a second mode signal; The self-refresh control signal generating module (100) is configured to receive the first mode signal and the second mode signal, and when the first mode signal is at an effective level, generate a signal inverted from the second mode signal as the self-refresh control signal (S2).

10. The refresh control circuit according to claim 9, wherein: The self-refresh control signal generating module (100) comprises a third inverter (NOT3), a second NOR gate (NOR2), a third NAND gate (NAND3) and a second latch (102), wherein the second latch (102) comprises a fourth NAND gate (NAND4) and a fifth NAND gate (NAND5); wherein: The receiving end of the third inverter (NOT3) is used to receive the second mode signal, the output end of the third inverter (NOT3) is connected to an input end of the third NAND gate (NAND3), the other input end of the third NAND gate (NAND3) is used to receive the first mode signal, and the output end of the third NAND gate (NAND3) is connected to an input end of the fourth NAND gate (NAND4); the other input end of the fourth NAND gate (NAND4) is connected to the output end of the fifth NAND gate (NAND5), and the output end of the fourth NAND gate (NAND4) is connected to an input end of the fifth NAND gate (NAND5); the other input end of the fifth NAND gate (NAND5) is connected to the output end of the second NOR gate (NOR2), one input end of the second NOR gate (NOR2) is used to receive the second mode signal, and the other input end of the second NOR gate (NOR2) is used to receive a start reset signal (PWR Reset); the output end of the fourth NAND gate (NAND4) is the first output end.

11. The refresh control circuit according to any one of claims 1 to 10, wherein: The refresh control circuit also includes a refresh operation module (300), and the refresh operation module (300) includes a first OR gate (OR); one input end of the first OR gate (OR) is used to receive an automatic refresh signal, the other input end of the first OR gate (OR) is connected to the second output end, and is used to receive the self-refresh signal (S3); the output end of the first OR gate (OR) is used to output a refresh signal (S5); the refresh signal (S5) is used to instruct the memory to perform a refresh operation.

12. The refresh control circuit according to claim 11, wherein: The automatic refresh signal is an automatic refresh command signal (SREF CMD) sent by a controller corresponding to the memory.

13. The refresh control circuit according to claim 11, wherein: The self-refresh mode signal (S1) includes a first mode signal and a second mode signal; The refresh control circuit also includes a second AND gate (AND2); one input end of the second AND gate (AND2) is used to receive the first mode signal, another input end of the second AND gate (AND2) is used to receive the second mode signal, and the output end of the second AND gate (AND2) is used to output the automatic refresh signal.

14. The refresh control circuit according to any one of claims 9, 10 and 13, wherein: The first mode signal is a refresh command signal (REF CMD) sent by a controller corresponding to the memory, and the second mode signal is a clock enable signal (CKE) input from the outside.

15. A memory comprising the refresh control circuit according to any one of claims 1 to 14.

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