Memory cell, memory and manufacturing method therefor, and electronic device

Abstract

Provided in the embodiments of the present application are a memory cell, a memory and a manufacturing method therefor, and an electronic device. The present application relates to the technical field of semiconductors. The memory cell comprises a vertical transistor. The vertical transistor comprises: a semiconductor column extending in the direction perpendicular to a substrate, wherein the semiconductor column comprises a drain region, a channel region and a source region which are sequentially arranged; a gate insulating layer; and a gate electrode, wherein at least part of the gate insulating layer and the gate electrode are sequentially arranged on the periphery of the channel region of the semiconductor column. The vertical transistor involves at least one of the following: the dielectric constant of the gate insulating layer close to the source region is greater than the dielectric constant of the gate insulating layer close to the drain region; and the work function of the gate electrode close to the source region is greater than the work function of the gate electrode close to the drain region. The embodiments of the present application can inhibit the turning-on of a parasitic triode, and thus electric leakage can be reduced.

Description

Storage unit, memory and manufacturing method thereof, and electronic device Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a storage unit, a memory, a manufacturing method thereof, and an electronic device. Background Art

[0002] Currently, memory technology is developing in the direction of increasing integration and reducing component size. In order to improve integration capabilities, reduce unit area, and manufacture more memory cells within the same chip area, the size of memory devices needs to continue to shrink as technology develops.

[0003] Summary of the Invention

[0004] In response to at least one shortcoming of the existing method, the present application proposes a storage unit, a memory and a manufacturing method thereof, and an electronic device to solve the technical problem of large leakage in the existing memory.

[0005] In a first aspect, an embodiment of the present application provides a memory cell, comprising: a vertical transistor; the vertical transistor comprising:

[0006] A semiconductor column extending in a direction perpendicular to the substrate, wherein the semiconductor column comprises a drain region, a channel region and a source region arranged in sequence;

[0007] A gate insulating layer and a gate, wherein at least a portion of the gate insulating layer and the gate are sequentially arranged on the periphery of the channel region of the semiconductor column;

[0008] In which, the dielectric constant of the gate insulation layer near the source region is greater than the dielectric constant of the gate insulation layer near the drain region; and / or the work function of the gate near the source region is greater than the work function of the gate near the drain region; the drain region is used to be electrically connected to the bit line, and the source region is used to be electrically connected to the capacitor structure.

[0009] In a second aspect, an embodiment of the present application provides a memory, comprising: a plurality of word lines and memory cells arranged in an array as provided in the first aspect;

[0010] The word line is electrically connected to the gates of the memory cells arranged in the same row along a first direction, and the first direction is parallel to the substrate.

[0011] In a third aspect, an embodiment of the present application provides an electronic device comprising the memory described in the second aspect.

[0012] In a fourth aspect, an embodiment of the present application provides a method for manufacturing a memory, comprising:

[0013] Manufacturing semiconductor pillars arranged in an array and extending in a direction perpendicular to the substrate on one side of the substrate, wherein the semiconductor pillars include a drain region, a channel region, and a source region arranged in sequence;

[0014] Manufacturing a plurality of gates and a plurality of word lines, such that the gates and the word lines are sequentially disposed on the periphery of the channel region of the semiconductor pillar, and the gates are insulated from the semiconductor pillar;

[0015] A plurality of gate insulating layers are manufactured so that at least a portion of the gate insulating layers are arranged on the periphery of the channel region of the semiconductor column and are located between the semiconductor column and the gate, wherein the dielectric constant of the gate insulating layer near the source region is greater than the dielectric constant of the gate insulating layer near the drain region; and / or the work function of the gate near the source region is greater than the work function of the gate near the drain region; the drain region is used to be electrically connected to the bit line, and the source region is used to be electrically connected to the capacitor structure.

[0016] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0017] The dielectric constant of the gate insulating layer near the source region is greater than that of the gate insulating layer near the drain region. The larger dielectric constant of the gate insulating layer near the source region can enhance the coupling between the gate and the source, which is beneficial to increasing the energy band barrier height between the source region and the channel region; the smaller dielectric constant of the gate insulating layer near the drain region can reduce the electric field between the drain region and the channel region, and can increase the energy band barrier width between the drain region and the channel region. Therefore, the gate insulating layer with a gradient dielectric constant value can suppress the turn-on of the parasitic transistor, thereby reducing induced leakage.

[0018] The work function of the gate near the source region is greater than that of the gate near the drain region. The larger work function of the gate near the source region and the smaller work function of the gate near the drain region can make the electric field distribution in the channel region more uniform, thereby increasing the on-state current. At the same time, the increased lateral band-to-band tunneling width helps reduce the off-state leakage current, thereby improving the on-off ratio of the memory.

[0019] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0021] FIG1 is a schematic cross-sectional view of a first vertical transistor according to an embodiment of the present application;

[0022] FIG2 is a schematic cross-sectional view of a second vertical transistor according to an embodiment of the present application;

[0023] FIG3 is a schematic cross-sectional view of a third vertical transistor provided in an embodiment of the present application;

[0024] FIG4 is a schematic top view of a memory provided in an embodiment of the present application;

[0025] FIG5 is a schematic diagram of a cross-sectional structure of a first memory device provided in an embodiment of the present application along a first direction;

[0026] FIG6 is a schematic diagram of a cross-sectional structure of a first memory device provided in an embodiment of the present application along a second direction;

[0027] FIG7 is a schematic diagram of a cross-sectional structure of a second memory device provided in an embodiment of the present application along a first direction;

[0028] FIG8 is a schematic diagram of a cross-sectional structure of a second memory device provided in an embodiment of the present application along a second direction;

[0029] FIG9 is a schematic cross-sectional structure diagram of a third memory device provided in an embodiment of the present application along a first direction;

[0030] FIG10 is a schematic cross-sectional structure diagram of a third memory device provided in an embodiment of the present application along the second direction;

[0031] FIG11 is a schematic flow chart of a method for manufacturing any memory provided in an embodiment of the present application;

[0032] 12 to 27 are schematic diagrams of each step in the flowchart of any memory manufacturing method provided in the embodiments of the present application;

[0033] 28 to 43 are schematic diagrams obtained from each step in the flowchart of the method for manufacturing the first memory provided in an embodiment of the present application;

[0034] Figures 44 to 59 are schematic diagrams obtained from each step in the flow chart of the manufacturing method of the second memory provided in an embodiment of the present application.

[0035] Explanation of the accompanying drawings: 1-substrate; 2-semiconductor pillar; 21-drain region; 22-channel region; 23-source region; 3-gate; 31-first gate; 32-second gate; 4-gate insulating layer with a gradient dielectric constant; 41-gate insulating layer with a constant dielectric constant; 5-word line; 51-first word line; 52-second word line; 6-bit line; 61-first bit line; 62-second bit line; 71-capacitor structure; 711-first electrode; 712-second electrode; 713-dielectric layer; 72-metal plug; 73-first isolation layer; 74-second isolation layer; 75-third isolation layer; 81-first dielectric layer ;82-second dielectric layer;821-second dielectric structure;83-metal layer;831-first metal layer;8311-first metal structure;832-second metal layer;8321-second metal structure;84-metal structure;85-first hole;86-sacrificial dielectric layer;91-initial substrate;92-second bit line layer;93-conductive structure;94-initial first bit line;95-third dielectric layer;96-protective film;98-fourth dielectric layer. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0037] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a", "an", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of this application refers to the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0038] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0039] The research and development strategy of this application includes: 4F2 DRAM (Magnetic Random Access Memory) technology, which combines vertical transistors with capacitors, is a major future DRAM research and development direction. However, current DRAM suffers from significant leakage, which can easily lead to a degradation in charge retention time.

[0040] Specifically, the floating body effect generated by the vertical transistor in the memory easily forms a parasitic transistor, resulting in leakage problems, which degrades the charge retention time.

[0041] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0042] An embodiment of the present application provides a memory cell, which includes a vertical transistor. The structural schematic diagram of the vertical transistor is shown in Figures 1 to 3 and includes a semiconductor column 2, a gate insulating layer and a gate 3.

[0043] The semiconductor column 2 extends in a direction perpendicular to the substrate 1 , and includes a drain region 21 , a channel region 22 and a source region 23 arranged in sequence.

[0044] At least a portion of the gate insulating layer 4 and the gate 3 are sequentially disposed on the periphery of the channel region 22 of the semiconductor pillar 2 .

[0045] Among them, the dielectric constant of the gate insulation layer 4 near the source region 23 is greater than the dielectric constant of the gate insulation layer 4 near the drain region 21; and / or, the work function of the gate 3 near the source region 23 is greater than the work function of the gate 3 near the drain region 21; the drain region 21 is used to be electrically connected to the bit line 6, and the source region 23 is used to be electrically connected to the capacitor structure 71.

[0046] It is understood that the semiconductor pillar 2 includes a drain region 21, a channel region 22, and a source region 23, which are arranged in sequence. The drain region 21 or the source region 23 is arranged on the side of the channel region 22 close to the substrate 1. Typically, the source region 23 is electrically connected to the capacitor structure 71, so this application uses the example of the drain region 21 being arranged on the side of the channel region 22 close to the substrate 1 and the source region 23 being arranged on the side of the channel region 22 away from the substrate 1 for specific description.

[0047] In this embodiment, FIG1 is a schematic structural diagram of the first vertical transistor provided in the embodiment of the present application. The work function of the gate 3 in FIG1 is the same, and the gate insulating layer 4 has a gradient dielectric constant value, specifically: the dielectric constant of the gate insulating layer 4 close to the source region 23 is greater than the dielectric constant of the gate insulating layer 4 close to the drain region 21. The dielectric constant of the gate insulating layer 4 close to the source region 23 is larger, which can enhance the coupling between the gate 3 and the source, and is beneficial to improving the energy band barrier height between the source region 23 and the channel region 22; the dielectric constant of the gate insulating layer 4 close to the drain region 21 is smaller, which can reduce the electric field between the drain region 21 and the channel region 22, and can increase the energy band barrier width between the drain region 21 and the channel region 22, so that the gate insulating layer 4 with a gradient dielectric constant value can suppress the opening of the parasitic transistor, thereby reducing induced leakage.

[0048] FIG2 is a schematic diagram of the structure of the second vertical transistor provided in an embodiment of the present application. In FIG2 , the gate insulating layer 41 has a constant dielectric constant value, and the gate 3 has different work functions. Specifically, the work function of the gate 3 near the source region 23 is greater than the work function of the gate 3 near the drain region 21. The work function of the gate 3 near the source region 23 is larger, and the work function of the gate 3 near the drain region 21 is smaller, which can make the electric field distribution in the channel region 22 more uniform, thereby increasing the on-state current; at the same time, the lateral band-to-band tunneling width is increased, which is conducive to reducing the off-state leakage current, thereby improving the switching ratio of the memory.

[0049] Figure 3 is a schematic diagram of the structure of a third vertical transistor provided by an embodiment of the present application. In Figure 3, the gate insulating layer 4 has a gradient dielectric constant value, and the gate 3 has different work functions. The gradient dielectric constant value of the gate insulating layer 4 can suppress the turn-on of the parasitic transistor, thereby reducing leakage. The gate 3 with different work functions can make the electric field distribution in the channel region 22 more uniform, thereby increasing the on-state current. At the same time, the lateral band-to-band tunneling width is increased and the off-state leakage current is reduced, thereby improving the on-off ratio of the memory.

[0050] It should be noted that the material of the semiconductor pillar 2 can be silicon or silicon germanium.

[0051] Optionally, the electric field distribution in the channel region 22 is uniform.

[0052] In this embodiment, the electric field distribution in the channel region 22 is uniform, which can increase the on-state current.

[0053] Optionally, the dielectric constant of the gate insulating layer 4 close to the source region 23 is greater than 1 and not greater than 3.9, and the dielectric constant of the gate insulating layer 4 close to the drain region 21 is greater than 3.9 and not greater than 50.

[0054] In this embodiment, the dielectric constant of the gate insulating layer 4 is within the above range, which can reduce the electric field between the channel and the drain, enhance the coupling between the gate 3 and the source, inhibit the turn-on of the parasitic transistor, and reduce leakage.

[0055] Optionally, the gate insulating layer 4 is disposed on the peripheries of the drain region 21 , the channel region 22 and the source region 23 .

[0056] In this embodiment, the gate insulating layer 4 is simultaneously arranged on the periphery of the drain region 21, the source region 23 and the channel region 22. The dielectric constant of the gate insulating layer 4 arranged on the periphery of the drain region 21 is smaller than the dielectric constant of the gate insulating layer 4 arranged on the periphery of the source region 23, which can suppress the turning on of the parasitic transistor and reduce leakage.

[0057] Optionally, the gate 3 includes a stacked first gate 31 and a second gate 32, and the work function of the second gate 32 close to the source region 23 is greater than the work function of the first gate 31 close to the drain region 21; the difference between the work function of the second gate 32 and the work function of the first gate 31 is not less than 0.1 electron volts and not greater than 0.5 electron volts.

[0058] In this embodiment, the work function of the second gate 32 close to the source region 23 is greater than the work function of the first gate 31 close to the drain region 21, and the difference between the work function of the second gate 32 and the work function of the first gate 31 is within the above range, which can help make the electric field distribution in the channel region 22 more uniform, increase the on-state current, and reduce the off-state current, which is beneficial to improving the switching ratio of the memory.

[0059] Optionally, the material of the first gate 31 includes undoped polysilicon, and the material of the second gate 32 includes polysilicon with a P-type doping element.

[0060] In this embodiment, the first gate 31 may be undoped polysilicon, and the second gate 32 may be heavily P-type doped polysilicon, so that the work function of the second gate 32 is greater than that of the first gate 31 .

[0061] Optionally, the doping ions in the source region 23 , the doping ions in the drain region 21 , and the doping ions in the channel region 22 are of the same polarity.

[0062] In this embodiment, the doping ions in the source region 23, the doping ions in the drain region 21, and the doping ions in the channel region 22 are of the same polarity, that is, the vertical transistor of the present application is a junction-less type transistor, which can reduce leakage. The doping concentrations of the doping ions in the source region 23, the doping ions in the drain region 21, and the doping ions in the channel region 22 are the same, or the doping concentrations of the doping ions in the source region 23, the doping ions in the drain region 21, and the doping ions in the channel region 22 are different. The doping concentrations of the doping ions in the source region 23, the doping ions in the drain region 21, and the doping ions in the channel region 22 can be selected according to actual conditions.

[0063] Based on the same inventive concept, an embodiment of the present application provides a memory, the structural schematic diagrams of the memory are shown in Figures 4 to 10, and the memory includes multiple word lines 5 and array-arranged storage cells as provided in the above embodiment.

[0064] The word line 5 is electrically connected to the gates 3 of the memory cells arranged in the same row along a first direction, where the first direction is parallel to the substrate 1 .

[0065] In this embodiment, FIG4 is a schematic top view of a memory device provided by an embodiment of the present application. In the case where vertical transistors have three structures, the memory device formed by vertical transistors also has three structures. FIG5 is a schematic cross-sectional structure diagram of the first memory device provided by an embodiment of the present application along a first direction; FIG6 is a schematic cross-sectional structure diagram of the first memory device provided by an embodiment of the present application along a second direction. The work function of the gate 3 in FIG5 and FIG6 is the same, and the gate insulating layer 4 has a gradient dielectric constant value. Specifically, the dielectric constant of the gate insulating layer 4 near the source region 23 is greater than the dielectric constant of the gate insulating layer 4 near the drain region 21. The larger dielectric constant of the gate insulating layer 4 near the source region 23 can enhance the coupling between the gate 3 and the source, which is beneficial to increasing the energy band barrier height between the source region 23 and the channel region 22. The smaller dielectric constant of the gate insulating layer 4 near the drain region 21 can reduce the electric field between the drain region 21 and the channel region 22, which can increase the energy band barrier height between the drain region 21 and the channel region 22. Therefore, the gate insulating layer 4 having a gradually changing dielectric constant value can suppress the turn-on of the parasitic transistor, thereby reducing leakage.

[0066] Figure 7 is a schematic diagram of the cross-sectional structure of the second memory provided by an embodiment of the present application along the first direction; Figure 8 is a schematic diagram of the cross-sectional structure of the second memory provided by an embodiment of the present application along the second direction. In Figures 7 and 8, the gate insulating layer 41 has a constant dielectric constant value, and the gate 3 has different work functions, specifically: the work function of the gate 3 close to the source region 23 is greater than the work function of the gate 3 close to the drain region 21. The work function of the gate 3 close to the source region 23 is larger, and the work function of the gate 3 close to the drain region 21 is smaller, which can make the electric field distribution in the channel region 22 more uniform, thereby increasing the on-state current; at the same time, the lateral band-to-band tunneling width is increased, and the off-state leakage current is reduced, thereby improving the switching ratio of the memory.

[0067] FIG9 is a schematic diagram of the cross-sectional structure of the third memory provided by an embodiment of the present application along the first direction; FIG10 is a schematic diagram of the cross-sectional structure of the third memory provided by an embodiment of the present application along the second direction. In FIG9 and FIG10, the gate insulating layer 4 has a gradually changing dielectric constant value, and the gate 3 has different work functions. The gradually changing dielectric constant value of the gate insulating layer 4 can suppress the turning on of the parasitic transistor, thereby reducing leakage; the gate 3 with different work functions can make the electric field distribution in the channel region 22 more uniform, thereby increasing the on-state current. At the same time, the lateral band-to-band tunneling width is increased and the off-state leakage current is reduced, thereby improving the switching ratio of the memory.

[0068] It should be noted that, in this embodiment, the gate 3 and the word line 5 are sequentially arranged on the periphery of the channel region 22 of the semiconductor pillar 2. The dotted lines in Figures 5, 7 and 9 do not exist in actual products and are only used to illustrate the positional relationship between the gate 3 and the word line 5.

[0069] Optionally, the word line 5 includes a stacked first word line 51 and a second word line 52, the first word line 51 is electrically connected to the first gate of the memory cell, the second word line 52 is electrically connected to the second gate of the memory cell, the second word line 52 is arranged close to the source region 23, and the first word line 51 is arranged close to the drain region 21.

[0070] As shown in Figures 7 to 10, the word line 5 includes a stacked first word line 51 and a second word line 52. The second word line 52 arranged near the source region 23 is electrically connected to the second gate, and the first word line 51 arranged near the drain region 21 is electrically connected to the first gate. The work function of the second word line 52 is greater than the work function of the first word line 51.

[0071] Optionally, referring to Figures 4 to 10, the memory also includes a plurality of bit lines 6, which extend along a second direction. The bit lines 6 are arranged on a side of the semiconductor pillars 2 of each memory cell arranged in the same column along the second direction close to the substrate 1. The second direction is parallel to the substrate 1 and has a designed angle with the first direction.

[0072] In this embodiment, the bit line 6 is electrically connected to the semiconductor pillars 2 of the memory cells arranged in the same column along the second direction.

[0073] It should be noted that the first direction and the second direction have a design angle, which can be 45°, 60°, 90°, 120° or 145°, etc., and can be designed according to actual needs. In this embodiment, the first direction is perpendicular to the second direction, and the design angle is 90°.

[0074] Optionally, the bit line 6 includes a first bit line 61 and a second bit line 62 . The second bit line 62 is located on a side of the first bit line 61 away from the substrate 1 . The first bit line 61 includes a metallized semiconductor, and the second bit line 62 includes a doped semiconductor.

[0075] In this embodiment, the second bit line 62 is electrically connected to the semiconductor pillar 2, which is epitaxially grown on the side of the second bit line 62 facing away from the substrate 1. The metallized semiconductor includes a non-metallic silicide. The second bit line 62 forms an ohmic contact with the drain region 21 of the semiconductor pillar 2, reducing the contact resistance between the second bit line 62 and the drain region 21. The first bit line 61 includes a metal silicide, which reduces the resistance of the first bit line 61 itself.

[0076] Optionally, the memory further includes a capacitor structure 71 , and the capacitor structure 71 is electrically connected to the semiconductor pillar 2 through a metal plug 72 .

[0077] Optionally, the capacitor structure 71 includes a first electrode 711 , a dielectric layer 713 , and a second electrode 712 , which are sequentially spaced away from the semiconductor pillar 2 .

[0078] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes the memory provided by the above embodiment.

[0079] In this embodiment, since the electronic device adopts any of the memories provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0080] Optionally, the electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device or a smart mobile terminal.

[0081] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any of the memories provided in the above-mentioned embodiments of this application in different devices according to actual application requirements, thereby obtaining the electronic device provided in the embodiments of this application.

[0082] Based on the same inventive concept, an embodiment of the present application provides a method for manufacturing a memory. The method is shown in FIG11 . The method includes the following steps S101 to S103 :

[0083] S101 : manufacturing semiconductor pillars 2 arranged in an array and extending in a direction perpendicular to the substrate 1 on one side of the substrate 1 , wherein the semiconductor pillars 2 include a drain region 21 , a channel region 22 and a source region 23 arranged in sequence.

[0084] Optionally, step S101 includes the following steps S11 to S12 , with reference to the flowchart shown in FIG12 .

[0085] S11: A stacked first dielectric layer 81, a metal layer 83, and a second dielectric layer 82 are manufactured on the side of the bit line 6 away from the substrate 1, and the second dielectric layer 82, the metal layer 83, and the first dielectric layer 81 are patterned to obtain a metal structure 84 and an array of first holes 85, so that the side surface of the metal structure 84 and the upper surface of the bit line 6 are exposed in the first hole 85.

[0086] In this embodiment, FIG28 is a schematic cross-sectional view of the structure along the first direction after fabricating a stacked first dielectric layer 81, a metal layer 83, and a second dielectric layer 82 on the side of the bit line 6 away from the substrate 1. FIG29 is a schematic cross-sectional view of the structure along the second direction after fabricating a stacked first dielectric layer 81, a metal layer 83, and a second dielectric layer 82 on the side of the bit line 6 away from the substrate 1. FIG30 is a schematic cross-sectional view of the structure along the first direction after patterning the second dielectric layer 82, the metal layer 83, and the first dielectric layer 81 to obtain a metal structure 84 and arrayed first holes 85, such that the side surfaces of the metal structure 84 and the top surface of the bit line 6 are exposed within the first holes 85. FIG31 is a schematic cross-sectional view of the structure along the second direction after patterning the second dielectric layer 82, the metal layer 83, and the first dielectric layer 81 to obtain a metal structure 84 and arrayed first holes 85, such that the side surfaces of the metal structure 84 and the top surface of the bit line 6 are exposed within the first holes 85.

[0087] In this embodiment, the material of the first dielectric layer 81 and the material of the second dielectric layer 82 may both be silicon dioxide, and the material of the metal layer 83 may be titanium nitride.

[0088] S12 : manufacturing a sacrificial dielectric layer 86 on the sidewall of the first hole 85 , and epitaxially growing a semiconductor pillar 2 along the first hole 85 on a side of the bit line 6 away from the substrate 1 .

[0089] In this embodiment, Figure 32 is a schematic cross-sectional view of the structure along a first direction after forming a sacrificial dielectric layer 86 on the sidewalls of the first hole 85; Figure 33 is a schematic cross-sectional view of the structure along a second direction after forming a sacrificial dielectric layer 86 on the sidewalls of the first hole 85. Figure 34 is a schematic cross-sectional view of the structure along a first direction after epitaxial growth of a semiconductor pillar 2 along the first hole 85 on the side of the bitline 6 away from the substrate 1; Figure 35 is a schematic cross-sectional view of the structure along a second direction after epitaxial growth of a semiconductor pillar 2 along the first hole 85 on the side of the bitline 6 away from the substrate 1.

[0090] In this embodiment, a sacrificial dielectric layer 86 is formed on the sidewall of the first hole 85 to expose the upper surface of the second bit line 62 , so as to facilitate epitaxial growth of the semiconductor pillar 2 on the upper surface of the second bit line 62 .

[0091] Specifically, the sacrificial dielectric layer 86 may be silicon nitride; the thickness of the sacrificial dielectric layer 86 may be no less than 4 nanometers and no more than 6 nanometers. In this embodiment, the thickness of the sacrificial dielectric layer 86 may be 5 nanometers.

[0092] The semiconductor pillar 2 is formed by direct epitaxial growth on the surface of the bit line 6. The drain region 21, the channel region 22 and the source region 23 of the semiconductor pillar 2 can be of the same polarity, for example, they can all be n-type silicon. The doping concentration of the semiconductor pillar 2 is not less than 5×10 18 cm -3 (per cubic centimeter) and not more than 1×10 19 cm -3 .

[0093] S102 : manufacturing a plurality of gates 3 and a plurality of word lines 5 , such that the gates 3 and the word lines 5 are sequentially arranged at the periphery of the channel region 22 of the semiconductor pillar 2 , and the gates 3 are insulated from the semiconductor pillar 2 .

[0094] Optionally, in the above step S102 , it includes: patterning the metal structure 84 to obtain the gate 3 and the word line 5 sequentially arranged on the periphery of the sacrificial dielectric layer 86 .

[0095] In this embodiment, Figure 36 is a schematic diagram of the cross-sectional structure along the first direction after the metal structure 84 is patterned to obtain the gate 3 and the word line 5 that are sequentially arranged on the periphery of the sacrificial dielectric layer 86; Figure 37 is a schematic diagram of the cross-sectional structure along the second direction after the metal structure 84 is patterned to obtain the gate 3 and the word line 5 that are sequentially arranged on the periphery of the sacrificial dielectric layer 86.

[0096] In this embodiment, the word line 5 extends along the second direction and is electrically connected to the gates 3 located in the same column along the second direction.

[0097] While the metal structure 84 is being patterned, the second dielectric layer 82 is also patterned to obtain a second dielectric structure 821 .

[0098] S103: Manufacture multiple gate insulation layers 4, so that at least part of the gate insulation layers 4 are arranged on the periphery of the channel region 22 of the semiconductor column 2, and are located between the semiconductor column 2 and the gate 3, wherein the dielectric constant of the gate insulation layer 4 close to the source region 23 is greater than the dielectric constant of the gate insulation layer 4 close to the drain region 21; and / or, the work function of the gate 3 close to the source region 23 is greater than the work function of the gate 3 close to the drain region 21; the drain region 21 is used to be electrically connected to the bit line 6, and the source region 23 is used to be electrically connected to the capacitor structure 71.

[0099] Optionally, in the above step S103, it includes: removing the sacrificial dielectric layer 86, manufacturing a gate insulation layer 4 between the semiconductor column 2 and the gate 3, so that at least part of the gate insulation layer 4 is arranged on the periphery of the channel region 22 of the semiconductor column 2 and is located between the semiconductor column 2 and the gate 3.

[0100] In this embodiment, Figure 38 is a schematic diagram of the cross-sectional structure along the first direction after removing the sacrificial dielectric layer 86 and manufacturing the gate insulation layer 4 between the semiconductor column 2 and the gate 3; Figure 39 is a schematic diagram of the cross-sectional structure along the second direction after removing the sacrificial dielectric layer 86 and manufacturing the gate insulation layer 4 between the semiconductor column 2 and the gate 3.

[0101] Optionally, the sacrificial dielectric layer 86 is removed and a gate insulating layer 4 is manufactured between the semiconductor column 2 and the gate 3, including: controlling the dielectric constant of the gate insulating layer 4 based on an ALD (Atomic Layer Depositio, chemical vapor deposition technology) doping process, so that the dielectric constant of the gate insulating layer 4 near the source region 23 of the semiconductor column 2 is greater than the dielectric constant of the gate insulating layer 4 near the drain region 21.

[0102] In this embodiment, referring to FIG. 38 and FIG. 39 , a gate insulating layer 4 having a gradient dielectric constant is manufactured, which can suppress the turn-on of the parasitic transistor and reduce leakage.

[0103] Optionally, in the above step S11, a stacked first dielectric layer 81, a metal layer 83, and a second dielectric layer 82 are manufactured on a side of the bit line 6 away from the substrate 1, including:

[0104] A stacked first dielectric layer 81, a first metal layer 831, a second metal layer 832, and a second dielectric layer 82 are manufactured on the side of the bit line 6 away from the substrate 1, so that the work function of the second metal layer 832 is greater than the work function of the first metal layer 831, and the metal layer 83 includes a stacked first metal layer 831 and a second metal layer 832.

[0105] In this embodiment, Figure 44 is a schematic diagram of the cross-sectional structure along the first direction after the stacked first dielectric layer 81, first metal layer 831, second metal layer 832 and second dielectric layer 82 are manufactured on the side of the bit line 6 away from the substrate 1; Figure 45 is a schematic diagram of the cross-sectional structure along the second direction after the stacked first dielectric layer 81, first metal layer 831, second metal layer 832 and second dielectric layer 82 are manufactured on the side of the bit line 6 away from the substrate 1.

[0106] In this embodiment, the work function of the manufactured second metal layer 832 is greater than the work function of the first metal layer 831 , which can make the electric field distribution in the channel region 22 more uniform and improve the on / off ratio of the device.

[0107] Optionally, after manufacturing the stacked first dielectric layer 81, the first metal layer 831, the second metal layer 832, and the second dielectric layer 82 on the side of the bit line 6 away from the substrate 1, the memory manufacturing method further includes:

[0108] The first dielectric layer 81 , the first metal layer 831 , the second metal layer 832 and the second dielectric layer 82 are patterned to obtain a first metal structure 8311 , a first metal structure 8321 and an array-arranged first hole 85 , so that the surfaces of the first metal structure 8311 , the first metal structure 8321 and the bit line 6 are all exposed in the first hole 85 .

[0109] In this embodiment, Figure 46 is a schematic diagram of the cross-sectional structure along the first direction after patterning the first dielectric layer 81, the first metal layer 831, the second metal layer 832 and the second dielectric layer 82 to obtain the first metal structure 8311, the first metal structure 8321 and the first holes 85 arranged in an array, so that the surfaces of the first metal structure 8311, the first metal structure 8321 and the bit line 6 are all exposed in the first holes 85; Figure 47 is a schematic diagram of the cross-sectional structure along the second direction after patterning the first dielectric layer 81, the first metal layer 831, the second metal layer 832 and the second dielectric layer 82 to obtain the first metal structure 8311, the first metal structure 8321 and the first holes 85 arranged in an array, so that the surfaces of the first metal structure 8311, the first metal structure 8321 and the bit line 6 are all exposed in the first holes 85.

[0110] A sacrificial dielectric layer 86 is formed on the sidewalls of the first hole 85 .

[0111] In this embodiment, Figure 48 is a schematic diagram of the cross-sectional structure along the first direction after the sacrificial dielectric layer 86 is manufactured on the side wall of the first hole 85; Figure 49 is a schematic diagram of the cross-sectional structure along the second direction after the sacrificial dielectric layer 86 is manufactured on the side wall of the first hole 85.

[0112] The semiconductor pillar 2 is epitaxially grown along the first hole 85 on a side of the bit line 6 away from the substrate 1 .

[0113] In this embodiment, Figure 50 is a schematic diagram of the cross-sectional structure along the first direction after the semiconductor column 2 is epitaxially grown along the first hole 85 on the side of the bit line 6 away from the substrate 1; Figure 51 is a schematic diagram of the cross-sectional structure along the second direction after the semiconductor column 2 is epitaxially grown along the first hole 85 on the side of the bit line 6 away from the substrate 1.

[0114] The first metal structure 8311 and the first metal structure 8321 are patterned to manufacture a plurality of gates 3 and a plurality of word lines 5, so that the gates 3 and the word lines 5 are sequentially arranged on the periphery of the channel region 22 of the semiconductor pillar 2, and the gates 3 are insulated from the semiconductor pillar 2.

[0115] In this embodiment, Figure 52 is a schematic diagram of the cross-sectional structure along the first direction after patterning the first metal structure 8311 and the first metal structure 8321 to obtain the gate 3 and the word line 5 sequentially arranged on the periphery of the sacrificial dielectric layer 86; Figure 53 is a schematic diagram of the cross-sectional structure along the second direction after patterning the first metal structure 8311 and the first metal structure 8321 to obtain the gate 3 and the word line 5 sequentially arranged on the periphery of the sacrificial dielectric layer 86.

[0116] The sacrificial dielectric layer 86 is removed, and a gate insulating layer 41 is formed between the semiconductor pillar 2 and the gate 3 , so that the dielectric constants of the gate insulating layer 41 are the same.

[0117] In this embodiment, Figure 54 is a schematic diagram of the cross-sectional structure along the first direction after removing the sacrificial dielectric layer 86 and manufacturing a gate insulating layer 41 between the semiconductor pillar 2 and the gate 3 so that the dielectric constants of the gate insulating layer 41 are the same; Figure 55 is a schematic diagram of the cross-sectional structure along the second direction after removing the sacrificial dielectric layer 86 and manufacturing a gate insulating layer 41 between the semiconductor pillar 2 and the gate 3 so that the dielectric constants of the gate insulating layer 41 are the same.

[0118] A second isolation layer 74 is formed on the surface of each of the semiconductor pillars 2 in the same row along the second direction, and a third isolation layer 75 is formed between each of the semiconductor pillars 2 .

[0119] In this embodiment, FIG56 is a schematic diagram of a cross-sectional structure along the first direction after a second isolation layer 74 is formed on the surface of each semiconductor pillar 2 in the same row along the second direction; FIG57 is a schematic diagram of a cross-sectional structure along the second direction after a second isolation layer 74 is formed on the surface of each semiconductor pillar 2 in the same row along the second direction. FIG58 is a schematic diagram of a cross-sectional structure along the first direction after a third isolation layer 75 is formed between each semiconductor pillar 2; FIG59 is a schematic diagram of a cross-sectional structure along the second direction after a third isolation layer 75 is formed between each isolation pillar.

[0120] Optionally, after the above step S103, the memory manufacturing method further includes:

[0121] A first isolation layer 73 is manufactured on a side of the semiconductor pillar 2 away from the substrate 1 , and the first isolation layer 73 located above the semiconductor pillar 2 is patterned to obtain a metal via, and a metal plug 72 is provided in the metal via.

[0122] A capacitor structure 71 is fabricated above the vertical transistor, such that the capacitor structure 71 is electrically connected to the semiconductor pillar 2 through a metal plug 72 .

[0123] In this embodiment, the capacitor structure 71 includes a first electrode 711 , a dielectric layer 713 , and a second electrode 712 , which are sequentially spaced away from the vertical transistor.

[0124] The first electrode 711 and the second electrode 712 may each include at least one of titanium nitride and tantalum nitride; the dielectric layer 713 includes stacked zirconium oxide, aluminum oxide, and zirconium oxide.

[0125] Figure 40 is a schematic cross-sectional view of the structure along a first direction after a first isolation layer 73 is formed on the side of the semiconductor pillar 2 away from the substrate 1; Figure 41 is a schematic cross-sectional view of the structure along a second direction after the first isolation layer 73 is formed on the side of the semiconductor pillar 2 away from the substrate 1. Figure 42 is a schematic cross-sectional view of the structure along a first direction after the first isolation layer 73 above the semiconductor pillar 2 is patterned to form a metal via, and a metal plug 72 is provided in the metal via; Figure 43 is a schematic cross-sectional view of the structure along a second direction after the first isolation layer 73 above the semiconductor pillar 2 is patterned to form a metal via, and a metal plug 72 is provided in the metal via.

[0126] Optionally, before step S101 , the method further includes the following step S100 : manufacturing a plurality of bit lines 6 spaced apart from each other along a first direction and extending along a second direction on one side of the substrate 1 ; the first direction and the second direction have a designed angle and are both parallel to the substrate 1 .

[0127] Optionally, in the above step S100, the following steps S01 to S04 are also included, with reference to the flowchart of FIG13 .

[0128] S01 : performing ion implantation and annealing on the initial substrate 91 to form a second bit line layer 92 .

[0129] In this embodiment, Figure 14 is a schematic diagram of the cross-sectional structure along the first direction after the initial substrate 91 is ion implanted and annealed to form the second bit line layer 92; Figure 15 is a schematic diagram of the cross-sectional structure along the second direction after the initial substrate 91 is ion implanted and annealed to form the second bit line layer 92.

[0130] Specifically, the ion implantation concentration is not less than 1×20 cm -3 and no larger than 1×20cm -3, so as to form an ohmic contact with the drain of the semiconductor column 2 manufactured subsequently, thereby reducing the contact resistance.

[0131] S02: Patterning the entire initial substrate 91 to obtain a substrate 1 and a plurality of conductive structures 93 spaced apart from each other along a first direction and extending along a second direction. The conductive structure 93 includes a second bit line 62 and an initial first bit line 94 located on a side of the second bit line 62 close to the substrate 1.

[0132] In this embodiment, optionally, FIG16 is a schematic diagram of a cross-sectional structure along the first direction obtained after patterning the entire initial substrate 91 and the second bitline layer 92 to obtain a substrate 1 and a plurality of conductive structures 93 spaced apart from each other along the first direction and extending along the second direction. FIG17 is a schematic diagram of a cross-sectional structure along the second direction obtained after patterning the entire initial substrate 9 and the second bitline layer 921 to obtain a substrate 1 and a plurality of conductive structures 93 spaced apart from each other along the first direction and extending along the second direction.

[0133] Specifically, patterning includes coating a photoresist on one side of the initial substrate 91 and performing processes such as exposing, developing, and etching the photoresist using a mask. The resulting conductive structure 93 exposes the second bit line 62 and the initial first bit line 94 .

[0134] S03 : forming a third dielectric layer 95 between one side of the substrate 1 and the conductive structure 93 , and exposing the second bit line 62 ; and forming a protective film 96 around the second bit line 62 .

[0135] In this embodiment, Figure 18 is a schematic cross-sectional view of the structure along the first direction after forming a third dielectric layer 95 between one side of the substrate 1 and the conductive structure 93, exposing the second bit line 62. Figure 19 is a schematic cross-sectional view of the structure along the second direction after forming a third dielectric layer 95 between one side of the substrate 1 and the conductive structure 93, exposing the second bit line 62. Figure 20 is a schematic cross-sectional view of the structure along the first direction after forming a protective film 96 around the periphery of the second bit line 62. Figure 21 is a schematic cross-sectional view of the structure along the second direction after forming a protective film 96 around the periphery of the second bit line 62.

[0136] Alternatively, the material of the protection film 96 may be oxygen-doped silicon nitride. Specifically, silicon nitride is formed by nitrogen doping under thermal oxygen conditions.

[0137] Optionally, the third dielectric layer 95 may be silicon nitride.

[0138] Optionally, the step S03 includes depositing an initial third dielectric layer 95 between one side of the substrate 1 and the conductive structure 93 , and etching back the initial third dielectric layer 95 to expose the second bit line 62 to obtain the third dielectric layer 95 .

[0139] S04 : patterning the third dielectric layer 95 to expose the sidewalls of the initial first bit line 94 ; performing metal deposition and annealing processes on the initial first bit line 94 to obtain the first bit line 61 comprising metal silicide.

[0140] In this embodiment, FIG22 is a schematic diagram of a cross-sectional structure along a first direction after patterning the third dielectric layer 95 to expose the sidewalls of the initial first bit line 94; FIG23 is a schematic diagram of a cross-sectional structure along a second direction after patterning the third dielectric layer 95 to expose the sidewalls of the initial first bit line 94. FIG24 is a schematic diagram of a cross-sectional structure along a first direction after metal deposition and annealing processes are performed on the initial first bit line 94 to obtain the first bit line 61 comprising metal silicide; FIG25 is a schematic diagram of a cross-sectional structure along a second direction after metal deposition and annealing processes are performed on the initial first bit line 94 to obtain the first bit line 61 comprising metal silicide.

[0141] The first bit line 61 includes metal silicide, which can reduce the resistance of the first bit line 61 itself.

[0142] Optionally, after step S04 and before step S11, the method further includes:

[0143] The protection film 96 is removed, and a fourth dielectric layer 98 is formed on the third dielectric layer 95 to expose the upper surface of the second bit line 62 .

[0144] In this embodiment, FIG26 is a schematic diagram of a cross-sectional structure along a first direction after a fourth dielectric layer 98 is manufactured above the third dielectric layer 95 to expose the upper surface of the second bit line 62; FIG27 is a schematic diagram of a cross-sectional structure along a second direction after a fourth dielectric layer 98 is manufactured above the third dielectric layer 95 to expose the upper surface of the second bit line 62.

[0145] The semiconductor pillar 2 can be epitaxially grown on the exposed upper surface of the second bit line 62 .

[0146] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0147] 1. The gate insulating layer provided in the embodiment of the present application has a gradient dielectric constant value, and the gate has different work functions. The gate insulating layer with a gradient dielectric constant value can suppress the turn-on of the parasitic transistor, thereby reducing leakage; the gates with different work functions can make the electric field distribution in the channel region more uniform, thereby increasing the on-state current. At the same time, the lateral band-to-band tunneling width is increased and the off-state leakage current is reduced, thereby improving the switching ratio of the memory.

[0148] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0149] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0150] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0151] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0152] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0153] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time. The execution order of these sub-steps or stages may be flexibly configured as required, and the embodiments of the present application do not limit this.

[0154] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. A storage unit, wherein: A vertical transistor is included; the vertical transistor includes: A semiconductor column extending in a direction perpendicular to the substrate, wherein the semiconductor column comprises a drain region, a channel region and a source region arranged in sequence; A gate insulating layer and a gate, at least a portion of the gate insulating layer and the gate are sequentially arranged at the periphery of the channel region of the semiconductor column; The dielectric constant of the gate insulating layer near the source region is greater than the dielectric constant of the gate insulating layer near the drain region; and / or the work function of the gate near the source region is greater than the work function of the gate near the drain region; the drain region is used to be electrically connected to the bit line, and the source region is used to be electrically connected to the capacitor structure.

2. The storage unit according to claim 1, wherein: The gate insulating layer is disposed at the peripheries of the drain region, the channel region and the source region.

3. The storage unit according to claim 1 or 2, wherein: The gate includes a first gate and a second gate stacked together, and a work function of the second gate close to the source region is greater than a work function of the first gate close to the drain region; a difference between the work function of the second gate and the work function of the first gate is not less than 0.1 electron volts and not greater than 0.5 electron volts.

4. The storage unit according to claim 3, wherein: The material of the first gate includes undoped polysilicon, and the material of the second gate includes polysilicon with a P-type doping element.

5. The storage unit according to any one of claims 1 to 4, wherein: The doping ions in the source region, the doping ions in the drain region and the doping ions in the channel region are of the same polarity.

6. A memory, wherein: A memory cell comprising a plurality of word lines and an array arrangement; the memory cell comprising a vertical transistor; the vertical transistor comprising: A semiconductor column extending in a direction perpendicular to the substrate, wherein the semiconductor column comprises a drain region, a channel region and a source region arranged in sequence; A gate insulating layer and a gate, at least a portion of the gate insulating layer and the gate are sequentially arranged at the periphery of the channel region of the semiconductor column; The dielectric constant of the gate insulating layer near the source region is greater than the dielectric constant of the gate insulating layer near the drain region; and / or the work function of the gate near the source region is greater than the work function of the gate near the drain region; the drain region is used to be electrically connected to the bit line, and the source region is used to be electrically connected to the capacitor structure; The word line is electrically connected to the gates of the memory cells arranged in the same row along a first direction, and the first direction is parallel to the substrate.

7. The memory according to claim 6, wherein: The gate insulating layer is disposed at the peripheries of the drain region, the channel region and the source region.

8. The memory according to claim 6, wherein: The gate includes a first gate and a second gate stacked together, the word line includes a first word line and a second word line stacked together, the first word line is electrically connected to the first gate, the second word line is electrically connected to the second gate, the second word line is arranged close to the source region, and the first word line is arranged close to the drain region; the work function of the second word line is greater than the work function of the first word line.

9. The memory according to claim 8, wherein: The material of the first word line includes undoped polysilicon, and the material of the second word line includes polysilicon with a P-type doping element.

10. The memory according to claim 6, wherein: It also includes a plurality of bit lines extending along a second direction. The bit lines are arranged on a side of each semiconductor column arranged in the same row along the second direction close to the substrate. The second direction is parallel to the substrate and has a designed angle with the first direction.

11. The memory according to claim 10, wherein: The bit line includes a first bit line and a second bit line, wherein the second bit line is located at a side of the first bit line away from the substrate, a material of the first bit line includes a metallized semiconductor, and a material of the second bit line includes a doped semiconductor.

12. The memory according to claim 6, wherein: The doping ions in the source region, the doping ions in the drain region and the doping ions in the channel region are of the same polarity.

13. An electronic device, wherein: A memory comprising any one of claims 6 to 12.

14. A method for manufacturing a memory, wherein: include: Manufacturing semiconductor columns arranged in an array and extending in a direction perpendicular to the substrate on one side of the substrate, wherein the semiconductor columns include a drain region, a channel region and a source region arranged in sequence; Manufacturing a plurality of gates and a plurality of word lines, so that the gates and the word lines are sequentially arranged at the periphery of the channel region of the semiconductor column, and the gates are insulated from the semiconductor column; A plurality of gate insulating layers are manufactured, so that at least a portion of the gate insulating layers are disposed on the periphery of the channel region of the semiconductor column and between the semiconductor column and the gate, wherein the dielectric constant of the gate insulating layer close to the source region is greater than that of the gate insulating layer close to the source region. The dielectric constant of the gate insulating layer near the drain region; and / or the work function of the gate near the source region is greater than the work function of the gate near the drain region; the drain region is used to be electrically connected to the bit line, and the source region is used to be electrically connected to the capacitor structure.

15. The method for manufacturing a memory according to claim 14, wherein: Before manufacturing semiconductor pillars arranged in an array and extending in a direction perpendicular to the substrate on one side of the substrate, the method further includes: A plurality of bit lines are manufactured on one side of a substrate, which are spaced from each other along a first direction and extend along a second direction; the first direction and the second direction have a designed angle and are both parallel to the substrate; And, manufacturing an array of semiconductor columns extending in a direction perpendicular to the substrate on one side of the substrate, comprising: Manufacturing a stacked first dielectric layer, a metal layer, and a second dielectric layer on a side of the bit line away from the substrate, and patterning the second dielectric layer, the metal layer, and the first dielectric layer to obtain a metal structure and a first hole arranged in an array, so that the side surface of the metal structure and the upper surface of the bit line are exposed in the first hole; A sacrificial dielectric layer is manufactured on the sidewall of the first hole, and a semiconductor column is epitaxially grown along the first hole on a side of the bit line away from the substrate.

16. The method for manufacturing a memory according to claim 15, wherein: Manufacturing a plurality of gates and a plurality of word lines so that the gates and the word lines are sequentially arranged at the periphery of the channel region of the semiconductor column, comprising: The metal structure is patterned to obtain a gate and a word line which are sequentially arranged on the periphery of the sacrificial dielectric layer.

17. The method for manufacturing a memory according to claim 16, wherein: The word line is electrically connected to each of the gates arranged in the same row along the first direction.

18. The method for manufacturing a memory according to claim 17, wherein: The gate includes a first gate and a second gate stacked together, and a work function of the second gate close to the source region is greater than a work function of the first gate close to the drain region; a difference between the work function of the second gate and the work function of the first gate is not less than 0.1 electron volts and not greater than 0.5 electron volts.

19. The method for manufacturing a memory according to claim 18, wherein: The material of the first gate includes undoped polysilicon, and the material of the second gate includes polysilicon with a P-type doping element.

20. The method for manufacturing a memory according to claim 18, wherein: The word line includes a stacked first word line and a second word line, the first word line is electrically connected to the first gate, the second word line is electrically connected to the second gate, the second word line is arranged close to the source region, and the first word line is arranged close to the drain region.

21. The method for manufacturing a memory according to claim 15, wherein: Manufacturing a plurality of gate insulating layers so that at least a portion of the gate insulating layers are disposed at the periphery of the channel region of the semiconductor column and between the semiconductor column and the gate, comprising: The sacrificial dielectric layer is removed, and the gate insulating layer is manufactured between the semiconductor column and the gate, so that at least a portion of the gate insulating layer is disposed at the periphery of the channel region of the semiconductor column and between the semiconductor column and the gate.

22. The method for manufacturing a memory according to claim 21, wherein: Removing the sacrificial dielectric layer and manufacturing a gate insulating layer between the semiconductor pillar and the gate comprises: The dielectric constant of the gate insulating layer is controlled based on the ALD doping process, so that the dielectric constant of the gate insulating layer close to the source region of the semiconductor column is greater than the dielectric constant of the gate insulating layer close to the drain region.

23. The method for manufacturing a memory according to claim 22, wherein: The gate insulating layer is disposed at the peripheries of the drain region, the channel region and the source region.

24. The method for manufacturing a memory according to claim 15, wherein: A stacked first dielectric layer, a metal layer, and a second dielectric layer are manufactured on a side of the bit line away from the substrate, comprising: A stacked first dielectric layer, a first metal layer, a second metal layer and a second dielectric layer are manufactured on a side of the bit line away from the substrate so that the work function of the second metal layer is greater than the work function of the first metal layer. The metal layer includes a stacked first metal layer and a second metal layer.

25. The method for manufacturing a memory according to claim 15, wherein: A plurality of bit lines are fabricated on one side of a substrate, the bit lines being spaced from each other along a first direction and extending along a second direction, comprising: Performing ion implantation and annealing on the initial substrate to form a second bit line layer; Patterning the entire initial substrate to obtain a substrate and a plurality of conductive structures spaced apart from each other along a first direction and extending along a second direction, wherein the conductive structures include a second bit line and an initial first bit line located on a side of the second bit line close to the substrate; A third dielectric layer is fabricated between one side of the substrate and the conductive structure, and the second bit line is exposed; a protective film is fabricated around the second bit line; The third dielectric layer is patterned to expose the sidewall of the initial first bit line; and the initial first bit line is subjected to metal deposition and annealing processes to obtain a first bit line containing metal silicide.

26. The method for manufacturing a memory according to claim 25, wherein: The material of the first bit line includes a metallized semiconductor, and the material of the second bit line includes a doped semiconductor.

27. The method for manufacturing a memory according to claim 14, wherein: The doping ions in the source region, the doping ions in the drain region and the doping ions in the channel region are of the same polarity.

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