Light-emission driving circuit, timing control method, and display panel

Abstract

A light-emission driving circuit, a timing control method, and a display panel. In the light-emission driving circuit, a first pull-up control module (10) is used for pulling up the potential of a first node (EPU) to a first potential in preparation and reset stages, a pull-up module (30) is used for pulling up a light-emission driving signal (En), which is output from an output end of the light-emission driving signal, to a high potential when the first node (EPU) is at the first potential, a first pull-down control module (40) is used for pulling down the potential of a second node (EPD) to a second potential in the preparation and reset stages, a second pull-up control module (20) is used for pulling up the potential of the second node (EPD) to a third potential in an output stage, a pull-down module (60) is used for pulling down the light-emission driving signal (En) to a low potential when the second node (EPD) is at the third potential, a second pull-down control module (50) is used for pulling down the potential of the first node (EPU) to a fourth potential in the output stage, and a first maintaining module (70) is used for maintaining the potential of the first node (EPU) in a maintaining stage.

Description

Light-emitting driving circuit, timing control method and display panel

[0001] This application claims priority to the Chinese patent application number 202310789277.6 filed with the Patent Office of the State Intellectual Property Office of China on June 30, 2023, and entitled “Light-emitting driving circuit, timing control method and display panel”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a light-emitting driving circuit, a timing control method, and a display panel. Background Art

[0003] Light-emitting devices such as organic light emitting diodes (OLEDs) are increasingly being used in products such as televisions and mobile phones due to their characteristics of being light, energy-efficient, having a wide color gamut, and high contrast.

[0004] OLED is an active light-emitting device. In addition to requiring a row scanning drive circuit to provide a corresponding scanning signal, it also generally requires a light-emitting drive circuit to provide a corresponding light-emitting control signal.

[0005] However, the current light-emitting drive circuit architecture is complex and requires a large number of modules or components to achieve control of the light-emitting control signal. Summary of the Invention

[0006] In view of this, embodiments of the present application provide a light-emitting driving circuit, a timing control method, and a display panel to reduce the complexity of the light-emitting driving circuit architecture.

[0007] To achieve the above objectives, in a first aspect, an embodiment of the present application provides a light-emitting driving circuit, comprising: a first pull-up control module, a second pull-up control module, a pull-up module, a first pull-down control module, a second pull-down control module, a pull-down module, and a first maintaining module;

[0008] The first pull-up control module has an input terminal connected to a first power supply or a clock signal, a control terminal connected to a clock signal, and an output terminal electrically connected to the first node. The first pull-up control module is configured to pull up the potential of the first node to a first potential during a preparation phase and a reset phase.

[0009] The pull-up module has an input terminal connected to a first power supply, a control terminal electrically connected to a first node, and an output terminal electrically connected to a light-emitting drive signal output terminal. The pull-up module is configured to pull up the light-emitting drive signal outputted from the light-emitting drive signal output terminal to a high potential when the potential of the first node is a first potential.

[0010] The input end of the first pull-down control module is connected to the second power supply, the control end is connected to the clock signal, and the output end is electrically connected to the second node. The first pull-down control module is used to pull down the potential of the second node to the second potential in the preparation stage and the reset stage;

[0011] The input end of the second pull-up control module is connected to the scan signal or the first power supply, the control end is connected to the scan signal, and the output end is electrically connected to the second node. The second pull-up control module is used to pull up the potential of the second node to a third potential in the output stage;

[0012] The pull-down module has an input terminal connected to the clock signal, a control terminal electrically connected to the second node, and an output terminal electrically connected to the light-emitting drive signal output terminal. The pull-down module is configured to pull down the light-emitting drive signal output from the light-emitting drive signal output terminal to a low potential when the potential of the second node is a third potential.

[0013] The second pull-down control module has an input terminal connected to the second power supply, a control terminal electrically connected to the second node, and an output terminal electrically connected to the first node. The second pull-down control module is configured to pull down the potential of the first node to a fourth potential during the output phase.

[0014] One end of the first maintaining module is electrically connected to the control end of the pull-up module, and the other end is electrically connected to the light-emitting driving signal output end. The first maintaining module is used to maintain a high potential of the first node in the maintaining phase.

[0015] As an optional implementation of the embodiment of the present application, the light-emitting driving circuit also includes: a potential stabilization module, wherein the first input end of the potential stabilization module is electrically connected to the first power supply, the second input end is electrically connected to the output end of the second pull-down control module, the first control end is electrically connected to the first node, the second control end is electrically connected to the second node, and the output end is electrically connected to the first node, and the potential stabilization module is used to stabilize the potential of the first node in the preparation stage, the reset stage and the maintenance stage.

[0016] As an optional implementation of the embodiment of the present application, the potential stabilization module includes: a first transistor and a second transistor;

[0017] A first electrode of the first transistor is connected to the first power supply, a control electrode is electrically connected to the first node, and a second electrode is electrically connected to the output end of the second pull-down control module;

[0018] The first electrode of the second transistor is electrically connected to the output end of the second pull-down control module, the control electrode is electrically connected to the second node, and the second electrode is electrically connected to the first node.

[0019] As an optional implementation of the embodiment of the present application, the light-emitting driving circuit also includes: a second maintaining module, the input end of the second maintaining module is connected to the second power supply, the control end is electrically connected to the first node, and the output end is electrically connected to the second node, and the second maintaining module is used to maintain the low potential of the second node in the preparation stage, reset stage and maintenance stage.

[0020] As an optional implementation of the embodiment of the present application, the second maintenance module includes a third transistor, a first electrode of the third transistor is electrically connected to the second node, a control electrode is electrically connected to the first node, and a second electrode is connected to the second power supply.

[0021] As an optional implementation of the embodiment of the present application, the first maintaining module includes a capacitor, one end of the capacitor is electrically connected to the control end of the pull-up module, and the other end is electrically connected to the light-emitting drive signal output end.

[0022] As an optional implementation of the embodiment of the present application, the pull-down module includes a fourth transistor, a first electrode of the fourth transistor is connected to the clock signal, a control electrode is electrically connected to the second node, and a second electrode is electrically connected to the light-emitting drive signal output end.

[0023] As an optional implementation of an embodiment of the present application, the second pull-up control module includes a fifth transistor, the first electrode of the fifth transistor is connected to the scan signal or the first power supply, the control electrode is connected to the scan signal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0024] As an optional implementation of the embodiment of the present application, the first pull-up control module includes a sixth transistor, the first electrode of the sixth transistor is connected to the first power supply, the second electrode of the sixth transistor is electrically connected to the first node, and the control electrode of the sixth transistor is connected to the clock signal.

[0025] As an optional implementation of the embodiment of the present application, the first pull-up control module includes a tenth transistor, the first electrode and the control electrode of the tenth transistor are both connected to the clock signal, and the second electrode of the tenth transistor is electrically connected to the first node.

[0026] As an optional implementation of an embodiment of the present application, the pull-up module includes a seventh transistor, the first electrode of the seventh transistor is connected to the first power supply, the control electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the light-emitting drive signal output end.

[0027] As an optional implementation of an embodiment of the present application, the first pull-down control mode includes an eighth transistor, the second electrode of the eighth transistor is connected to the second power supply, the control electrode of the eighth transistor is connected to the clock signal, and the first electrode of the eighth transistor is electrically connected to the second node.

[0028] As an optional implementation of an embodiment of the present application, the second pull-down control module includes a ninth transistor, the second electrode of the ninth transistor is connected to the second power supply, the control electrode of the ninth transistor is electrically connected to the second node, and the first electrode of the ninth transistor is electrically connected to the first node and the second node.

[0029] In a second aspect, an embodiment of the present application provides a timing control method, which is applied to the light-emitting driving circuit according to the first aspect or any one of the first aspects, the method comprising:

[0030] In the preparation stage, the clock signal line is controlled to output a high-potential clock signal, so that the first pull-up control module and the first pull-down control module are turned on, the potential of the first node is pulled up to the first potential, the first maintaining module is charged, and the potential of the second node is pulled down to the second potential; the scan signal line is controlled to output a low-potential scan signal, so that the second pull-up control module is turned off;

[0031] In the output phase, the clock signal line is controlled to output a low-potential clock signal, so that the first pull-up control module and the first pull-down control module are turned off; the scan signal line is controlled to output a high-potential scan signal, so that the second pull-up control module is turned on, and the potential of the second node is pulled up to a third potential, and the second pull-down control module is turned on, and the potential of the first node is pulled down to a fourth potential;

[0032] In a reset phase, the clock signal line is controlled to output a high-potential clock signal, so that the first pull-up control module and the first pull-down control module are turned on, the potential of the first node is pulled up to a first potential, and the potential of the second node is pulled down to a second potential; the scan signal line is controlled to output a low-potential scan signal, so that the second pull-up control module is turned off;

[0033] In the sustaining stage, the clock signal line is controlled to output a clock signal that continuously switches between high and low potentials, and the first sustaining module is discharged to maintain the high potential of the first node.

[0034] In a third aspect, an embodiment of the present application provides a display panel, comprising a light-emitting driving circuit as described in the first aspect or any one of the first aspects above and a pixel driving circuit connected to the light-emitting driving circuit, wherein the light-emitting driving circuit is used to output a corresponding light-emitting driving signal to the pixel driving circuit.

[0035] The technical solution provided by the embodiment of the present application includes a first pull-up control module, a second pull-up control module, a pull-up module, a first pull-down control module, a second pull-down control module, a pull-down module and a first maintaining module; the input end of the first pull-up control module is connected to the first power supply, the control end is connected to the clock signal, and the output end is electrically connected to the first node. The first pull-up control module is used to pull up the potential of the first node to the first potential in the preparation stage and the reset stage; the input end of the pull-up module is connected to the first power supply or the clock signal, the control end is electrically connected to the first node, and the output end is electrically connected to the light-emitting drive signal output end. The pull-up module is used to pull up the light-emitting drive signal output from the light-emitting drive signal output end to a high potential when the potential of the first node is the first potential; the input end of the first pull-down control module is connected to the second power supply, the control end is connected to the clock signal, and the output end is electrically connected to the second node. The first pull-down control module is used to pull down the potential of the second node in the preparation stage and the reset stage. to the second potential; the input end of the second pull-up control module is connected to the scan signal or the first power supply, the control end is connected to the scan signal, and the output end is electrically connected to the second node. The second pull-up control module is used to pull up the potential of the second node to a third potential in the output stage; the input end of the pull-down module is connected to the clock signal, the control end is electrically connected to the second node, and the output end is electrically connected to the light-emitting drive signal output end. The pull-down module is used to pull down the light-emitting drive signal output from the light-emitting drive signal output end to a low potential when the potential of the second node is the third potential; the input end of the second pull-down control module is connected to the second power supply, the control end is electrically connected to the second node, and the output end is electrically connected to the first node. The second pull-down control module is used to pull down the potential of the first node to a fourth potential in the output stage; one end of the first maintaining module is electrically connected to the control end of the pull-up module, and the other end is electrically connected to the light-emitting drive signal output end. The first maintaining module is used to maintain the high potential of the first node in the maintaining stage. In the above scheme, the light-emitting driving circuit can modulate the required light-emitting control signal through the first pull-up control module, the second pull-up control module, the pull-up module, the first pull-down control module, the second pull-down control module, the pull-down module and the first maintaining module and their corresponding connection relationships. The number of modules used is small, thereby simplifying the architecture of the light-emitting driving circuit and reducing the complexity of the light-emitting driving circuit architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] FIG1 is a schematic diagram of a circuit structure of a light-emitting driving circuit provided in an embodiment of the present application;

[0038] FIG2 is a schematic diagram of the circuit structure of another light-emitting driving circuit provided in an embodiment of the present application;

[0039] FIG3 is a schematic diagram of the circuit structure of another light-emitting driving circuit provided in an embodiment of the present application;

[0040] FIG4 is a schematic diagram of the circuit structure of another light-emitting driving circuit provided in an embodiment of the present application;

[0041] FIG5 is a timing diagram of the operation of the light-emitting driving circuit controlled by the timing control method provided in an embodiment of the present application;

[0042] FIG6 is a schematic diagram showing a connection relationship of light-emitting driving circuits of various levels in a display panel provided by an embodiment of the present application. Modes for Carrying Out the Invention

[0043] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0044] The terms used in the implementation methods of the embodiments of this application are only used to explain the specific embodiments of this application and are not intended to limit this application. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0045] The light-emitting device in the embodiment of the present application can be any one of OLED, quantum dot light-emitting diodes (QLED) and sub-millimeter light-emitting diodes (Mini LED); this embodiment will be described illustratively using OLED as the light-emitting device.

[0046] Figure 1 is a schematic diagram of the circuit structure of a light-emitting driving circuit provided in an embodiment of the present application. As shown in Figure 1, the light-emitting driving circuit provided in an embodiment of the present application may include: a first pull-up control module 10, a second pull-up control module 20, a pull-up module 30, a first pull-down control module 40, a second pull-down control module 50, a pull-down module 60 and a first maintaining module 70.

[0047] The first pull-up control module 10 has an input connected to a first power source EVGH, a control terminal connected to a clock signal ECK, and an output electrically connected to a first node EPU. The first pull-up control module 10 is configured to pull up the potential of the first node EPU to a first potential during a preparation phase and a reset phase. The first power source EVGH may be a DC power source that outputs a high-potential voltage, and the first potential may be a high potential.

[0048] The input end of the pull-up module 30 is connected to the first power supply EVGH, the control end of the pull-up module 30 is electrically connected to the first node EPU, and the output end of the pull-up module 30 is electrically connected to the output end of the light-emitting drive signal En. The pull-up module 30 is used to pull up the light-emitting drive signal En output from the light-emitting drive signal En output end to a high potential when the potential of the first node EPU is the first potential.

[0049] The input terminal of the first pull-down control module 40 is connected to the second power supply EVGL, the control terminal of the first pull-down control module 40 is connected to the clock signal ECK, and the output terminal of the first pull-down control module 40 is electrically connected to the second node EPD. The first pull-down control module 40 is configured to pull down the potential of the second node EPD to a second potential during the preparation and reset phases. The second power supply EVGL can be a DC power supply and output a low-voltage voltage, and the second potential can be a low potential. In addition, during the hold phase, when the clock signal ECK is high, the eighth transistor M8 is turned on, the potential of the second node EPD is pulled down to a low potential by the second power supply EVGL, and the fourth transistor M4 is turned off. When the clock signal ECK is low, the parasitic capacitance between the gate and channel of the fourth transistor M4 can maintain the off state of the fourth transistor M4.

[0050] The input terminal and control terminal of the second pull-up control module 20 are both connected to the scan signal Gn. The output terminal of the second pull-up control module 20 is electrically connected to the second node EPD. The second pull-up control module 20 is configured to pull up the potential of the second node EPD to a third potential during the output phase. The second potential can be a high potential.

[0051] The input end of the pull-down module 60 is connected to the clock signal ECK, the control end of the pull-down module 60 is electrically connected to the second node EPD, and the output end of the pull-down module 60 is electrically connected to the output end of the light-emitting drive signal En. The pull-down module 60 is used to pull down the light-emitting drive signal En output from the output end of the light-emitting drive signal En to a low potential when the potential of the second node EPD is the third potential.

[0052] The input terminal of the second pull-down control module 50 is connected to the second power supply EVGL, the control terminal of the second pull-down control module 50 is electrically connected to the second node EPD, and the output terminal of the second pull-down control module 50 is electrically connected to the first node EPU. The second pull-down control module 50 is configured to pull down the potential of the first node EPU to a fourth potential during the output phase. The fourth potential can be a low potential.

[0053] One end of the first maintaining module 70 is electrically connected to the control end of the pull-up module 30, and the other end of the first maintaining module 70 is electrically connected to the output end of the light-emitting driving signal En. The first maintaining module 70 is used to maintain the high potential of the first node EPU during the maintaining stage. In this way, during the maintaining stage, the pull-up module 30 can also pull up the light-emitting driving signal En outputted from the output end of the light-emitting driving signal En to a high potential.

[0054] The light-emitting drive signal En output terminal of the light-emitting drive circuit outputs a high-potential light-emitting drive signal En in the preparation stage, the reset stage, and the maintenance stage, and outputs a low-potential light-emitting drive signal En in the output stage. In this way, the required light-emitting control signal can be modulated through the first pull-up control module 10, the second pull-up control module 20, the pull-up module 30, the first pull-down control module 40, the second pull-down control module 50, the pull-down module 60, and the first maintenance module 70 and their corresponding connection relationships. Only seven modules are used, thereby simplifying the architecture of the light-emitting drive circuit and reducing the complexity of the light-emitting drive circuit architecture.

[0055] The light-emitting drive circuit may further include a potential stabilization module 80, wherein a first input terminal of the potential stabilization module 80 is electrically connected to the first power supply EVGH, a second input terminal is electrically connected to the output terminal of the second pull-down control module 50, a first control terminal is electrically connected to the first node EPU, a second control terminal is electrically connected to the second node EPD, and an output terminal is electrically connected to the first node EPU. The potential stabilization module 80 is used to reduce the leakage current of the second pull-down control module 50 in the preparation stage, the reset stage, and the maintenance stage, and to weaken the influence of the leakage current of the second pull-down control module 50 on the potential of the first node EPU, so that the potential of the first node EPU is more stable, thereby making the high-potential light-emitting drive signal En output by the pull-up module 30 more stable.

[0056] The light-emitting drive circuit may further include a second maintaining module 90, the input end of the second maintaining module 90 being connected to the second power supply EVGL, the control end of the second maintaining module 90 being electrically connected to the first node EPU, and the output end of the second maintaining module 90 being electrically connected to the second node EPD. The second maintaining module 90 is used to maintain the low potential of the second node EPD in the preparation stage, the reset stage and the maintenance stage, so that the pull-down module 60 is continuously turned off, so that the output end of the light-emitting drive signal En only outputs the high-potential light-emitting drive signal En.

[0057] It is understood that in another embodiment of the present application, the light-emitting driver circuit may further include a second maintaining module 90 instead of the first pull-down control module 40. In this manner, the second maintaining module 90 maintains the low potential of the second node EPD during the preparation phase, the reset phase, and the maintaining phase, thereby continuously turning off the pull-down module 60 and allowing the output terminal of the light-emitting driver signal En to output only the high-potential light-emitting driver signal En. The embodiments of the present application will be described hereinafter using an example in which the light-emitting driver circuit includes both the second maintaining module 90 and the first pull-down control module 40.

[0058] Specifically, the potential stabilization module 80 may include a first transistor M1 and a second transistor M2. A first electrode of the first transistor M1 is connected to the first power supply EVGH, a control electrode of the first transistor M1 is electrically connected to the first node EPU, and a second electrode of the first transistor M1 is electrically connected to the output terminal of the second pull-down control module 50.

[0059] A first electrode of the second transistor M2 is electrically connected to the output end of the second pull-down control module 50 , a control electrode of the second transistor M2 is electrically connected to the second node EPD, and a second electrode of the second transistor M2 is electrically connected to the first node EPU.

[0060] The second maintaining module 90 may include a third transistor M3 , a first electrode of the third transistor M3 is electrically connected to the second node EPD, a control electrode of the third transistor M3 is electrically connected to the first node EPU, and a second electrode of the third transistor M3 is connected to the second power supply EVGL.

[0061] The pull-down module 60 may include a fourth transistor M4 , a first electrode of which is connected to the clock signal ECK, a control electrode of which is electrically connected to the second node EPD, and a second electrode of which is electrically connected to the output terminal of the light-emitting driving signal En.

[0062] The second pull-up control module 20 may include a fifth transistor M5 , a first electrode and a control electrode of the fifth transistor M5 are both connected to the scan signal Gn, and a second electrode of the fifth transistor M5 is electrically connected to the second node EPD.

[0063] The first pull-up control module 10 may include a sixth transistor M6 , a first electrode of the sixth transistor M6 is connected to the first power supply EVGH, a second electrode of the sixth transistor M6 is electrically connected to the first node EPU, and a control electrode of the sixth transistor M6 is connected to the clock signal ECK.

[0064] The pull-up module 30 may include a seventh transistor M7 , a first electrode of the seventh transistor M7 is connected to the first power supply EVGH, a control electrode of the seventh transistor M7 is electrically connected to the first node EPU, and a second electrode of the seventh transistor M7 is electrically connected to the output end of the light-emitting driving signal En.

[0065] The first pull-down control module 40 may include an eighth transistor M8 , a second electrode of the eighth transistor M8 is connected to the second power supply EVGL, a control electrode of the eighth transistor M8 is connected to the clock signal ECK, and a first electrode of the eighth transistor M8 is electrically connected to the second node EPD.

[0066] The second pull-down control module 50 may include a ninth transistor M9, a second electrode of the ninth transistor M9 being connected to the second power supply EVGL, a control electrode of the ninth transistor M9 being electrically connected to the second node EPD, and a first electrode of the ninth transistor M9 being electrically connected to the second electrode of the first transistor M1 and the first electrode of the second transistor M2.

[0067] The first maintaining module 70 may include a capacitor C1 , one end of the capacitor C1 is electrically connected to the control electrode of the seventh transistor M7 , and the other end of the capacitor C1 is electrically connected to the output end of the light-emitting driving signal En.

[0068] In some embodiments of the present application, the input end and the control end of the first pull-up control module 10 can also be connected to the clock signal ECK. As shown in Figure 2, the first pull-up control module 10 may include a tenth transistor M10, and the first electrode and the control electrode of the tenth transistor M10 are both connected to the clock signal ECK, and the second electrode of the tenth transistor M10 is electrically connected to the first node EPU.

[0069] In other embodiments of the present application, the input end of the second pull-up control module 20 can also be connected to the first power supply EVGH. As shown in Figure 3, the second pull-up control module 20 may include an eleventh transistor M11, the first electrode of the eleventh transistor M11 is connected to the first power supply EVGH, the control electrode of the eleventh transistor M11 is connected to the scan signal Gn, and the second electrode of the eleventh transistor M11 is electrically connected to the second node EPD.

[0070] The driving control circuit of the present application may also include both the tenth transistor M10 and the eleventh transistor M11 as shown in FIG4 .

[0071] The transistor in the embodiment of the present application can be an NMOS transistor or other types of transistors, which is not specifically limited in the present application. When the transistor in the embodiment of the present application is an NMOS transistor, the first electrode is the drain, the second electrode is the source, and the control electrode is the gate.

[0072] An embodiment of the present application also provides a timing control method, which is applied to the above-mentioned light-emitting drive circuit. In the preparation stage, the method controls the clock signal ECK line to output a high-potential clock signal ECK, so that the first pull-up control module 10 and the first pull-down control module 40 are turned on, the potential of the first node EPU is pulled up to the first potential, the first maintenance module 70 is charged, and the potential of the second node EPD is pulled down to the second potential; and controls the scan signal Gn line to output a low-potential scan signal Gn, so that the second pull-up control module 20 is turned off.

[0073] In the output stage, the clock signal ECK line is controlled to output a low-potential clock signal ECK to turn off the first pull-up control module 10 and the first pull-down control module 40; the scan signal Gn line is controlled to output a high-potential scan signal Gn to turn on the second pull-up control module 20, pull up the potential of the second node EPD to the third potential, turn on the second pull-down control module 50, and pull down the potential of the first node EPU to the fourth potential.

[0074] In the reset stage, the clock signal ECK line is controlled to output a high-potential clock signal ECK, so that the first pull-up control module 10 and the first pull-down control module 40 are turned on, the potential of the first node EPU is pulled up to the first potential, and the potential of the second node EPD is pulled down to the second potential; the scan signal Gn line is controlled to output a low-potential scan signal Gn, so that the second pull-up control module 20 is turned off.

[0075] In the sustaining stage, the clock signal ECK line is controlled to output the clock signal ECK with a continuously switching high and low potentials, and the first sustaining module 70 is discharged to maintain the high potential of the first node EPU.

[0076] FIG5 is a timing diagram of the operation of the light-emitting drive circuit according to the timing control method provided by an embodiment of the present application. As shown in FIG5 , in the preparation phase T1, the scanning signal Gn is at a low level, the fifth transistor M5 is turned off, the clock signal ECK is at a high level, the sixth transistor M6 is turned on, and the high level of the first power supply EVGH is written to the first node EPU through the sixth transistor M6 and charges the capacitor C1, pulling the potential of the first node EPU up to the first potential, turning on the seventh transistor M7, and writing the high level of the first power supply EVGH to the output terminal of the light-emitting drive signal En through the seventh transistor M7. The light-emitting drive signal En output terminal outputs a high-level light-emitting drive signal En. Simultaneously, due to the high level of the first node EPU, the third transistor M3 is turned on, and the high level of the clock signal ECK also turns on the eighth transistor M8. The low level of the second power supply EVGL is written to the second node EPD through the third transistor M3 and the eighth transistor M8, turning off the fourth transistor M4. In addition, the low potential of the second node EPD causes the second transistor M2 and the ninth transistor M9 to be in the off state. At this time, the source potential of the ninth transistor M9 is VGL and the drain potential is VGH, which will generate leakage current. The high potential of the first node EPU turns on the first transistor M1, so that the drain and source potentials of the second transistor M2 are both VGH, and no current passes through the second transistor M2. In this way, the leakage current of the ninth transistor M9 can be blocked from flowing to the first node EPU, so that the leakage current of the ninth transistor M9 will not affect the potential of the first node EPU.

[0077] During output phase T2, the clock signal ECK switches from a high potential to a low potential, turning off the sixth transistor M6 and the eighth transistor M8. The scan signal Gn switches to a high potential, turning on the fifth transistor M5, and pulling up the potential of the second node EPD to the third potential, turning on the fourth transistor M4. The low potential of the clock signal ECK is written to the output terminal of the light-emitting drive signal En via the fourth transistor M4, and the output terminal of the light-emitting drive signal En outputs the low potential light-emitting drive signal En. Simultaneously, the high potential of the second node EPD turns on the second transistor M2 and the ninth transistor M9. The second power supply EVGL is written to the first node EPU via the second transistor M2 and the ninth transistor M9, pulling down the potential of the first node EPU to the fourth potential, turning off the first transistor M1, the third transistor M3, and the seventh transistor M7.

[0078] During the reset phase T3, the scan signal Gn switches to a low potential, turning off the fifth transistor M5. The clock signal ECK switches to a high potential, turning on the sixth transistor M6. The high potential of the first power supply EVGH is written to the first node EPU via the sixth transistor M6 and charges the capacitor C1, pulling the potential of the first node EPU up to the first potential, turning on the seventh transistor M7. The high potential of the first power supply EVGH is written to the output terminal of the light-emitting drive signal En via the seventh transistor M7, and the output terminal of the light-emitting drive signal En outputs a high-potential light-emitting drive signal En. Simultaneously, the high potential of the first node EPU turns on the third transistor M3, and the high potential of the clock signal ECK also turns on the eighth transistor M8. The low potential of the second power supply EVGL is written to the second node EPD via the third and eighth transistors M3 and M8, turning off the fourth transistor M4. In addition, the low potential of the second node EPD causes the second transistor M2 and the ninth transistor M9 to be in the off state. At this time, the source potential of the ninth transistor M9 is VGL and the drain potential is VGH, which will generate leakage current. The high potential of the first node EPU turns on the first transistor M1, so that the drain and source potentials of the second transistor M2 are both VGH, and no current passes through the second transistor M2. In this way, the leakage current of the ninth transistor M9 can be blocked from flowing to the first node EPU, so that the leakage current of the ninth transistor M9 will not affect the potential of the first node EPU.

[0079] During the sustaining phase T4, the scan signal Gn maintains a low potential, the ninth transistor M9 maintains an off state, the second node EPD maintains a low potential, and the fourth transistor M4 maintains an off state. The clock signal ECK continuously switches between high and low potentials. When the clock signal ECK is high, the sixth transistor M6 is turned on, the first node EPU is written to a high potential, the seventh transistor M7 is turned on, and the light-emitting drive signal En output terminal outputs a high-potential light-emitting drive signal En. When the clock signal ECK is low, the capacitor C1 discharges to maintain the high potential of the first node EPU, the seventh transistor M7 remains turned on, and the light-emitting drive signal En output terminal continues to output a high-potential light-emitting drive signal En.

[0080] An embodiment of the present application further provides a display panel, comprising the above-mentioned light-emitting driving circuit and a pixel driving circuit connected to the light-emitting driving circuit, wherein the light-emitting driving circuit is configured to output a corresponding light-emitting driving signal to the pixel driving circuit.

[0081] The display panel provided in the embodiment of the present application may include multiple light-emitting driving circuits. Figure 6 is a schematic diagram of the connection relationship of the light-emitting driving circuits of each level in the display panel provided in the embodiment of the present application. As shown in Figure 6, each level of the light-emitting driving circuit is connected to a clock signal, and each level of the light-emitting driving circuit can provide the same light-emitting driving signal to two adjacent pixels. Each pixel is connected to the light-emitting driving signal output by the light-emitting driving circuit of the corresponding row, and reuses the light-emitting driving signal output by the light-emitting driving circuit of the next row. This can reduce the number of light-emitting driving circuits and the number of clock signal lines, thereby reducing the horizontal layout size of the display panel and realizing a narrow frame of the display panel.

[0082] In addition, each pixel in the display panel can also only receive the light-emitting driving signal output by the light-emitting driving circuit of the corresponding row, or multiplex the light-emitting driving signals output by the light-emitting driving circuits of more other rows. This application does not impose specific restrictions on this.

[0083] It should be understood that the circuit modules illustrated in the embodiments of this application do not constitute a specific limitation on the light-emitting driver circuit. In other embodiments of this application, the light-emitting driver circuit may include more or fewer circuit modules than shown, or combine or separate certain circuit modules; each circuit module may include more or fewer components than shown. The illustrated circuit modules may be implemented in hardware, software, or a combination of software and hardware.

[0084] The technical solution provided by the embodiment of the present application includes a first pull-up control module, a second pull-up control module, a pull-up module, a first pull-down control module, a second pull-down control module, a pull-down module and a first maintaining module; the input end of the first pull-up control module is connected to the first power supply, the control end is connected to the clock signal, and the output end is electrically connected to the first node. The first pull-up control module is used to pull up the potential of the first node to the first potential in the preparation stage and the reset stage; the input end of the pull-up module is connected to the first power supply or the clock signal, the control end is electrically connected to the first node, and the output end is electrically connected to the light-emitting drive signal output end. The pull-up module is used to pull up the light-emitting drive signal output from the light-emitting drive signal output end to a high potential when the potential of the first node is the first potential; the input end of the first pull-down control module is connected to the second power supply, the control end is connected to the clock signal, and the output end is electrically connected to the second node. The first pull-down control module is used to pull down the potential of the second node in the preparation stage and the reset stage. to the second potential; the input end of the second pull-up control module is connected to the scan signal or the first power supply, the control end is connected to the scan signal, and the output end is electrically connected to the second node. The second pull-up control module is used to pull up the potential of the second node to a third potential in the output stage; the input end of the pull-down module is connected to the clock signal, the control end is electrically connected to the second node, and the output end is electrically connected to the light-emitting drive signal output end. The pull-down module is used to pull down the light-emitting drive signal output from the light-emitting drive signal output end to a low potential when the potential of the second node is the third potential; the input end of the second pull-down control module is connected to the second power supply, the control end is electrically connected to the second node, and the output end is electrically connected to the first node. The second pull-down control module is used to pull down the potential of the first node to a fourth potential in the output stage; one end of the first maintaining module is electrically connected to the control end of the pull-up module, and the other end is electrically connected to the light-emitting drive signal output end. The first maintaining module is used to maintain the high potential of the first node in the maintaining stage. In the above scheme, the light-emitting driving circuit can modulate the required light-emitting control signal through the first pull-up control module, the second pull-up control module, the pull-up module, the first pull-down control module, the second pull-down control module, the pull-down module and the first maintaining module and their corresponding connection relationships. The number of modules used is small, thereby simplifying the architecture of the light-emitting driving circuit and reducing the complexity of the light-emitting driving circuit architecture.

[0085] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0086] In addition, the size ratio relationship between the components in the drawings is only schematic and does not reflect the actual size ratio relationship between the components.

[0087] In the description of this application, the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, they should not be understood as limiting the present invention.

[0088] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this invention based on specific circumstances.

[0089] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0090] In the description of this application, unless otherwise specified, " / " indicates that the objects associated before and after are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0091] Furthermore, in the description of this application, unless otherwise specified, "plurality" refers to two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, "at least one of a, b, or c" can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0092] In addition, in the description of this application specification and the appended claims, the terms "first," "second," "third," etc. are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that shown or described herein.

[0093] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A light-emitting driving circuit, wherein: include: A first pull-up control module, a second pull-up control module, a pull-up module, a first pull-down control module, a second pull-down control module, a pull-down module, and a first maintaining module; The input end of the first pull-up control module is connected to the first power supply or clock signal, the control end is connected to the clock signal, and the output end is electrically connected to the first node. The first pull-up control module is used to pull up the potential of the first node to the first potential in the preparation stage and the reset stage; The input end of the pull-up module is connected to the first power supply, the control end is electrically connected to the first node, and the output end is electrically connected to the light-emitting drive signal output end. The pull-up module is used to pull up the light-emitting drive signal output from the light-emitting drive signal output end to a high potential when the potential of the first node is the first potential; The input end of the first pull-down control module is connected to the second power supply, the control end is connected to the clock signal, and the output end is electrically connected to the second node. The first pull-down control module is used to pull down the potential of the second node to the second potential in the preparation stage and the reset stage; The input end of the second pull-up control module is connected to the scan signal or the first power supply, the control end is connected to the scan signal, the output end is electrically connected to the second node, and the second pull-up control module is used to pull up the potential of the second node to a third potential in the output stage; The input end of the pull-down module is connected to the clock signal, the control end is electrically connected to the second node, and the output end is electrically connected to the light-emitting drive signal output end. The pull-down module is used to pull down the light-emitting drive signal output from the light-emitting drive signal output end to a low potential when the potential of the second node is the third potential; The input end of the second pull-down control module is connected to the second power supply, the control end is electrically connected to the second node, and the output end is electrically connected to the first node. The second pull-down control module is used to pull down the potential of the first node to a fourth potential in the output stage; One end of the first maintaining module is electrically connected to the control end of the pull-up module, and the other end is electrically connected to the light-emitting driving signal output end. The first maintaining module is used to maintain a high potential of the first node in the maintaining stage.

2. The light-emitting driving circuit according to claim 1, wherein: The light-emitting driving circuit also includes: a potential stabilization module, a first input end of the potential stabilization module is electrically connected to the first power supply, a second input end is electrically connected to the output end of the second pull-down control module, a first control end is connected to the first node, a second control end is electrically connected to the second node, and an output end is electrically connected to the first node. The potential stabilization module is used to stabilize the potential of the first node in the preparation stage, the reset stage and the maintenance stage.

3. The light-emitting driving circuit according to claim 2, wherein: The potential stabilization module comprises: a first transistor and a second transistor; A first electrode of the first transistor is connected to the first power supply, a control electrode is electrically connected to the first node, and a second electrode is electrically connected to the output end of the second pull-down control module; The first electrode of the second transistor is electrically connected to the output end of the second pull-down control module, the control electrode is electrically connected to the second node, and the second electrode is electrically connected to the first node.

4. The light-emitting driving circuit according to claim 1, wherein: The light-emitting driving circuit also includes: a second maintaining module, the input end of the second maintaining module is connected to the second power supply, the control end is electrically connected to the first node, and the output end is electrically connected to the second node, and the second maintaining module is used to maintain the low potential of the second node in the preparation stage, the reset stage and the maintenance stage.

5. The light-emitting driving circuit according to claim 4, wherein: The second maintaining module includes a third transistor, a first electrode of the third transistor is electrically connected to the second node, a control electrode is electrically connected to the first node, and a second electrode is connected to the second power supply.

6. The light-emitting driving circuit according to claim 1, wherein: The first maintaining module includes a capacitor, one end of which is electrically connected to the control end of the pull-up module, and the other end of which is electrically connected to the light-emitting driving signal output end.

7. The light-emitting driving circuit according to claim 1, wherein: The pull-down module includes a fourth transistor, a first electrode of the fourth transistor is connected to the clock signal, a control electrode is electrically connected to the second node, and a second electrode is electrically connected to the light-emitting drive signal output terminal.

8. The light-emitting driving circuit according to claim 1, wherein: The second pull-up control module includes a fifth transistor, a first electrode of the fifth transistor is connected to the scan signal or the first power supply, a control electrode is connected to the scan signal, and a second electrode of the fifth transistor is electrically connected to the second node.

9. The light-emitting driving circuit according to claim 1, wherein: The first pull-up control module includes a sixth transistor, a first electrode of the sixth transistor is connected to the first power supply, a second electrode of the sixth transistor is electrically connected to the first node, and a control electrode of the sixth transistor is connected to the clock signal.

10. The light emitting driving circuit according to claim 1, wherein: The first pull-up control module includes a tenth transistor, a first electrode and a control electrode of the tenth transistor are both connected to the clock signal, and a second electrode of the tenth transistor is electrically connected to the first node.

11. The light-emitting driving circuit according to claim 1, wherein: The pull-up module includes a seventh transistor, a first electrode of the seventh transistor is connected to the first power supply, a control electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to the light-emitting drive signal output terminal.

12. The light emitting driving circuit according to claim 1, wherein: The first pull-down control mode includes an eighth transistor, a second electrode of the eighth transistor is connected to the second power supply, a control electrode of the eighth transistor is connected to the clock signal, and a first electrode of the eighth transistor is electrically connected to the second node.

13. The light-emitting driving circuit according to any one of claims 1 to 12, wherein: The second pull-down control module includes a ninth transistor, a second electrode of the ninth transistor is connected to the second power supply, a control electrode of the ninth transistor is electrically connected to the second node, and a first electrode of the ninth transistor is electrically connected to the first node and the second node.

14. A timing control method, wherein: Applied to the light-emitting driving circuit according to any one of claims 1 to 13, the method comprises: In the preparation stage, the clock signal line is controlled to output a high-potential clock signal, so that the first pull-up control module and the first pull-down control module are turned on, the potential of the first node is pulled up to the first potential, the first maintaining module is charged, and the potential of the second node is pulled down to the second potential; the scan signal line is controlled to output a low-potential scan signal, so that the second pull-up control module is turned off; In the output stage, the clock signal line is controlled to output a low-potential clock signal, so that the first pull-up control module and the first pull-down control module are turned off; the scan signal line is controlled to output a high-potential scan signal, so that the second pull-up control module is turned on, the potential of the second node is pulled up to a third potential, the second pull-down control module is turned on, and the potential of the first node is pulled down to a fourth potential; In the reset stage, the clock signal line is controlled to output a high-potential clock signal, so that the first pull-up control module and the first pull-down control module are turned on, the potential of the first node is pulled up to the first potential, and the potential of the second node is pulled down to the second potential; the scan signal line is controlled to output a low-potential scan signal, so that the second pull-up control module is turned off; In the sustaining stage, the clock signal line is controlled to output a clock signal with a continuously switching high and low potentials, and the first sustaining module is discharged to maintain a high potential of the first node.

15. A display panel, wherein: It comprises a light-emitting driving circuit as described in any one of claims 1 to 13 and a pixel driving circuit connected to the light-emitting driving circuit, wherein the light-emitting driving circuit is used to output a corresponding light-emitting driving signal to the pixel driving circuit.

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