Fast recovery diode, and semiconductor device and manufacturing method therefor

Abstract

Provided are a fast recovery diode, and a semiconductor device and a manufacturing method therefor. The fast recovery diode comprises a substrate of a first conductivity type, a drift layer of the first conductivity type, and an anode layer of a second conductivity type. The drift layer comprises a first concentration doping layer, a second concentration doping layer, and a third concentration doping layer. The first concentration doping layer is provided on the substrate, the second concentration doping layer is provided on the side of the first concentration doping layer distant from the substrate, and the third concentration doping layer is provided on the side of the second concentration doping layer distant from the substrate. The doping concentration of the second concentration doping layer is less than or equal to the doping concentration of the first concentration doping layer and is less than the doping concentration of the third concentration doping layer. The doping concentration of the first concentration doping layer is reduced in the direction moving away from the substrate.

Description

Fast recovery diode, semiconductor device and manufacturing method thereof

[0001] This application claims the priority of Chinese patent application No. CN202311867242.6 filed on December 29, 2023; the priority of Chinese patent application No. CN202311440320.4 filed on October 31, 2023; the priority of Chinese patent application No. CN202311441714.1 filed on October 31, 2023; the priority of Chinese patent application No. CN202311441714.1 filed on June 30, 2023 310800555.3; the priority of the Chinese patent application with application number CN202311556312.6 filed on November 20, 2023; the priority of the Chinese patent application with application number CN202311556201.5 filed on November 20, 2023; the priority of the Chinese patent application with application number CN202311556338.0 filed on November 20, 2023; the priority of the Chinese patent application with application number CN202311556338.0 filed on November 20, 2023 Priority to the Chinese patent application number CN202311556157.8 filed on November 20, 2023; priority to the Chinese patent application number CN202311284578.X filed on September 28, 2023; priority to the Chinese patent application number CN202311517111.5 filed on November 14, 2023; priority to the Chinese patent application number CN202311517102.6 filed on November 14, 2023 The priority of the Chinese patent application with application number CN202311518612.5 filed on November 14, 2023; the priority of the Chinese patent application with application number CN202311433549.5 filed on October 31, 2023; the priority of the Chinese patent application with application number CN202311440142.5 filed on October 31, 2023, all of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a fast recovery diode, a semiconductor device, and a manufacturing method thereof. Background Art

[0003] A fast recovery diode (FRD) typically includes a substrate, a drift layer, and an anode layer, and the doping concentration of the drift layer greatly affects the withstand voltage and reverse recovery softness of the fast recovery diode. However, due to the unreasonable structural setting of the fast recovery diode in the related art, the doping concentration of the drift layer of some fast recovery diodes is too low. During the reverse recovery process, when the voltage across the fast recovery diode reaches the bus voltage, the width of the depletion region widens too much, resulting in a small number of residual carriers on the side of the drift layer close to the substrate, which is prone to current interruption. In other fast recovery diodes, the doping concentration of the drift layer is too high, the width of the depletion region widens too small, and the residual carriers in the drift layer are too many. The reverse current shows soft recovery, but the electric field gradient becomes larger during reverse withstand voltage, and the electric field peak becomes larger, which leads to a significant decrease in the reverse withstand voltage of the fast recovery diode.

[0004] Summary of the Invention

[0005] In one aspect, a fast recovery diode is provided. The fast recovery diode includes a substrate of a first conductivity type, a drift layer of the first conductivity type, and an anode layer of a second conductivity type. The drift layer includes a first-concentration doped layer, a second-concentration doped layer, and a third-concentration doped layer. The first-concentration doped layer is disposed on the substrate, the second-concentration doped layer is disposed on a side of the first-concentration doped layer away from the substrate, and the third-concentration doped layer is disposed on a side of the second-concentration doped layer away from the substrate. The doping concentration of the second-concentration doped layer is less than or equal to the doping concentration of the first-concentration doped layer and less than the doping concentration of the third-concentration doped layer. The doping concentration of the first-concentration doped layer decreases in a direction away from the substrate. The anode layer is disposed on a side of the third-concentration doped layer facing away from the substrate.

[0006] In another aspect, a semiconductor device is provided. The semiconductor device includes a drift layer of a first conductivity type, a voltage-resistant ring of a second conductivity type, a dielectric layer, a metal field plate, and a first polysilicon field plate. The voltage-resistant ring is disposed on the upper surface of the drift layer and corresponds to a transition region of the semiconductor device. The dielectric layer is disposed on the upper surface of the voltage-resistant ring. The metal field plate is disposed on the upper surface of the dielectric layer. The first polysilicon field plate is disposed on the upper surface of the voltage-resistant ring and located between the dielectric layer and the voltage-resistant ring, and the metal field plate is at least partially in contact with the first polysilicon field plate.

[0007] In another aspect, a semiconductor device is provided. The semiconductor device includes a drift layer of a first conductivity type, a trench portion, a field stop layer of the first conductivity type, and a collector layer of a second conductivity type. The trench portion extends downward from the upper surface of the drift layer. The trench portion extends in a first direction and is provided in a plurality. The plurality of trench portions are spaced apart in a second direction and form a gate trench group and a dummy gate trench group. The gate trench groups and the dummy gate trench groups are alternately arranged in the second direction. The field stop layer is provided on the lower surface of the drift layer. The collector layer of the second conductivity type is provided on the lower surface of the field stop layer. A first emitter layer of the first conductivity type is provided within the collector layer, and the first emitter layer corresponds to the dummy gate trench group from top to bottom.

[0008] In another aspect, a semiconductor device is provided. The semiconductor device includes a drift layer of a first conductivity type, a well layer of a second conductivity type, a field stop layer, and a collector layer of a second conductivity type. The well layer is disposed in a portion of the drift layer corresponding to a transition region of the semiconductor device, with the upper surface of the well layer constituting a portion of the upper surface of the drift layer. The field stop layer is disposed on the lower surface of the drift layer. The collector layer of the second conductivity type is disposed on the lower surface of the field stop layer. An emitter layer of the first conductivity type is disposed within the collector layer, and the emitter layer is located in a portion of the collector layer corresponding to the transition region.

[0009] In another aspect, a semiconductor device is provided. The semiconductor device includes a drift layer of a first conductivity type, a field stop layer of the first conductivity type, a collector layer of a second conductivity type, a first emitter layer of the first conductivity type, a ring layer of the second conductivity type, and a well layer of the second conductivity type. The field stop layer is disposed on the lower surface of the drift layer. The collector layer is disposed on the lower surface of the field stop layer. The first emitter layer is disposed on the lower surface of the field stop layer, and the collector layer is disposed circumferentially around the outside of the first emitter layer. The ring layer is disposed within the drift layer, with its upper surface constituting at least a portion of the upper surface of the drift layer. The ring layer corresponds to the junction of the collector layer and the first emitter layer, and a plurality of grooves are disposed within the ring layer. The well layer is disposed within the drift layer, with its upper surface constituting at least a portion of the upper surface of the drift layer. The well layer is disposed on both sides of the ring layer and at least partially corresponds to the collector layer and the first emitter layer. The portion of the well layer corresponding to the collector layer is provided with a plurality of grooves. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG1 is a structural diagram of a fast recovery diode according to some embodiments;

[0011] FIG2 is a linear graph of doping concentration of a fast recovery diode according to some embodiments;

[0012] FIG3 is a graph showing doping concentration of another fast recovery diode according to some embodiments;

[0013] FIG4 is a linear graph of electric field strength of a fast recovery diode according to some embodiments;

[0014] FIG5 is a graph showing the electric field strength of another fast recovery diode according to some embodiments;

[0015] FIG6 is a partial process diagram of a fast recovery diode manufacturing process according to some embodiments;

[0016] FIG7 is another partial process diagram of a fast recovery diode manufacturing process according to some embodiments;

[0017] FIG8 is another partial process diagram of a fast recovery diode manufacturing process according to some embodiments;

[0018] FIG9 is another partial process diagram of a fast recovery diode manufacturing process according to some embodiments;

[0019] FIG10 is a top view of a semiconductor device according to some embodiments;

[0020] FIG11 is a cross-sectional view of a semiconductor device according to some embodiments;

[0021] FIG12 is a schematic diagram of area A in FIG11 ;

[0022] FIG13 is another schematic diagram of area A in FIG11 ;

[0023] FIG14 is a diagram showing a withstand voltage curve of a semiconductor device according to some embodiments;

[0024] FIG15 is a diagram showing a withstand voltage curve of a semiconductor device in the related art;

[0025] FIG16 is a top view of another semiconductor device according to some embodiments;

[0026] FIG17 is a partial structural diagram of a semiconductor device according to some embodiments;

[0027] FIG18 is a partial cross-sectional view of a semiconductor device according to some embodiments;

[0028] FIG19 is a partial process diagram of a semiconductor device manufacturing process according to some embodiments;

[0029] FIG20 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0030] FIG21 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0031] FIG22 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0032] FIG23 is a structural diagram of yet another semiconductor device according to some embodiments;

[0033] FIG24 is a structural diagram of a semiconductor device according to some embodiments from another perspective;

[0034] FIG25 is a structural diagram of yet another semiconductor device according to some embodiments;

[0035] FIG26 is a structural diagram of yet another semiconductor device according to some embodiments;

[0036] FIG27 is a diagram showing simulation results of the on-state voltage drop of a fast recovery diode device in a semiconductor device when the emitter layer portion on the back side of the semiconductor device corresponds to the gate bus line in the upper and lower directions according to some embodiments;

[0037] FIG28 is a structural diagram of yet another semiconductor device according to some embodiments;

[0038] FIG29 is a partial cross-sectional view of line A1-A1 in FIG28;

[0039] FIG30 is another partial cross-sectional view of the line A1-A1 in FIG28;

[0040] FIG31 is another partial cross-sectional view of line A1-A1 in FIG28;

[0041] FIG32 is a structural diagram of another semiconductor device according to some embodiments;

[0042] FIG33 is a structural diagram of another semiconductor device according to some embodiments;

[0043] FIG34 is a structural diagram of another semiconductor device according to some embodiments;

[0044] FIG35 is a partial cross-sectional view along line A2-A2 in FIG32 or along line A3-A3 in FIG33;

[0045] FIG36 is a partial enlarged view of the B1 area in FIG33;

[0046] FIG37 is a partial enlarged view of the B2 area in FIG34 or the B3 area in FIG32;

[0047] FIG38 is a structural diagram of a semiconductor device according to some embodiments from another perspective;

[0048] FIG39 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments;

[0049] FIG40 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0050] FIG41 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0051] FIG42 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0052] FIG43 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0053] FIG44 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0054] FIG45 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0055] FIG46 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0056] FIG47 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0057] FIG48 is a structural diagram of yet another semiconductor device according to some embodiments;

[0058] FIG49 is a partial cross-sectional view of the semiconductor device along line AA in FIG48;

[0059] FIG50 is another flow chart of a method for manufacturing a semiconductor device according to some embodiments;

[0060] FIG51 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0061] FIG52 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0062] FIG53 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0063] FIG54 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0064] FIG55 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0065] FIG56 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0066] FIG57 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0067] FIG58 is a cross-sectional view of yet another semiconductor device according to some embodiments;

[0068] FIG59 is a partial cross-sectional view of a semiconductor device according to some embodiments;

[0069] FIG60 is a partial cross-sectional view of another location of a semiconductor device according to some embodiments;

[0070] FIG61 is a partial cross-sectional view of yet another semiconductor device according to some embodiments;

[0071] FIG62 is a partial enlarged view of a polysilicon field plate according to some embodiments;

[0072] FIG63 is a structural diagram of yet another semiconductor device according to some embodiments;

[0073] FIG64 is a schematic diagram of a layout design of a transition region according to some embodiments;

[0074] FIG65 is a cross-sectional view of the transition region along line AA in FIG64;

[0075] FIG66 is a cross-sectional view of the transition region along line BB in FIG64;

[0076] FIG67 is a cross-sectional view of the transition region along line CC in FIG64;

[0077] FIG68 is another flow chart of a method for manufacturing a semiconductor device according to some embodiments;

[0078] FIG69 is another flowchart of a method for manufacturing a semiconductor device according to some embodiments;

[0079] FIG70 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0080] FIG. 71 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0081] FIG72 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0082] FIG73 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0083] FIG. 74 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0084] FIG. 75 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0085] FIG76 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0086] FIG77 is a top view of yet another semiconductor device according to some embodiments;

[0087] FIG78 is a partial enlarged view of area A in FIG77 ;

[0088] FIG79 is a partial enlarged view of area B in FIG77 ;

[0089] FIG80 is a cross-sectional view of the semiconductor device along line AA in FIG78;

[0090] FIG81 is a cross-sectional view of the semiconductor device along line BB in FIG78;

[0091] FIG82 is a partial enlarged view of yet another semiconductor device according to an embodiment;

[0092] FIG83 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0093] FIG84 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0094] FIG85 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0095] FIG86 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0096] FIG87 is a structural diagram of yet another semiconductor device according to some embodiments;

[0097] FIG88 is a top view of yet another semiconductor device according to some embodiments;

[0098] FIG89 is a partial enlarged view of yet another semiconductor device according to some embodiments;

[0099] FIG90 is a cross-sectional view of the semiconductor device along line AA in FIG89;

[0100] FIG91 is a cross-sectional view of the semiconductor device along line BB in FIG89;

[0101] FIG92 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0102] FIG93 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0103] FIG. 94 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0104] FIG. 95 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0105] FIG. 96 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0106] FIG. 97 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0107] FIG. 98 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0108] FIG99 is a partial enlarged view of yet another semiconductor device according to some embodiments;

[0109] FIG100 is a partial enlarged view of yet another semiconductor device according to some embodiments;

[0110] FIG101 is a partial enlarged view of yet another semiconductor device according to some embodiments;

[0111] FIG102 is a partial enlarged view of yet another semiconductor device according to some embodiments;

[0112] FIG103 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0113] FIG104 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0114] FIG105 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0115] FIG106 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0116] FIG107 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0117] FIG108 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0118] FIG109 is a structural diagram of yet another semiconductor device according to some embodiments;

[0119] FIG110 is a partial enlarged view of yet another semiconductor device according to some embodiments;

[0120] FIG111 is a structural diagram of yet another semiconductor device according to some embodiments;

[0121] FIG112 is a partial enlarged view of yet another semiconductor device according to some embodiments;

[0122] FIG113 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0123] FIG114 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0124] FIG. 115 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0125] FIG116 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0126] FIG. 117 is another partial process diagram of a semiconductor device fabrication process according to some embodiments;

[0127] FIG. 118 is another partial process diagram of a semiconductor device fabrication process according to some embodiments. DETAILED DESCRIPTION

[0128] The following will be combined with the accompanying drawings to clearly and completely describe some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, rather than all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0129] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0130] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0131] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean a fixed connection, a removable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediary. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The embodiments disclosed herein are not necessarily limited to the contents herein.

[0132] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0133] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0134] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0135] In some embodiments, as shown in FIG. 1 to FIG. 9 , the fast recovery diode 1 includes a substrate 2 of a first conductivity type, a drift layer 10 of a first conductivity type, and an anode layer 300 of a second conductivity type.

[0136] The drift layer 10 includes a first concentration-doped layer 210, a second concentration-doped layer 220 and a third concentration-doped layer 230. The first concentration-doped layer 210 is arranged on the substrate 2, the second concentration-doped layer 220 is arranged on the side of the first concentration-doped layer 210 away from the substrate 2, and the third concentration-doped layer 230 is arranged on the side of the second concentration-doped layer 220 away from the substrate 2. The doping concentration of the second concentration-doped layer 220 is less than or equal to the doping concentration of the first concentration-doped layer 210 and less than the doping concentration of the third concentration-doped layer 230. The doping concentration of the first concentration-doped layer 210 decreases in the direction away from the substrate 2, and the anode layer 300 is arranged on the side of the third concentration-doped layer 230 facing away from the substrate 2.

[0137] The substrate 2 may be formed by arsenic doping, the drift layer 10 may be composed of a phosphorus doped silicon epitaxial layer, and the anode layer 300 may be formed by boron ion implantation.

[0138] According to some embodiments of the fast recovery diode 1 of the present disclosure, the drift layer 10 is provided with a first concentration doping layer 210, a second concentration doping layer 220, and a third concentration doping layer 230, wherein the first concentration doping layer 210 is provided on the substrate 2, the second concentration doping layer 220 is provided on the side of the first concentration doping layer 210 away from the substrate 2, and the third concentration doping layer 230 is provided on the side of the second concentration doping layer 220 away from the substrate 2. The doping concentration of the second concentration doping layer 220 is less than or equal to the doping concentration of the first concentration doping layer 210 and less than the doping concentration of the third concentration doping layer 230. In other words, the concentration of the third concentration doping layer 230 can be relatively high, that is, the doping concentration of the side of the drift layer 10 close to the anode layer 300 can be relatively high. In this way, the carrier concentration on the side of the drift layer 10 close to the anode layer 300 during forward conduction can be reduced, thereby effectively reducing the peak current of reverse recovery.

[0139] Moreover, the doping concentration of the second concentration-doped layer 220 can be relatively low, that is, the doping concentration of the second concentration-doped layer 220 can be less than the doping concentration of the first concentration-doped layer 210 and the doping concentration of the third concentration-doped layer 230, or the doping concentration of the second concentration-doped layer 220 can be equal to the doping concentration of the first concentration-doped layer 210 and less than the doping concentration of the third concentration-doped layer 230. This can reduce the electric field gradient of the second concentration-doped layer 220, which is beneficial to improving the reverse withstand voltage performance of the fast recovery diode 1.

[0140] In addition, the doping concentration of the first concentration doped layer 210 decreases in a direction away from the substrate 2 , and the anode layer 300 is disposed on a side of the third concentration doped layer 230 facing away from the substrate 2 . That is, the side of the first-concentration-doped layer 210 away from the anode layer 300 is the point where the doping concentration of the first-concentration-doped layer 210 is the highest, and the side of the first-concentration-doped layer 210 close to the anode layer 300 is the point where the doping concentration of the first-concentration-doped layer 210 is the lowest. The doping concentration of the side of the first-concentration-doped layer 210 away from the anode layer 300 can be higher, and the doping concentration of the side of the first-concentration-doped layer 210 close to the anode layer 300 can be lower. This can increase the electric field gradient in the direction away from the anode layer 300, thereby narrowing the width of the depletion region 600 of the fast recovery diode 1 during the reverse recovery process at the same reverse withstand voltage, thereby avoiding current interruption. In addition, the first-concentration-doped layer 210 can inject sufficient carriers so that there are more residual carriers on the side of the first-concentration-doped layer 210 away from the anode layer 300, which is beneficial to increasing the reverse recovery softness factor of the fast recovery diode 1, that is, improving the reverse recovery softness, which is beneficial to improving the stability and reliability of the circuit. At the same time, it can also ensure that the reverse withstand voltage of the fast recovery diode 1 is high, thereby avoiding circuit damage.

[0141] Thus, the fast recovery diode 1 in some embodiments of the present disclosure has the advantages of good voltage resistance, small reverse recovery peak current and high circuit stability.

[0142] In some embodiments, as shown in Figures 2 and 3, the concentration of the first concentration doped layer 210 decreases linearly in a direction away from the substrate 2. Multiple sub-concentration doped layers 26 (as shown in Figures 6 to 9) may be provided in the first concentration doped layer 210, and the concentrations of the multiple sub-concentration doped layers 26 decrease in a direction away from the substrate 2. That is, the first concentration doped layer 210 is composed of multiple layers of decreasing doped concentration layers epitaxially. The first concentration doped layer 210 is then diffused through a thermal process to obtain a distribution in which the doping concentration decreases approximately linearly. This allows the electric field gradient to increase linearly in a direction away from the anode layer 300, thereby narrowing the width of the depletion region 600 of the fast recovery diode 1 during the reverse recovery process at the same reverse withstand voltage, thereby avoiding current interruption. The first concentration doped layer 210 can have more residual carriers on the side away from the anode layer 300, which is beneficial for increasing the reverse recovery softness factor of the fast recovery diode 1, thereby improving the stability and reliability of the circuit.

[0143] In some embodiments, as shown in Figures 1 to 9, the thickness of the first concentration-doped layer 210, the thickness of the second concentration-doped layer 220, and the thickness of the third concentration-doped layer 230 decrease in sequence. That is, the minimum thickness of the first concentration-doped layer 210 is greater than or equal to the maximum thickness of the second concentration-doped layer 220, and the minimum thickness of the second concentration-doped layer 220 is greater than or equal to the maximum thickness of the first concentration-doped layer 210. In this way, the thickness of the third concentration-doped layer 230 can be relatively thin, thereby ensuring that the reverse withstand voltage of the fast recovery diode 1 is relatively large. At the same time, the thickness of the first concentration-doped layer 210 can be relatively thick to reduce the forward conduction voltage drop and allow more carriers to be injected into the first concentration-doped layer 210 to ensure soft recovery of the fast recovery diode 1.

[0144] In some embodiments, the thickness of the first concentration-doped layer 210 is 30 μm to 35 μm. For example, the thickness of the first concentration-doped layer 210 is 30 μm, 31 μm, 32 μm, 33 μm, 34 μm, or 35 μm. This can prevent the thickness of the first concentration-doped layer 210 from being too small, so that sufficient carriers can be injected into the first concentration-doped layer 210 to ensure the soft recovery of the fast recovery diode 1. It can also prevent the thickness of the first concentration-doped layer 210 from being too large, thereby preventing an increase in the forward conduction voltage drop of the fast recovery diode 1.

[0145] In addition, the thickness of the second concentration doped layer 220 is 20 μm to 25 μm. For example, the thickness of the second concentration doped layer 220 is 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, or 25 μm. This can prevent the thickness of the second concentration doped layer 220 from being too small, thereby improving the withstand voltage performance of the fast recovery diode 1. On the other hand, it can prevent the thickness of the second concentration doped layer 220 from being too large, thereby preventing an increase in the forward conduction voltage drop of the fast recovery diode 1.

[0146] In addition, the thickness of the third concentration doped layer 230 is 8 μm to 12 μm. For example, the thickness of the third concentration doped layer 230 is 8 μm, 9 μm, 10 μm, 11 μm, or 12 μm. This can prevent the thickness of the third concentration doped layer 230 from being too small, thereby effectively reducing the peak current of reverse recovery. On the other hand, it can prevent the thickness of the third concentration doped layer 230 from being too large, thereby preventing the reverse withstand voltage of the fast recovery diode 1 from being reduced.

[0147] In some embodiments, the drift layer 10 has a thickness of 60 μm to 80 μm. The thickness of the drift layer 10 is the sum of the thicknesses of the first-concentration-doped layer 210, the second-concentration-doped layer 220, and the third-concentration-doped layer 230. Thus, the sum of the thicknesses of the first-concentration-doped layer 210, the second-concentration-doped layer 220, and the third-concentration-doped layer 230 is 60 μm to 80 μm.

[0148] For example, the thickness of the drift layer 10 is 60 μm, 62 μm, 64 μm, 66 μm, 68 μm, 70 μm, 72 μm, 74 μm, 76 μm, 78 μm, or 80 μm. This can prevent the thickness of the drift layer 10 from being too small, thereby ensuring good withstand voltage performance of the fast recovery diode 1, and can also prevent the thickness of the drift layer 10 from being too large, thereby preventing a significant increase in the forward conduction voltage drop of the fast recovery diode 1.

[0149] In addition, the junction depth of the anode layer 300 is 3 μm to 5 μm. For example, the junction depth of the anode layer 300 is 3 μm, 4 μm or 5 μm, which can ensure that the overall thickness of the fast recovery diode 1 is moderate.

[0150] In some embodiments, as shown in FIG2 , the doping concentration of the second-concentration-doped layer 220 is a constant value. The doping concentration of the second-concentration-doped layer 220 needs to be less than or equal to the minimum doping concentration of the first-concentration-doped layer 210, and the doping concentration of the second-concentration-doped layer 220 is less than the minimum doping concentration of the third-concentration-doped layer 230. This can reduce the electric field gradient of the second-concentration-doped layer 220, which is beneficial for improving the reverse withstand voltage performance of the fast recovery diode 1, thereby facilitating a compromise between the reverse recovery peak current and the withstand voltage performance of the fast recovery diode 1.

[0151] In other embodiments, as shown in FIG3 , the doping concentration of the second-concentration-doped layer 220 increases in a direction away from the substrate 2. For example, the doping concentration of the second-concentration-doped layer 220 on the side away from the substrate 2 is greater than the minimum doping concentration of the first-concentration-doped layer 210, and the doping concentration of the second-concentration-doped layer 220 on the side away from the substrate 2 is less than the minimum doping concentration of the third-concentration-doped layer 230. This can reduce the electric field gradient of the second-concentration-doped layer 220, which is beneficial for improving the reverse withstand voltage performance of the fast recovery diode 1, thereby facilitating a compromise between the reverse recovery peak current and the withstand voltage performance of the fast recovery diode 1.

[0152] In some embodiments, as shown in FIG2 , the doping concentration of the third-concentration-doped layer 230 is a constant value. The doping concentration of the third-concentration-doped layer 230 needs to be greater than the maximum concentration of the second-concentration-doped layer 220. This can reduce the carrier concentration on the side of the drift layer 10 close to the anode layer 300 during forward conduction, thereby effectively reducing the peak current of reverse recovery.

[0153] In other embodiments, as shown in FIG3 , the doping concentration of the third-concentration-doped layer 230 increases in a direction away from the substrate 2. The doping concentration of the third-concentration-doped layer 230 on the side close to the substrate 2 needs to be greater than the maximum concentration of the second-concentration-doped layer 220. This can reduce the carrier concentration on the side of the drift layer 10 close to the anode layer 300 during forward conduction, thereby effectively reducing the peak current of reverse recovery.

[0154] In some embodiments, as shown in FIG2 , the doping concentration of the side of the first-concentration-doped layer 210 close to the substrate 2 is greater than the doping concentration of the third-concentration-doped layer 230 . Thus, the doping concentration of the side of the first-concentration-doped layer 210 close to the substrate 2 can be higher, which can narrow the width of the depletion region 600 of the fast recovery diode 1 during the reverse recovery process at the same reverse withstand voltage, thereby preventing the depletion region 600 from expanding toward the side close to the substrate 2 during the reverse recovery process, ensuring that the cathode stores sufficient carriers and avoiding current interruption. Furthermore, the doping concentration of the side of the first-concentration-doped layer 210 away from the substrate 2 is equal to the doping concentration of the side of the second-concentration-doped layer 220 close to the substrate 2 . This prevents the doping concentration of the first-concentration-doped layer 210 from being too high, allowing sufficient carriers to be injected into the first-concentration-doped layer 210 , resulting in more residual carriers on the side of the first-concentration-doped layer 210 close to the substrate 2 , which is beneficial for increasing the reverse recovery softness factor of the fast recovery diode 1, i.e., improving the reverse recovery softness.

[0155] In some embodiments, the doping concentration of the first concentration doped layer 210 near the side of the substrate 2 is 8×10 14 cm -3 ~10×1014cm -3On the one hand, this can prevent the doping concentration of the first concentration-doped layer 210 from being too low, so that the width of the depletion region 600 of the fast recovery diode 1 during the reverse recovery process at the same reverse withstand voltage is narrower, avoiding current interruption. On the other hand, it can prevent the doping concentration of the first concentration-doped layer 210 from being too high, so that sufficient carriers can be injected into the first concentration-doped layer 210, so that the residual carriers on the side of the first concentration-doped layer 210 close to the substrate 2 can be more, which is beneficial to increasing the reverse recovery softness factor of the fast recovery diode 1, that is, improving the reverse recovery softness.

[0156] In addition, the doping concentration of the second concentration doped layer 220 is 1×10 14 cm -3 ~1.5×1014cm -3 On the one hand, this can prevent the doping concentration of the second concentration doped layer 220 from being too low, so that the fast recovery diode 1 has better withstand voltage performance. On the other hand, it can prevent the doping concentration of the second concentration doped layer 220 from being too high, thereby preventing the forward conduction voltage drop of the fast recovery diode 1 from increasing.

[0157] In addition, the doping concentration of the third concentration doping layer 230 is 5×10 14 cm -3 ~6×1014cm -3 On the one hand, this can prevent the doping concentration of the third concentration doped layer 230 from being too low, thereby effectively reducing the peak current of reverse recovery. On the other hand, it can prevent the doping concentration of the third concentration doped layer 230 from being too high, thereby preventing the reverse withstand voltage of the fast recovery diode 1 from being reduced.

[0158] In some embodiments, as shown in FIG. 9 , the fast recovery diode 1 further includes an anode metal layer 400 and a cathode metal layer 500 .

[0159] The anode metal layer 400 is disposed on the side of the anode layer 300 facing away from the drift layer 10, and the cathode metal layer 500 is disposed on the side of the substrate 2 facing away from the drift layer 10. That is, the third-concentration-doped layer 230, the second-concentration-doped layer 220, and the first-concentration-doped layer 210 are arranged in sequence along the anode metal layer 400 toward the cathode metal layer 500, with the doping concentration of the first-concentration-doped layer 210 increasing from the anode metal layer 400 toward the cathode metal layer 500.

[0160] The following describes the manufacturing process of the fast recovery diode 1 according to some embodiments of the present disclosure with reference to the accompanying drawings:

[0161] First, as shown in FIG6 , a first concentration-doped layer 210, a second concentration-doped layer 220, and a third concentration-doped layer 230 are sequentially grown epitaxially on substrate 2. Then, as shown in FIG7 , P-well (Pwell) ions are implanted into the side of the third concentration-doped layer 230 facing away from substrate 2 to form a P-type region, i.e., anode layer 300. Next, as shown in FIG8 , anode metal is deposited on the side of the anode layer 300 facing away from substrate 2 to form anode metal layer 400. Finally, as shown in FIG9 , substrate 2 is thinned, and cathode metal is deposited on the side of substrate 2 facing away from anode metal layer 400 to form cathode metal layer 500.

[0162] The following describes a semiconductor device 100 in some embodiments of the present disclosure with reference to Figures 10 to 15. The semiconductor device 100 is, for example, an insulated gate bipolar transistor (IGBT). In the following description, N and P represent the conductivity type of the semiconductor. In some embodiments of the present disclosure, the first conductivity type is N-type and the second conductivity type is P-type.

[0163] 11 , the semiconductor device 100 includes a drift layer 10 of a first conductivity type, a voltage-resistant ring 25 of a second conductivity type, a dielectric layer 13 , a metal field plate 90 , and a first polysilicon field plate 91 .

[0164] In some embodiments, a first conductive type field stop layer 15 is provided below the first conductive type drift layer 10, a second conductive type collector layer 16 is provided below the field stop layer 15, and a collector metal layer 18 is provided below the collector layer 16. This can form the basic structure of the semiconductor device 100 and ensure the normal operation of the semiconductor device 100.

[0165] Considering that the transition region 102 of the semiconductor device 100 is located between the terminal region 103 and the active region 101, the structure of the transition region 102 is relatively complex and voltage breakdown is likely to occur there. By setting the voltage-resistant ring 25 on the surface of the drift layer 10 corresponding to the portion of the transition region 102 of the semiconductor device 100, the voltage-resistant ring 25 can optimize the electric field distribution of the transition region 102 and improve the voltage resistance of the transition region 102.

[0166] As shown in Figures 11 to 13, the dielectric layer 13 is arranged on the upper surface of the voltage-resistant ring 25, the metal field plate 90 is arranged on the upper surface of the dielectric layer 13, and the first polysilicon field plate 91 is arranged on the upper surface of the voltage-resistant ring 25. The first polysilicon field plate 91 is located between the dielectric layer 13 and the voltage-resistant ring 25, and the metal field plate 90 is at least partially in contact with the first polysilicon field plate 91.

[0167] In some embodiments, by setting the dielectric layer 13 on the upper surface of the voltage-resistant ring 25 and setting the metal field plate 90 on the upper surface of the dielectric layer 13, a portion of the metal field plate 90 can be in direct contact with the voltage-resistant ring 25, and another portion can be in contact with the dielectric layer 13. In this way, when the semiconductor device 100 is subjected to a reverse bias voltage, the metal field plate 90 can offset the effect of the positive charge in the dielectric layer 13 on the surface, repel surface electrons, and widen the surface depletion region 600 at the interface, thereby increasing the breakdown voltage.

[0168] In some embodiments, considering that the contact area between the metal field plate 90 and the voltage-resistant ring 25 is small, the improvement in the voltage-resistant capability of the semiconductor device 100 in the transition zone 102 is limited. Compared with the embodiments in which the first polysilicon field plate 91 is not provided, some embodiments of the present disclosure provide a first polysilicon field plate 91 between the dielectric layer 13 and the voltage-resistant ring 25. The first polysilicon field plate 91 can achieve large-area direct contact with the voltage-resistant ring 25, and the metal field plate 90 can be at least partially in contact with the first polysilicon field plate 91, so that the first polysilicon field plate 91 and the metal field plate 90 have the same electric potential.

[0169] In this way, when the semiconductor device 100 is subjected to a reverse bias voltage, the metal field plate 90 and the first polysilicon field plate 91 can offset the influence of the positive charge in the dielectric layer 13 on the surface, repel surface electrons, and widen the surface depletion region 600 at the interface, thereby significantly improving the surface charge and electric field distribution at the contact position between the first polysilicon field plate 91 and the voltage-resistant ring 25, effectively reducing the surface charge of the semiconductor device 100, and further significantly improving the breakdown voltage of the semiconductor device 100, thereby avoiding the transition region 102 of the semiconductor device 100 from being broken down and failing, and improving the voltage resistance and reliability of the semiconductor device 100.

[0170] Therefore, by setting the first polysilicon field plate 91 on the upper surface of the voltage-resistant ring 25, the first polysilicon field plate 91 is located between the dielectric layer 13 and the voltage-resistant ring 25, and the metal field plate 90 is at least partially in contact with the first polysilicon field plate 91, the electric field distribution in the transition zone 102 can be optimized, the breakdown voltage of the semiconductor device 100 can be significantly improved, and the voltage resistance and reliability of the semiconductor device 100 can be significantly improved.

[0171] In some embodiments, as shown in FIG. 11 , the semiconductor device 100 further includes a field oxide layer 60 . The field oxide layer 60 is disposed on the upper surface of the voltage-resistant ring 25 and is located between the first polysilicon field plate 91 and the voltage-resistant ring 25 . By disposing the field oxide layer 60 in the semiconductor device 100 and positioning it on the upper surface of the voltage-resistant ring 25 , the field oxide layer 60 can be used to achieve isolation and prevent the occurrence of parasitic transistors. Furthermore, by positioning the field oxide layer 60 between the first polysilicon field plate 91 and the voltage-resistant ring 25 , the first polysilicon field plate 91 can be positioned above the field oxide layer 60 . The first polysilicon field plate 91 can modulate the electric field in the contact area with the field oxide layer 60 to make the electric field distribution more uniform, thereby improving the voltage withstand capability and reliability of the semiconductor device 100 in some embodiments.

[0172] In some embodiments, as shown in FIG. 13 , the field oxide layer 60 may mainly include a field oxide body 61 and a protrusion 62 . The protrusion 62 is disposed at one end of the field oxide body 61 , and at least a portion of the first polysilicon field plate 91 covers the protrusion 62 .

[0173] Considering the growth process of the field oxide layer 60, the field oxide layer 60 includes a field oxide body 61 and a protrusion 62, with the protrusion 62 located at one end of the field oxide body 61. In the region of the protrusion 62, the surface charge of the semiconductor device 100 is concentrated, and the electric field distribution is relatively uneven, representing a weak area of ​​the transition region 102. By at least partially covering the protrusion 62, the first polysilicon field plate 91 can improve the surface charge and electric field distribution in the region of the protrusion 62, thereby increasing the breakdown voltage, improving the withstand voltage capability of the semiconductor device 100, and enhancing the reliability of the semiconductor device 100.

[0174] In some embodiments, in combination with what is shown in FIG13 , the first polysilicon field plate 91 may include a main body portion 911, a cover portion 912 and an extension portion 913, wherein the cover portion 912 is connected between the main body portion 911 and the extension portion 913, the main body portion 911 covers the upper surface of the field oxide body 61, the cover portion 912 covers the upper surface of the protrusion 62, and the extension portion 913 extends outside the protrusion 62 and contacts the pressure-resistant ring 25.

[0175] By covering the main body 911 on the upper surface of the field oxide body 61 and the covering portion 912 on the upper surface of the protrusion 62, the first polysilicon field plate 91 can cover the field oxide layer 60, ensuring the uniform distribution of the electric field on the surface above the field oxide layer 60 in the transition region 102.

[0176] Furthermore, by making the extension portion 913 cover the outside of the protruding nozzle 62 , the extension portion 913 can modulate the electric field in the area outside the protruding nozzle 62 , thereby ensuring uniform distribution of the electric field in the area outside the protruding nozzle 62 .

[0177] In this way, by adjusting the structure and setting position of the first polysilicon field plate 91, the electric field modulation capability of the first polysilicon field plate 91 on the transition region 102 can be improved, electric field concentration can be avoided, and the electric field distribution in the transition region 102 can be made more uniform. In addition, the voltage resistance and reliability of the semiconductor device 100 can also be improved.

[0178] In some embodiments, as shown in FIG. 13 , the length of the extension portion 913 is L1, where L1 satisfies the relationship: L1 ≥ 2μ1. By setting the length of the extension portion 913 within a reasonable range, that is, by setting the length of the first polysilicon field plate 91 extending to one side relative to the protruding nozzle 62 within a reasonable range, the first polysilicon field plate 91 can optimize the electric field distribution in the area near the protruding nozzle 62. This avoids the extension portion 913 being too short, which would result in localized electric field concentration on the side of the main portion 911 near the protruding nozzle 62. This ensures uniform electric field distribution across the transition region 102 and improves the reliability of the transition region 102 and, therefore, the semiconductor device 100.

[0179] In some embodiments, as shown in FIG. 12 , a first through-hole 31 is provided on the dielectric layer 13 , and a first electrical connection protrusion 41 is provided on the metal field plate 90 . The first electrical connection protrusion 41 passes through the first through-hole 31 and contacts the first polysilicon field plate 91 .

[0180] By providing a first through-hole 31 on the dielectric layer 13 and a first electrical connection protrusion 41 on the metal field plate 90, the metal field plate 90 can be at least partially in contact with the first polysilicon field plate 91, and the connection between the metal field plate 90 and the first polysilicon field plate 91 can be made simpler, more convenient, more stable and more reliable.

[0181] In some embodiments, as shown in FIG. 12 , the metal field plate 90 is at least partially in contact with the pressure-resistant ring 25 .

[0182] By at least partially contacting the metal field plate 90 with the voltage-resistant ring 25, the metal field plate 90 and the voltage-resistant ring 25 are at the same potential. Furthermore, because the metal field plate 90 also at least partially contacts the first polysilicon field plate 91, the metal field plate 90 and the first polysilicon field plate 91 are at the same potential. This ensures that the voltage-resistant ring 25, the metal field plate 90, and the first polysilicon field plate 91 are at the same potential. This prevents the formation of a floating electric field in the transition region 102, and prevents external interference with the floating electric field during operation of the semiconductor device 100, which could lead to uneven electric field distribution in the transition region 102 and reduced withstand voltage and reliability. This improves the withstand voltage capability and reliability of the semiconductor device 100.

[0183] In some embodiments, as shown in Figure 12, a second perforation 32 is provided on the dielectric layer 13, and a second electrical connection protrusion 42 is provided on the metal field plate 90. The second electrical connection protrusion 42 passes through the second perforation 32 and contacts the voltage-resistant ring 25. The second electrical connection protrusion 42 is spaced apart from the first polysilicon field plate 91.

[0184] In this case, in the area of ​​the transition region 102 where the first polysilicon field plate 91 is not provided, at least a portion of the dielectric layer 13 is still located between the voltage-resistant ring 25 and the metal field plate 90. By providing the second through-hole 32 in the dielectric layer 13 and the second electrical connection protrusion 42 on the metal field plate 90, and by spacing the second electrical connection protrusion 42 from the first polysilicon field plate 91, the metal field plate 90 can be at least partially connected to the voltage-resistant ring 25, and the connection between the metal field plate 90 and the voltage-resistant ring 25 can be made simpler, more convenient, more stable and more reliable.

[0185] In some embodiments, as shown in FIG. 10 and FIG. 11 , the semiconductor device 100 further includes an active region 101 and a terminal region 103 . The terminal region 103 is disposed at the periphery of the active region 101 , and the transition region 102 is connected between the active region 101 and the terminal region 103 .

[0186] The active region 101 can carry most of the forward current during forward conduction and also withstand a high blocking voltage when a reverse voltage is applied. By arranging the termination region 103 outside the active region 101 and connecting the transition region 102 between the active region 101 and the termination region 103, the termination region 103 can alleviate electric field crowding at the edge of the active region 101 when a reverse voltage is applied to the semiconductor device 100, thereby improving the reverse breakdown voltage of the semiconductor device 100.

[0187] Here, the active region 101 is provided with an emitter metal layer 14, which can serve as the emitter of the semiconductor device 100 and has a conductive and connecting function. Furthermore, a gate bus 84 is provided in the transition region 102. The parallel gates in the semiconductor device 100 are connected to a gate pad via the gate bus 84, and are then connected to an external gate drive circuit via the gate pad.

[0188] In some embodiments, as shown in conjunction with FIG10 and FIG11 , the metal field plate 90 is connected to the emitter metal layer 14 of the active region 101. Considering that the metal field plate 90 is in contact with the first polysilicon field plate 91, by connecting the metal field plate 90 to the emitter metal layer 14 of the active region 101, the metal field plate 90, the first polysilicon field plate 91, and the emitter metal layer 14 of the active region 101 can be brought to the same potential, thereby making the electric field distribution in the transition region 102 more uniform, thereby improving the voltage withstand capability of the transition region 102 and, therefore, the semiconductor device 100.

[0189] In some embodiments, as shown in FIG. 11 , a second polysilicon field plate 85 is provided in the terminal region 103 , and the first polysilicon field plate 91 and the second polysilicon field plate 85 are made of the same material and are spaced apart.

[0190] Considering that the electric field strength in the terminal region 103 is relatively strong and the voltage per unit length is relatively large, voltage breakdown is likely to occur there. By setting a second polysilicon field plate 85 in the terminal region 103, the second polysilicon field plate 85 can effectively widen the main junction depletion region 600 outward, avoiding the electric field concentration phenomenon, thereby increasing the breakdown voltage of the terminal region 103 and improving the voltage resistance of the terminal region 103 and even the semiconductor device 100.

[0191] By setting the materials of the first polysilicon field plate 91 and the second polysilicon field plate 85 to be the same, and arranging the first polysilicon field plate 91 and the second polysilicon field plate 85 to be spaced apart, the first polysilicon field plate 91 and the second polysilicon field plate 85 can be manufactured and formed simultaneously during the manufacturing process of the semiconductor device 100, and the processes of the first polysilicon field plate 91 and the second polysilicon field plate 85 can be combined without adding unnecessary processes, thereby simplifying the production process of the semiconductor device 100.

[0192] The following describes a semiconductor device 100 in some embodiments of the present disclosure with reference to Figures 16 to 22. The semiconductor device 100 may be a reverse conducting IGBT (RC-IGBT). The first semiconductor device type region 1011 may be an IGBT region, and the second semiconductor device type region 1012 may be an FRD region. In the following description, N and P represent the conductivity type of the semiconductor. In some embodiments of the present disclosure, the first conductivity type is N-type and the second conductivity type is P-type.

[0193] 16 to 18 , the semiconductor device 100 includes a drift layer 10 of a first conductivity type, a field stop layer 15 of a first conductivity type, and a collector layer 16 of a second conductivity type.

[0194] In some embodiments, the upper surface of the drift layer 10 of the first conductivity type is provided with a well layer 11 of the second conductivity type, a first emitter layer 17 of the first conductivity type located in the well layer 11, a dielectric layer 13 located above the first emitter layer 17, and an emitter metal layer 14 located above the dielectric layer 13; the lower surface of the drift layer 10 of the first conductivity type is provided with a field stop layer 15 of the first conductivity type, a collector layer 16 of the second conductivity type located on the lower surface of the field stop layer 15, a first emitter layer 17 of the first conductivity type, and a collector metal layer 18 located at the bottom.

[0195] The dielectric layer 13 can protect the well layer 11, reducing the risk of damage to the semiconductor device 100. A contact hole 171 is defined in the dielectric layer 13. The contact hole 171 is located above the well layer 11 and between two adjacent grooves 2110. The contact hole 171 extends in the second direction, and the second emitter layer 12 is at least partially located below the contact hole 171. Thus, the emitter metal layer 14 can contact the second emitter layer 12 through the contact hole 171.

[0196] In some embodiments, the semiconductor device 100 includes an active region 101 and a termination region 103 surrounding the active region 101. A first emitter layer 17 is disposed within the collector layer 16. The regions corresponding to the collector layer 16 in the vertical direction are the first semiconductor device type regions 1011, and the regions corresponding to the first emitter layer 17 in the vertical direction are the second semiconductor device type regions 1012. In other words, the active region 101 of the semiconductor device 100 may include the first semiconductor device type regions 1011 and the second semiconductor device type regions 1012. The emitter metal layer 14 may serve not only as the emitter terminal of the first semiconductor device type region 1011 but also as the anode terminal of the second semiconductor device type region 1012. The collector metal layer 18 may serve not only as the collector terminal of the first semiconductor device type region 1011 but also as the cathode terminal of the second semiconductor device type region 1012. In this way, the first semiconductor device type region 1011 can realize forward conduction of the semiconductor device 100 , and the second semiconductor device type region 1012 can realize reverse conduction of the semiconductor device 100 , so that the semiconductor device 100 has both forward conduction and reverse conduction characteristics.

[0197] As shown in Figures 17 and 18, the semiconductor device 100 may further include a groove portion 2110, which extends downward from the upper surface of the drift layer 10, and the groove portion 2110 is extended in the first direction and is multiple, and the multiple groove portions 2110 are spaced apart in the second direction and form a gate trench group 21 and a dummy gate trench group 22, and the gate trench group 21 and the dummy gate trench group 22 are alternately arranged in the second direction.

[0198] In some embodiments, the gate trench group 21 includes at least one gate trench portion 211, and the dummy gate trench group 22 includes at least one dummy gate trench portion 221. Both the gate trench portion 211 and the dummy gate trench portion 221 are provided with an oxide insulating layer 70 and deposited with polysilicon 71. A gate can be formed in the gate trench portion 211, and a second emitter layer 12 is provided on both sides of the gate trench portion 211 in the second direction. The gate trench portion 211 has a conductive channel 4 (as shown in FIG. 23 ) with current flow capability, ensuring normal operation of the first semiconductor device type region 1011 and even the semiconductor device 100. However, the dummy gate trench portion 221 does not have a second emitter layer 12 on both sides of the second direction. The dummy gate trench portion 221 does not have a conductive channel 4 and does not have current flow capability. The dummy gate trench portion 221 can be connected to the emitter, reducing Miller capacitance and current density, thereby improving the short-circuit capability of the semiconductor device 100.

[0199] By alternating the gate trench groups 21 and the dummy gate trench groups 22 in the second direction, the uniformity of the circuit distribution of the semiconductor device 100 can be improved, and the thermal distribution and anti-interference capability of the circuit can be improved. The specific number of dummy gate trench portions 221 in the dummy gate trench group 22 and the specific number of gate trench portions 211 in the gate trench group 21 can be set according to the specific short-circuit requirements of the semiconductor device 100, and are not specifically limited here.

[0200] In some embodiments, the first emitter layer 17 is vertically aligned with the dummy gate trench group 22. The region corresponding to the dummy gate trench group 22 in the vertical direction is a dummy gate region 1014. Compared to the related art in which the second semiconductor device type region and the dummy gate region are separately provided, by having the first emitter layer 17 and the dummy gate trench group 22 vertically aligned, the area of ​​the dummy gate region 1014 can be fully utilized, eliminating the need to separately provide the second semiconductor device type region 1012. Therefore, while ensuring that the semiconductor device 100 has both forward and reverse conduction characteristics and the short-circuit capability of the semiconductor device 100, the dummy gate region 1014 can also be used as the second semiconductor device type region 1012. This can reduce the area of ​​the semiconductor device 100, improve the operating performance of the semiconductor device 100, and reduce the production cost of the semiconductor device 100.

[0201] Therefore, by making the first emitter layer 17 correspond to the dummy gate trench group 22 in the upper and lower directions, the dummy gate region 1014 can be fully utilized without having to separately set up the second semiconductor device type region 1012, so that the dummy gate region 1014 can also be used as the second semiconductor device type region 1012, thereby reducing the area of ​​the semiconductor device 100, improving the working performance of the semiconductor device 100, and reducing the production cost of the semiconductor device 100.

[0202] In some embodiments, as shown in conjunction with FIG. 16 to FIG. 18 , there are multiple first emitter layers 17 and multiple dummy gate trench groups 22, and the multiple first emitter layers 17 are disposed correspondingly to the multiple dummy gate trench groups 22. By disposing the first emitter layers 17 correspondingly to the multiple dummy gate trench groups 22, not only can the area of ​​the dummy gate region 1014 be fully utilized to reduce the area of ​​the semiconductor device 100, but the multiple first emitter layers 17 can also be more evenly distributed within the semiconductor device 100, thereby improving the operating performance of the semiconductor device 100.

[0203] In some embodiments, the first emitter layer 17 is extended in the first direction. Extending the first emitter layer 17 in the first direction facilitates placement of the first emitter layer 17 in the semiconductor device 100 while ensuring current specifications of the second semiconductor device type region 1012 . This simplifies the workflow of the second semiconductor device type region 1012 and even the semiconductor device 100 , thereby improving production efficiency.

[0204] In other embodiments, as shown in Figures 16 to 18 , the first emitter layer 17 includes a plurality of sub-emitter portions 131, which are spaced apart in the first direction. This allows for a more uniform and reasonable distribution of the plurality of sub-emitter portions 131 within the semiconductor device 100, thereby improving the operating performance of the second semiconductor device type region 1012 and, therefore, the semiconductor device 100.

[0205] It should be noted that the length and spacing of the multiple sub-emitter portions 131 in the first direction are related to the current specifications of the second semiconductor device type region 1012. The greater the rated current of the second semiconductor device type region 1012, the larger the total area of ​​the first emitter layer 17, that is, the longer the length of the sub-emitter portion 131, the smaller the spacing between two adjacent sub-emitter portions 131. When the spacing between two adjacent sub-emitter portions 131 is zero, the first emitter layer 17 is extended in the first direction. In actual production and manufacturing, the first emitter layer 17 can be selectively extended in the first direction, or the first emitter layer 17 can include multiple sub-emitter portions 131 spaced apart in the first direction, depending on the actual application scenario.

[0206] In some embodiments, as shown in conjunction with Figures 16 to 18 , the orthographic projection of the dummy gate trench group 22 on the lower surface of the drift layer 10 overlaps the orthographic projection of the first emitter layer 17 on the lower surface of the drift layer 10. The region to which the gate trench group 21 corresponds in the vertical direction is the gate region 1013. To ensure normal operation of the first semiconductor device type region 1011, the gate trench group 21 should correspond in the vertical direction to the collector layer 16, not the first emitter layer 17. That is, the collector layer 16 should be located in the gate region 1013, and the first emitter layer 17 should be located in the dummy gate region 1014.

[0207] By making the orthographic projection of the dummy gate trench group 22 on the lower surface of the drift layer 10 cover the orthographic projection of the first emitter layer 17 on the lower surface of the drift layer 10, it can be ensured that the first emitter layer 17 only corresponds to the dummy gate trench group 22 in the upper and lower directions, thereby preventing the first emitter layer 17 from entering the gate area 1013 and avoiding affecting the first semiconductor device type area 1011, thereby improving the working performance of the first semiconductor device type area 1011 and ensuring the normal operation of the semiconductor device 100.

[0208] In some embodiments, as shown in FIG17 , the length of the first emitter layer 17 in the first direction is less than the length of the dummy gate trench group 22 in the first direction. This prevents the first emitter layer 17 from protruding in the first direction beyond both ends of the dummy gate trench group 22 in the first direction, which would cause the first emitter layer 17 to enter the gate region 1013 in the first direction and affect the first semiconductor device type region 1011. This improves the operating performance of the first semiconductor device type region 1011 and ensures normal operation of the semiconductor device 100.

[0209] In some embodiments, as shown in FIG17 , the width of the first emitter layer 17 in the second direction is equal to the width of the dummy gate trench group 22 in the second direction. In this way, the area of ​​the dummy gate trench group 22 in the second direction can be fully utilized, thereby effectively utilizing the area of ​​the semiconductor device 100, improving the performance of the semiconductor device 100, and reducing the cost.

[0210] In other embodiments, the width of the first emitter layer 17 in the second direction is smaller than the width of the dummy gate trench group 22 in the second direction. In this way, the first emitter layer 17 can be prevented from protruding beyond the ends of the dummy gate trench group 22 in the second direction, and the first emitter layer 17 can be prevented from entering the gate region 1013 in the second direction and affecting the first semiconductor device type region 1011. This can improve the operating performance of the first semiconductor device type region 1011 and ensure normal operation of the semiconductor device 100.

[0211] In some embodiments, the dummy gate trench group 22 may include a dummy gate trench portion 221, the width of the first emitter layer 17 in the second direction is less than the width of a dummy gate trench portion 221 in the second direction, or the width of the first emitter layer 17 in the second direction is equal to the width of a dummy gate trench portion 221 in the second direction.

[0212] When the dummy gate trench group 22 includes a dummy gate trench portion 221, the dummy gate trench portion 221 is spaced apart from the gate trench group 21, and the width of the dummy gate trench group 22 in the second direction is equal to the width of one gate trench portion 211 in the second direction. In this case, the width of the first emitter layer 17 in the second direction can be set to be less than or equal to the width of one dummy gate trench portion 221 in the second direction. In this way, each first emitter layer 17 can be located in the dummy gate region 1014 corresponding to each dummy gate trench portion 221, preventing the first emitter layer 17 from entering the gate region 1013 in the second direction, thereby ensuring the performance of the second semiconductor device type region 1012 and the first semiconductor device type region 1011.

[0213] In other embodiments, as shown in Figure 17, the dummy gate trench group 22 includes at least two dummy gate trench portions 221 spaced apart in the second direction, the width of the first emitter layer 17 in the second direction is D1, the sum of the widths of the at least two dummy gate trench portions 221 in the second direction is D2, the sum of the spacing distances between the at least two dummy gate trench portions 221 in the second direction is D3, and D1, D2 and D3 satisfy the relationship: D1≤D2+D3.

[0214] When the dummy gate trench group 22 includes at least two dummy gate trench portions 221 spaced apart in the second direction, the at least two dummy gate trench portions 221 are spaced apart from the gate trench group 21. The width of the dummy gate trench group 22 in the second direction can be understood as the sum of the widths of the at least two dummy gate trench portions 221 in the second direction plus the sum of the spacing distances between the at least two dummy gate trench portions 221 in the second direction. In this case, the width of the first emitter layer 17 in the second direction can be set to be less than or equal to the sum of the sum of the widths of the at least two dummy gate trench portions 221 in the second direction plus the sum of the spacing distances between the at least two dummy gate trench portions 221 in the second direction. This ensures that each first emitter layer 17 falls within each dummy gate region 1014, preventing the first emitter layer 17 from entering the gate region 1013 in the second direction. This ensures the performance of the second semiconductor device type region 1012 and the first semiconductor device type region 1011, and ensures the normal operation of the semiconductor device 100.

[0215] The following describes a method for manufacturing the semiconductor device 100 using an RC-IGBT as an example with reference to FIG. 18 to FIG. 21 . The method includes the following steps:

[0216] In step 1, as shown in FIG19 , an N-substrate 2 material is provided as a drift layer 10 to form a structure 1.

[0217] In step 2, as shown in FIG20 , based on structure 1, a groove portion 2110 is etched, and an oxide insulating layer 70 and a polysilicon 71 are sequentially grown in the groove portion 2110 , and then the polysilicon 71 is etched to form structure 2.

[0218] In step 3, as shown in FIG21 , based on structure 2, a P well layer 11 is formed by implantation, an N+ second emitter layer 12 is implanted into the well layer 11 and annealed, and then a dielectric layer 13 is deposited on top to form structure 3.

[0219] In step 4, as shown in FIG22 , based on structure 3, the contact hole 171 is etched, and metal sputtering is performed to prepare the emitter metal layer 14 to form structure 4.

[0220] In step 5, as shown in FIG18 , based on structure 4, the N+ field stop layer 15 is implanted, the P+ collector layer 16 is implanted, the N+ first emitter layer 17 in the FRD region is implanted, laser annealing is performed, and metal sputtering is performed to prepare the collector metal layer 18, ultimately forming the semiconductor device 100. It should be noted that P+ indicates that the impurity concentration in the corresponding layer of the second conductivity type is heavily doped, and P- indicates that the impurity concentration in the corresponding layer of the first conductivity type is lightly doped; N- indicates that the impurity concentration in the corresponding layer of the first conductivity type is lightly doped, and N+ indicates that the impurity concentration in the corresponding layer of the first conductivity type is heavily doped.

[0221] The following describes a semiconductor device 100 in some embodiments of the present disclosure with reference to Figures 23 to 26. The semiconductor device 100 is, for example, a reverse-conducting insulated gate bipolar transistor (i.e., a reverse-conducting IGBT). In the following description, N and P represent the conductivity type of the semiconductor. In some embodiments of the present disclosure, the first conductivity type is N-type and the second conductivity type is P-type.

[0222] As shown in FIG23 , semiconductor device 100 includes a drift layer 10 of a first conductivity type, a well layer 11 of a second conductivity type, a field stop layer 15, and a collector layer 16 of a second conductivity type. The well layer 11 is disposed in a portion of the drift layer 10 corresponding to a transition region 102 of the semiconductor device 100, and the upper surface of the well layer 11 constitutes a portion of the upper surface of the drift layer 10. The field stop layer 15 is disposed on the lower surface of the drift layer 10, and the collector layer 16 is disposed on the lower surface of the field stop layer 15. In this way, the basic structure of a semiconductor structure is formed, ensuring the normal operation of the semiconductor device 100.

[0223] In some embodiments, an emitter layer 3 of the first conductivity type is disposed within the collector layer 16, and the emitter layer 3 is located in a portion of the collector layer 16 corresponding to the transition region 102. The collector layer 16 has the second conductivity type, and the emitter layer 3 in the collector layer 16 has the first conductivity type. Disposing the emitter layer 3 in the portion of the collector layer 16 corresponding to the transition region 102 allows the emitter layer 3 of the first conductivity type in the collector layer 16, the drift layer 10 of the first conductivity type, and the well layer 11 of the second conductivity type in the transition region 102 to form a reverse conducting structure in the semiconductor device 100, thereby achieving reverse conduction of the semiconductor device 100.

[0224] In the related art, the insulated gate bipolar transistor (IGBT) and fast recovery diode (FRD) in a reverse-conducting insulated gate bipolar transistor (IGBT) are integrated into the active region of a semiconductor device. When the semiconductor device is forward-conducting, driven by the gate voltage, the emitter layer of the first conductivity type in the IGBT device injects electrons into the drift region of the first conductivity type through the channel, and the collector region of the second conductivity type on the back of the semiconductor device injects holes upward, forming a conductive path from top to bottom. During reverse conduction, the integrated FRD device in the semiconductor device begins to operate. The well layer 11 of the second conductivity type on the front side acts as the anode of the fast recovery diode to inject holes into the drift region, and the emitter layer of the second conductivity type on the back side acts as the cathode to inject electrons into the drift region, thereby integrating the IGBT device and the FRD device in the same semiconductor device. However, the FRD device requires a portion of the active region of the semiconductor device. To achieve the on-state voltage drop of the IGBT, the area of ​​the active region of the semiconductor device needs to be increased, which increases the overall size of the semiconductor device. In addition, the increased area of ​​the active region of the semiconductor device leads to increased heat generation during operation of the IGBT, thereby reducing the reliability of the IGBT.

[0225] In some embodiments of the present disclosure, by setting the emitter layer 3 structure constituting the fast recovery diode 1 in the portion of the collector layer 16 corresponding to the transition region 102 in the semiconductor device 100, the fast recovery diode 1 can be set in the transition region 102, which not only can realize reverse conduction of the semiconductor device 100, but also can reduce the structure set in the active region 101 in the semiconductor device 100, so that the area of ​​the active region 101 can be used as much as possible to set the insulated gate bipolar transistor 9, thereby improving the area utilization of the active region 101 and enhancing the area effectiveness of the semiconductor device 100.

[0226] In addition, while ensuring that the theoretical performance of the insulated gate bipolar transistor 9 meets the requirements, the area of ​​the active region 101 of the semiconductor device 100 can be reduced, so that the heat generated by the insulated gate bipolar transistor 9 during operation is reduced, and the power consumption of the semiconductor device 100 is reduced, thereby reducing the overall area of ​​the semiconductor device 100 and improving the reliability of the semiconductor device 100.

[0227] Therefore, by setting the emitter layer 3 at the position of the collector layer 16 corresponding to the transition zone 102, not only can the semiconductor device 100 be reverse-conducted, but also the area utilization of the semiconductor device 100 can be improved, and the overall area of ​​the semiconductor device 100 can be prevented from increasing. Therefore, while achieving reverse conduction of the semiconductor device 100, the effective area of ​​the semiconductor device 100 can be increased and the size of the semiconductor device 100 can be reduced.

[0228] In some embodiments, as shown in FIG23 , the well layer 11 and the emitter layer 3 correspond to each other in the vertical direction. The well layer 11 of the second conductivity corresponds to the emitter layer 3 of the first conductivity in the vertical direction. A drift region of the first conductivity is provided between the well layer 11 and the emitter layer 3. The doping concentration of the well layer 11 and the emitter layer 3 are both greater than the doping concentration of the drift layer 10. Therefore, the structure of the portion of the semiconductor device 100 where the well layer 11 is located is, from top to bottom, the P+ well layer 11, the N- drift layer 10, and the N+ emitter layer 3. With this arrangement, the well layer 11, the drift region, and the emitter layer 3 can form a PIN junction in the fast recovery diode 1 structure, achieving a high withstand voltage, thereby facilitating reverse conduction in the semiconductor device 100.

[0229] In some embodiments, as shown in conjunction with FIG. 23 and FIG. 24 , the emitter layer 3 is circumferentially disposed within the transition region 102 . This arrangement can increase the area occupied by the emitter layer 3 within the transition region 102 and adjust the reverse conduction performance of the semiconductor device 100 . Thus, the transition region 102 occupies a larger and more concentrated proportion of the area of ​​the semiconductor device 100 , and the area where the emitter layer 3 can be disposed within the transition region 102 is larger. This increases the adjustability of the emitter layer 3 within the transition region 102 . By adjusting the position and area of ​​the emitter layer 3 within the transition region 102 , it is possible to avoid affecting the short-circuit performance of the semiconductor device 100 , thereby ensuring the reliability of the semiconductor device 100 .

[0230] In some embodiments, as shown in FIG. 24 , the termination region 103 of the semiconductor device 100 is circumferentially disposed outside the active region 101 of the semiconductor device 100, with the termination region 103 spaced apart from the active region 101. The transition region 102 is circumferentially disposed outside the active region 101 and located between the active region 101 and the termination region 103. The emitter layer 3 is circumferentially disposed outside the active region 101. Considering that the electric field strength in the termination region 103 of the semiconductor device 100 is relatively strong and the voltage per unit length is relatively high, voltage breakdown is likely to occur there. By providing the termination structure 7 in the termination region 103, the electric field distribution in the termination region 103 can be optimized, thereby improving the withstand voltage capability of the termination region 103. The circumferential arrangement of the termination region 103 outside the active region 101 of the semiconductor device 100 can ensure the withstand voltage reliability of the termination region 103 of the semiconductor device 100.

[0231] The termination region 103 and the active region 101 are spaced apart, allowing the transition region 102 to be disposed between the termination region 103 and the active region 101. The transition region 102 needs to connect the termination region 103 and the active region 101. Furthermore, for the insulated gate bipolar transistor 9 device, a gate electrical connection region is designed in the transition region 102. Therefore, the width of the transition region 102 is generally relatively wide, which facilitates the placement of the emitter layer 3 of the fast recovery diode 1. Furthermore, the well layer 11 on the transition region 102 is connected to the main junction, which ensures the voltage resistance of the transition region 102 and thus the reliability of the semiconductor device 100.

[0232] Furthermore, the transition region 102 is circumferentially disposed outside the active region 101, ensuring the reliability of the transition between the terminal region 103 and the active region 101, thereby ensuring the reliability of the semiconductor device 100. The emitter layer 3 is circumferentially disposed outside the active region 101 to form a fast recovery diode 1 structure within the transition region 102, thereby achieving reverse conduction of the semiconductor device 100. Compared to the active region 101, the transition region 102 provides a larger space for the emitter layer 3. This not only effectively utilizes the space in the active region 101, facilitating a reduction in the size of the semiconductor device 100, but also increases the adjustable space of the fast recovery diode 1 while ensuring the electrical performance of the semiconductor device 100.

[0233] In some embodiments, as shown in FIG23 and FIG24 , the emitter layer 3 is spaced apart from the active region 101. In this way, the fast recovery diode 1 and the insulated gate bipolar transistor 9 can be integrated into the semiconductor device 100 and spaced apart, thereby ensuring the forward voltage drop of the fast recovery diode 1 and the forward voltage drop of the insulated gate bipolar transistor 9, thereby improving the reliability of the semiconductor device 100.

[0234] In some embodiments, as shown in FIG. 23 , the emitter layer 3 is spaced apart from the termination region 103. A termination structure 7 is provided within the termination region 103. The termination structure 7 can improve the voltage resistance of the termination region 103 in the semiconductor device 100, thereby preventing voltage breakdown in the termination region 103 and improving the voltage resistance of the semiconductor device 100. Spaced apart from the emitter layer 3, the voltage resistance of the termination region 103 can be ensured, thereby ensuring the voltage resistance of the semiconductor device 100.

[0235] In other embodiments, as shown in conjunction with FIG. 23 and FIG. 25 , there are multiple emitter layers 3, and the multiple emitter layers 3 are spaced apart in the transition region 102. A single emitter layer 3 having a larger area can be split into multiple emitter layers 3 having smaller areas, and the multiple emitter layers 3 can be spaced apart in the transition region 102. The transition region 102 occupies a larger area in the semiconductor device 100, which can provide a larger adjustment space for the emitter layer 3, so that the multiple emitter layers 3 can be arranged according to the specifications of the fast recovery diode 1. In addition, by splitting a single emitter layer 3 having a larger area into multiple emitter layers 3 having smaller areas, a single fast recovery diode 1 having a larger area integrated in the semiconductor device 100 can be dispersed into multiple fast recovery diodes 1 having smaller areas. This can prevent current concentration in the fast recovery diode 1 in the semiconductor device 100, thereby affecting the short-circuit performance of the semiconductor device 100, thereby improving the reliability of the semiconductor device 100.

[0236] As shown in Figure 25, the terminal region 103 of the semiconductor device 100 is circumferentially arranged outside the active region 101 of the semiconductor device 100, and the terminal region 103 is spaced apart from the active region 101. The transition region 102 is circumferentially arranged outside the active region 101 and is located between the active region 101 and the terminal region 103. Multiple emitter layers 3 are circumferentially spaced apart in the transition region 102.

[0237] Considering that the electric field strength in the terminal region 103 of the semiconductor device 100 is relatively strong and the voltage per unit length is relatively large, it is relatively easy for voltage breakdown to occur there. By providing a terminal structure 7 in the terminal region 103, the electric field distribution in the terminal region 103 can be optimized and the voltage resistance of the terminal region 103 can be improved. The terminal region 103 is circumferentially arranged on the outside of the active region 101 of the semiconductor device 100, which can ensure the voltage resistance reliability of the terminal region 103 of the semiconductor device 100.

[0238] Furthermore, the termination region 103 and the active region 101 are spaced apart, allowing the transition region 102 to be disposed between the termination region 103 and the active region 101. The transition region 102 needs to connect the termination region 103 and the active region 101. Furthermore, for the insulated gate bipolar transistor 9, a gate electrical connection region is designed in the transition region 102. Therefore, the width of the transition region 102 is generally relatively wide, which facilitates the placement of the emitter layer 3 of the fast recovery diode 1. Furthermore, the well layer 11 on the transition region 102 is connected to the main junction, which ensures the voltage resistance of the transition region 102 and thus the reliability of the semiconductor device 100.

[0239] In addition, multiple emitter layers 3 are arranged at circumferential intervals in the transition region 102, and the fast recovery diodes 1 in the semiconductor device 100 can be dispersed in the transition region 102. This not only meets the specification setting requirements of the fast recovery diodes 1, but also prevents current concentration on the fast recovery diodes 1 from affecting the short-circuit performance of the semiconductor device 100, thereby ensuring the reliability of the semiconductor device 100.

[0240] In some embodiments, as shown in FIG25 , the emitter layer 3 is spaced apart from the active region 101. In this way, the fast recovery diode 1 and the insulated gate bipolar transistor 9 can be integrated into the semiconductor device 100 and spaced apart, thereby ensuring the forward voltage drop of the fast recovery diode 1 and the forward voltage drop of the insulated gate bipolar transistor 9, thereby ensuring the reliability of the semiconductor device 100.

[0241] In some embodiments, as shown in FIG. 25 , the emitter layer 3 is spaced apart from the termination region 103. A termination structure 7 is provided within the termination region 103. The termination structure 7 can improve the voltage resistance of the termination region 103 in the semiconductor device 100, thereby preventing voltage breakdown in the termination region 103 and improving the voltage resistance of the semiconductor device 100. Spaced apart from the emitter layer 3, the voltage resistance of the termination region 103 can be ensured, thereby ensuring the voltage resistance of the semiconductor device 100.

[0242] In some embodiments, the doping concentration of the emitter layer 3 is greater than the doping concentration of the drift layer 10. Electrons need to be injected into the portion of the collector layer 16 corresponding to the well layer 11 to form the emitter layer 3. The electron concentration of the emitter layer 3 needs to be greater than the doping concentration of the drift layer 10. This ensures that the emitter layer 3 has enough electrons for current injection, so that the emitter layer 3 outputs a sufficiently large current to ensure normal operation of the semiconductor device 100.

[0243] In some embodiments, as shown in conjunction with FIG. 23 and FIG. 26 , the transition region 102 is connected to the active region 101, a metal electrode is present above the transition region 102, and the metal electrode is connected to the emitter metal 6 (as shown in FIG. 29 ) disposed above the front surface of the active region 101, forming the basic structure of the semiconductor structure and ensuring the normal operation of the semiconductor device 100. The emitter layer 3 is disposed below the well layer 11, which not only forms the fast recovery diode 1 but also ensures the normal electrical performance of the semiconductor device 100, avoiding affecting the withstand voltage and reliability of the semiconductor device 100.

[0244] In some embodiments, the transition region 102 includes a gate bus 84 region, where the metal is not connected to the emitter metal 6 of the active region 101. However, due to the relatively small area of ​​the transition region 102 occupied by the gate bus 84 region and the inherent characteristics of the semiconductor device 100, the carrier path does not completely correspond to the location of the metal electrodes in the semiconductor device 100. Therefore, even if the emitter layer 3 on the back side of the semiconductor device 100 partially aligns with the gate bus 84, reverse conduction can still be achieved in the semiconductor device 100. Simulation experiments have confirmed the feasibility of achieving reverse conduction in the semiconductor device 100 when the emitter layer 3 on the back side of the semiconductor device 100 partially aligns with the gate bus 84. Figure 27 shows the simulation results of the on-state voltage drop of the fast recovery diode 1 in the semiconductor device 100 when the emitter layer 3 on the back side of the semiconductor device 100 partially aligns with the gate bus 84.

[0245] The following describes a semiconductor device 100 in some embodiments of the present disclosure with reference to Figures 28 to 47. The semiconductor device 100 is, for example, a reverse-conducting insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In some embodiments of the present disclosure, the first conductivity type is N-type and the second conductivity type is P-type.

[0246] As shown in Figures 28 to 35 , semiconductor device 100 includes: a drift layer 10 of a first conductivity type, a well layer 11 of a second conductivity type, a dielectric layer 13, a gate pad 104, a field stop layer 15, and a collector layer 16 of a second conductivity type. The drift layer 10 of a first conductivity type, the well layer 11 of a second conductivity type, the dielectric layer 13, the gate pad 104, the field stop layer 15, and the collector layer 16 of a second conductivity type are arranged in semiconductor device 100. Furthermore, the field stop layer 15 is arranged on the lower surface of the drift layer 10, the collector layer 16 is arranged on the lower surface of the field stop layer 15, and the gate pad 104 is arranged on the upper surface of the drift layer 10. This forms the basic structure of a semiconductor structure and ensures the normal operation of semiconductor device 100.

[0247] In some embodiments, the well layer 11 is disposed on the drift layer 10, and its upper surface constitutes at least a portion of the upper surface of the drift layer 10. The well layer 11 of the second conductivity type can serve as a main junction to optimize the terminal electric field distribution, thereby improving the withstand voltage of the semiconductor device 100. Furthermore, the well layer 11 is at least partially disposed on the upper surface of the drift layer 10 and is located below the gate pad 104. It can correspond to the emitter layer 3 in the fast recovery diode 1 to form a current flow path for the fast recovery diode 1.

[0248] In some embodiments, dielectric layer 13 is disposed on the upper surface of well layer 11 to prevent well layer 11 from contacting and forming an electrical connection with gate pad 104, thereby ensuring the reliability of semiconductor device 100. Furthermore, gate pad 104 is disposed on the upper surface of dielectric layer 13, field stop layer 15 is disposed on the lower surface of drift layer 10, and collector layer 16 is disposed on the lower surface of drift layer 10. This forms the basic structure of a semiconductor structure and ensures the normal operation of semiconductor device 100.

[0249] In some embodiments, at least a portion of the collector layer 16 is provided with an emitter layer 3. The collector layer 16 is located in the insulated gate bipolar transistor region 1015 (as shown in FIG87 ) of the semiconductor device 100. The emitter layer 3 is located in the fast recovery diode region 1018 (as shown in FIG88 ) of the semiconductor device 100. The emitter layer 3 corresponds to the gate pad 104 above and below. The collector layer 16 has the second conductivity type, and the emitter layer 3 in the collector layer 16 has the first conductivity type. The emitter layer 3 is provided partially below the collector layer 16 corresponding to the gate pad 104. The emitter layer 3 can form a PN junction with the portion of the well layer 11 corresponding to the portion below the gate pad 104. The well layer 11 corresponding to the portion above the emitter layer 3 can serve as the collector of the fast recovery diode 1. In this way, a fast recovery diode 1 can be formed in the region of the semiconductor device 100 corresponding to the gate pad 104, thereby achieving reverse conduction of the semiconductor device 100.

[0250] In related art, the insulated gate bipolar transistor (IGBT) and fast recovery diode (FRD) in a reverse-conducting insulated gate bipolar transistor (IGBT) are integrated into the active region of a semiconductor device. When the semiconductor device is forward-conducting, driven by a gate voltage, the emitter layer of the first conductivity type in the IGBT device injects electrons into the drift region of the first conductivity type through the channel, while the collector region of the second conductivity type on the back of the semiconductor device injects holes upward, forming a conductive path from top to bottom. During reverse conduction, the integrated FRD region in the semiconductor device begins to operate. The well layer of the second conductivity type on the front side acts as the anode of the FRD to inject holes into the drift region, while the emitter layer of the second conductivity type on the back side acts as the cathode to inject electrons into the drift region, thereby integrating the IGBT region and the FRD region within the same semiconductor device. However, the FRD region requires a portion of the active region of the semiconductor device. Assuming the proportion of the effective gate trench in the IGBT region remains unchanged, the saturation current of the IGBT decreases, requiring the area of ​​the active region of the semiconductor device to be supplemented, which increases the overall size of the semiconductor device. In addition, the increase in the area of ​​the active region of the semiconductor device may lead to an increase in the heat generated during operation of the IGBT, thereby reducing the reliability of the IGBT.

[0251] In some embodiments of the present disclosure, by disposing the emitter layer 3 constituting the fast recovery diode 1 in the portion of the collector layer 16 corresponding to the gate pad 104 in the semiconductor device 100, the fast recovery diode 1 can be disposed in the pad region 19. This not only enables reverse conduction of the semiconductor device 100, but also reduces the number of structures disposed in the active region 101 of the semiconductor device 100, thereby reducing the area of ​​the active region 101 of the semiconductor device 100, thereby improving the integration of the semiconductor device 100. It should be noted that a second contact hole 1102 can be provided on the upper surface of the gate pad 104, thereby optimizing the heat distribution on the gate metal 1021.

[0252] This arrangement allows more semiconductor devices 100 to be produced on wafers of the same size, thereby improving wafer utilization and reducing the production cost of the semiconductor devices 100. Taking a current-spec semiconductor device 100 as an example, by integrating the fast recovery diode 1 below the gate pad 104, approximately 27% of the area can be saved. Taking a 1.5-inch wafer as an example, the number of semiconductor devices 100 that can be produced on each wafer increases from 100 to 100, greatly improving the production efficiency and wafer utilization of the semiconductor devices 100, thereby reducing the production cost of the semiconductor devices 100.

[0253] Furthermore, while ensuring that the theoretical performance of the insulated gate bipolar transistor 9 meets the requirements, the area of ​​the active region 101 of the semiconductor device 100 is reduced, thereby reducing the overall area of ​​the semiconductor device 100. This can reduce the heat generated by the insulated gate bipolar transistor 9 during operation, thereby reducing the power consumption of the semiconductor device 100 and improving the reliability of the semiconductor device 100. The emitter layer 3 is disposed below the gate pad 104 of the semiconductor device 100. The emitter layer 3 and the well layer 11 below the gate pad 104 can form a PN junction. The corresponding well layer 11 above the emitter layer 3 can serve as the collector of the fast recovery diode 1, thereby forming a fast recovery diode 1. Above the drift layer 10, except for the portion of the well layer 11 corresponding to the portion below the gate pad 104, which can serve as the collector of the fast recovery diode 1, the remaining portion of the well layer 11 serves as the main junction to optimize the terminal electric field distribution. This arrangement not only ensures that the withstand voltage capability of the semiconductor device 100 is not affected, but also integrates the well layer 11 into the fast recovery diode region 1018, thereby improving the chip's integration density, reducing the overall chip area, and thus reducing costs.

[0254] Therefore, by setting the emitter layer 3 below the collector layer 16 corresponding to the gate pad 104, not only can the semiconductor device 100 be reverse-conducted, but the integration of the semiconductor device 100 can also be improved. Therefore, while achieving reverse conduction of the semiconductor device 100, the saturation current of the insulated gate bipolar transistor 9 can be guaranteed without increasing the area of ​​the active region 101. Compared with the reverse-conducting insulated gate bipolar transistor 9 of the same specification, the semiconductor device 100 disclosed in the present invention has an advantage in area size.

[0255] In some embodiments, as shown in FIG29 and FIG30 , the width of the well layer 11 in the first direction is W1, and the width of the emitter layer 3 in the first direction is W2, where W1 and W2 satisfy the relationship: W1>W2. By setting the width of the well layer 11 in the first direction to be greater than the width of the emitter layer 3 in the first direction, the reliability of the reverse flow of current in the fast recovery diode 1 can be ensured, thereby ensuring the reliability of the reverse conduction of the semiconductor device 100.

[0256] In other embodiments, the width of the well layer 11 in the first direction is equal to the width of the emitter layer 3 in the first direction. This can also achieve reverse conduction of the semiconductor device 100. It should be noted that the width of the emitter layer 3 in the fast recovery diode region 1018 in the semiconductor device 100 in the first direction needs to be set according to the specifications of the fast recovery diode 1 in the reverse conducting insulated gate bipolar transistor 9.

[0257] In some embodiments, as shown in FIG30 , the emitter layer 3 has a vertical cross-section that is continuous and strip-shaped in the first direction. In this case, the width of the well layer 11 in the first direction is sufficient to allow the emitter layer 3 of the fast recovery diode 1 to be disposed in the portion of the collector layer 16 corresponding to the gate pad 104, thereby providing a sufficiently large space for the emitter layer 3 to be disposed, so that the fast recovery diode 1 meets the actual requirements and design goals of the semiconductor device 100.

[0258] In other embodiments, as shown in FIG31 , the cross-section of the emitter layer 3 in the vertical direction includes multiple emitter portions 501, the multiple emitter portions 501 are spaced apart in the first direction, and the sum of the widths of the multiple emitter portions 501 in the first direction is W. The emitter layer 3 of the fast recovery diode 1 in the semiconductor device 100 may also be composed of multiple emitter portions 501. The width of the well layer 11 in the first direction is sufficient to accommodate the portion of the emitter layer 3 of the fast recovery diode 1 corresponding to the gate pad 104 on the collector layer 16, thereby providing a sufficiently large installation space for the emitter layer 3, so that the fast recovery diode 1 meets the actual needs and design objectives of the semiconductor device 100. It should be noted that the sum of the widths of the cross-sections of the multiple emitter portions 501 in the first direction in the vertical direction is less than or equal to the width of the well layer 11 in the first direction, to ensure that the multiple emitter portions 501 correspond to the well layer 11 in the vertical direction.

[0259] In some embodiments, the widths of the multiple emitters 501 in the first direction are all the same. This not only ensures that the fast recovery diode 1 meets the actual requirements and design goals of the semiconductor device 100, but also simplifies the manufacturing process of the fast recovery diode 1, thereby improving the production convenience of the semiconductor device 100. In other embodiments, the widths of the multiple emitters 501 in the first direction may also be different. Such an arrangement can improve the convenience of disposing the emitter layer 3, which is of great significance for insulated gate bipolar transistors operating at high frequencies.

[0260] In some embodiments, when viewed from above, the emitter layer 3 is at least one of a square, a rounded rectangle, a circle, a small ellipse, and a hexagon. This allows the emitter layer 3 in the fast recovery diode 1 to be configured into different shapes based on the actual needs and design objectives of the semiconductor device 100, thereby adapting to semiconductor devices 100 of different specifications and improving the reliability of the semiconductor device 100. It should be noted that the top-down perspective is a perspective perpendicular to the first and second directions.

[0261] In other embodiments, when viewed from above, the emitter layer 3 is formed by a combination of at least two of a plurality of small squares, small circles, small ovals, and small rounded rectangles. In this way, the emitter layer 3 in the fast recovery diode 1 can be configured into different shapes and sizes according to the actual needs and design objectives of the semiconductor device 100, thereby being suitable for semiconductor devices 100 of different specifications, thereby improving the reliability of the semiconductor device 100.

[0262] In some other embodiments, when viewed from above, the emitter layer 3 is at least one of a square, a rounded rectangle, and a circle, or is a combination of at least two of a plurality of small squares, small circles, small ovals, and small rounded rectangles. In this way, the emitter layer 3 in the fast recovery diode 1 can be configured into different shapes and sizes based on the actual needs and design objectives of the semiconductor device 100, thereby being suitable for semiconductor devices 100 of different specifications, thereby improving the reliability of the semiconductor device 100.

[0263] In some embodiments, as shown in conjunction with FIG. 30 and FIG. 31 , the drift layer 10 is provided with a plurality of trench portions 2110 spaced apart in a first direction in a portion corresponding to the active region 101 of the semiconductor device 100. The distance between two adjacent trench portions 2110 in the first direction is L2. A distance W3 between one of the plurality of trench portions 2110 adjacent to the well layer 11 and the well layer 11 in the first direction is W3, where W3 and L2 satisfy the relationship: W3 ≥ L2. The trench portions 2110 are used to form the gate of the semiconductor device 100, and there are a plurality of trench portions 2110. It should be noted that the number of trench portions 2110 can be set according to the specifications of the semiconductor device 100, and the plurality of trench portions 2110 spaced apart along the first direction can ensure the independence of the plurality of trench portions 2110, thereby ensuring the reliability of the semiconductor device 100.

[0264] In some embodiments of the present disclosure, the area of ​​the active region 101 of the semiconductor device 100 is only used to set up the insulated gate bipolar transistor. This can reduce the area of ​​the active region 101, increase the density of the effective trench, and further increase the current density of the insulated gate bipolar transistor, thereby reducing the on-state voltage drop of the semiconductor device 100, which is beneficial to reducing the switching loss of the semiconductor device 100.

[0265] Moreover, by setting the spacing distance between two adjacent groove portions 2110 in the first direction to be less than or equal to the distance from one of the multiple groove portions 2110 adjacent to the well layer 11 to the well layer 11 in the first direction, a setting space can be provided for the transition region 102 in the semiconductor device 100, so that the transition region 102 transitions to the active region 101 and the terminal region 103 of the semiconductor device 100, thereby ensuring the reliability of the semiconductor device 100.

[0266] In some embodiments, as shown in FIG. 28 and FIG. 32 , the drift layer 10 is provided with a groove portion 2110. The groove portion 2110 extends in the second direction. There are multiple groove portions 2110, and the multiple groove portions 2110 are spaced apart in the first direction. This can meet the structural configuration of semiconductor devices 100 of different specifications, and can make the fast recovery diode 1 meet the actual needs and design goals of the semiconductor device 100.

[0267] In other embodiments, as shown in FIG33 and FIG34 , the groove portion 2110 extends in the first direction, and there are multiple groove portions 2110, which are spaced apart in the second direction. In this way, the structure of semiconductor devices 100 of different specifications can be satisfied, and the fast recovery diode 1 can meet the actual needs and design goals of the semiconductor device 100.

[0268] In some embodiments, as shown in conjunction with FIG. 28 and FIG. 33 , gate pad 104 is located on one side of drift layer 10 in the second direction, and gate pad 104 is symmetrically arranged about a centerline extending in the second direction of drift layer 10. In this way, while ensuring the structural and functional reliability of semiconductor device 100, the structure of semiconductor devices 100 of different specifications can be accommodated, and the fast recovery diode 1 can be freely arranged at a position corresponding to gate pad 104 in semiconductor device 100, thereby ensuring that the arrangement of fast recovery diode 1 meets the actual needs and design objectives of semiconductor device 100.

[0269] In other embodiments, as shown in Figures 32 and 34, the gate pad 104 is located on one side of the drift layer 10 in the second direction, and the gate pad 104 is located at one end of the drift layer 10 in the first direction. Such a configuration can save the area of ​​the semiconductor device 100 while ensuring the structural reliability and functional reliability of the semiconductor device 100. This can meet the structural settings of semiconductor devices 100 of different specifications, and can allow the fast recovery diode 1 to be freely set at the position corresponding to the gate pad 104 in the semiconductor device 100, so that the configuration of the fast recovery diode 1 can meet the actual needs and design goals of the semiconductor device 100.

[0270] In some embodiments, as shown in conjunction with Figures 29, 35, and 38, an emitter metal 6 is further provided on the upper surface of the dielectric layer 13. A first contact hole 1101 is provided on the dielectric layer 13. At least a portion of the emitter metal 6 passes through the first contact hole 1101 and contacts the well layer 11. The emitter metal 6 on the upper surface of the dielectric layer 13 can serve as the emitter of the insulated gate bipolar transistor region 1015, forming the basic structure of the insulated gate bipolar transistor region 1015 in the semiconductor, ensuring the normal operation of the semiconductor device 100. The first contact hole 1101 is formed on the dielectric layer 13 by etching, and the first contact hole 1101 can be used to electrically connect the emitter metal 6 and the well layer 11. When depositing metal to form the emitter metal 6, at least a portion of the emitter metal 6 penetrates the first contact hole 1101 for electrical connection to the well layer 11, thereby enabling electrical conduction of the fast recovery diode 1 in the semiconductor device 100. At this time, the emitter layer 3 in the fast recovery diode region 1018 forms a PN junction with the corresponding portion of the well layer 11 below the gate pad 104. This portion of the well layer 11 can serve as the collector in the fast recovery diode 1.

[0271] In some embodiments, the first contact hole 1101 is in the shape of a continuous long strip, which can facilitate the contact between the emitter metal 6 and the polysilicon field plate 8 (as shown in Figure 43) to form an electrical connection, and can increase the contact area between the emitter metal 6 and the polysilicon field plate 8, thereby ensuring the circuit reliability of the semiconductor device 100.

[0272] In other embodiments, as shown in FIG36 , the first contact holes 1101 are rectangular and multiple, and the multiple first contact holes 1101 are spaced apart in the first direction. In this way, the emitter metal 6 can be electrically connected to the polysilicon field plate 8 at multiple spaced locations in the first direction, suitable for electrically conducting fast recovery diodes 1 of different specifications and sizes, thereby ensuring the reliability of the semiconductor device 100.

[0273] In some embodiments, as shown in conjunction with Figures 29, 35, 36, and 37, the trench portion 2110 includes a gate trench portion 211 and a dummy gate trench portion 221, with at least one dummy gate trench portion 221 disposed between two adjacent gate trench portions 211. This not only ensures the structural reliability of the insulated gate bipolar transistor region in the semiconductor device 100, but also controls the short-circuit performance of the semiconductor device 100, thereby ensuring the reliability of the semiconductor device 100. The first contact hole 1101 is located between two adjacent gate trench portions 211 and is spaced apart from the dummy gate trench portion 221 in the second direction; and / or, the first contact hole 1101 is spaced apart from the gate trench portion 211 in the second direction.

[0274] In some examples, as shown in FIG37 , the first contact hole 1101 is located between two adjacent gate trench portions 211 and is spaced apart from the dummy gate trench portion 221 in the second direction. In other examples, the first contact hole 1101 is spaced apart from the gate trench portion 211 in the first direction. In still other examples, at least a portion of the first contact hole 1101 is located between two adjacent gate trench portions 211 and is spaced apart from the dummy gate trench portion 221 in the second direction, and at least a portion of the first contact hole 1101 is spaced apart from the gate trench portion 211 in the first direction. With such a configuration, the first contact hole 1101 can be freely arranged on the semiconductor device 100 to meet the structural configuration of semiconductor devices 100 of different specifications, and the fast recovery diode 1 can be made to meet the actual needs and design goals of the semiconductor device 100.

[0275] As shown in Figures 35 and 36 , the structure of the insulated gate bipolar transistor region in the semiconductor device 100 further includes: an emitter region 105 of the first conductivity type, a base region 106 of the second conductivity type, a carrier storage layer 110 (as shown in Figure 65 ), a collector metal layer 18, a gate, an active region 101, a transition region 102, a pad region 19, and a termination region 103. The termination region 103 includes structures such as a field stop ring 1302, a field limiting ring 1303, a metal field plate 90, and a polysilicon field plate 8. These structures are sequentially arranged on the termination region 103 at a predetermined distance to improve the withstand voltage capability of the insulated gate bipolar transistor and ensure the stability of the semiconductor device 100.

[0276] In some embodiments, the pad region 19 includes a gate metal 1021, which is used to connect to external wires and serves as the focal point of a gate runner 1022 to control the gate of the insulated gate bipolar transistor. A dummy gate trench 221 may or may not be provided in the transition region 102, and no first conductivity type emitter region 105 or second conductivity type contact layer is provided in the transition region 102.

[0277] With reference to FIG. 39 to FIG. 47 , a method for manufacturing a semiconductor device 100 in some embodiments of the present disclosure is described below. The method includes the following steps:

[0278] Step 1: Provide a semiconductor substrate of the first conductivity type, which is structure 1.

[0279] Step 2: Based on the structure 1, after taking corresponding protection measures, a well layer 11 of the second conductivity type is implanted into the terminal region 103 to form the structure 2.

[0280] Step 3: Based on the structure 2, a field oxide layer 1301 is grown to obtain the structure 3.

[0281] Step 4: Based on the structure three, the groove portion 2110 is etched, and processes such as rounding of the groove portion 2110 and growth of the gate oxide layer are completed to obtain the structure four.

[0282] Step 5: Based on structure 4, polysilicon 71 is grown to obtain structure 5.

[0283] Step 6: Based on the structure five, the emitter region 105 of the first conductivity type, the carrier storage layer 110 , the contact layer of the second conductivity type and other structures are implanted to obtain the structure six.

[0284] Step 7: On the basis of structure 6, a dielectric layer 13 is grown to obtain structure 7.

[0285] Step 8: Based on the structure 7, the dielectric layer 13 is etched to obtain the structure 8.

[0286] Step 9: On the basis of structure eight, emitter metal 6 is deposited to obtain structure nine.

[0287] Step 10: Based on the structure nine, a field stop layer 15 and a collector layer 16 of the second conductivity type are formed on the back surface of the semiconductor device 100 to obtain the structure ten.

[0288] Step 11: Based on the structure 10, an emitter layer 3 of the first conductivity type is formed in the region of the collector layer 16 corresponding to the gate pad 104 to form the structure 11.

[0289] Step 12: Based on the structure 11, a collector metal layer 18 is deposited on the back side of the semiconductor device 100 to finally form the structure of an insulated gate bipolar transistor device.

[0290] The following describes a semiconductor device 100 in some embodiments of the present disclosure with reference to Figures 48 to 57. The semiconductor device 100 may employ a method for manufacturing the semiconductor device 100. The semiconductor device 100 may be an RC-IGBT, the first semiconductor device type region 1011 may be an IGBT region, and the second semiconductor device type region 1012 may be an FRD region. In the following description, N and P represent the conductivity type of the semiconductor. In some embodiments of the present disclosure, the first conductivity type is N-type and the second conductivity type is P-type.

[0291] 48 and 49 , the semiconductor device 100 includes: a drift layer 10 of a first conductive type, a field stop layer 15 of a first conductive type, a collector layer 16 of a second conductive type, a first emitter layer 17 of a first conductive type, a ring layer 107 of a second conductive type, and a well layer 11 of a second conductive type.

[0292] In some embodiments, a ring layer 107 of the second conductivity type and a well layer 11 of the second conductivity type are provided in a drift layer 10 of the first conductivity type. The upper surface of the ring layer 107 constitutes at least a portion of the upper surface of the drift layer 10, and the upper surface of the well layer 11 constitutes at least a portion of the upper surface of the drift layer 10. The upper surface of the drift layer 10 of the first conductivity type is provided with the well layer 11 of the second conductivity type, a first emitter layer 17 of the first conductivity type located in the well layer 11, a dielectric layer 13 located above the first emitter layer 17, and an emitter metal layer 14 located above the dielectric layer 13. The lower surface of the drift layer 10 of the first conductivity type is provided with a field stop layer 15 of the first conductivity type, a collector layer 16 of the second conductivity type located on the lower surface of the field stop layer 15, a first emitter layer 17 of the first conductivity type, and a collector metal layer 18 located at the bottom.

[0293] In some embodiments, the semiconductor device 100 includes an active area 101 and a terminal area 103 surrounding the outside of the active area 101. The collector layer 16 is circumferentially arranged on the outside of the first emitter layer 17. The area corresponding to the collector layer 16 in the up and down directions is the first semiconductor device type area 1011, and the area corresponding to the first emitter layer 17 in the up and down directions is the second semiconductor device type area 1012. That is, the active area 101 of the semiconductor device 100 can include the first semiconductor device type area 1011 and the second semiconductor device type area 1012. The emitter metal layer 14 can not only serve as the first semiconductor device type area 1011, but also as the second semiconductor device type area 1012. The emitter terminal of a semiconductor device type region 1011 can also serve as the anode terminal of a second semiconductor device type region 1012. The collector metal layer 18 can not only serve as the collector terminal of the first semiconductor device type region 1011, but also serve as the cathode terminal of the second semiconductor device type region 1012. In this way, the first semiconductor device type region 1011 can realize forward conduction of the semiconductor device 100, and the second semiconductor device type region 1012 can realize reverse conduction of the semiconductor device 100, so that the semiconductor device 100 has both forward conduction and reverse conduction characteristics.

[0294] As shown in Figure 49, the ring layer 107 corresponds to the junction of the collector layer 16 and the first emitter layer 17, and a plurality of groove portions 2110 are provided in the ring layer 107. The well layer 11 is provided on both sides of the ring layer 107 and at least partially corresponds to the collector layer 16 and the first emitter layer 17. A plurality of groove portions 2110 are provided in the portion of the well layer 11 corresponding to the collector layer 16.

[0295] Here, the ring layer 107 corresponds to the junction of the collector layer 16 and the first emitter layer 17, that is, the ring layer 107 is provided at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012, and the well layer 11 is provided on both sides of the ring layer 107, and the well layer 11 at least partially corresponds to the collector layer 16 and the first emitter layer 17, that is, the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are both provided with the well layer 11.

[0296] By setting a plurality of groove portions 2110 in the ring layer 107 and setting a plurality of groove portions 2110 in the portion of the well layer 11 corresponding to the collector layer 16, that is, a groove portion 2110 is set in the first semiconductor device type region 1011, and a groove portion 2110 is not set in the second semiconductor device type region 1012. In this way, on the one hand, the oxide insulation layer 70 and the polysilicon 71 can be deposited in sequence in the groove portion 2110, and a gate is formed at the groove portion 2110 to ensure the normal operation of the first semiconductor device type region 1011. On the other hand, the groove portion 2110 at the second semiconductor device type region 1012 can be eliminated, so that the second semiconductor device type region 1012 is only a planar PN junction, thereby effectively increasing the effective area of ​​the PN junction and reducing the forward conduction voltage drop of the second semiconductor device type region 1012. In this way, the working performance of the semiconductor device 100 can be improved.

[0297] In some embodiments, because the trench portion 2110 is omitted from the second semiconductor device type region 1012, the width of the second semiconductor type dopant required to be implanted in the first semiconductor device type region 1011 is significantly greater than the width of the second semiconductor type dopant required to be implanted in the second semiconductor device type region 1012. If the same implantation dose and annealing conditions are used, the junction depth and doping concentration at the interface between the first semiconductor device type region 1011 and the second semiconductor device type region 1012 will be less than the junction depth and doping concentration of the first semiconductor device type region 1011, resulting in voltage withstand issues for the semiconductor device 100. By separately providing the ring layer 107 and the well layer 11, the junction depth and doping concentration at the interface between the first semiconductor device type region 1011 and the second semiconductor device type region 1012 can be increased, ensuring that the junction depth and doping concentration of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same, ensuring that the voltage withstand capabilities of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same, and thus ensuring the voltage withstand capability of the semiconductor device 100.

[0298] Therefore, by making the ring layer 107 correspond to the junction of the collector layer 16 and the first emitter layer 17, a plurality of groove portions 2110 are provided in the ring layer 107, and the well layer 11 is provided on both sides of the ring layer 107 and at least partially corresponds to the collector layer 16 and the first emitter layer 17. A plurality of groove portions 2110 are provided in the portion of the well layer 11 corresponding to the collector layer 16. In this way, while ensuring the voltage resistance of the semiconductor device 100, the on-state voltage drop of the second semiconductor device type region 1012 can be improved, thereby improving the working performance of the semiconductor device 100.

[0299] In some embodiments, as shown in FIG49 , the depth of the well layer 11 in the vertical direction is less than the depth of the ring layer 107. By setting the depth of the well layer 11 in the vertical direction to be less than the depth of the ring layer 107 in the vertical direction, the junction depth and doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 can be ensured to be the same as the junction depth and doping concentration of the first semiconductor device type region 1011, thereby ensuring the voltage withstand capability of the second semiconductor device type region 1012 and, therefore, the semiconductor device 100.

[0300] In some embodiments, as shown in FIG49 , the vertical depth of the trench portion 2110 is greater than the vertical depth of the well layer 11, and the vertical depth of the trench portion 2110 is less than the vertical depth of the ring layer 107. In this way, the trench portion 2110 in the first semiconductor device type region 1011 located in the well layer 11 can penetrate the well layer 11 and reach the drift layer 10, thereby ensuring normal operation of the first semiconductor device 100.

[0301] By setting the depth of the groove portion 2110 in the vertical direction to be smaller than the depth of the ring layer 107 in the vertical direction, the ring layer 107 can surround the groove portion 2110 located at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012, thereby ensuring that the junction depth and doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same as the junction depth and doping concentration of the first semiconductor device type region 1011, ensuring that the withstand voltages of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same, and ensuring the working performance of the semiconductor device 100.

[0302] In some embodiments, as shown in FIG49 , the cross-section of the ring layer 107 in the vertical direction is arc-shaped, and the cross-section of the well layer 11 in the vertical direction is rectangular. By making the cross-section of the well layer 11 in the vertical direction rectangular, and the lower surface of the well layer 11 parallel to the upper surface of the drift layer 10, the well layer 11 in the second semiconductor device type region 1012 can be evenly distributed and have the same depth as the first semiconductor device type region 1011. This can ensure the operating performance of the second semiconductor device type region 1012 and ensure that the junction depth and doping concentration in the middle of the first semiconductor device type region 1011 and the middle of the second semiconductor device type region 1012 in the first direction are the same.

[0303] Furthermore, by forming an arc-shaped cross-section of the ring layer 107 in the vertical direction and an arc-shaped bottom surface of the ring layer 107, the ring layer 107 can surround the groove portion 2110 located at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012, thereby ensuring that the junction depth and doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same as the junction depth and doping concentration of the first semiconductor device type region 1011. In this way, the withstand voltages of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 can be made the same, thereby ensuring the withstand voltage capability of the semiconductor device 100 and the operating performance of the semiconductor device 100.

[0304] In some embodiments, as shown in Figure 49, a second emitter layer 12 is provided on both sides of the groove portion 2110, a dielectric layer 13 is provided on the upper surfaces of the ring layer 107 and the well layer 11, a first contact hole 1101 is opened in the dielectric layer 13 between the two adjacent groove portions 2110, a second contact hole 1102 is opened in the portion of the dielectric layer 13 corresponding to the first emitter layer 17, an emitter metal layer 14 is provided on the upper surface of the dielectric layer 13, at least a portion of the emitter metal layer 14 passes through the first contact hole 1101 and is electrically connected to the second emitter layer 12, at least a portion of the emitter metal layer 14 passes through the second contact hole 1102 and is electrically connected to the portion of the well layer 11 located in the middle of the ring layer 107, a plurality of groove portions 2110 are spaced apart in the first direction, and the length of the second contact hole 1102 in the first direction is greater than the length of the first contact hole 1101 in the first direction.

[0305] By providing a dielectric layer 13 on the upper surfaces of the ring layer 107 and the well layer 11, the dielectric layer 13 can protect the well layer 11, thereby reducing the risk of damage to the semiconductor device 100. Furthermore, by providing a second emitter layer 12 on both sides of the groove portion 2110, and defining a first contact hole 1101 between two adjacent groove portions 2110 in the dielectric layer 13, at least a portion of the emitter metal layer 14 can pass through the first contact hole 1101 and be electrically connected to the second emitter layer 12, thereby ensuring the normal operation of the first semiconductor device type region 1011.

[0306] In addition, by opening a second contact hole 1102 in the portion of the dielectric layer 13 corresponding to the first emitter layer 17, the length of the second contact hole 1102 in the first direction is made greater than the length of the first contact hole 1101 in the first direction, and the second contact hole 1102 directly corresponds to the second semiconductor device type region 1012. This is different from setting multiple first contact holes 1101 in the first semiconductor device type region 1011, and only setting one second contact hole 1102 in the second semiconductor device type region 1012. At least a portion of the emitter metal layer 14 passes through the second contact hole 1102 and is electrically connected to the portion of the well layer 11 located in the middle of the ring layer 107, that is, the emitter metal layer 14 is in contact with the well layer 11 of the second semiconductor device type region 1012, thereby ensuring the normal operation of the second semiconductor device type region 1012.

[0307] In some embodiments, as shown in FIG49 , a barrier metal layer 108 is provided on the surface of the dielectric layer 13. The barrier metal layer 108 is located between the dielectric layer 13 and the emitter metal layer 14. A third contact hole 341 is formed in the portion of the barrier metal layer 108 corresponding to the second contact hole 1102. The third contact hole 341 and the second contact hole 1102 are formed through at least a portion of the emitter metal layer 14. The barrier metal layer 108 is electrically connected to the portion of the well layer 11 located in the middle of the ring layer 107.

[0308] Considering that the width of the first contact hole 1101 on the dielectric layer 13 is relatively small, in order to facilitate the setting of the emitter metal layer 14 and ensure the contact between the emitter metal layer 14 and the second emitter layer 12, a barrier metal layer 108 can be set on the surface of the dielectric layer 13, and then the emitter metal layer 14 is deposited. In this way, the barrier metal layer 108 is located between the dielectric layer 13 and the emitter metal layer 14, thereby ensuring the normal extraction of current and ensuring the normal operation of the first semiconductor device type region 1011 and even the semiconductor device 100.

[0309] Furthermore, considering that the width of the second contact hole 1102 is relatively large, under the premise of not affecting the electrical connection between the emitter metal layer 14 and the portion of the well layer 11 located in the middle of the ring layer 107, a third contact hole 341 is opened in the portion of the barrier metal layer 108 corresponding to the second contact hole 1102. In this way, the barrier metal layer 108 in the second semiconductor device type region 1012 can be eliminated, so that at least a portion of the emitter metal layer 14 can pass through the third contact hole 341 and the second contact hole 1102, and be directly electrically connected to the portion of the well layer 11 located in the middle of the ring layer 107, thereby reducing the contact resistance, reducing the forward conduction voltage drop of the second semiconductor device type region 1012, and improving the working performance of the second semiconductor device type region 1012 and even the semiconductor device 100.

[0310] In some embodiments, as shown in FIG. 50 , the method for manufacturing the semiconductor device 100 in some embodiments of the present disclosure may include the following steps:

[0311] Step 1: Prepare the drift layer 10.

[0312] Step 2: implanting a ring layer 107 of the second conductivity type into the drift layer 10 and annealing the ring layer 107 .

[0313] Step 3: etching a trench portion 2110 in the drift layer 10 , and disposing an oxidized insulating layer 70 on the upper surface of the drift layer 10 .

[0314] Step 4: implanting a well layer 11 of the second conductivity type into the drift layer 10 and annealing the well layer 11. The well layer 11 is located on both sides of the ring layer 107.

[0315] In some embodiments, when manufacturing the semiconductor device 100, a drift layer 10 of the first conductivity type is provided. A ring layer 107 of the second conductivity type can be first implanted into the drift layer 10, and the ring layer 107 is annealed. The ring layer 107 is located at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012. Then, a groove portion 2110 is etched only in the drift layer 10 corresponding to the first semiconductor device type region 1011, and an oxidized insulating layer 70 is provided on the upper surface of the drift layer 10. Then, a well layer 11 of the second conductivity type is implanted into the drift layer 10, and the well layer 11 is annealed so that the upper surfaces of the well layer 11 and the ring layer 107 together constitute the upper surface of the drift layer 10.

[0316] In this way, the trench portion 2110 in the second semiconductor device type region 1012 can be eliminated, thereby increasing the effective area of ​​the PN junction of the second semiconductor device type region 1012 and reducing the forward conduction voltage drop of the second semiconductor device type region 1012 .

[0317] In addition, since the injection dose and annealing time of the ring layer 107 are greater than the injection dose and annealing time of the well layer 11, by adopting the method of first injecting the ring layer 107 and then injecting the well layer 11, the junction depth and doping concentration of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 can be guaranteed to be the same, and the withstand voltage of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 can be guaranteed to be the same, thereby ensuring the withstand voltage capability of the semiconductor device 100.

[0318] As shown in FIG. 50 , after implanting a well layer 11 of the second conductivity type into the drift layer 10 and annealing the well layer 11, the method for manufacturing the semiconductor device 100 further includes: implanting a second emitter layer 12 into the drift layer 10; disposing a dielectric layer 13 on the upper surface of the oxidized insulating layer 70; and defining a first contact hole 1101 in the dielectric layer 13 between two adjacent trench portions 2110, and defining a second contact hole 1102 in the dielectric layer 13 corresponding to a portion of the well layer 11 located in the middle of the ring layer 107. The length of the second contact hole 1102 in the first direction is greater than the length of the first contact hole 1101 in the first direction.

[0319] After implanting a well layer 11 of the second conductivity type into the drift layer 10 and annealing the well layer 11, a second emitter layer 12 can be implanted on both sides of the trench portion 2110 in the drift layer 10. A dielectric layer 13 is then formed on the surface of the oxidized insulating layer 70, covering the well layer 11, the ring layer 107, the second emitter layer 12, and the oxidized insulating layer 70. A first contact hole 1101 and a second contact hole 1102 are then formed in the dielectric layer 13. The first contact hole 1101 corresponds to the region between two adjacent trench portions 2110, i.e., the second emitter layer 12 can be exposed through the first contact hole 1101. The second contact hole 1102 corresponds to the portion of the well layer 11 located in the middle of the ring layer 107, i.e., the well layer 11 corresponding to the second semiconductor device type region 1012 can be exposed through the second contact hole 1102.

[0320] It can be understood that the width of the well layer 11 corresponding to the second semiconductor device type region 1012 is much larger than the width between two adjacent groove portions 2110. Therefore, the length of the second contact hole 1102 in the first direction is much larger than the length of the first contact hole 1101 in the first direction.

[0321] In some embodiments, as shown in FIG. 50 , after a first contact hole 1101 is formed in the dielectric layer 13 between two adjacent trench portions 2110 and a second contact hole 1102 is formed in the dielectric layer 13 corresponding to a portion of the well layer 11 located in the middle of the ring layer 107 , the method for manufacturing the semiconductor device 100 further includes:

[0322] A barrier metal layer 108 is provided on the upper surface of the dielectric layer 13, on the side walls of the dielectric layer 13 corresponding to the first contact hole 1101 and the second contact hole 1102, and on the upper surfaces of the ring layer 107 and the well layer 11; portions of the barrier metal layer 108 corresponding to the second contact hole 1102 and the opposite side walls of the groove portion 2110 on both sides of the second contact hole 1102 are etched to etch a third contact hole 341.

[0323] After a first contact hole 1101 is opened between two adjacent groove portions 2110 in the dielectric layer 13 and a second contact hole 1102 is opened in the middle portion of the ring layer 107 in the dielectric layer 13 corresponding to the well layer 11, a barrier metal layer 108 can be provided on the upper surface of the dielectric layer 13, on the sidewalls of the dielectric layer 13 corresponding to the first contact hole 1101 and the second contact hole 1102, and on the upper surfaces of the ring layer 107 and the well layer 11, and the second contact hole 1102 and portions of the opposite side walls of the groove portions 2110 on both sides of the second contact hole 1102 are etched, thereby forming a third contact hole 341.

[0324] In this way, on the one hand, the barrier metal layer 108 of the first semiconductor device type region 1011 still exists, so that the barrier metal layer 108 can be in contact with the second emitter layer 12, which is convenient for the subsequent electrical connection between the emitter metal layer 14 and the second emitter layer 12, thereby ensuring the normal operation of the first semiconductor device type region 1011. On the other hand, the barrier metal layer 108 of the second semiconductor device type region 1012 can be cancelled, which is convenient for the subsequent electrical connection between the emitter metal layer 14 and the well layer 11 of the second semiconductor device type region 1012, thereby reducing the conduction voltage drop of the second semiconductor device type region 1012.

[0325] In some embodiments, as shown in FIG. 50 , after etching portions of the barrier metal layer 108 corresponding to the second contact hole 1102 and the opposite side walls of the trench portion 2110 on both sides of the second contact hole 1102 to form the third contact hole 341 , the method for manufacturing the semiconductor device 100 further includes:

[0326] An emitter metal layer 14 is arranged on the upper surface of the barrier metal layer 108, and at least a portion of the emitter metal layer 14 passes through a first contact hole 1101 and is electrically connected to the second emitter layer 12, and at least a portion of the emitter metal layer 14 passes through a third contact hole 341 and a second contact hole 1102 and is electrically connected to a portion of the well layer 11 located in the middle of the ring layer 107; a field stop layer 15 is arranged on the lower surface of the drift layer 10; a collector layer 16 of a second conductive type is arranged on the lower surface of the field stop layer 15; a first emitter layer 17 is arranged at a position of the collector layer 16 corresponding to the middle of the ring layer 107; and a collector metal layer 18 is arranged on the lower surface of the collector layer 16.

[0327] After etching the barrier metal layer 108 on the opposite side walls corresponding to the second contact hole 1102 and the trench portion 2110 on both sides of the second contact hole 1102 to form the third contact hole 341, an emitter metal layer 14 can be first disposed on the upper surface of the barrier metal layer 108. In this way, at least a portion of the emitter metal layer 14 penetrates the first contact hole 1101 to contact the second emitter layer 12, and at least a portion of the emitter metal layer 14 can penetrate the third contact hole 341 and the second contact hole 1102 to connect to the well layer 11. A field stop layer 15 is then disposed on the lower surface of the drift layer 10, and a collector layer 16 of the second conductivity type is disposed on the lower surface of the field stop layer 15. A first emitter layer 17 is disposed in the middle of the collector layer 16 corresponding to the ring layer 107. Finally, a collector metal layer 18 is disposed on the lower surfaces of the collector layer 16 and the first emitter layer 17. The collector metal layer 18 is electrically connected to both the collector layer 16 and the first emitter layer 17.

[0328] In this way, a semiconductor device 100 can be manufactured, including the first semiconductor device type region 1011 and the second semiconductor device type region 1012 , and having a lower on-state voltage drop and better voltage resistance.

[0329] The following describes a method for manufacturing the semiconductor device 100 by taking the semiconductor device 100 as an RC-IGBT as an example with reference to FIG. 49 and FIG. 51 to FIG. 57 . The method includes the following steps:

[0330] In step 1, as shown in FIG51 , an N-substrate 2 material is provided as a drift layer 10 to form structure 1.

[0331] In step 2, as shown in FIG52 , based on structure 1, a P-type ring layer 107 is implanted and annealed to form structure 2.

[0332] In step 3, as shown in FIG53 , based on structure 2, a groove portion 2110 is etched, and an oxide insulating layer 70 and a polysilicon 71 are sequentially grown in the groove portion 2110 , and then the polysilicon 71 is etched to form structure 3.

[0333] In step 4, as shown in FIG54 , based on structure three, the P-type well layer 11 is implanted and annealed to form structure four.

[0334] In step 5, as shown in FIG55 , based on structure 4, an N+ second emitter layer 12 is implanted and annealed, and then a dielectric layer 13 is deposited thereon to form structure 5.

[0335] In step 6, as shown in FIG56 , based on structure five, a first contact hole 1101 and a second contact hole 1102 are etched on the dielectric layer 13, and then a titanium (Ti) or titanium nitride (TiN) barrier metal layer 108 is deposited on the dielectric layer 13 to form structure six.

[0336] In step 7, as shown in FIG57 , based on structure 6, a third contact hole 341 is etched on the barrier metal layer 108 to ensure that there is no barrier metal layer 108 in the FRD region, thereby forming structure 7.

[0337] In step 8, as shown in FIG49 , based on structure seven, metal sputtering is performed to prepare an emitter metal layer 14, and then the N+ field stop layer 15 is injected, the P+ collector layer 16 is injected, the FRD region N+ first emitter layer 17 is injected, laser annealing is performed, and metal sputtering is performed to prepare a collector metal layer 18, and finally the semiconductor device 100 is formed.

[0338] The following describes a semiconductor device 100 in some embodiments of the present disclosure with reference to Figures 58 to 62. The semiconductor device 100 is, for example, an IGBT. In the following description, "N" and "P" represent the conductivity type of the semiconductor. In some embodiments of the present disclosure, the first conductivity type is N-type and the second conductivity type is P-type.

[0339] 58 , the semiconductor device 100 includes: a drift layer 10 of a first conductivity type, a voltage-resistant ring 25 of a second conductivity type, a polysilicon field plate 8 , a first dielectric layer 1305 and a metal field plate 90 .

[0340] In some embodiments, a first conductive type field stop layer 15 is provided below the first conductive type drift layer 10, a second conductive type collector layer 16 is provided below the field stop layer 15, and a collector metal layer 18 is provided below the collector layer 16. This can form the basic structure of the semiconductor structure and ensure the normal operation of the semiconductor device 100.

[0341] Considering that the electric field strength in the terminal region 103 of the semiconductor device 100 is relatively strong and the voltage per unit length is relatively large, voltage breakdown is likely to occur there. By setting the voltage-resistant ring 25 on the surface of the drift layer 10 corresponding to the portion of the terminal region 103 of the semiconductor device 100, the voltage-resistant ring 25 can optimize the electric field distribution in the terminal region 103 and improve the voltage resistance of the terminal region 103.

[0342] In some embodiments, as shown in conjunction with FIG. 58 and FIG. 60 , the polysilicon field plate 8 is disposed above the surface of the voltage-resistant ring 25 and is electrically connected to the voltage-resistant ring 25. The polysilicon field plate 8 defines a first via 801. The first dielectric layer 1305 is disposed above the surface of the polysilicon field plate 8. The first dielectric layer 1305 defines a second via 1031 and a third via 1032. The second via 1031 corresponds to the first via 801. The third via 1032 and the second via 1031 are spaced apart on the surface of the first dielectric layer 1305. For example, the third via 1032 and the second via 1031 are spaced apart in the left-right direction of the first dielectric layer 1305. The metal field plate 90 is provided with a first electrical connection protrusion 41 and a second electrical connection protrusion 42. The first electrical connection protrusion 41 passes through the second via 1031 and the first via 801 in sequence and is electrically connected to the voltage-resistant ring 25. The second electrical connection protrusion 42 passes through the third via 1032 and is electrically connected to the polysilicon field plate 8.

[0343] Considering that a PN junction typically has a curved surface, the electric field at the curved junction is greater, making the semiconductor device 100 susceptible to breakdown at such locations. Therefore, by disposing the polysilicon field plate 8 above the surface of the voltage-resistant ring 25, disposing the first dielectric layer 1305 above the surface of the polysilicon field plate 8, and disposing the metal field plate 90 above the surface of the first dielectric layer 1305, the main junction depletion region 600 can be effectively widened outward, avoiding electric field concentration, and increasing the breakdown voltage, thereby improving the voltage resistance of the terminal region 103 and, therefore, the semiconductor device 100.

[0344] In addition, a first via 801 is provided in the polysilicon field plate 8, a second via 1031 is provided in the first dielectric layer 1305, the first via 801 corresponds to the second via 1031, and a first electrical connection protrusion 41 is provided on the metal field plate 90, so that the first electrical connection protrusion 41 can pass through the second via 1031 and the first via 801 in sequence, and contact and electrically connect with the voltage-resistant ring 25, thereby realizing electrical connection between the metal field plate 90 and the voltage-resistant ring 25, making the metal field plate 90 and the voltage-resistant ring 25 have the same electric potential.

[0345] In addition, by providing a third via 1032 in the first dielectric layer 1305 and correspondingly providing a second electrical connection protrusion 42 on the metal field plate 90, it is only necessary to make the second electrical connection protrusion 42 pass through the third via 1032 so that the second electrical connection protrusion 42 can be in contact and electrically connected with the polysilicon field plate 8, thereby realizing electrical connection between the metal field plate 90 and the polysilicon field plate 8, and making the metal field plate 90 and the polysilicon field plate 8 have the same electric potential.

[0346] When the third via 1032 and the second via 1031 are spaced apart in the left-right direction of the first dielectric layer 1305, the left-right length of the polysilicon field plate 8 needs to be correspondingly extended so that the polysilicon field plate 8 can correspond to the second via 1031 and the third via 1032. In this way, the area of ​​the polysilicon field plate 8 can be increased, and the electric field modulation capability of the polysilicon field plate 8 on the terminal region 103 can be improved. This can avoid electric field concentration and make the electric field distribution in the terminal region 103 more uniform, thereby increasing the breakdown voltage of the semiconductor device 100 and improving the withstand voltage capability of the semiconductor device 100.

[0347] In addition, the third via 1032 and the second via 1031 are spaced apart on the surface of the first dielectric layer 1305, and the first electrical connection protrusion 41 and the second electrical connection protrusion 42 are also spaced apart on the metal field plate 90. This not only facilitates the opening of the second via 1031 and the first via 801 on the first dielectric layer 1305, and facilitates the setting of the first electrical connection protrusion 41 and the second electrical connection protrusion 42 on the metal field plate 90, which can reduce the manufacturing difficulty, but also allows the first electrical connection protrusion 41 to pass through the first via 801 and the second via 1031 at the same time as the second electrical connection protrusion 42 passes through the third via 1032, which can improve assembly efficiency.

[0348] In this way, the equipotential of the voltage-resistant ring 25, the polysilicon field plate 8 and the metal field plate 90 can be achieved, thereby avoiding the occurrence of a floating electric field due to the lack of interconnection among the structures, and avoiding the floating electric field being disturbed by the outside world when the semiconductor device 100 is working, resulting in uneven electric field distribution in the terminal area 103 and causing reduced voltage resistance and reliability. The voltage resistance capability of the semiconductor device 100 can be improved, and the reliability of the semiconductor device 100 can be improved.

[0349] Therefore, by making the first electrical connection protrusion 41 pass through the second via 1031 and the first via 801 in sequence and electrically connected to the voltage-resistant ring 25, and making the second electrical connection protrusion 42 pass through the third via 1032 and electrically connected to the polysilicon field plate 8, the voltage-resistant ring 25, the polysilicon field plate 8 and the metal field plate 90 are made to have the same electric potential, thereby improving the voltage resistance and reliability of the semiconductor device 100.

[0350] 58 to 61 , the second via 1031 and the first via 801 are disposed above and within the boundaries of the voltage-resistant ring 25 , and both sides of the metal field plate 90 and the polysilicon field plate 8 extend out of the boundaries of the voltage-resistant ring 25 .

[0351] By arranging the second via 1031 and the first via 801 above the boundaries of the two sides of the voltage-resistant ring 25, when the first electrical connection protrusion 41 on the metal field plate 90 passes through the second via 1031 and the first via 801 in sequence, it can directly contact and electrically connect with the voltage-resistant ring 25, and it can be ensured that the end of the first electrical connection protrusion 41 is in full contact with the voltage-resistant ring 25, thereby not only making the electrical connection between the metal field plate 90 and the voltage-resistant ring 25 simpler to implement, but also ensuring that there is sufficient contact area between the metal field plate 90 and the voltage-resistant ring 25, ensuring the stability of the electrical connection between the metal field plate 90 and the voltage-resistant ring 25, and thus more stably and reliably ensuring the equipotential between the metal field plate 90 and the voltage-resistant ring 25.

[0352] Furthermore, by extending both sides of the metal field plate 90 and the polysilicon field plate 8 out of the two side boundaries of the voltage-resistant ring 25, the electric field modulation capability of the metal field plate 90 and the polysilicon field plate 8 on the terminal region 103 can be improved, thereby avoiding electric field concentration and making the electric field distribution in the terminal region 103 more uniform, thereby increasing the breakdown voltage of the semiconductor device 100 and enhancing the voltage resistance of the semiconductor device 100.

[0353] In some embodiments, as shown in conjunction with Figures 60 and 61 , the aperture of the first via hole 801 is larger than the aperture of the second via hole 1031. The polysilicon field plate 8 is located below the first dielectric layer 1305. During the production process, the first via hole 801 can be first formed in the polysilicon field plate 8, and then the first dielectric layer 1305 is placed on the polysilicon field plate 8. Then, the second via hole 1031 can be formed in the first dielectric layer 1305. By setting the aperture of the first via hole 801 larger than the aperture of the second via hole 1031, the morphology and size of the first via hole 801 can be prevented from being affected when the second via hole 1031 is formed, thereby ensuring the reliability of the polysilicon field plate 8 and even the semiconductor device 100.

[0354] In some embodiments, as shown in FIG60 , the first electrical connection protrusion 41 is circumferentially spaced from the inner wall of the first via hole 801 corresponding to the polysilicon field plate 8. This facilitates the penetration of the first electrical connection protrusion 41 through the first via hole 801 and prevents damage to the inner wall of the polysilicon field plate 8 corresponding to the first via hole 801 during the penetration process, thereby improving the reliability of the semiconductor device 100.

[0355] In some embodiments, as shown in FIG62 , the first via 801 is at least one of a square, a rectangle, a circle, and a diamond. Accordingly, the shape of the second via 1031 and the cross-sectional shape of the first electrical connection protrusion 41 can be designed accordingly. This simplifies the shape of the first via 801, facilitates the creation of the first via 801 and the second via 1031, and facilitates the manufacture of the first electrical connection protrusion 41, thereby reducing the difficulty in producing the semiconductor device 100.

[0356] In some embodiments, as shown in FIG62 , there are multiple first vias 801, and multiple first vias 801 are spaced apart on the upper surface of the polysilicon field plate 8. There are multiple first electrical connection protrusions 41, and multiple first electrical connection protrusions 41 correspond to multiple first vias 801. Relatively speaking, multiple second vias 1031 are also provided. In this way, multiple electrical connections can be made between the metal field plate 90 and the voltage-resistant ring 25, thereby improving the stability and reliability of the electrical connection between the metal field plate 90 and the voltage-resistant ring 25, and stably and reliably ensuring the equipotential between the metal field plate 90 and the voltage-resistant ring 25. It should be noted that multiple first vias 801 are spaced apart on the polysilicon field plate 8, which can ensure that the polysilicon field plate 8 remains a whole and is not disconnected after the opening.

[0357] In some embodiments, as shown in Figure 61, the semiconductor device 100 also includes a field oxide layer 60, which is arranged above the surface of the voltage-resistant ring 25 and at least partially located between the polysilicon field plate 8 and the voltage-resistant ring 25. The field oxide layer 60 is provided with a fourth via 63, and the fourth via 63 corresponds to the first via 801 and the second via 1031. The first electrical connection protrusion 41 passes through the second via 1031, the first via 801 and the fourth via 63 in sequence and is electrically connected to the voltage-resistant ring 25.

[0358] By opening a fourth via 63 corresponding to the first via 801 and the second via 1031 in the field oxide layer 60, the field oxide between the polysilicon field plate 8 and the voltage-resistant ring 25 can be at least partially removed. After the first electrical connection protrusion 41 can pass through the second via 1031, the first via 801 and the fourth via 63 in sequence, the first electrical connection protrusion 41 can be electrically connected to the voltage-resistant ring 25, that is, the contact electrical connection between the metal field plate 90 and the voltage-resistant ring 25 can be achieved, thereby ensuring the equipotential between the voltage-resistant ring 25 and the metal field plate 90.

[0359] In some embodiments, as shown in Figure 61, the aperture of the fourth via 63 is equal to the aperture of the second via 1031. This not only ensures that the first electrical connection protrusion 41 can smoothly pass through the fourth via 63, facilitating the electrical connection between the metal field plate 90 and the voltage-resistant ring 25, but also facilitates the simultaneous formation of the fourth via 63 and the second via 1031, thereby improving the production efficiency of the semiconductor device 100.

[0360] In some embodiments, as shown in FIG. 58 , the semiconductor device 100 includes an active region 101 and a transition region 102 . The transition region 102 is disposed between the active region 101 and the terminal region 103 . There are multiple voltage-resistant rings 25 , and the multiple voltage-resistant rings 25 are disposed at intervals.

[0361] The active region 101 can bear most of the forward current during forward conduction and can also bear a high blocking voltage when a reverse voltage is applied. When a reverse voltage is applied to the semiconductor device 100, the terminal region 103 can alleviate the electric field crowding at the edge of the active region 101, thereby improving the reverse breakdown voltage of the semiconductor device 100.

[0362] Considering that the terminal area 103 bears a large voltage, by setting multiple voltage-resistant rings 25 in the terminal area 103 and setting the multiple voltage-resistant rings 25 at intervals, the electric field distribution of the terminal area 103 can be optimized, the breakdown voltage of the terminal area 103 can be increased, and the voltage resistance of the terminal area 103 can be improved.

[0363] In some embodiments, as shown in FIG58 , a polysilicon field plate 8 and a metal field plate 90 are disposed above the one of the plurality of voltage-resistant rings 25 that is furthest from the transition region 102. The one of the plurality of voltage-resistant rings 25 that is furthest from the transition region 102 bears the highest voltage. By disposing the polysilicon field plate 8 and the metal field plate 90 above the one, the structure of the semiconductor device 100 can be simplified, and the production difficulty and cost of the semiconductor device 100 can be reduced, while improving the voltage resistance and reliability of the terminal region 103.

[0364] In other embodiments, a polysilicon field plate 8 and a metal field plate 90 are disposed above at least one of the plurality of voltage-resistant rings 25. This can increase the number of polysilicon field plates 8 and metal field plates 90, thereby optimizing the electric field distribution in the terminal region 103 and improving the voltage resistance and reliability of the terminal region 103 and even the semiconductor device 100.

[0365] Of course, whether a polysilicon field plate 8 and a metal field plate 90 are correspondingly arranged above the one farthest from the transition zone 102 among the multiple voltage-resistant rings 25, or a polysilicon field plate 8 and a metal field plate 90 are correspondingly arranged above at least one of the multiple voltage-resistant rings 25, it is necessary to ensure the equipotentiality of the polysilicon field plate 8, the first dielectric layer 1305 and the metal field plate 90, which will not be elaborated here.

[0366] In some embodiments, there are multiple polysilicon field plates 8, and the multiple polysilicon field plates 8 are arranged at intervals. The multiple polysilicon field plates 8 are all provided with a first via 801. A second dielectric layer 1306 is provided between two adjacent polysilicon field plates 8 (as shown in Figure 91). The first vias 801 on the multiple polysilicon field plates 8 correspond to each other, and the second dielectric layer 1306 is provided with a fifth via, which corresponds to the first via 801. The first electrical connection protrusion 41 passes through the fifth via, the first via 801 and the second via 1031 and is electrically connected to the voltage-resistant ring 25.

[0367] When the terminal region 103 includes a plurality of spaced-apart polysilicon field plates 8 and a second dielectric layer 1306 is provided between the plurality of polysilicon field plates 8, first vias 801 corresponding to each other can be provided on the plurality of polysilicon field plates 8, and a fifth via corresponding to the first via 801 can be provided on the second dielectric layer 1306. In this way, the first electrical connection protrusion 41 can simultaneously penetrate the plurality of fifth vias, the plurality of first vias 801 and the second via 1031, and be electrically connected to the voltage-resistant ring 25, thereby realizing mutual electrical connection between the metal field plate 90 and the voltage-resistant ring 25. In addition, the plurality of polysilicon field plates 8 can also be electrically connected to the metal field plate 90 by opening holes in the polysilicon field plate 8 located above the polysilicon field plate 8 and the second dielectric layer 1306. In this way, even if a plurality of polysilicon field plates 8 are included, the improvement of the electric field distribution in the terminal region 103 can be ensured, and the voltage resistance and reliability of the semiconductor device 100 can be improved.

[0368] The following describes a semiconductor device 100 in some embodiments of the present disclosure with reference to Figures 63 to 76. The semiconductor device 100 may employ a method for manufacturing the semiconductor device 100. The semiconductor device 100 may be an insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In some embodiments of the present disclosure, the first conductivity type is N-type and the second conductivity type is P-type.

[0369] 63 to 67 , the semiconductor device 100 includes a substrate 80 , a drift layer 10 of a first conductivity type, a well layer 11 of a second conductivity type, and a base layer 109 of a second conductivity type.

[0370] In some embodiments, the substrate 80 has a first main surface 81 and a second main surface 82, and the first main surface 81 and the second main surface 82 are spaced apart from each other in the vertical direction. The drift layer 10 is disposed in the substrate 80 so that the drift layer 10 is located between the first main surface 81 and the second main surface 82, and a well layer 11 is disposed on a side of the drift layer 10 facing the first main surface 81 corresponding to a portion of the transition region 102 of the semiconductor device 100. The side of the well layer 11 adjacent to the first main surface 81 constitutes a portion of the first main surface 81. The length of the well layer 11 extends in the first direction, the depth of the well layer 11 extends in the vertical direction, and the well layer 11 is disposed on the drift layer 10. A base layer 109 is further provided on the portion of the transition zone 102 of the semiconductor device 100 that faces the first main surface 81. The side of the base layer 109 adjacent to the first main surface 81 constitutes a portion of the first main surface 81. The length of the base layer 109 extends in the first direction and extends from the active area 101 of the semiconductor device 100 to the transition zone 102 of the semiconductor device 100. The depth of the base layer 109 extends in the up and down directions, so that the base layer 109 and the well layer 11 are arranged in the first direction. In this way, the basic structure of the transition zone 102 of the semiconductor device 100 can be formed to ensure the normal operation of the semiconductor device 100.

[0371] Considering that the transition region 102 of the semiconductor device 100 is located between the terminal region 103 and the active region 101, the structure of the transition region 102 is relatively complex and voltage breakdown is more likely to occur there. By setting the well layer 11, the depth of the well layer 11 is set to be greater than the depth of the base layer 109, and the doping concentration of the second conductive type dopant in the well layer 11 is greater than the doping concentration of the second conductive type dopant in the base layer 109, the electric field distribution in the transition region 102 can be optimized and the voltage resistance of the transition region 102 can be improved.

[0372] In some embodiments, as shown in conjunction with FIG. 64 and FIG. 65 , the semiconductor device 100 further includes a first trench 20. The first trench 20 is disposed in the transition region 102. The depth of the first trench 20 extends from the first main surface 81 toward the second main surface 82. The length of the first trench 20 extends in the second direction. The first trench 20 is located between the well layer 11 and the base layer 109 in the first direction. The first trench 20 contacts the well layer 11 and the base layer 109 on both sides of the first direction. The first direction, the second direction, and the up-down direction are perpendicular to each other.

[0373] Typically, since the base layer 109 is spaced apart from the well layer 11 in the first direction, and there is a difference in the doping concentration of the second conductive type dopant in the base layer 109 and the well layer 11, the second conductive type dopant in the well layer 11 will diffuse toward the base layer 109 in the first direction, and since there is a difference in the depth of the base layer 109 and the well layer 11, a curved surface will be formed at the junction of the base layer 109 and the well layer 11. When the semiconductor device 100 is in reverse withstand voltage, electric field concentration will occur at this position, and the electric field intensity is large, which may cause the safe operating area to become smaller, and the reliability of the semiconductor device 100 will be reduced.

[0374] In some embodiments of the present disclosure, by setting a second trench 30, an oxide insulating layer 70 and deposited polysilicon 71 can be grown in the second trench 30, and the first trench 20 is located between the well layer 11 and the base layer 109 in the first direction. The first trench 20 has two side walls spaced apart in the first direction, and the two side walls of the first trench 20 extend in the up and down directions. By making the two side walls of the first trench 20 in the first direction contact the well layer 11 and the base layer 109 respectively, the first trench 20 can be blocked between the well layer 11 and the base layer 109 in the first direction, thereby blocking the second conductive type dopant in the well layer 11 from diffusing toward the base layer 109, thereby avoiding the formation of a curved surface in the transition region 102, avoiding the electric field concentration in the transition region 102 when the semiconductor device 100 withstands reverse voltage, improving the reliability of the semiconductor device 100, and increasing the safe working area of ​​the semiconductor device 100.

[0375] Therefore, by setting the first trench 20, the first trench 20 is located between the well layer 11 and the base layer 109, so that the first trench 20 can block the second conductive type dopant of the well layer 11 from diffusing toward the base layer 109, thereby avoiding the formation of a curved surface in the transition region 102, optimizing the electric field distribution in the transition region 102, and avoiding electric field concentration, thereby improving the reliability of the semiconductor device 100 and increasing the safe operating area of ​​the semiconductor device 100.

[0376] In some embodiments, as shown in FIG65 , the depth of the first trench 20 is D4, and the depth of the base layer 109 is D5, where D4 and D5 satisfy the relationship: D4 ≥ D5. By setting the depth of the first trench 20 to be greater than or equal to the depth of the base layer 109, the first trench 20 can completely block the base layer 109 in the vertical direction, thereby more reliably preventing the second conductivity type dopant in the well layer 11 from diffusing into the base layer 109, avoiding the formation of a curved surface at the interface between the well layer 11 and the base layer 109, thereby improving the reliability of the semiconductor device 100 and increasing the safe operating area of ​​the semiconductor device 100.

[0377] In some embodiments, as shown in FIG65 , the depth of the well layer 11 is D6, and D4 and D6 satisfy the relationship: D4 ≤ D6. The first trench 20 is also provided with a bottom wall, which connects the two side walls toward the ends of the second main surface 82. The curvature of the bottom wall is small, which makes it easy for electric field concentration to occur. By setting the depth of the first trench 20 to be less than or equal to the depth of the well layer 11, it can be ensured that the well layer 11 wraps at least a portion of the bottom wall of the first trench 20. This can optimize the electric field near the bottom wall and avoid electric field concentration, thereby ensuring the voltage resistance of the semiconductor device 100 and the reliability of the semiconductor device 100.

[0378] In some embodiments, in combination with Figures 64 to 67, the semiconductor device 100 further includes: a carrier storage layer 110 of a first conductivity type, the carrier storage layer 110 is arranged on the side of the drift layer 10 facing the first main surface 81, the carrier storage layer 110 is located between the drift layer 10 and the base layer 109, the length of the carrier storage layer 110 extends in the first direction and extends from the active area 101 of the semiconductor device 100 to the transition area 102 of the semiconductor device 100, the carrier storage layer 110 is located on the side of the first trench 20 facing the base layer 109 in the first direction, the depth of the carrier storage layer 110 extends in the up and down directions, the depth of the carrier storage layer 110 is D7, D7, D5 and D4 satisfy the relationship: D7+D5≤D4.

[0379] By setting a first conductive type carrier storage layer 110, the carrier storage layer 110 is set on the side of the drift layer 10 facing the first main surface 81, and the length of the carrier storage layer 110 extends in the first direction and extends from the active area 101 of the semiconductor device 100 to the transition area 102 of the semiconductor device 100, so that the carrier storage layer 110 is at least partially located between the drift layer 10 and the base layer 109, and the depth of the carrier storage layer 110 extends in the up and down directions. In this way, the carrier storage layer 110 can play a role in blocking holes and promote electron injection into the drift layer 10, thereby enhancing the conductivity modulation effect, reducing the forward conduction voltage drop of the semiconductor device 100, and improving the normal operation of the semiconductor device 100.

[0380] In addition, the carrier storage layer 110 is located on the side of the first trench 20 facing the base layer 109 in the first direction. By setting the sum of the depth of the carrier storage layer 110 and the depth of the base layer 109 to be smaller than the depth of the first trench 20, the first trench 20 can completely block the carrier storage layer 110 in the up and down directions, thereby preventing the first conductive type dopant in the carrier storage layer 110 from diffusing toward the well layer 11, avoiding the carrier storage layer 110 and the well layer 11 from generating a PN junction with a small curvature in the first direction, optimizing the electric field distribution in the transition region 102, avoiding electric field concentration, and thereby improving the reliability of the semiconductor device 100 and increasing the safe operating area of ​​the semiconductor device 100.

[0381] In some embodiments, in combination with Figures 64 and 67, the semiconductor device 100 also includes a second trench 30, the depth of the second trench 30 extends from the first main surface 81 in the up and down directions to the drift layer 10, the length of the second trench 30 extends in the first direction, and the second trench 30 extends from the active area 101 of the semiconductor device 100 to the transition area 102 of the semiconductor device 100 in the first direction, there are multiple second trenches 30, and the multiple second trenches 30 are arranged at intervals in the third direction.

[0382] By setting the second trench 30, the second trench 30 extends from the first main surface 81 in the up and down directions to the drift layer 10, and the second trench 30 extends in the first direction, and by growing the oxide insulation layer 70 in the second trench 30 and depositing polysilicon 71, the first conductive type emitter layer 3 is set on both sides of the second trench 30, so that the second trench 30 can have a conductive channel 4 and current flow capability.

[0383] In some embodiments, the second trench 30 can be set as a plurality, and the plurality of second trenches 30 are spaced apart in the second direction, and when the second trench 30 extends in the first direction, it can extend from the active area 101 to the transition area 102. In this way, the plurality of second trenches 30 can be connected to the gate pad 104 through the planar gate polysilicon 712 of the transition area 102, so that the current can be drawn out to ensure the normal operation of the semiconductor device 100.

[0384] In some embodiments, the second trench 30 has the same depth as the first trench 20 , so that the first trench 20 and the second trench 30 can be etched simultaneously, thereby simplifying the process flow of the semiconductor device 100 .

[0385] The method for manufacturing the semiconductor device 100 in some embodiments of the present disclosure may be used to manufacture the aforementioned semiconductor device 100 .

[0386] In some embodiments, as shown in FIG. 68 , a method for manufacturing the semiconductor device 100 includes the following steps:

[0387] Step 1: implanting a second conductivity type dopant with a first doping concentration into a portion of the drift layer 10 corresponding to the transition region 102 on a side facing the first main surface 81 to form a well layer 11 with a first depth.

[0388] Step 2: Doping a second conductive type dopant with a second doping concentration into the side of the drift layer 10 facing the first main surface 81 to form a base layer 109 of a second depth aligned with the well layer 11 in the first direction. The second doping concentration is lower than the first doping concentration, and the second depth is lower than the first depth.

[0389] In step 3, a first trench 20 extending from the first main surface 81 in the vertical direction is etched between the well layer 11 and the base layer 109 .

[0390] When manufacturing the semiconductor device 100, a substrate 2 material can be first provided as the drift layer 10. A first doping concentration of a second conductivity type dopant is implanted into the portion of the drift layer 10 facing the first main surface 81, corresponding to the transition region 102, to form a well layer 11 of a first depth. This can improve the withstand voltage capability of the transition region 102. Then, a second doping concentration of a second conductivity type dopant is implanted into the side of the drift layer 10 facing the first main surface 81, to form a base layer 109 of a second depth. The second doping concentration is lower than the first doping concentration, and the second depth is lower than the first depth. Specifically, the doping concentration of the second conductivity type dopant in the well layer 11 is higher than the doping concentration of the second conductivity type dopant in the base layer 109, and the vertical depth of the well layer 11 is greater than the vertical depth of the base layer 109. Thus, while ensuring the withstand voltage capability of the transition region 102, a depth and concentration difference exists between the well layer 11 and the base layer 109.

[0391] Next, a first trench 20 extending vertically from the first main surface 81 is etched between the well layer 11 and the base layer 109. The first trench 20 is located between the well layer 11 and the base layer 109, thereby preventing the second conductivity type dopant in the well layer 11 from diffusing toward the base layer 109, thereby improving the reliability of the semiconductor device 100. The first conductivity type dopant may be phosphorus ions, and the second conductivity type dopant may be boron ions, which are not specifically limited herein.

[0392] As shown in Figure 64, a first trench 20 extending from the first main surface 81 toward the up and down directions is etched between the well layer 11 and the base layer 109, including: the first trench 20 and the ion injection region of the well layer 11 are spaced apart from each other in the first direction toward the side boundary of the base layer 109.

[0393] After the second conductive type dopant is injected into the portion of the transition zone 102 corresponding to the side of the drift layer 10 facing the first main surface 81, the second conductive type dopant will diffuse in the first direction, that is, the well layer 11 finally formed will exceed the ion implantation area of ​​the well layer 11 in the first direction. By etching the first trench 20 extending from the first main surface 81 toward the up and down directions between the well layer 11 and the base layer 109, the first trench 20 and the boundary of the ion implantation area of ​​the well layer 11 facing the side of the base layer 109 are spaced apart from each other in the first direction. In this way, a distance can be reserved for the diffusion of the second conductive type dopant in the well layer 11 in the first direction, ensuring that the first trench 20 can be located between the well layer 11 and the subsequent base layer 109, avoiding electric field concentration, and thereby increasing the safe operating area of ​​the semiconductor device 100.

[0394] In some embodiments, the first trench 20 and the boundary of the ion implantation region of the well layer 11 facing the base layer 109 are separated by a distance D8 in the first direction, where D8 satisfies the relationship: 0.5 μm ≤ D8 ≤ 2.0 μm. This not only ensures that the first trench 20 is located between the well layer 11 and the subsequently formed base layer 109, thus preventing the formation of a curved surface between the well layer 11 and the base layer 109, but also ensures that the base layer 109 formed after the second conductivity type dopant diffuses in the first direction at least partially wraps around the bottom wall of the first trench 20, thus preventing electric field concentration in the first trench 20. This optimizes the electric field distribution in the transition region 102, increases the safe operating area of ​​the semiconductor device 100, and improves the reliability of the semiconductor device 100.

[0395] In some embodiments, in combination with what is shown in FIG69 , after a second conductive type dopant of a first doping concentration is injected into a portion of the transition zone 102 on a side of the drift layer 10 facing the first main surface 81 to form a well layer 11 of a first depth, and before a second conductive type dopant of a second doping concentration is injected into a side of the drift layer 10 facing the first main surface 81 to form a base layer 109 of a second depth arranged in the first direction with the well layer 11, the manufacturing method of the semiconductor device 100 further includes: injecting a first conductive type dopant into a side of the drift layer 10 facing the first main surface 81 to form a carrier storage layer 110.

[0396] During the process of manufacturing the semiconductor device 100, after forming the well layer 11 and before forming the base layer 109, a first conductive type dopant can be injected into the side of the drift layer 10 facing the first main surface 81. In this way, a carrier storage layer 110 can be formed in the semiconductor device 100, thereby improving the operating performance of the semiconductor device 100.

[0397] In some embodiments, the carrier storage layer 110 is at least partially located between the drift layer 10 and the base layer 109, and the carrier storage layer 110 and the well layer 11 are spaced apart in the first direction, so that the well layer 11 and the carrier storage layer 110 can also be separated by the first trench 20. The first trench 20 can block the first conductive type dopant in the carrier storage layer 110 from diffusing into the well layer 11, thereby preventing the formation of a PN junction with a small curvature and optimizing the electric field distribution.

[0398] In some embodiments, as shown in FIG. 69 , after implanting a first conductivity type dopant into the side of the drift layer 10 facing the first main surface 81 to form the carrier storage layer 110 , the method for manufacturing the semiconductor device 100 further includes:

[0399] A high temperature gas at a first preset temperature is used to push the trap at a high temperature for a first preset time.

[0400] In this way, the rate and uniformity of distribution and diffusion of the first conductive type dopant in the substrate 2 can be improved, thereby optimizing the operating performance of the carrier storage layer 110 and even the semiconductor device 100, and improving the reliability of the semiconductor device 100. The high-temperature gas can be N2, the first preset temperature can be 1150° C., and the first preset time can be 120 minutes, which are not specifically limited herein.

[0401] In some embodiments, as shown in conjunction with FIG. 68 and FIG. 69 , after implanting a second conductive type dopant into a portion of the drift layer 10 corresponding to the transition region 102 on a side facing the first main surface 81 to form the well layer 11, the method for manufacturing the semiconductor device 100 further includes:

[0402] High temperature gas at a second preset temperature is used to push the trap at a high temperature for a second preset time.

[0403] In this way, the rate and uniformity of distribution and diffusion of the second conductive type dopant in the substrate 2 can be improved, thereby optimizing the operating performance of the well layer 11 and even the semiconductor device 100, and improving the reliability of the semiconductor device 100. The high-temperature gas can be N2, the second preset temperature can be 1150° C., and the second preset time can be 80 minutes, which are not specifically limited herein.

[0404] In some embodiments, as shown in conjunction with FIG. 68 and FIG. 69 , after implanting a second conductivity type dopant of a second doping concentration into the side of the drift layer 10 facing the first main surface 81 to form a base layer 109 of a second depth aligned with the well layer 11 in the first direction, the method for manufacturing the semiconductor device 100 further includes:

[0405] A high temperature gas at a third preset temperature is used to push the trap at a high temperature for a third preset time.

[0406] In this way, the rate and uniformity of distribution and diffusion of the second conductive type dopant in the substrate 2 can be improved, thereby optimizing the operating performance of the base layer 109 and even the semiconductor device 100, and improving the reliability of the semiconductor device 100. The high-temperature gas can be N2, the third preset temperature can be 1150° C., and the third preset time can be 80 minutes, which are not specifically limited herein.

[0407] In some embodiments, as shown in FIG. 68 and FIG. 69 , after etching the first trench 20 extending vertically from the first main surface 81 between the well layer 11 and the carrier storage layer 110 , the method for manufacturing the semiconductor device 100 further includes:

[0408] An oxidized insulating layer 70 is grown on the surfaces of the well layer 11 , the first trench 20 , and the base layer 109 .

[0409] Polysilicon 71 is deposited on the surface of the oxidized insulating layer 70 and then etched.

[0410] A dielectric layer 13 is deposited on the surfaces of the polysilicon 71 , the well layer 11 and the base layer 109 .

[0411] After etching the first trench 20 extending from the first main surface 81 in the up-down direction between the well layer 11 and the base layer 109, an oxide insulating layer 70 can be grown on the surface of the well layer 11, the first trench 20 and the carrier storage layer 110, and then polysilicon 71 is deposited on the surface of the oxide insulating layer 70, so that the polysilicon 71 can be located on the surface of the well layer 11, in the first trench 20 and on the surface of the base layer 109. The polysilicon 71 is then etched to retain the polysilicon 71 located in the first trench 20 to form a trench gate polysilicon 711, and a portion of the polysilicon 71 on the surface of the well layer 11 is retained to form a planar gate polysilicon 712. A dielectric layer 13 is then deposited on the surfaces of the polysilicon 71, the well layer 11 and the base layer 109. The dielectric layer 13 can protect the surfaces of the polysilicon 71, the well layer 11 and the base layer 109, thereby improving the structural reliability of the semiconductor device 100.

[0412] In some embodiments, as shown in FIG. 68 and FIG. 69 , while etching the first trench 20 extending vertically from the first main surface 81 between the well layer 11 and the base layer 109 , the method for manufacturing the semiconductor device 100 further includes:

[0413] The etching extends from the first main surface 81 in the vertical direction to the second trench 30 in the drift layer 10 .

[0414] The second trench 30 extends in the first direction. There are multiple second trenches 30, which are spaced apart in the second direction. The second trenches 30 and the first trenches 20 have the same depth. This allows for simultaneous formation of the first trench 20 and the second trench 30. In subsequent steps, an oxide insulating layer 70 can be grown and polysilicon 71 can be deposited within the second trench 30, connecting the second trench 30 to the gate. This simplifies the manufacturing method of the semiconductor device 100 and ensures normal operation of the semiconductor device 100.

[0415] The following describes a method for manufacturing the semiconductor device 100 by way of example with reference to FIG65 and FIG70 to FIG75. The method includes the following steps:

[0416] Step 1, as shown in FIG70 , provides a substrate 2 material. The substrate 2 material can be a phosphorus-doped silicon substrate 2 with a resistivity of 25 ohm·cm to form a structure 1.

[0417] Step 2, as shown in FIG71, is to implant impurity boron ions based on structure 1 with an energy of 60keV and a dose of 5e13cm -2 The high temperature well pushing is performed using N2 gas at a high temperature of 1150°C for 80 minutes to form the well layer 11, thereby forming the second structure.

[0418] Step 3, as shown in FIG72, is to inject impurity phosphorus ions based on structure 2 with an energy of 200keV and a dose of 5e12cm - 2 The high temperature well-pushing process uses N2 gas at a temperature of 1150°C for 120 minutes to form the carrier storage layer 110, thereby forming structure three.

[0419] In step 4, as shown in FIG73 , the first trench 20 is etched on the basis of structure 3 to form structure 4.

[0420] Step 5, as shown in Figure 74, based on structure 4, inject 1100℃ gas O 2 , generating 0.12um thick silicon dioxide as insulating oxide insulating layer 70, thereby forming structure five.

[0421] In step 6, as shown in FIG75 , based on structure five, 0.8 μm thick polysilicon 71 is deposited into the first trench 20 and on the flat surface, and the excess polysilicon 71 is etched away to form structure six.

[0422] Step 7, as shown in FIG75 , is to implant impurity boron ions based on structure 6 with an energy of 100 kev and a dose of 2e13 cm - 2The high temperature well-push-in process uses N2 gas at a temperature of 1150° C. for 80 minutes to form the base layer 109, thereby forming structure seven.

[0423] In step 8, as shown in FIG65 , a 1 μm thick silicon dioxide layer is deposited on the basis of structure 7 as a dielectric layer 13, thereby forming a semiconductor device 100. It should be noted that the semiconductor device 100 provided with a carrier storage layer 110 is used as an example here. The specific manufacturing process of a semiconductor device 100 without a carrier storage layer 110 is similarly obtainable and is not further described here.

[0424] The semiconductor device 100 in some embodiments of the present disclosure is described below with reference to Figures 77 to 86. In the following description, N and P represent the conductivity type of the semiconductor. In some embodiments of the present disclosure, the first conductivity type is set to N type and the second conductivity type is set to P type.

[0425] As shown in Figures 77 to 82 , the semiconductor device 100 includes a semiconductor substrate 810, a drift layer 10, a ring layer 107, and a main trench portion 213. The semiconductor substrate 810 has a first main surface 81 and a second main surface 82 opposite the first main surface 81. The ring layer 107 is disposed on the side of the drift layer 10 facing the first main surface 81. The surface of the ring layer 107 facing away from the drift layer 10 constitutes a portion of the first main surface 81. The main trench portion 213 is disposed in the ring layer 107 and extends in a first direction. The first direction is perpendicular to the second direction.

[0426] In some embodiments, the ring layer 107 and the drift layer 10 are both located between the first main surface 81 and the second main surface 82. The ring layer 107 is disposed on the side of the drift layer 10 facing the first main surface 81, and the surface of the ring layer 107 facing away from the drift layer 10 constitutes part of the first main surface 81. Furthermore, an oxide insulating layer 70, a polycrystalline layer 111, and an interlayer dielectric layer 1304 are stacked above the ring layer 107. A field stop layer 15 and a collector layer 16 are disposed below the drift layer 10.

[0427] Furthermore, the ring layer 107 is provided with a main trench portion 213, which extends in the first direction, so that a gate can be formed in the main trench portion 213. In addition, an emitter metal layer 14 is provided on the interlayer dielectric layer 1304, and a collector metal layer 18 is provided below the collector layer 16, thereby forming the basic structure of the semiconductor device 100 and ensuring normal operation of the semiconductor device 100.

[0428] In some embodiments, the main trench portion 213 may include a plurality of gate trench groups 21 and a plurality of dummy gate trench portions 221. The plurality of gate trench groups 21 are spaced apart in the second direction. At least one dummy gate trench portion 221 is provided between two adjacent gate trench groups 21. The gate trench group 21 includes at least two gate trench portions 211 spaced apart in the second direction.

[0429] Both the gate groove portion 211 and the dummy gate groove portion 221 are provided with an oxide insulating layer 70, and polysilicon 71 is deposited, but the first conductive type dopant is injected into the gate groove portion 211, and a second conductive type well layer 11 is provided. A gate can be formed at the gate groove portion 211, and it has a conductive channel 4 and a current-carrying capability to ensure the normal operation of the semiconductor device 100. The first conductive type dopant is not injected into the dummy gate groove portion 221, and the second conductive type well layer 11 is not provided. It does not have a conductive channel 4 and does not have a current-carrying capability. The dummy gate groove portion 221 can be connected to the emitter to reduce the Miller capacitance and reduce the current density.

[0430] At least two gate trench portions 211 form a gate trench group 21, at least one dummy gate trench portion 221 forms a dummy gate trench group 22, and both the gate trench group 21 and the dummy gate trench group 22 are arranged in plurality, and the plurality of gate trench groups 21 and the plurality of dummy gate trench groups 22 are alternately arranged in sequence in the second direction. In this way, the arrangement of the plurality of gate trench portions 211 and the plurality of dummy gate trench portions 221 in the second direction can be more reasonable, thereby improving the working performance of the semiconductor device 100 in some embodiments.

[0431] As shown in Figures 77, 78 and 82, the semiconductor device 100 also includes a connecting groove portion 214, which is arranged in the ring layer 107 and extends in the second direction. The connecting groove portion 214 is located at the edge of the active area 101 of the semiconductor device 100. The connecting groove portion 214 connects at least one end of at least two gate groove portions 211 in each gate groove group 21.

[0432] Since at least two gate trench portions 211 in each gate trench group 21 are spaced apart in the second direction, that is, the ends of at least two gate trench portions 211 in each gate trench group 21 are also spaced apart in the second direction. Therefore, considering that the electric field distribution is relatively concentrated and uneven in the region where the ends of the gate trench portions 211 are located, which can easily lead to electrostatic protection failure and low dielectric breakdown withstand voltage, the connecting trench portion 214 is disposed in the ring layer 107, extending in the second direction, and located at the edge of the active area 101 of the semiconductor device 100. The connecting trench portion 214 connects at least one end of the at least two gate trench portions 211 in each gate trench group 21. Thus, within each gate trench group 21, the connecting trench portion 214 can surround at least one end of the at least two gate trench portions 211 in the first direction, connecting the connecting trench portion 214 to the at least two gate trench portions 211 in each gate trench group 21.

[0433] On the one hand, the connecting groove portion 214 surrounds the outside of the end portions of at least two gate groove portions 211 in each gate groove group 21, which can optimize the electric field distribution at the end portions of at least two gate groove portions 211 in each gate groove group 21, making the electric field distribution at the end portions of at least two gate groove portions 211 in each gate groove group 21 more uniform, thereby effectively improving the electrostatic protection capability of the semiconductor device 100, avoiding electrostatic failure of the semiconductor device 100 at the end portions of the main groove portion 213, and improving the insulation withstand voltage breakdown capability of the semiconductor device 100, thereby improving the reliability of the semiconductor device 100.

[0434] On the other hand, the connecting trench portion 214 can serve as a gate path, thereby increasing the gate path, improving the turn-on speed of the semiconductor device 100 , and reducing turn-on loss.

[0435] Therefore, by setting the connecting groove portion 214, the connecting groove portion 214 is set in the ring layer 107 and extended in the second direction, the connecting groove portion 214 is located at the edge of the active area 101 of the semiconductor device 100, and the connecting groove portion 214 connects at least one end of at least two gate groove portions 211 in each gate groove group 21. This can not only optimize the electric field distribution of the semiconductor device 100, improve the electrostatic protection capability and insulation breakdown withstand voltage capability of the semiconductor device 100, but also improve the turn-on speed of the semiconductor device 100 and reduce the turn-on loss.

[0436] In some embodiments, as shown in FIG82 , both ends of at least two gate trench portions 211 in each gate trench group 21 are provided with connecting trench portions 214. The gate trench portion 211 has two ends in the first direction. By providing connecting trench portions 214 at both ends of at least two gate trench portions 211 in each gate trench group 21, the connecting trench portion 214 at one end can connect one end of the at least two gate trench portions 211, thereby connecting them to each other, and the connecting trench portion 214 at the other end can connect the other ends of the at least two gate trench portions 211, thereby connecting all ends of each gate trench group 21 to the connecting trench portion 214, thereby avoiding the existence of unconnected ends of each gate trench group 21. This can optimize the electric field distribution of the semiconductor device 100, improve the electrostatic protection capability and dielectric breakdown capability of the semiconductor device 100, and increase the turn-on speed of the semiconductor device 100.

[0437] It should be noted that the semiconductor device 100 is provided with a gate pad 104, which is used to be connected to the gate and serves as a gate lead-out terminal. The gate groove portion 211 and the dummy gate groove portion 221 are disconnected at the gate pad 104. Therefore, a connecting groove portion 214 can also be provided at the end of the gate groove group 21 close to the gate pad 104, so that the connecting groove portion 214 connects the end of the gate groove group 21 close to the gate pad 104, thereby more reliably improving the electrostatic protection capability of the semiconductor device 100 and improving the turn-on speed of the semiconductor device 100.

[0438] In some embodiments, a dummy gate trench portion 221 is disposed between at least two gate trench portions 211 in each gate trench group 21. The length of the dummy gate trench portion 221 in the first direction is less than or equal to the length of the gate trench portion 211, thereby preventing the dummy gate trench portion 221 from affecting the connection between at least one end of the at least two gate trench portions 211 in each gate trench group 21 by the connecting trench portion 214.

[0439] In some embodiments, as shown in FIG82 , each gate trench group 21 includes two gate trench portions 211, and a connecting trench portion 214 connects at least one end of the two gate trench portions 211 in each gate trench group 21. This can make the number of gate trench portions 211 in each gate trench group 21 more reasonable and facilitate the arrangement of the connecting trench portion 214.

[0440] In some embodiments, as shown in FIG. 77 to FIG. 79 , the connecting trench portion 214 connects at least one end of the plurality of gate trench groups 21 .

[0441] When the connecting groove portion 214 connects at least two gate groove portions 211 in each gate groove group 21, although the electric field distribution of the semiconductor device 100 can be optimized to a certain extent and the electrostatic protection capability and insulation breakdown capability of the semiconductor device 100 can be improved, the multiple gate groove groups 21 are still in an unconnected state, and each gate groove group 21 still has an end area in the second direction, and the electric field will still be concentrated here. The electrostatic protection capability and insulation breakdown capability of the semiconductor device 100 still need to be improved.

[0442] By making the connecting groove portion 214 connect at least one end of multiple gate groove groups 21, it is convenient to connect the connecting groove portion 214 with at least one end of all gate groove portions 211 of the semiconductor device 100, so that the connecting groove portion 214 can surround at least one end of all gate groove portions 211 of the semiconductor device 100, and the connecting groove portion 214 is connected to at least one end of all gate groove portions 211 of the semiconductor device 100.

[0443] On the one hand, the connecting groove portion 214 surrounds the outside of the end portions of all the gate groove portions 211, which can not only optimize the electric field distribution at the end portions of all the gate groove portions 211, making the electric field distribution at the end portions of all the gate groove portions 211 more uniform and avoiding electric field concentration at the end portions of all the gate groove portions 211, but also increase the gate oxide thickness at the end portions of all the gate groove portions 211, thereby effectively improving the electrostatic protection capability of the semiconductor device 100, avoiding electrostatic failure of the semiconductor device 100 at the end portions of the gate groove portions 211, and improving the reliability of the semiconductor device 100.

[0444] On the other hand, the connecting groove portion 214 can serve as a gate path, thereby increasing the gate path, improving the turn-on speed of the semiconductor device 100 , reducing turn-on loss, and improving the operating performance of the semiconductor device 100 .

[0445] On the other hand, in order to ensure the normal extraction of current, it is necessary to set a contact hole 171 in the semiconductor device 100. The contact hole 171 can connect the gate with other materials to realize the function of the circuit. By setting the connecting groove portion 214, the connecting groove portion 214 is connected to the end portions of multiple gate groove portions 211. In this way, under the premise of ensuring the normal operation of the semiconductor device 100, the contact hole 171 can be directly set in the connecting groove portion 214, which facilitates the manufacture of the contact hole 171 and reduces the manufacturing difficulty of the contact hole 171 and even the semiconductor device 100.

[0446] In this way, not only can the electric field distribution of the semiconductor device 100 be optimized and the electrostatic protection capability of the semiconductor device 100 be improved, but also the turn-on speed of the semiconductor device 100 can be increased, the turn-on loss can be reduced, and the manufacturing difficulty of the semiconductor device 100 can be reduced.

[0447] In some embodiments, as shown in Figures 77 to 79, the length of the gate groove portion 211 in the first direction is greater than the length of the dummy gate groove portion 221 in the first direction, the two ends of the gate groove portion 211 in the first direction protrude from the two ends of the dummy gate groove portion 221 in the first direction, and the connecting groove portion 214 is in the shape of a long strip and is spaced apart from the dummy gate groove portion 221.

[0448] Considering that the dummy gate groove portion 221 has no conductive ability, the end of the dummy gate groove portion 221 will not experience electrostatic failure. When the length of the gate groove portion 211 in the first direction is greater than the length of the dummy gate groove portion 221 in the first direction, and the two ends of the gate groove portion 211 in the first direction protrude from the two ends of the dummy gate groove portion 221 in the first direction, it is only necessary to connect the connecting groove portion 214 with each gate groove group 21, without connecting multiple dummy gate groove groups 22. The connecting groove portion 214 is in a long strip shape and is spaced apart from the dummy gate groove portion 221, which can improve the electrostatic protection capability of the semiconductor device 100 and the turn-on speed of the semiconductor device 100, thereby reducing the manufacturing cost of the semiconductor device 100.

[0449] In other embodiments, the connecting trench portion 214 connects at least one end of the plurality of gate trench groups 21 and the plurality of dummy gate trench portions 221. That is, the connecting trench portion 214 can connect at least one end of all the main trench portions 213. This facilitates the creation of the connecting trench portion 214 while optimizing the electric field distribution of the semiconductor device 100, thereby reducing the difficulty of manufacturing the semiconductor device 100.

[0450] In some embodiments, the length of the dummy gate trench portion 221 in the first direction is equal to the length of the gate trench portion 211 in the first direction, and both ends of the gate trench portion 211 in the first direction are flush with both ends of the dummy gate trench portion 221. In this way, the connecting trench portion 214 can be directly connected between the ends of the gate trench portion 211 and the ends of the dummy gate trench portion 221, so that the connecting trench portion 214 passes through the active area 101 of the semiconductor device 100 in the first direction, making the structure of the semiconductor device 100 simpler and more reliable.

[0451] In some other embodiments, the connecting trench portion 214 connects at least one end of the plurality of dummy gate trench portions 221. When the connecting trench portion 214 connects at least one end of the plurality of gate trench portions 211 in each gate trench group 21, the connecting trench portion 214 may also connect at least one end of the plurality of dummy gate trench portions 221 between two adjacent gate trench groups 21. In this way, on the one hand, the connecting trench portion 214 can optimize the electric field distribution at at least one end of the plurality of dummy gate trench portions 221, avoid electric field concentration, and improve the reliability of the semiconductor device 100. On the other hand, it can also facilitate the separate design of the connecting trench portion 214 and the dummy gate trench portion 221, thereby expanding the application scenarios of the semiconductor device 100.

[0452] In some embodiments, the length of the dummy gate trench portion 221 in the first direction is greater than the length of the gate trench portion 211 in the first direction, and both ends of the dummy gate trench portion 221 in the first direction protrude beyond both ends of the gate trench portion 211 in the first direction. In this way, a separate connecting trench portion 214 can be provided within each gate trench group 21, and a separate connecting trench portion 214 can be provided between the multiple dummy gate trench portions 221 between two adjacent gate trench groups 21, thereby preventing the two from interfering with each other and ensuring the electrostatic protection capability and dielectric breakdown withstand voltage capability of the semiconductor device 100.

[0453] In some embodiments, in combination with Figures 80 and 81, the main groove portion 213 and the connecting groove portion 214 are both extended in the direction from the first main surface 81 toward the second main surface 82. In the direction from the first main surface 81 to the second main surface 82, the depth of the main groove portion 213 is L1, and the depth of the connecting groove portion 214 is L2. L1 and L2 satisfy the relationship: L1≤L2.

[0454] By setting the depth of the connecting groove portion 214 to be greater than or equal to the depth of the main groove portion 213 in the direction from the first main surface 81 to the second main surface 82, the connecting groove portion 214 can completely connect the main groove portion 213 in the direction from the first main surface 81 to the second main surface 82, thereby avoiding insufficient depth of the connecting groove portion 214, and the bottom of the main groove portion 213 is not connected to the connecting groove portion 214, resulting in uneven electric field distribution below the main groove portion 213, and the electrostatic protection of the semiconductor device 100 is still prone to failure. In this way, the optimization of the electric field at each position of the end of the main groove portion 213 can be guaranteed, thereby improving the electrostatic protection capability of the semiconductor device 100.

[0455] In some embodiments, as shown in Figures 80 and 81, the width of the main groove portion 213 in the second direction is W1, and the width of the connecting groove portion 214 in the first direction is W2, and W1 and W2 satisfy the relationship: W1≤W2.

[0456] The width of the connecting groove portion 214 in the first direction can affect the path size of the connecting groove portion 214. By setting the width of the connecting groove portion 214 in the first direction to be greater than or equal to the width of the main groove portion 213 in the second direction, the path capacity of the connecting groove portion 214 can be increased while increasing the gate path through the connecting groove portion 214, thereby improving the turn-on speed of the semiconductor device 100 and reducing the loss of the semiconductor device 100.

[0457] In some embodiments, in the direction from the first main surface 81 to the second main surface 82, the depth of the connecting groove portion 214 can be the same as the depth of the main groove portion 213, and the width of the connecting groove portion 214 in the first direction can be the same as the width of the main groove portion 213 in the second direction. In this way, while improving the electrostatic protection capability of the semiconductor device 100 and improving the switching speed of the semiconductor device 100, the synchronous etching of the main groove portion 213 and the connecting groove portion 214 can be facilitated, and the structures are the same or almost the same, thereby reducing processing complexity and improving production efficiency.

[0458] In some embodiments, as shown in conjunction with FIG80 and FIG81 , the main trench portion 213 and the connecting trench portion 214 are both spaced apart from the drift layer 10. The main trench portion 213 and the connecting trench portion 214 are etched and formed on the ring layer 107. By spaced apart from the drift layer 10, that is, by not penetrating the ring layer 107, the main trench portion 213 and the connecting trench portion 214 are spaced apart from the drift layer 10. This ensures that the field ring layer 107 exists between the main trench portion 213 and the connecting trench portion 214 and the drift layer 10, thereby ensuring the electrical performance of the semiconductor device 100.

[0459] In some embodiments, as shown in Figures 77 and 78, the semiconductor base 810 may include an active area 101 and a terminal area 103, the terminal area 103 is arranged around the outside of the active area 101, the main groove portion 213 is arranged in the active area 101, and the connecting groove portion 214 is located between the active area 101 and the terminal area 103.

[0460] The active region 101 can bear most of the forward current during forward conduction and can also bear a high blocking voltage when a reverse voltage is applied. When a reverse voltage is applied to the semiconductor device 100, the terminal region 103 can alleviate the electric field crowding at the edge of the active region 101, thereby improving the reverse breakdown voltage of the semiconductor device 100.

[0461] In some embodiments, the main trench portion 213 is disposed in the active region 101, with the end of the main trench portion 213 located between the active region 101 and the terminal region 103. In this manner, the connecting trench portion 214 can block the diffusion of the electric field in the active region 101, thereby more effectively and reliably preventing the failure of electrostatic protection in the region between the active region 101 and the terminal region 103, thereby improving the electrostatic protection capability of the semiconductor device 100.

[0462] The following describes a method for manufacturing the semiconductor device 100 by way of example with reference to FIG. 83 to FIG. 86 . The method includes the following steps:

[0463] Step 1, as shown in FIG83 , provides a substrate 2 , which is an N-type drift layer 10 , and implants a P-type dopant into the substrate 2 to form an N-type drift layer 10 and a P-type ring layer 107 .

[0464] In step 2, as shown in FIG. 84 , a connection groove portion 214 is etched in the ring layer 107 , and an oxidized insulating layer 70 is grown above the ring layer 107 .

[0465] In step 3, as shown in FIG85 , polysilicon 71 is deposited and polycrystalline etching is performed on the oxidized insulating layer 70 to form a polycrystalline layer 111 .

[0466] In step 4, as shown in FIG86 , an interlayer dielectric is grown above the polycrystalline layer 111 to form an interlayer dielectric layer 1304 , metal sputtering is performed above the interlayer dielectric layer 1304 to form an emitter metal layer 14 , and a field stop layer 15 , a collector layer 16 and a collector metal layer 18 are prepared below the drift layer 10 to finally form a semiconductor device 100 .

[0467] It should be noted that this preparation method only uses the preparation of the connection groove portion 214 as an example. While etching the connection groove portion 214 on the ring layer 107, the main groove portion 213 can be simultaneously etched, which is not described in detail here. In addition, this preparation method only illustrates a portion of the preparation process. The other structures and operations of the semiconductor device 100 according to some embodiments of the present disclosure are well known to those skilled in the art and will not be described in detail here.

[0468] The following describes a semiconductor device 100 according to some embodiments of the present disclosure with reference to Figures 87 to 98 . This semiconductor device 100 may be an RC-IGBT. In the following description, N and P represent the conductivity type of the semiconductor. In some embodiments of the present disclosure, the first conductivity type is N-type and the second conductivity type is P-type.

[0469] 87 to 91 , the semiconductor device 100 includes a substrate 80 , a drift layer 10 of a first conductivity type, a first trench 20 , and a second trench 30 .

[0470] In some embodiments, a drift layer 10 of the first conductivity type is disposed within a substrate 80 and is located between a first major surface 81 and a second major surface 82. A well layer 11 of the second conductivity type is further disposed within the substrate 80. The well layer 11 is disposed on a side of the drift layer 10 close to the first major surface 81. An emitter layer 3 of the first conductivity type is further disposed within the well layer 11. Furthermore, a field stop layer 15 of the first conductivity type is further disposed within the substrate 80. The field stop layer 15 is disposed on a side of the drift layer 10 close to the second major surface 82. A collector layer 16 of the second conductivity type and a short-circuit region 112 of the first conductivity type are disposed on the side of the field stop layer 15 close to the second major surface 82. A dielectric layer 13 is disposed on the first major surface 81. An emitter metal layer 14 is disposed on a side of the dielectric layer 13 facing away from the first major surface 81. A collector metal layer 18 is further disposed on the second major surface 82 of the substrate 80.

[0471] The semiconductor device 100 may include an active area 101 and a terminal area 103 arranged outside the active area 101. The collector layer 16 and the short-circuit area 112 are both located in the active area 101. The emitter metal layer 14 can not only serve as the emitter lead-in terminal of the area corresponding to the collector layer 16, but also serve as the anode lead-in terminal of the area corresponding to the short-circuit area 112. The collector metal layer 18 can not only serve as the collector lead-in terminal of the area corresponding to the collector layer 16, but also serve as the cathode lead-in terminal of the area corresponding to the short-circuit area 112. In this way, the area corresponding to the collector layer 16 can realize forward conduction of the semiconductor device 100, and the area corresponding to the short-circuit area 112 can realize reverse conduction of the semiconductor device 100, so that the semiconductor device 100 has both forward conduction and reverse conduction characteristics.

[0472] In some embodiments, the first trench 20 is located in the area corresponding to the collector layer 16, the first trench 20 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10, and the first trench 20 is extended in the first direction. By setting the first trench 20 as multiple, the multiple first trenches 20 are spaced apart in the second direction, and the oxide insulation layer 70 and the polysilicon 71 are sequentially arranged in the first trench 20, the normal operation of the area corresponding to the collector layer 16 and even the semiconductor device 100 can be ensured.

[0473] In addition, a portion of the multiple first trenches 20 is a first spacing trench 23, there are multiple first spacing trenches 23, the first spacing trench 23 may include a first sub-trench 231 and a second sub-trench 212 spaced apart in the first direction, and the second trench 30 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10, the second trench 30 extends in the first direction, and the second trench 30 is at least partially located in the area corresponding to the short-circuit zone 112.

[0474] The region where the multiple first trenches 20 are located is defined as the insulated gate bipolar transistor region 1015, and the region where the multiple second trenches 30 are located is defined as the fast recovery diode region 1018. By setting the second trenches 30 in multiple numbers and corresponding to the multiple first spacing trenches 23, not only can the junction depth and doping concentration of the well layer 11 of the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 be the same, ensuring that the two regions have the same withstand voltage, but also the process steps of the semiconductor device 100 can be simplified, thereby simplifying the manufacturing process of the semiconductor device 100.

[0475] Furthermore, by spacing the second trench 30 between the first sub-trench 231 and the second sub-trench 212, the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 can be disconnected, thereby disconnecting the region corresponding to the short-circuit region 112 and the region corresponding to the collector layer 16, thereby ensuring the performance of each of the two regions and ensuring the working performance of the semiconductor device 100.

[0476] As shown in Figures 89 to 91, the semiconductor device 100 may further include a first connecting trench 40, which extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The first connecting trench 40 is extended in the second direction. There are two first connecting trenches 40, one of the two first connecting trenches 40 connects one end of the multiple second trenches 30, and the other connects the other end of the multiple second trenches 30.

[0477] In some embodiments, one ends of the plurality of second trenches 30 are flush with each other, and the other ends of the plurality of second trenches 30 are flush with each other. By providing a first connecting trench 40, the first connecting trench 40 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The first connecting trench 40 extends in the second direction, and two first connecting trenches 40 are provided. In this way, one of the two first connecting trenches 40 can extend in the second direction while connecting one ends of the plurality of second trenches 30, and the other of the two first connecting trenches 40 can extend in the second direction while connecting the other ends of the plurality of second trenches 30, so that the two first connecting trenches 40 can enclose the plurality of second trenches 30, that is, the two first connecting trenches 40 can separate the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, thereby preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process, ensuring the performance of the two regions, ensuring the working performance of the semiconductor device 100, and improving the reliability of the semiconductor device 100.

[0478] Thus, by connecting one end of the plurality of second trenches 30 with one of the two first connecting trenches 40 and connecting the other end of the plurality of second trenches 30 with the other of the two first connecting trenches 40, the first connecting trench 40 can enclose the plurality of second trenches 30, separate the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, prevent the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process, ensure the performance of each of the two regions, and ensure the reliability of the semiconductor device 100.

[0479] In some embodiments, in combination with Figure 89, one of the multiple second trenches 30 that is adjacent to the first trench 20 on one side in the second direction is defined as a first boundary trench 361, and one of the multiple second trenches 30 that is adjacent to the first trench 20 on the other side in the second direction is defined as a second boundary trench 362. In this way, the area enclosed by the first boundary trench 361, the second boundary trench 362 and the two first connecting trenches 40 is the fast recovery diode region 1018. The two first connecting trenches 40 can serve as the boundaries of the fast recovery diode region 1018 in the first direction, thereby achieving the enclosed fast recovery diode region 1018, preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process, ensuring the performance of the two regions, and ensuring the reliability of the semiconductor device 100.

[0480] In some embodiments, in combination with what is shown in FIG89 , one of the two first connection trenches 40 corresponding to the first sub-trench 231 is spaced apart from the first sub-trench 231, and one of the two first connection trenches 40 corresponding to the second sub-trench 212 is spaced apart from the second sub-trench 212. By so arranging, the first connection trench 40 can be spaced apart from the insulated gate bipolar transistor region 1015, thereby spaced apart from the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, ensuring that the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 can be separated, and the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 can be more reliably prevented from interfering with each other in the process, thereby ensuring the respective performance of the two regions and ensuring the structural reliability of the semiconductor device 100.

[0481] In some embodiments, in combination with Figures 89 and 90, the semiconductor device 100 also includes a second connecting trench 50, which extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10, and is extended in the second direction. There are two second connecting trenches 50, one of the two second connecting trenches 50 connects one end of the multiple first sub-trenches 231 adjacent to the second trench 30, and the other connects one end of the multiple second sub-trenches 212 adjacent to the second trench 30.

[0482] Since the second groove 30 is arranged between the first sub-groove 231 and the second sub-groove 212, that is, the first sub-groove 231 has an end adjacent to the second groove 30, the second sub-groove 212 has an end adjacent to the second groove 30, and the ends of the multiple first sub-grooves 231 adjacent to the second groove 30 are flush with each other, and the ends of the multiple second sub-grooves 212 adjacent to the second groove 30 are flush with each other.

[0483] By setting two second connecting grooves 50, the second connecting grooves 50 extend from the surface of the drift layer 10 toward the inside of the drift layer 10, and the second connecting grooves 50 extend in the second direction. In this way, while one of the two second connecting grooves 50 extends in the second direction, multiple first sub-grooves 231 adjacent to one end of the second groove 30 can be connected. While the other of the two second connecting grooves 50 extends in the second direction, multiple second sub-grooves 212 adjacent to one end of the second groove 30 can be connected. In this way, the first sub-grooves 231 of the insulated gate bipolar transistor region 1015 can be connected, and the second sub-grooves 212 of the insulated gate bipolar transistor region 1015 can be connected, thereby ensuring the normal operation of the insulated gate bipolar transistor region 1015.

[0484] In some embodiments, in combination with Figures 88 and 89, the multiple first grooves 20 may include multiple first main grooves 24 and multiple first spacing grooves 23, and the multiple first main grooves 24 are respectively located on both sides of the multiple first spacing grooves 23 in the second direction, and the two ends of the second connecting groove 50 in the second direction are respectively connected to the first main grooves 24 on both sides.

[0485] One of the multiple first main trenches 24 that is adjacent to the multiple first spacing trenches 23 on one side in the second direction is a third boundary trench 241, and one of the multiple first main trenches 24 that is adjacent to the multiple first spacing trenches 23 on the other side in the second direction is a fourth boundary trench 242. The outside of the area enclosed by the third boundary trench 241, the fourth boundary trench 242 and the two second connecting trenches 50 is the insulated gate bipolar transistor area 1015, and the inside of the area enclosed by the third boundary trench 241, the fourth boundary trench 242 and the two second connecting trenches 50 is the fast recovery diode area 1018.

[0486] By connecting the two ends of the second connecting trench 50 in the second direction to the first main trenches 24 on both sides, that is, connecting the two ends of the second connecting trench 50 in the second direction to the third boundary trench 241 and the fourth boundary trench 242, respectively, the second connecting trench 50 can connect the multiple first spacing trenches 23 and the first main trench 24, thereby ensuring the normal operation of the IGBT region 1015 and even the semiconductor device 100. On the other hand, the area outside the area enclosed by the third boundary trench 241, the fourth boundary trench 242, and the two second connecting trenches 50 is the IGBT region 1015. In this way, the two second connecting trenches 50 can serve as the boundaries of the IGBT region 1015 in the first direction, better separating the IGBT region 1015 from the fast recovery diode region 1018. In some embodiments, this can prevent mutual interference between the IGBT region 1015 and the fast recovery diode region 1018 during the manufacturing process, thereby improving the reliability of the semiconductor device 100.

[0487] In some embodiments, as shown in FIG89 , a portion of the second trench 30 is a second spacing trench 35. The second spacing trench 35 includes a third sub-trench 351, a fourth sub-trench 352, and a fifth sub-trench 353. The third sub-trench 351 and the fifth sub-trench 353 are respectively disposed at opposite ends of the fourth sub-trench 352 in the first direction and are spaced apart from the fourth sub-trench 352. The fourth sub-trench 352 is located in a region corresponding to the short-circuit region 112, and the region corresponding to the short-circuit region 112 is defined as the main conductive region 1016 of the fast recovery diode.

[0488] By respectively arranging the third sub-trench 351 and the fifth sub-trench 353 at the two ends of the fourth sub-trench 352 in the first direction and spaced apart from the fourth sub-trench 352, the fast recovery diode region 1018 can be divided, thereby avoiding mutual interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016 in the process, and ensuring the respective performance of the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016.

[0489] In some embodiments, in combination with Figures 89 and 90, the semiconductor device 100 also includes a third connecting trench 113, which extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10, and is extended in the second direction. There are two third connecting trenches 113, one of the two third connecting trenches 113 connects one end of the multiple fourth sub-trenches 352, and the other connects the other end of the multiple fourth sub-trenches 352.

[0490] One ends of the multiple fourth sub-grooves 352 are flush with each other, and the other ends of the multiple fourth sub-grooves 352 are flush with each other. By setting the third connecting groove 113, one of the two third connecting grooves 113 can be extended in the second direction while connecting one ends of the multiple fourth sub-grooves 352, and the other of the two third connecting grooves 113 can be extended in the second direction while connecting the other ends of the multiple fourth sub-grooves 352.

[0491] In this way, not only can the multiple fourth sub-trenches 352 be connected to ensure the normal operation of the fast recovery diode main conductive region 1016, but the multiple fourth sub-trenches 352 can also be enclosed, that is, the two third connecting trenches 113 can enclose the fast recovery diode main conductive region 1016, thereby separating the fast recovery diode main conductive region 1016 and the insulated gate bipolar transistor region 1015, more effectively and reliably avoiding mutual interference between the fast recovery diode main conductive region 1016 and the insulated gate bipolar transistor region 1015 in the process, and ensuring the performance of each of the two regions, thereby ensuring the working performance of the semiconductor device 100.

[0492] In some embodiments, as shown in Figures 88 and 89, one of the two third connecting grooves 113 connects the multiple third sub-grooves 351 adjacent to one end of the fourth sub-groove 352, and the other connects the multiple fifth sub-grooves 353 adjacent to one end of the fourth sub-groove 352.

[0493] Since the third sub-groove 351, the fourth sub-groove 352 and the fifth sub-groove 353 are arranged in sequence in the first direction, the third sub-groove 351 has an end adjacent to the fourth sub-groove 352, the fifth sub-groove 353 has an end adjacent to the fourth sub-groove 352, and the ends of the multiple third sub-grooves 351 adjacent to the fourth sub-groove 352 are flush with each other, and the ends of the multiple fifth sub-grooves 353 adjacent to the fourth sub-groove 352 are flush with each other.

[0494] By extending one of the two third connecting grooves 113 in the second direction and connecting the multiple third sub-grooves 351 adjacent to one end of the fourth sub-grooves 352, and by extending the other of the two third connecting grooves 113 in the second direction and connecting the multiple fifth sub-grooves 353 adjacent to one end of the fourth sub-grooves 352, the multiple third sub-grooves 351 and the multiple fifth sub-grooves 353 can be connected, thereby avoiding interference between the processes of the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016.

[0495] In some embodiments, two fourth sub-grooves 352 on both sides of the second direction of the plurality of fourth sub-grooves 352 are defined as the fifth boundary groove 3521 and the sixth boundary groove 3522, respectively. In this way, the fifth boundary groove 3521, the sixth boundary groove 3522 and the two third connection grooves 113 are all located in the fast recovery diode area 1018, and the area enclosed by the fifth boundary groove 3521, the sixth boundary groove 3522 and the two third connection grooves 113 is the fast recovery diode main conductive area 1016, and the part of the fast recovery diode area 1018 located outside the fast recovery diode main conductive area 1016 is the fast recovery diode transition area 1017.

[0496] In this case, the active region 101 of the semiconductor device 100 includes an insulated gate bipolar transistor region 1015, a fast recovery diode main conductive region 1016, and a fast recovery diode transition region 1017. The first connection trench 40, the third connection trench 113, and the fast recovery diode transition region 1017 can work together to separate the insulated gate bipolar transistor region 1015 from the fast recovery diode main conductive region 1016, thereby more effectively and reliably avoiding mutual interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016 during the manufacturing process, ensuring the performance of the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016, and thereby improving the reliability of the semiconductor device 100.

[0497] In some embodiments, as shown in Figure 91, the dielectric layer 13 includes a first dielectric layer 1305 and a second dielectric layer 1306. The first dielectric layer 1305 corresponds to the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016, and the second dielectric layer 1306 corresponds to the fast recovery diode transition region 1017. A plurality of spaced contact holes 171 are provided on the first dielectric layer 1305. The emitter metal layer 14 passes through the contact holes 171 and contacts the first main surface 81. The second dielectric layer 1306 is a continuous layer and blocks the emitter metal layer 14 and the first main surface 81.

[0498] The dielectric layer 13 can protect the well layer 11 and reduce the risk of damage to the semiconductor device 100. By making the first dielectric layer 1305 correspond to the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016, and opening a plurality of spaced contact holes 171 on the first dielectric layer 1305, the emitter metal layer 14 can penetrate the contact holes 171 and contact the emitter metal layer 14 or the well layer 11 on the first main surface 81, thereby ensuring the normal conduction of current from the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016, and ensuring the normal operation of the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016.

[0499] By making the second dielectric layer 1306 correspond to the fast recovery diode transition region 1017 and setting the second dielectric layer 1306 as a continuous layer, the dielectric layer 13 can be blocked between the emitter metal layer 14 and the first main surface 81. In this way, the dielectric layer 13 can more reliably protect the first main surface 81 of the transition region 102, thereby improving the structural reliability of the fast recovery diode transition region 1017.

[0500] In some embodiments, in combination with Figure 89, at least a portion of one of the two first connecting grooves 40 connects the third sub-groove 351 away from one end of the fourth sub-groove 352, and at least a portion of the other of the two first connecting grooves 40 connects the fifth sub-groove 353 away from one end of the fourth sub-groove 352.

[0501] In some embodiments, the second groove 30 may include a second main groove 36 and a second spacing groove 35, there are multiple second main grooves 36, and they are respectively located on both sides of the multiple second spacing grooves 35 in the second direction, one end of the multiple second main grooves 36 and the end of the third sub-groove 351 away from the fourth sub-groove 352 are flush with each other, and the other end of the multiple second main grooves 36 and the end of the fifth sub-groove 353 away from the fourth sub-groove 352 are flush with each other.

[0502] By making one of the two first connecting trenches 40 connect one end of the plurality of second trenches 30, and the other connect the other end of the plurality of second trenches 30, that is: when one of the two first connecting trenches 40 is extended in the second direction, it at least partially connects the plurality of third sub-trenches 351 away from one end of the fourth sub-trench 352, and its other part connects one end of the plurality of second main trenches 36, and when the other of the two first connecting trenches 40 is extended in the second direction, it at least partially connects the plurality of fifth sub-trenches 353 away from one end of the fourth sub-trench 352, and its other part connects the other end of the plurality of second main trenches 36, thereby ensuring that the first connecting trench 40 encloses the fast recovery diode main conductive region 1016 and the transition region 102, thereby ensuring the working performance of the semiconductor device 100.

[0503] It should be noted that the processes in the first trench 20, the second trench 30, the first connecting trench 40, the second connecting trench 50 and the third connecting trench 113 are the same, and an oxide insulating layer 70 can be generated therein and polysilicon 71 can be deposited. The widths and depths of the first trench 20, the second trench 30, the first connecting trench 40, the second connecting trench 50 and the third connecting trench 113 can be set to be the same, so that the first trench 20, the second trench 30, the first connecting trench 40, the second connecting trench 50 and the third connecting trench 113 can be etched synchronously, which can simplify the process steps of the semiconductor device 100.

[0504] In some embodiments, as shown in Figure 90, the spacing distance between the first connecting groove 40 and the second connecting groove 50 in the first direction is D9, and the spacing distance between the first connecting groove 40 and the third connecting groove 113 in the first direction is D10, and D9 and D10 satisfy the relationship: D9<D10.

[0505] The second connection trench 50 is located between the insulated gate bipolar transistor region 1015 and the fast recovery diode transition region 1017, the third connection trench 113 is located between the fast recovery diode transition region 1017 and the fast recovery diode main conductive region 1016, and the first connection trench 40 is located in the fast recovery diode transition region 1017 and between the second connection trench 50 and the third connection trench 113.

[0506] By setting the spacing distance between the first connecting groove 40 and the second connecting groove 50 in the first direction to be the same as the spacing distance between the multiple first grooves 20 in the second direction, the manufacture of the first connecting groove 40 and the second connecting groove 50 can be facilitated, and by setting the spacing distance between the first connecting groove 40 and the second connecting groove 50 in the first direction to be smaller than the spacing distance between the first connecting groove 40 and the third connecting groove 113 in the first direction, the area of ​​the fast recovery diode transition region 1017 can be increased, thereby enhancing the separation effect on the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016.

[0507] In some embodiments, D10 satisfies the relationship: D10 ≥ 30 μm. This allows the area of ​​the fast recovery diode transition region 1017 to be set within a reasonable range, preventing the fast recovery diode transition region 1017 from being too small. This allows for more effective and reliable separation of the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016, thereby preventing mutual interference between the two regions during manufacturing processes, ensuring the performance of each region, and improving the reliability of the semiconductor device 100.

[0508] It should be noted that the greater the spacing distance between the first connecting trench 40 and the third connecting trench 113 in the first direction, the better the separation effect on the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016 will be. However, it will also cause the overall area of ​​the semiconductor device 100 to increase. Therefore, in actual production, the appropriate spacing distance between the first connecting trench 40 and the third connecting trench 113 in the first direction can be selected according to the actual application scenario and requirements to achieve a balance between the separation effect between the insulated gate bipolar transistor region 1015 and the fast recovery diode main conductive region 1016 and the overall area of ​​the semiconductor device 100.

[0509] The following describes a method for manufacturing the semiconductor device 100 using an RC-IGBT as an example with reference to FIG. 92 to FIG. 98 . The method includes the following steps:

[0510] Step 1, as shown in FIG92 , provides an N-substrate 2 material to form structure 1.

[0511] Step 2, as shown in Figure 93, on the basis of structure one, the first trench 20, the second trench 30, the first connecting trench 40, the second connecting trench 50 and the third connecting trench 113 are etched, and an oxide insulating layer 70 is grown in the first trench 20, the second trench 30, the first connecting trench 40, the second connecting trench 50 and the third connecting trench 113 to form structure two.

[0512] Step 3, as shown in FIG94 , polysilicon 71 is deposited on the basis of structure 2 to form structure 3.

[0513] In step 4, as shown in FIG95 , based on structure three, polysilicon 71 is etched to form structure four.

[0514] Step 5, as shown in FIG96 , based on structure four, the P well layer 11 and the N+ emitter layer 3 are sequentially implanted to form structure five.

[0515] In step 6, as shown in FIG97 , a dielectric layer 13 is deposited on the basis of structure 5, and contact holes 171 are etched on the dielectric layer 13 to form structure 6.

[0516] In step 7, as shown in FIG98 , based on structure six, a metal layer is sputtered to prepare an emitter metal layer 14, and then the back N+ field stop layer 15 is injected, the back P+ collector layer 16 is injected, the back FRD region N+ short circuit region 112 is injected, laser annealing is performed, and the back metal is sputtered to prepare a collector metal layer 18, and finally a semiconductor device 100 as structure seven is formed.

[0517] The following describes a semiconductor device 100 according to some embodiments of the present disclosure with reference to Figures 99 to 108. This semiconductor device 100 may be an RC-IGBT. In the following description, N and P represent the conductivity type of the semiconductor. In some embodiments of the present disclosure, the first conductivity type is N-type and the second conductivity type is P-type.

[0518] 99 to 108 , the semiconductor device 100 includes a substrate 80 , a drift layer 10 of a first conductivity type, a first trench 20 , and a second trench 30 .

[0519] A drift layer 10 of the first conductivity type is disposed within a substrate 80 and is located between a first major surface 81 and a second major surface 82. A well layer 11 of the second conductivity type is also disposed within the substrate 80. The well layer 11 is disposed on the side of the drift layer 10 near the first major surface 81. A second emitter layer 12 of the first conductivity type is also disposed within the well layer 11. Furthermore, a field stop layer 15 of the first conductivity type is also disposed within the substrate 80. The field stop layer 15 is disposed on the side of the drift layer 10 near the second major surface 82. A collector layer 16 of the second conductivity type and a first emitter layer 17 of the first conductivity type are disposed on the side of the field stop layer 15 near the second major surface 82. A dielectric layer 13 is disposed on the first major surface 81. An emitter metal layer 14 is disposed on the side of the dielectric layer 13 facing away from the first major surface 81. A collector metal layer 18 is also disposed on the second major surface 82 of the substrate 80. This constitutes the basic structure of the semiconductor device 100.

[0520] The semiconductor device 100 may include an active region 101 and a terminal region 103 disposed on the periphery of the active region 101. The region corresponding to the collector layer 16 is an insulated gate bipolar transistor region 1015, and the region corresponding to the first emitter layer 17 is a fast recovery diode region 1018. That is, the active region 101 of the semiconductor device 100 may include the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018. The emitter metal layer 14 may not only serve as an emitter lead of the insulated gate bipolar transistor region 1015, but also as a gate electrode of the emitter lead ... The collector metal layer 18 can serve not only as the collector lead-in terminal of the insulated gate bipolar transistor region 1015, but also as the cathode lead-in terminal of the fast recovery diode region 1018. In this way, the insulated gate bipolar transistor region 1015 can realize forward conduction of the semiconductor device 100, and the fast recovery diode region 1018 can realize reverse conduction of the semiconductor device 100, so that the semiconductor device 100 has both forward conduction and reverse conduction characteristics.

[0521] In some embodiments, the first trench 20 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The first trench 20 extends in a first direction. A plurality of first trenches 20 are provided, and the plurality of first trenches 20 are spaced apart in a second direction. Some of the plurality of first trenches 20 are spacer trenches 201. The spacer trench 201 may include two sub-trench portions 2011 spaced apart in the first direction. The sub-trench portions 2011 may include a plurality of gate trench groups 21 and a plurality of dummy gate trenches 223. The plurality of gate trench groups 21 are spaced apart in the second direction, with at least one dummy gate trench 223 disposed between two adjacent gate trench groups 21. The gate trench group 21 includes at least two gate trenches 2221 spaced apart in the second direction.

[0522] Both the gate trench 2221 and the dummy gate trench 223 are provided with an oxide insulating layer 70 and deposited with polysilicon 71. The gate trench 2221 is provided with a second emitter layer 12 on both sides thereof in the second direction. The gate trench 2221 has a conductive channel 4 with current-carrying capability and can be electrically connected to the gate, ensuring normal operation of the insulated gate bipolar transistor region 1015 and, therefore, the semiconductor device 100. However, the dummy gate trench 223 is not provided with a second emitter layer 12 on both sides thereof in the second direction and does not have current-carrying capability. The dummy gate trench 223 can be electrically connected to the emitter, thereby reducing Miller capacitance and current density while ensuring the withstand voltage capability of the semiconductor device 100, thereby improving the short-circuit capability of the semiconductor device 100.

[0523] In some embodiments, the second trench 30 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The second trench 30 is extended in the first direction. The second trench 30 is provided in multiple and corresponds to the multiple first spacing trenches 23. This not only makes the junction depth and doping concentration of the well layer 11 of the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 the same, ensuring that the two regions have the same withstand voltage, but also simplifies the process steps of the semiconductor device 100. By spacing the second trench 30 between the two sub-trench portions 2011 in the first direction, the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 can be separated, thereby ensuring the performance of each of the two regions and ensuring the working performance of the semiconductor device 100.

[0524] In some embodiments, in combination with Figures 99 to 101, the semiconductor device 100 also includes a first connecting trench 40, which extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The first connecting trench 40 is extended in the second direction. There are two first connecting trenches 40, one of the two first connecting trenches 40 connects one end of the multiple second trenches 30 in the first direction, and the other connects the other end of the multiple second trenches 30 in the first direction.

[0525] One ends of the multiple second trenches 30 are flush with each other, and the other ends of the multiple second trenches 30 are flush with each other. By setting the first connecting trench 40, the first connecting trench 40 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The first connecting trench 40 extends in the second direction, and the first connecting trench 40 is set as two, so that one of the two first connecting trenches 40 can extend in the second direction while connecting one end of the multiple second trenches 30, and the other of the two first connecting trenches 40 can extend in the second direction while connecting the other end of the multiple second trenches 30.

[0526] On the one hand, the two first connection trenches 40 can enclose the multiple second trenches 30, that is, the two first connection trenches 40 can separate the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, thereby preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process, thereby ensuring the performance of each of the two regions. On the other hand, the two first connection trenches 40 can increase the current carrying capacity of the fast recovery diode region 1018, thereby improving the working performance of the semiconductor device 100 and improving the reliability of the semiconductor device 100.

[0527] In some embodiments, in combination with Figures 99 and 100, the semiconductor device 100 also includes: a second connecting trench 50, the second connecting trench 50 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10, the second connecting trench 50 is extended in the second direction, the second connecting trench 50 connects the gate trench 2221 in the gate trench group 21 adjacent to one end of the second trench 30, and connects the two adjacent gate trench groups 21 adjacent to one end of the second trench 30.

[0528] The gate trench 2221 in each gate trench group 21 is flush with one end adjacent to the second trench 30. By setting the second connecting trench 50, the second connecting trench 50 can connect one end of the gate trench 2221 in the gate trench group 21 adjacent to the second trench 30 when extending along the second direction, and the end portions of multiple gate trenches 2221 in two adjacent gate trench groups 21 adjacent to the second trench 30 are flush. While the second connecting trench 50 connects one end of the gate trench 2221 in the gate trench group 21 adjacent to the second trench 30, it can continue to extend to connect one end of the two adjacent gate trench groups 21 adjacent to the second trench 30.

[0529] That is, the second connecting trench 50 can connect all the gate trenches 2221 in the sub-trench portion 2011 to one end adjacent to the second trench 30, and the second connecting trench 50 can enclose all the gate trenches 2221 in the sub-trench portion 2011, thereby not only improving the current-carrying capacity of the insulated gate bipolar transistor region 1015 and even the semiconductor device 100, but also enclosing one end adjacent to the second trench 30 of the gate trench 2221 in each gate trench group 21, avoiding mutual interference between the gate trench group 21 and the second trench 30 in the process, and preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process, thereby ensuring the performance of the two regions.

[0530] Therefore, by making one of the two first connecting trenches 40 connect one end of the multiple second trenches 30 in the first direction, and the other connecting the other end of the multiple second trenches 30 in the first direction, and making the second connecting trench 50 connect the gate trench 2221 in the gate trench group 21 adjacent to the end of the second trench 30, and connecting the ends of the two adjacent gate trench groups 21 adjacent to the second trench 30, this not only prevents the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process and ensures the performance of the two regions, but also improves the current flow capacity of the semiconductor device 100, thereby improving the working performance of the semiconductor device 100.

[0531] In some embodiments, as shown in Figures 99 and 100, one end of the gate trench 2221 adjacent to the second trench 30 protrudes from one end of the dummy gate trench 223 adjacent to the second trench 30, and the dummy gate trench 223 and the second connecting trench 50 are spaced apart from each other in the first direction.

[0532] In this way, the second connecting trench 50 can separate the dummy gate trench 223 from the first connecting trench 40 in the first direction, thereby avoiding mutual interference between the dummy gate trench 223 and the first connecting trench 40 or the second trench 30 in the process, preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 in the process, and ensuring the performance of each of the two regions.

[0533] In some embodiments, the semiconductor device 100 may further include a third connecting trench 113, which extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The third connecting trench 113 extends in the second direction, and at least two dummy gate trenches 223 are arranged between two adjacent gate trench groups 21. The third connecting trench 113 connects one end of the dummy gate trench 223 between the two adjacent gate trench groups 21 adjacent to the second trench 30.

[0534] When at least two dummy gate trenches 223 are provided between two adjacent gate trench groups 21, the ends of at least two dummy gate trenches 223 between the two adjacent gate trench groups 21 adjacent to the second trench 30 are flush. By providing a third connecting trench 113, the third connecting trench 113 extends in the second direction and is spaced apart from the second connecting trench 50 in the second direction. In this way, while the third connecting trench 113 extends in the second direction, it can connect the ends of the dummy gate trenches 223 between the two adjacent gate trench groups 21 adjacent to the second trench 30. This not only connects all the dummy gate trenches 223 between the two adjacent gate trench groups 21, but also allows the third connecting trench 113 to pass current, thereby improving the current passing capacity of the semiconductor device 100. In addition, the ends of the dummy gate trenches 223 between the two adjacent gate trench groups 21 adjacent to the second trench 30 can be enclosed, thereby preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process, thereby ensuring the working performance of the semiconductor device 100.

[0535] In some embodiments, as shown in Figure 100, the multiple second trenches 30 include a first sub-trench 231 and a second sub-trench 212. The multiple first sub-trenches 231 and the multiple gate trenches 2221 correspond to each other and are spaced apart from each other. The multiple second sub-trenches 212 and the multiple dummy gate trenches 223 correspond to each other and are spaced apart from each other. In this way, under the premise of preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process, not only can the circuit distribution of the semiconductor device 100 be made more uniform and the working performance of the semiconductor device 100 be improved, but also the first sub-trench 231 and the corresponding gate trench 2221 can be conveniently etched synchronously, and the second sub-trench 212 and the corresponding dummy gate trench 223 can be conveniently etched synchronously, which can simplify the manufacturing process of the semiconductor device 100.

[0536] In other embodiments, as shown in FIG102 , when there is no dummy gate trench 223 between two adjacent gate trench groups 21, that is, when no dummy gate trench 223 is provided in the insulated gate bipolar transistor region 1015 and only the gate trench 2221 is provided, the semiconductor device 100 does not need to provide the third connecting trench 113. It is only necessary to connect the multiple gate trenches 2221 to one end of the second trench 30 adjacent to the second trench 30 through the second connecting trench 50, and to connect one of the two first connecting trenches 40 to one end of the multiple second trenches 30 in the first direction, and the other to connect the other end of the multiple second trenches 30 in the first direction. This not only prevents the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process and ensures the performance of the two regions, but also increases the current carrying capacity of the two regions, thereby improving the working performance of the semiconductor device 100.

[0537] As described above, two of the second trenches 30 on both sides in the second direction are defined as the first boundary trench 361 and the second boundary trench 362, so that the interior of the area enclosed by the first boundary trench 361, the second boundary trench 362 and the two first connection trenches 40 is the fast recovery diode area 1018, and the exterior of the area enclosed by the first boundary trench 361, the second boundary trench 362 and the two first connection trenches 40 is the insulated gate bipolar transistor area 1015.

[0538] Considering that the first connection trench 40 is located at the junction of the fast recovery diode region 1018 and the insulated gate bipolar transistor region 1015, by arranging the first connection trench 40 and the second connection trench 50 at intervals in the first direction, not only can the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 be separated, effectively and reliably avoiding mutual interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 in the process, thereby ensuring the performance of the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, but also the current carrying capacity of the semiconductor device 100 can be increased, thereby improving the working performance of the semiconductor device 100.

[0539] In some embodiments, as shown in Figures 100 and 101, the spacing distance between the first connecting groove 40 and the second connecting groove 50 in the first direction is D11, the spacing distance between two adjacent first grooves 20 in the second direction is D12, and the spacing distance between two adjacent second grooves 30 in the second direction is D13. D11, D12 and D13 satisfy the relationship: D11=D12=D13.

[0540] By setting the spacing distance between the first connecting grooves 40 and the second connecting grooves 50 in the first direction, the spacing distance between two adjacent first grooves 20 in the second direction, and the spacing distance between two adjacent second grooves 30 in the second direction to be equal, the distribution of the first connecting grooves 40 and the second connecting grooves 50 can be made more uniform, which can improve the uniformity of the circuit distribution of the semiconductor device 100 and improve the working performance of the semiconductor device 100.

[0541] In addition, the processes in the first trench 20, the second trench 30, the first connecting trench 40, the second connecting trench 50, and the third connecting trench 113 are the same, and an oxide insulating layer 70 can be generated inside them and polysilicon 71 can be deposited. The widths and depths of the first trench 20, the second trench 30, the first connecting trench 40, the second connecting trench 50, and the third connecting trench 113 can be set to be the same, so that the first trench 20, the second trench 30, the first connecting trench 40, the second connecting trench 50, and the third connecting trench 113 can be etched synchronously, which can simplify the process steps of the semiconductor device 100.

[0542] In some embodiments, D11 satisfies the relationship: 1.5 μm ≤ D11 ≤ 2 μm. By setting the spacing between the first connection trench 40 and the second connection trench 50 in the first direction within a reasonable range, not only can the spacing between the first connection trench 40 and the second connection trench 50 in the first direction be prevented from being too small, resulting in the spacing between the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 being too small, causing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 to still interfere with each other during the manufacturing process, but also the spacing between the first connection trench 40 and the second connection trench 50 in the first direction be prevented from being too large, resulting in an excessively large overall area of ​​the semiconductor device 100. In this way, a balance can be achieved between the separation effect of the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 and the overall area of ​​the semiconductor device 100. In some embodiments, the structural design of the semiconductor device 100 can be optimized, thereby improving the operating performance of the semiconductor device 100.

[0543] 103 to 108 , a method for manufacturing the semiconductor device 100 will be described below, taking the semiconductor device 100 as an RC-IGBT as an example. The method includes the following steps:

[0544] Step 1, as shown in FIG103 , provides an N-substrate 2 material to form structure 1.

[0545] In step 2, as shown in FIG104 , based on structure 1, the first trench 20 , the second trench 30 , the first connecting trench 40 , the second connecting trench 50 and the third connecting trench 113 are etched, and an oxidized insulating layer 70 is grown to form structure 2.

[0546] In step 3, as shown in FIG105 , based on structure 2, polysilicon 71 is deposited and etched, and then a P well layer 11 and an N+ second emitter layer 12 are sequentially implanted to form structure 3.

[0547] In step 4, as shown in FIG106 , a dielectric layer 13 is deposited on the basis of structure 3, and contact holes are etched on the dielectric layer 13 to form structure 4.

[0548] In step 5, as shown in FIG107 , based on structure 4, a metal layer is sputtered to prepare an emitter metal layer 14 to form structure 5.

[0549] In step 6, as shown in FIG108 , based on structure 5, the back surface N+ field stop layer 15 is implanted, the back surface P+ collector layer 16 is implanted, the back surface FRD region N+ first emitter layer 17 is implanted, laser annealing is performed, and back surface metal sputtering is performed to prepare a collector metal layer 18. Finally, the semiconductor device 100 is formed.

[0550] The following describes a semiconductor device 100 in some embodiments of the present disclosure with reference to Figures 109 to 118. The semiconductor device 100 may be an RC-IGBT. In the following description, N and P represent the conductivity type of the semiconductor. In some embodiments of the present disclosure, the first conductivity type is N-type and the second conductivity type is P-type.

[0551] As shown in Figures 109 to 118 , the semiconductor device 100 includes: a base 80, a drift layer 10 of a first conductivity type, a first trench 20 and a second trench 30.

[0552] A drift layer 10 of the first conductivity type is disposed within a substrate 80 and is located between a first major surface 81 and a second major surface 82. A well layer 11 of the second conductivity type is also disposed within the substrate 80. The well layer 11 is disposed on the side of the drift layer 10 close to the first major surface 81. A second emitter layer 12 of the first conductivity type is also disposed within the well layer 11. Furthermore, a field stop layer 15 of the first conductivity type is also disposed within the substrate 80. The field stop layer 15 is disposed on the side of the drift layer 10 close to the second major surface 82. A collector layer 16 of the second conductivity type and a first emitter layer 17 of the first conductivity type are disposed on the side of the field stop layer 15 close to the second major surface 82. A dielectric layer 13 is disposed on the first major surface 81. An emitter metal layer 14 is disposed on the side of the dielectric layer 13 facing away from the first major surface 81. A collector metal layer 18 is also disposed on the second major surface 82 of the substrate 80. Thus, the basic structure of the semiconductor device 100 is formed.

[0553] The semiconductor device 100 may include an active region 101 and a terminal region 103 disposed on the periphery of the active region 101. The region corresponding to the collector layer 16 is an insulated gate bipolar transistor region 1015, and the region corresponding to the first emitter layer 17 is a fast recovery diode region 1018. That is, the active region 101 of the semiconductor device 100 may include the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018. The emitter metal layer 14 may not only serve as an emitter lead of the insulated gate bipolar transistor region 1015, but also as a gate electrode of the emitter lead ... The collector metal layer 18 can serve not only as the collector lead-in terminal of the insulated gate bipolar transistor region 1015, but also as the cathode lead-in terminal of the fast recovery diode region 1018. In this way, the insulated gate bipolar transistor region 1015 can realize forward conduction of the semiconductor device 100, and the fast recovery diode region 1018 can realize reverse conduction of the semiconductor device 100, so that the semiconductor device 100 has both forward conduction and reverse conduction characteristics.

[0554] In some embodiments, the first trench 20 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10, and the first trench 20 extends in the first direction, the first trench 20 is provided in plurality, the plurality of first trenches 20 are spaced apart in the second direction, and a portion of the plurality of first trenches 20 is a spaced trench 201. The spaced trench 201 may include two sub-trench portions 2011 spaced apart in the first direction, the sub-trench portions 2011 may include a plurality of gate trench groups 21 and a plurality of dummy gate trenches 223, the plurality of gate trench groups 21 are spaced apart in the second direction, at least one dummy gate trench 223 is provided between two adjacent gate trench groups 21, and the gate trench group 21 includes at least two gate trenches 2221 spaced apart in the second direction.

[0555] Both the gate trench 2221 and the dummy gate trench 223 are provided with an oxide insulating layer 70 and deposited with polysilicon 71. The gate trench 2221 is provided with a second emitter layer 12 on both sides thereof in the second direction. The gate trench 2221 has a conductive channel 4 with current-carrying capability and can be electrically connected to the gate, ensuring normal operation of the insulated gate bipolar transistor region 1015 and, therefore, the semiconductor device 100. However, the dummy gate trench 223 is not provided with a second emitter layer 12 on both sides thereof in the second direction and does not have current-carrying capability. The dummy gate trench 223 can be electrically connected to the emitter, thereby reducing Miller capacitance and current density while ensuring the withstand voltage capability of the semiconductor device 100, thereby improving the short-circuit capability of the semiconductor device 100.

[0556] The second trench 30 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The second trench 30 is extended in the first direction. By setting the second trench 30 as multiple and corresponding to the multiple first spacing trenches 23, not only can the junction depth and doping concentration of the well layer 11 of the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 be the same, ensuring that the two regions have the same withstand voltage, but also the process steps of the semiconductor device 100 can be simplified. In addition, by setting the second trench 30 between the two sub-trench portions 2011 in the first direction, the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 can be separated, thereby ensuring the performance of each of the two regions and ensuring the working performance of the semiconductor device 100.

[0557] In some embodiments, as shown in Figures 109 to 111, the semiconductor device 100 further includes a first connecting trench 40. The first connecting trench 40 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10, and is extended in the second direction. There are two first connecting trenches 40, one of which connects one end of the plurality of second trenches 30 in the first direction, and the other connects the other end of the plurality of second trenches 30 in the first direction. The first connecting trench 40 is connected to an end of the dummy gate trench 223 adjacent to the second trench 30.

[0558] One ends of the multiple second trenches 30 are flush with each other, and the other ends of the multiple second trenches 30 are flush with each other. By setting the first connecting trench 40, the first connecting trench 40 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The first connecting trench 40 extends in the second direction, and the first connecting trench 40 is set as two, so that one of the two first connecting trenches 40 can extend in the second direction while connecting one end of the multiple second trenches 30, and the other of the two first connecting trenches 40 can extend in the second direction while connecting the other end of the multiple second trenches 30.

[0559] On the one hand, the two first connection trenches 40 can enclose the multiple second trenches 30, that is, the two first connection trenches 40 can separate the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, thereby preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process, thereby ensuring the performance of each of the two regions. On the other hand, the two first connection trenches 40 can increase the current carrying capacity of the fast recovery diode region 1018, thereby improving the working performance of the semiconductor device 100 and improving the reliability of the semiconductor device 100.

[0560] In some embodiments, considering that the dummy gate trench 223 and the second trench 30 are of the same potential, the dummy gate trench 223 and the second trench 30 are both connected to the emitter. By connecting one end of the dummy gate trench 223 adjacent to the second trench 30 to the first connecting trench 40, not only can the connection between the dummy gate trench 223 and the second trench 30 be achieved through the first connecting trench 40, the connection between the dummy gate trench 223 and the second trench 30 can be facilitated, the production process of the semiconductor device 100 can be simplified, and the current flow capacity of the semiconductor device 100 can be improved.

[0561] In some embodiments, in combination with Figures 109 to 111, the semiconductor device 100 also includes a second connecting trench 50, which extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The second connecting trench 50 is extended in the second direction, and the second connecting trench 50 connects the gate trench 2221 in the gate trench group 21 to one end of the adjacent second trench 30.

[0562] The gate trench 2221 in each gate trench group 21 is flush with one end adjacent to the second trench 30. A second connecting trench 50 can be provided. When the second connecting trench 50 is extended along the second direction, the gate trench 2221 in the gate trench group 21 can be connected to one end adjacent to the second trench 30. This not only improves the current flow capacity of the semiconductor device 100, but also encloses one end adjacent to the second trench 30 of the gate trench 2221 in the gate trench group 21, thereby avoiding mutual interference between the gate trench group 21 and the second trench 30 in the process, that is, preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process, thereby ensuring the performance of the two regions.

[0563] Thus, by making one of the two first connecting trenches 40 connect one end of the multiple second trenches 30 in the first direction, and the other connecting the other end of the multiple second trenches 30 in the first direction, and the first connecting trench 40 is connected to the end of the dummy gate trench 223 adjacent to the second trench 30, and the second connecting trench 50 is connected to the end of the gate trench 2221 in the gate trench group 21 adjacent to the second trench 30, this not only prevents the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process and ensures the performance of each of the two regions, but also improves the current flow capacity of the semiconductor device 100, thereby improving the working performance of the semiconductor device 100.

[0564] In some embodiments, as shown in Figures 109 to 111, one end of the dummy gate trench 223 adjacent to the second trench 30 protrudes from one end of the gate trench 2221 adjacent to the second trench 30, and one end of the dummy gate trench 223 adjacent to the second trench 30 extends toward the second trench 30 and is connected to the first connecting trench 40.

[0565] One end of the dummy gate trench 223 adjacent to the second trench 30 protrudes from one end of the gate trench 2221 adjacent to the second trench 30. On the premise of setting a second connecting trench 50 to connect the gate trench 2221 in each gate trench group 21, the end of the dummy gate trench 223 adjacent to the second trench 30 can be extended toward the second trench 30, so that the dummy gate trench 223 is connected to the first connecting trench 40. This not only facilitates the connection between the dummy gate trench 223 and the corresponding second trench 30 and the emitter, thereby simplifying the manufacturing process of the semiconductor device 100, but also improves the current flow capacity of the semiconductor device 100 and enhances the working performance of the semiconductor device 100.

[0566] In some embodiments, as shown in Figures 109 to 111, the multiple second trenches 30 include a first sub-trench 231, and there are multiple first sub-trenches 231. The multiple first sub-trenches 231 correspond to the multiple dummy gate trenches 223 and are connected to each other. In this way, not only can the circuit distribution of the semiconductor device 100 be more uniform, but the dummy gate trench 223 and the corresponding first sub-trench 231 can also be conveniently etched synchronously, which can simplify the manufacturing process of the semiconductor device 100.

[0567] In some embodiments, in combination with Figures 109 to 111, the multiple second trenches 30 also include second sub-trenches 212, and there are multiple second sub-trenches 212. The multiple second sub-trenches 212 and the multiple gate trenches 2221 correspond to each other in the first direction and are spaced apart from each other. In this way, under the premise of avoiding interference between the second sub-trenches 212 and the gate trenches 2221 in the process, not only can the circuit distribution of the semiconductor device 100 be made more uniform and the working performance of the semiconductor device 100 be improved, but also the gate trenches 2221 and the corresponding second sub-trenches 212 can be conveniently etched synchronously, which can simplify the manufacturing process of the semiconductor device 100.

[0568] In other embodiments, as shown in Figures 112 and 113, when there is no dummy gate trench 223 between two adjacent gate trench groups 21, that is, no dummy gate trench 223 is set in the insulated gate bipolar transistor region 1015, but only the gate trench 2221, it can be understood that the multiple gate trenches 2221 of each sub-trench portion 2011 form a gate trench group 21, and it is only necessary to make the second connecting trench 50 connect the multiple gate trenches 2221 adjacent to one end of the second trench 30, and make one of the two first connecting trenches 40 connect one end of the multiple second trenches 30 in the first direction, and the other connect the other end of the multiple second trenches 30 in the first direction. This not only prevents the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the process and ensures the performance of the two regions, but also increases the current flow capacity of the two regions and improves the working performance of the semiconductor device 100.

[0569] As described above, two of the second trenches 30 on both sides in the second direction are defined as the first boundary trench 361 and the second boundary trench 362, so that the interior of the area enclosed by the first boundary trench 361, the second boundary trench 362 and the two first connection trenches 40 is the fast recovery diode area 1018, and the exterior of the area enclosed by the first boundary trench 361, the second boundary trench 362 and the two first connection trenches 40 is the insulated gate bipolar transistor area 1015.

[0570] Considering that the first connection trench 40 is located at the junction of the fast recovery diode region 1018 and the insulated gate bipolar transistor region 1015, by arranging the first connection trench 40 and the second connection trench 50 at intervals in the first direction, not only can the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 be separated, but also the mutual interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 in the process can be avoided more effectively and reliably, thereby ensuring the performance of the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, but also the current carrying capacity of the semiconductor device 100 can be increased, thereby improving the working performance of the semiconductor device 100.

[0571] In some embodiments, in combination with Figures 110 and 111, the spacing distance between the first connecting groove 40 and the second connecting groove 50 in the first direction is D11, the spacing distance between two adjacent first grooves 20 in the second direction is D12, and the spacing distance between two adjacent second grooves 30 in the second direction is D13. D11, D12 and D13 satisfy the relationship: D11=D12=D13.

[0572] By setting the spacing distance between the first connecting grooves 40 and the second connecting grooves 50 in the first direction, the spacing distance between two adjacent first grooves 20 in the second direction, and the spacing distance between two adjacent second grooves 30 in the second direction to be equal, the distribution of the first connecting grooves 40 and the second connecting grooves 50 can be made more uniform, which can improve the uniformity of the circuit distribution of the semiconductor device 100 and improve the working performance of the semiconductor device 100.

[0573] In addition, the processes in the first trench 20, the second trench 30, the first connecting trench 40 and the second connecting trench 50 are the same, and an oxide insulating layer 70 can be generated therein and polysilicon 71 can be deposited. The widths and depths of the first trench 20, the second trench 30, the first connecting trench 40 and the second connecting trench 50 can be set to be the same, so that the first trench 20, the second trench 30, the first connecting trench 40 and the second connecting trench 50 can be etched synchronously, which can simplify the process steps of the semiconductor device 100.

[0574] In some embodiments, D11 satisfies the relationship: 1.5 μm ≤ D11 ≤ 2 μm. By setting the spacing between the first connection trench 40 and the second connection trench 50 in the first direction within a reasonable range, it is possible to avoid the spacing between the first connection trench 40 and the second connection trench 50 in the first direction being too small, which would result in poor separation between the IGBT region 1015 and the fast recovery diode region 1018 and mutual interference between the IGBT region 1015 and the fast recovery diode region 1018 during the manufacturing process. It is also possible to avoid the spacing between the first connection trench 40 and the second connection trench 50 in the first direction being too large, which would result in an excessively large overall area of ​​the semiconductor device 100. In this way, a balance can be achieved between the separation between the IGBT region 1015 and the fast recovery diode region 1018 and the overall area of ​​the semiconductor device 100, thereby optimizing the structural design of the semiconductor device 100 and improving the operating performance of the semiconductor device 100.

[0575] 113 to 118 , a method for manufacturing the semiconductor device 100 will be described below, taking the semiconductor device 100 as an RC-IGBT as an example. The method includes the following steps:

[0576] Step 1, as shown in FIG113 , provides an N-substrate 2 material to form structure 1.

[0577] In step 2, as shown in FIG114 , based on structure one, the first trench 20 , the second trench 30 , the first connecting trench 40 and the second connecting trench 50 are etched, and an oxidized insulating layer 70 is grown to form structure two.

[0578] Step 3, as shown in FIG115 , based on the structure 2, polysilicon 71 is deposited and etched, and then the P well layer 11 and the N+ second emitter layer 12 are sequentially implanted to form the structure 3.

[0579] In step 4, as shown in FIG116 , a dielectric layer 13 is deposited on the basis of structure 3, and contact holes are etched on the dielectric layer 13 to form structure 4.

[0580] In step 5, as shown in FIG117 , based on structure 4, metal layer sputtering is performed to prepare an emitter metal layer 14 to form structure 5.

[0581] In step 6, as shown in FIG118 , based on structure 5, the back surface N+ field stop layer 15 is implanted, the back surface P+ collector layer 16 is implanted, the back surface FRD region N+ first emitter ...

Claims

1. A fast recovery diode, comprising: A substrate (2) of a first conductivity type; A drift layer (10) of a first conductivity type, the drift layer (10) comprising a first concentration doping layer (210), a second concentration doping layer (220) and a third concentration doping layer (230), the first concentration doping layer (210) being arranged on the substrate (2), the second concentration doping layer (220) being arranged on a side of the first concentration doping layer (210) away from the substrate (2), the third concentration doping layer (230) being arranged on a side of the second concentration doping layer (220) away from the substrate (2), the doping concentration of the second concentration doping layer (220) being less than or equal to the doping concentration of the first concentration doping layer (210) and less than the doping concentration of the third concentration doping layer (230), and the doping concentration of the first concentration doping layer (210) decreasing in a direction away from the substrate (2); as well as An anode layer (300) of the second conductivity type, the anode layer (300) being arranged on a side of the third concentration doped layer (230) facing away from the substrate (2).

2. A semiconductor device comprising: A drift layer (10) of a first conductivity type; A voltage-resistant ring (25) of a second conductivity type, the voltage-resistant ring (25) being arranged on the upper surface of the drift layer (10) and corresponding to the transition region (102) of the semiconductor device (100); a dielectric layer (13), the dielectric layer (13) being arranged on the upper surface of the pressure-resistant ring (25); A metal field plate (90), the metal field plate (90) being arranged on the upper surface of the dielectric layer (13); as well as A first polysilicon field plate (91) is arranged on the upper surface of the voltage-resistant ring (25) and is located between the dielectric layer (13) and the voltage-resistant ring (25); and the metal field plate (90) is at least partially in contact with the first polysilicon field plate (91).

3. A semiconductor device comprising: A drift layer (10) of a first conductivity type; A groove portion (2110) extending downward from the upper surface of the drift layer (10), the groove portion (2110) extending in a first direction and being in plurality, the plurality of groove portions (2110) being arranged at intervals in a second direction and forming a gate groove group (21) and a dummy gate groove group (22), the gate groove group (21) and the dummy gate groove group (22) being arranged alternately in the second direction; A field stop layer (15) of a first conductivity type, the field stop layer (15) being arranged on a lower surface of the drift layer (10); as well as A collector layer (16) of the second conductivity type is arranged on the lower surface of the field stop layer (15), and a first emitter layer (17) of the first conductivity type is arranged in the collector layer (16), and the first emitter layer (17) corresponds to the dummy gate trench group (22) in a vertical direction.

4. A semiconductor device comprising: A drift layer (10) of a first conductivity type; A well layer (11) of a second conductivity type, the well layer (11) being arranged in a portion of the drift layer (10) corresponding to a transition region (102) of the semiconductor device (100), and an upper surface of the well layer (11) constituting a portion of an upper surface of the drift layer (10); A field stop layer (15), the field stop layer (15) being arranged on the lower surface of the drift layer (10); as well as A collector layer (16) of the second conductivity type is arranged on the lower surface of the field stop layer (15), an emitter layer (3) of the first conductivity type is arranged in the collector layer (16), and the emitter layer (3) is located at a portion of the collector layer (16) corresponding to the transition zone (102).

5. A semiconductor device comprising: A drift layer (10) of a first conductivity type; A field stop layer (15) of a first conductivity type, the field stop layer (15) being arranged on a lower surface of the drift layer (10); A collector layer (16) of a second conductivity type, the collector layer (16) being arranged on a lower surface of the field stop layer (15); A first emitter layer (17) of a first conductivity type, the first emitter layer (17) being arranged on the lower surface of the field stop layer (15), and the collector layer (16) being arranged circumferentially around the outside of the first emitter layer (17); a ring layer (107) of a second conductivity type, the ring layer (107) being arranged in the drift layer (10), the upper surface of the ring layer (107) constituting at least a portion of the upper surface of the drift layer (10), the ring layer (107) corresponding to the junction of the collector layer (16) and the first emitter layer (17), and a plurality of groove portions (2110) being arranged in the ring layer (107); as well as A well layer (11) of a second conductivity type is arranged in the drift layer (10), the upper surface of the well layer (11) constitutes at least a part of the upper surface of the drift layer (10), the well layer (11) is arranged on both sides of the ring layer (107) and at least partially corresponds to the collector layer (16) and the first emitter layer (17), and a portion of the well layer (11) corresponding to the collector layer (16) is provided with a plurality of groove portions (2110).

Images