Data processing methods, data processing system and computer-readable storage medium

Abstract

Provided in the present disclosure is a data processing method, which is applied to a first cache unit in a data processing system. The method comprises: predicting a second cache unit as a target cache unit; sending a first data reading request message to the second cache unit, the first data reading request message being used for reading first target data from the target cache unit; receiving the first target data, and updating the state of the first target data according to the type of the first data reading request message; and sending a first data reading response message to a node sending the first target data. Further provided in the present disclosure are a data processing system and a computer-readable storage medium.

Description

Data processing method, data processing system, and computer-readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310781052.6 filed on June 28, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to the field of computer processing technology, and in particular to a data processing method, a data processing system, and a computer-readable storage medium. Background Art

[0004] An SMP (Symmetric multiprocessing) system is one in which multiple CPUs in a server operate symmetrically, with no primary or secondary relationships between them. Each CPU shares the same physical memory, and each CPU takes the same amount of time to access any memory address. Therefore, SMP is also known as a uniform memory access architecture (UMA).

[0005] In SMP systems, data access typically involves a cache unit directly initiating a data read request to the HN (Home Node). The HN then initiates a data snoop with other cache units storing the corresponding data, fetching the data from those units and then sending the read data to the requesting cache unit. This data access process results in high bus bandwidth overhead, high chip power consumption, low data read efficiency, and a significant impact on the processing core's performance.

[0006] Public content

[0007] On the one hand, an embodiment of the present disclosure provides a data processing method, which is applied to a first cache unit in a data processing system, including: predicting that a second cache unit is a target cache unit, and sending a first data read request message to the second cache unit; the first data read request message is used to read first target data from the target cache unit; receiving the first target data, and updating the status of the first target data according to the type of the first data read request message; and sending a first data read response message to the node that sent the first target data.

[0008] On the other hand, an embodiment of the present disclosure also provides a data processing method, applied to a second cache unit in a data processing system, including: receiving a first data read request message sent by the first cache unit, the first data read request message being used to read first target data from the second cache unit; when it is determined that the first target data is stored in the second cache unit, updating the status of the first target data according to the type of the first data read request message, and sending the first target data to the first cache unit.

[0009] On the other hand, an embodiment of the present disclosure also provides a data processing method, which is applied to a data processing device in a data processing system, including: receiving a status update message sent by a second cache unit, and obtaining information, address information and status information of the first cache unit carried in the status update message; updating the status of the corresponding first target data to the status information according to the address information, and updating the cache unit to which the first target data belongs to the first cache unit; sending a status update response message to the second cache unit; or, receiving a first data read request message sent by the second cache unit, and obtaining information, address information and status information of the first cache unit carried in the first data read request message; reading the first target data from the memory according to the address information, updating the status of the first target data to the status information, and updating the cache unit to which the first target data belongs to the first cache unit; sending the first target data to the first cache unit, and receiving a first data read response message sent by the first cache unit.

[0010] On the other hand, an embodiment of the present disclosure further provides a data processing method, which is applied to a data processing system including a first cache unit, a second cache unit and a data processing device, including: the first cache unit predicts that the second cache unit is a target cache unit, and sends a first data read request message to the second cache unit; the second cache unit, when determining that the first target data requested by the first data read request message is stored in the second cache unit, updates the state of the first target data according to the type of the first data read request message, and sends the first target data to the first cache unit; when the type of the first data read request message is to read shared state data or read exclusive state data, sends a status update message to the data processing device; the data processing device obtains the first cache unit carried in the status update message. The data processing device comprises the following steps: obtaining the information, address information and status information of the first cache unit carried in the first data read request message; reading the first target data from the memory according to the address information, updating the status of the corresponding first target data to the status information, and updating the cache unit to which the first target data belongs to the first cache unit; or, the second cache unit sends a first data read request message to the data processing device when it is determined that the first target data requested by the first data read request message is not stored in the second cache unit; the data processing device obtains the information, address information and status information of the first cache unit carried in the first data read request message; reading the first target data from the memory according to the address information, updating the status of the first target data to the status information, and updating the cache unit to which the first target data belongs to the first cache unit; and sending the first target data to the first cache unit.

[0011] On the other hand, the embodiment of the present disclosure further provides a data processing system, comprising at least one processing chip, wherein the processing chip comprises: a first cache unit, configured to predict that the second cache unit is a target cache unit, and send a first data read request message to the second cache unit; and receive the first target data, and update the state of the first target data according to the type of the first data read request message; a second cache unit, configured to receive the first data read request message sent by the first cache unit, and when determining that the first target data requested by the first data read request message is stored in the second cache unit, update the state of the first target data according to the type of the first data read request message, and send the first target data to the first cache unit; a data processing device, configured to Receive a status update message sent by the second cache unit, and obtain the information, address information and status information of the first cache unit carried in the status update message; update the status of the corresponding first target data to the status information according to the address information, and update the cache unit to which the first target data belongs to the first cache unit; or, receive a first data read request message sent by the second cache unit, and obtain the information, address information and status information of the first cache unit carried in the first data read request message; read the first target data from the memory according to the address information, update the status of the first target data to the status information, and update the cache unit to which the first target data belongs to the first cache unit; and send the first target data to the first cache unit.

[0012] On the other hand, an embodiment of the present disclosure further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor so that the processor implements the data processing method as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG1 is a schematic diagram of a process of RDE requesting to read data in a related technology according to an embodiment of the present disclosure;

[0014] FIG2 is a schematic diagram of a data processing flow with the first cache unit as the execution subject provided by an embodiment of the present disclosure;

[0015] FIG3 is a schematic diagram of a data processing flow with the first cache unit as the execution subject provided by an embodiment of the present disclosure;

[0016] FIG4 is a schematic diagram of a process of requesting to read third target data in which the first cache unit is the execution subject, provided by an embodiment of the present disclosure;

[0017] FIG5a is a schematic diagram of a cache unit prediction failure according to an embodiment of the present disclosure;

[0018] FIG5 b is a schematic diagram of a cache unit prediction failure according to an embodiment of the present disclosure;

[0019] FIG6 is a schematic diagram of a data processing flow with the second cache unit as the execution subject provided by an embodiment of the present disclosure;

[0020] FIG7 is a schematic diagram of a data processing flow with the second cache unit as the execution subject provided by an embodiment of the present disclosure;

[0021] FIG8 is a schematic diagram of a data processing flow with a data processing device as the execution subject provided by an embodiment of the present disclosure;

[0022] FIG9 is a schematic diagram of a data processing flow with a data processing device as the execution subject provided by an embodiment of the present disclosure;

[0023] FIG10 is a schematic diagram of an RDE process when a target cache unit prediction is successful according to an embodiment of the present disclosure;

[0024] FIG11 is a schematic diagram of an RDE process when a target cache unit prediction fails according to an embodiment of the present disclosure;

[0025] FIG12 is a schematic diagram of an RDS process when a target cache unit prediction is successful according to an embodiment of the present disclosure;

[0026] FIG13 is a schematic diagram of an RDI process flow when a target cache unit prediction is successful according to an embodiment of the present disclosure;

[0027] FIG14 is a schematic diagram of the structure of a data processing system (SMP) provided in an embodiment of the present disclosure;

[0028] FIG15 is a schematic diagram of the structure of a data processing system provided by an embodiment of the present disclosure;

[0029] FIG16 is a schematic diagram of the structure of a data processing system (CC-NUMA) provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] Hereinafter, example embodiments will be described more fully with reference to the accompanying drawings, but the example embodiments may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth herein. These examples are provided to make this disclosure more thorough and complete and to enable those skilled in the art to fully understand the scope of this disclosure.

[0031] As used herein, the term "and / or" includes any and all combinations of at least one of the associated listed items.

[0032] The terms used herein are used only to describe specific embodiments and do not limit the present disclosure. As used herein, the singular forms "a," "an," and "the" also include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, they specify the presence of a particular feature, whole, step, operation, element, and / or component, but do not exclude the presence or addition of at least one other feature, whole, step, operation, element, component, and / or group thereof.

[0033] The embodiments described herein may be described with reference to plan views and / or cross-sectional views, with the aid of idealized schematic diagrams of the present disclosure. Thus, the example illustrations may be modified based on manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to those shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions of the components, but are not intended to be limiting.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0035] The data processing method and system provided by the embodiments of the present disclosure are applicable to any data processing system involving atomic operations, such as an SMP system, a cache-coherent non-uniform memory access (CC-NUMA) system, and the like. In the following examples, an SMP system is used as an example, but the embodiments of the present disclosure are not limited thereto.

[0036] Figure 14 is a schematic diagram of an SMP system architecture. As shown in Figure 14, the SMP system includes: a processing core (Core), a second-level cache (L2), a network-on-chip (NOC), a host node (HN), and memory. Both the L2 and the HN are connected to the NOC, and the HN is connected to the memory. The L2 can include at least one cache unit, each of which can be connected to at least one processing core. In the SMP system shown in Figure 14, the L2 includes three cache units: L2-0, L2-1, and L2-2. L2-0 is connected to processing core Core0, L2-1 is connected to processing core Core1, and L2-2 is connected to processing core Core2. In the SMP system, the HN interacts with each cache unit of the L2 to achieve cache coherence. The HN manages the entire memory space in units of cache lines and tracks the memory access status of each L2 cache unit.

[0037] M, E, S, and I represent the four states of cache line data. By switching these four states, the purpose of managing cache data is achieved. The states of M, E, S, and I and their corresponding descriptions are shown in Table 1:

[0038] Table 1

[0039] HN can track the access of all cache line data by maintaining a directory table (dir table). The data structure of the directory table (dir table) is shown in Table 2:

[0040] Table 2

[0041] As shown in Table 2, each entry corresponds to a cache line of data, and the location of the cache line data can be determined based on the address information. An entry includes a state field (State) and a bit width field (VEC). The state field records the state of the data read by the cache unit. The bit width field corresponds to the number of cache units in the L2, n. Each bit corresponds to an L2 cache unit, indicating which L2 cache unit stores the data.

[0042] The state field shown in Table 2 only records the three states: E, S, and I. Because after the L2 cache unit obtains data in the M state, the data modification action will not notify the HN. Therefore, the HN does not know whether the state of the data stored in the L2 cache unit is E or M. For example, dir.state = E, VEC = 'b001, which means that the data in this cache line in L2-0 may be in M ​​state, E state, S state (downgraded from E state to S state without notifying the HN), or I state (data replaced from the cache unit without notifying the HN); dir.state = S, VEC = 'b011, which means that the data in this cache line in L2-0 and L2-1 may be in S state or I state (data replaced from the cache unit without notifying the HN); dir.state = I, which means that no L2 cache unit stores this cache line data.

[0043] Figure 1 is a schematic diagram of a process of RDE requesting to read data in the related art provided by an embodiment of the present disclosure. As shown in Figure 1 , the process includes the following steps S1 to S6.

[0044] In step S1, L2-0 sends an RDE (Read Date E, exclusive state data read request) message to HN, requesting to read data.

[0045] In step S2, after receiving the RDE message, the HN searches Table 2 according to the address information carried in the RDE message and finds that the data corresponding to the address information is in the E state in L2-1. Then, the HN sends a SNPtoI (Snoop to Invalid) message to L2-1 to snoop L2-1.

[0046] Step S3: After receiving the SNPToI message, L2-1 changes the state of the data requested to be read from E / M to I state, and returns SNPRSPI_DATA (invalid state snoop response data, that is, changes the data requested to be read by L2-0 to invalid state and returns the data to HN) to HN.

[0047] Step S4: After receiving SNPRSPI_DATA, HN modifies the data to point to L2-0 and returns a DATE (Date E, exclusive status data response) message to L2-0. The message carries the data requested by L2-0.

[0048] Step S5: L2-0 caches the data and changes the state of the data to E state.

[0049] In step S6, L2-0 returns a CmpAck (data read response) message to HN, notifying HN that the RDE request processing is completed.

[0050] In the related technical solution: L2-0 data read requests must be sent to the HN for query, and then the HN initiates monitoring to other cache units and reads data from other cache units. The data reading time is long, the reading efficiency is low, and the processing performance of the processing core is low.

[0051] The present disclosure provides a data processing method that can be applied to a data processing system where lock performance is particularly important. The data processing system can be either an SMP system or a CC-NUMA system. In the present disclosure, the data processing system (SMP) shown in FIG14 is used as an example for illustration. L2-0 is the first cache unit, L2-1 is the second cache unit, and the data processing device interacting with L2-1 and L2-0 is an HN.

[0052] FIG2 is a schematic diagram of a data processing flow with the first cache unit as the execution body provided by an embodiment of the present disclosure. As shown in FIG2 , the data processing method is applied to the first cache unit in the data processing system, and includes the following steps S11 to S13.

[0053] Step S11 , predicting that the second cache unit is the target cache unit, and sending a first data read request message to the second cache unit; the first data read request message is used to read first target data from the target cache unit.

[0054] The target cache unit is a cache unit suspected of storing the first target data. The target cache unit and the first cache unit can be cache units of the same level or cache units of different levels. In the embodiment of the present disclosure, the target cache unit and the first cache unit are cache units of the same level as an example for explanation.

[0055] In this step, L2-0 predicts that the requested data (i.e., the first target data) is stored in L2-1. That is, L2-0 predicts that the target cache unit is L2-1, and then sends a first data read request message to L2-1, so that L2-1 returns the first target data. The first data read request message can be one of the following: RDE message, RDS (Read Date S, shared state data read request) message, RDI (Read Date I, invalid state data read request) message. The RDE message indicates a request to read data and record the read data in the E state, RDS indicates a request to read data and record the read data in the S state, and RDI indicates a request to read data and record the read data in the I state.

[0056] Step S12: Receive the first target data, and update the state of the first target data according to the type of the first data read request message.

[0057] Types of the first data read request message include RDE message, RDS message, and RDI message.

[0058] In this step, after receiving the first target data, L2 - 0 updates the state of the first target data to a corresponding state according to whether the type of the first data read request message is an RDE message, an RDS message, or an RDI message.

[0059] In some embodiments, the node sending the first target data may be a second cache unit or a data processing device. If the target cache unit prediction succeeds in step S11, indicating that the predicted target cache unit L2-1 stores the first target data, L2-1 then sends the first target data to L2-0. If the target cache unit prediction fails in step S11, indicating that the predicted target cache unit L2-1 does not store the first target data, the data processing device HN then sends the first target data to L2-0.

[0060] In some embodiments, updating the status of the first target data according to the type of the first data read request message includes: when the type of the first data read request message is to read shared state data, that is, the first data read request message is an RDS message, updating the status of the first target data to a shared state (S state); when the type of the first data read request message is to read exclusive state data, that is, the first data read request message is an RDE message, updating the status of the first target data to an exclusive state (E state); when the type of the first data read request message is to read invalid state data, that is, the first data read request message is an RDI message, keeping the status of the first target data in an invalid state (I state).

[0061] Step S13: Send a first data read response message to the node that sent the first target data.

[0062] In this step, L2-0 sends a CmpAck message to the corresponding node that sends the first target data.

[0063] The data processing method provided by the embodiment of the present disclosure is applied to the first cache unit in the data processing system, including: predicting the second cache unit as the target cache unit, sending a first data read request message to the second cache unit, the first data read request message being used to read the first target data from the target cache unit; receiving the first target data, and updating the state of the first target data according to the type of the first data read request message; sending a first data read response message to the node that sent the first target data; the embodiment of the present disclosure sends the data read request message to the predicted target cache unit by predicting the target cache unit, if the target cache unit hits, that is, the predicted target cache unit stores the requested data, then the data response can be directly returned without first sending the data read request to the data processing device and then the data processing device monitoring the cache unit to return the data response, which can reduce the data reading time, improve the data reading efficiency, and enhance the system performance. It should be noted that the target cache unit can be predicted based on multiple previous data reading processes. The embodiment of the present disclosure takes the prediction of the target cache unit based on the previous data reading process as an example for explanation.

[0064] In some embodiments, after receiving the first target data (i.e., step S12), the data processing method further includes the following steps: caching the first target data if the type of the first data read request message is a read shared state data or a read exclusive state data. That is, if the type of the first data read request message is an RDS message or an RDE message, then after receiving the first target data, the L2-0 locally caches the first target data. If the type of the first data read request message is an RDI message, then the first target data does not need to be cached, but can be directly sent to the processing core requesting the first target data.

[0065] In the case where the target cache unit prediction fails, the node sending the first target data is a data processing device. In some embodiments, as shown in Figure 3, after sending the first data read response message to the data processing device (i.e., step S13), the data processing method may further include steps S21 and S22.

[0066] Step S21: Send a second data read request message to the data processing device, where the second data read request message is used to read second target data from the data processing device.

[0067] In this step, if the L2-0 predicts the target cache unit fails, a second data read request message is sent to the HN to request the HN to read the second target data. The second data read request message can be one of the following: RDE message, RDS message, RDI message.

[0068] Step S22: receiving the second target data sent by the data processing device, and sending a second data read response message to the data processing device.

[0069] In this step, after receiving the second target data sent by HN, L2-0 returns a CmpAck message to HN.

[0070] It can be seen from the above steps S21 and S22 that if the previous target cache unit prediction fails and the first target data requested to be read is provided by HN, then when it is necessary to request to read the second target data again, L2-0 directly requests HN to read the second target data, and HN reads the second target data from the memory and directly returns it to L2-0.

[0071] In some embodiments, before predicting that the second cache unit is the target cache unit (ie, step S11 ), the data processing method further includes requesting to read data n times, where n is an integer greater than or equal to 1.

[0072] Accordingly, the step of predicting the second cache unit as the target cache unit (i.e., step S11) includes the following steps: determining the cache unit to which the data of each read request belongs, and predicting the second cache unit as the target cache unit based on each cache unit. In other words, the target cache unit is predicted based on the source of the data of one or more previous read requests.

[0073] FIG4 is a flow chart of a request to read third target data with the first cache unit as the execution subject provided by an embodiment of the present disclosure. As shown in FIG4 , one of n times of requesting to read data includes the following steps S31 to S33 .

[0074] Step S31: Send a third data read request message to the data processing device.

[0075] In this step, L2-0 sends a third data read request message to HN. The third data read request message can be one of the following: RDE message, RDS message, RDI message. It should be noted that the type of the third data read request message can be the same as or different from the type of the first data read request message.

[0076] Step S32: receiving the third target data and the cache unit information storing the third target data sent by the data processing device, and updating the status of the third target data according to the type of the third data read request message.

[0077] If HN finds that the third target data is stored in L2-1, it sends an SNPtoI message to L2-1 to monitor L2-1. After receiving the SNPToI message, L2-1 updates the status of the third target data and returns the third target data to HN. HN updates the cache unit to which the third target data belongs by updating the bit width field in Table 2, and returns the third target data and the source of the third target data (that is, from which cache unit the third target data is read) to L2-0.

[0078] In this step, after receiving the third target data and the cache unit information storing the third target data sent by HN, L2-0 updates the state of the third target data according to the type of the third data read request message, that is, updates the state of the third data from I state to E state, S state, or keeps I state unchanged.

[0079] Step S33: Send a third data read response message to the data processing device.

[0080] In this step, after completing the third data status update, L2-0 returns a CmpAck message to HN to notify HN that the third data reading process is completed.

[0081] By initiating a third target data read request to the HN, the source of the third target data is determined so as to serve as a target cache unit predicted in subsequent data read requests.

[0082] If the target cache unit prediction fails, the data read request is first sent to the predicted target cache unit and then to the HN. In a real topology, this can cause routing detours, resulting in additional latency. As shown in Figure 5a, L2-0 is the cache unit that initiates the data read request, and L2-1 is the predicted target cache unit. If the target cache unit prediction fails, the actual message transmission path is indicated by the arrows: first from L2-0 through routing module xp to L2-1, and then from L2-1 to the HN. This shows that the routing path is detours.

[0083] The disclosed embodiments further define the strategy for predicting the target cache unit. In some embodiments, predicting a second cache unit as the target cache unit based on each cache unit includes the following steps: For each cache unit, predicting a second cache unit located on the route from the first cache unit to the data processing device as the target cache unit. In other words, a cache unit located on the route from the L2-0 (i.e., the cache unit initiating the data read request) to the HN is selected as the target cache unit.

[0084] As shown in FIG5b , selecting L2-2 on the routing path from L2-0 to HN as the target cache unit can avoid routing detours, reduce data read latency, and further improve data read efficiency.

[0085] FIG6 is a schematic diagram of a data processing flow with the second cache unit as the execution body provided by an embodiment of the present disclosure. As shown in FIG6 , the data processing method is applied to the second cache unit in the data processing system, including the following steps S41 and S42.

[0086] Step S41 : receiving a first data read request message sent by a first cache unit, where the first data read request message is used to read first target data from a second cache unit.

[0087] In this step, L2-1 receives the first data read request message sent by L2-0, and obtains the address information carried in the first data read request message.

[0088] Step S42 : when it is determined that the first target data is stored in the second cache unit, the state of the first target data is updated according to the type of the first data read request message, and the first target data is sent to the first cache unit.

[0089] In this step, L2-1 queries locally according to the address information. If the corresponding first target data is found, that is, data hit, the state of the first target data is updated according to the type of the first data read request message, and the first target data is returned to L2-0.

[0090] In some embodiments, updating the status of the first target data according to the type of the first data read request message includes: when the type of the first data read request message is to read shared status data, that is, the first data read request message is an RDS message, updating the status of the first target data to a shared status; when the type of the first data read request message is to read exclusive status data, that is, the first data read request message is an RDE message, updating the status of the first target data to an invalid status; when the type of the first data read request message is to read invalid status data, that is, the first data read request message is an RDI message, keeping the status of the first target data unchanged.

[0091] It can be seen from steps S41 and S42 that when the target cache unit prediction is successful, the predicted second cache unit L2-1 can directly return the first target data to L2-0 without the need for interaction between the first cache unit and the HN, thereby saving bandwidth and power consumption, reducing data reading time, improving data reading efficiency, and enhancing system performance.

[0092] In some embodiments, after sending the first target data to the first cache unit (step S42), the data processing method further includes the following step: receiving a first data read response message sent by the first cache unit. That is, after receiving the first target data sent by L2-1, L2-0 returns a CmpAck message to L2-1.

[0093] As shown in FIG. 7 , after the state of the first target data is updated according to the type of the first data read request message (ie, step S42 ), the data processing method may further include the following steps S51 and S52 .

[0094] Step S51: When the type of the first data read request message is to read shared state data or read exclusive state data, a state update message is sent to the data processing device, where the state update message carries information, address information and state information of the first cache unit.

[0095] The status update message is used to instruct the data processing device to update the status of the first target data according to the status information and the address information, and to update the cache unit to which the first target data belongs according to the information of the first cache unit.

[0096] In this step, if L2-1 receives an RDE message or RDS message sent by L2-0, it sends a status update message (UpDir) to the HN. The status update message carries information about the first cache unit, address information, and status information. The address information is the address of the first target data. The HN can determine the cache unit to which the first target data belongs in Table 2 based on the address information. The status information is the status of the first target data that needs to be recorded in Table 2. The status update message instructs the HN to modify the status of the first target data in the status field of Table 2 to the status information and update the cache unit to which the first target data belongs in the bit width field of Table 2. In the present embodiment, the cache unit to which the first target data belongs is the first cache unit.

[0097] Step S52: Receive a status update response message sent by the data processing device.

[0098] In this step, L2-1 receives a status update response message (UpCmp) from the HN. The UpCmp message is sent by the HN to L2-1 after the status of the first target data and the cache unit to which the first target data belongs are updated. After L2-1 receives the CmpAck message from L2-0 and the UpCmp message from the HN, the first data read request process is completed.

[0099] In some embodiments, after receiving the first data read request message sent by the first cache unit (i.e., step S41), the data processing method may further include the following steps: if it is determined that the first target data is not stored in the second cache unit, sending the first data read request message to the data processing device, so that the data processing device reads the first target data from the memory and sends the first target data to the first cache unit, and updating the status of the first target data and the cache unit to which the first target data belongs. In other words, if the target cache unit prediction fails, L2-1 receives the first target data read request message sent by L2-0 and fails to find the first target data locally, then forwards the first target data read request message to the HN, which reads the first target data from the memory and directly returns it to L2-0. In addition, the HN also updates the status of the first target data and the cache unit to which the first target data belongs in Table 2. If the first data read request message is an RDS message, the HN updates the state of the first target data to the S state and records the L2-0 to which it belongs; if the first data read request message is an RDE message, the HN updates the state of the first target data to the E state and records the L2-0 to which it belongs; if the first data read request message is an RDI message, the HN does not update the state of the first target data.

[0100] FIG8 is a schematic diagram of a data processing flow with a data processing device as the execution subject provided by an embodiment of the present disclosure. As shown in FIG8 , the data processing method is applied to the data processing device in a data processing system, and includes the following steps S61 to S63 .

[0101] Step S61: Receive a status update message sent by the second cache unit, and obtain the information, address information, and status information of the first cache unit carried in the status update message.

[0102] In this step, the HN receives the status update message (UpDir) sent by L2-1, and obtains the L2-0 information, the address information of the first target data, and the status information of the first target data carried in the status update message. The status information of the first target data is the modified status information of the first target data.

[0103] Step S62 : updating the state of the corresponding first target data to the state information according to the address information, and updating the cache unit to which the first target data belongs to the first cache unit.

[0104] In this step, HN determines the entry corresponding to the address information in Table 2, which is the entry corresponding to the first target data, updates the status field in the entry to the status information, and updates the bit width field in the entry to the information of the first cache unit.

[0105] Step S63: Send a status update response message to the second cache unit.

[0106] In this step, the HN sends a status update response message (UpCmp) to L2-1.

[0107] Steps S61 to S63 are the process of successful target cache unit prediction. When the target cache unit prediction is successful, HN only needs to modify the state of the first target data requested to be read by the first cache unit and the cache unit to which the first target data belongs in Table 2 without reading data from the memory.

[0108] FIG9 is a schematic diagram of a data processing flow with a data processing device as the execution subject provided by an embodiment of the present disclosure. As shown in FIG9 , the data processing method is applied to a data processing device in a data processing system, and includes the following steps S71 to S73.

[0109] Step S71: Receive a first data read request message sent by the second cache unit, and obtain information, address information, and status information of the first cache unit carried in the first data read request message.

[0110] In this step, HN receives the first data read request message sent by L2-1, and obtains L2-0 information, address information of the first target data, and status information of the first target data carried in the first data read request message. The status information of the first target data is the modified status information of the first target data.

[0111] The first data read request message may be one of the following: an RDE message, an RDS message, or an RDI message.

[0112] Step S72 : reading the first target data from the memory according to the address information, updating the state of the first target data to the state information, and updating the cache unit to which the first target data belongs to to the first cache unit.

[0113] In this step, the HN searches the memory for the first target data based on the address information, determines the entry corresponding to the address information in Table 2, which is the entry corresponding to the first target data, updates the status field in the entry to the status information, and updates the bit width field in the entry to the information of the first cache unit.

[0114] Step S73: Send the first target data to the first cache unit, and receive a first data read response message sent by the first cache unit.

[0115] In this step, the HN sends the first target data read from the memory to the L2 - 0 , and receives a first data read response message (CmpAck) sent by the L2 - 0 .

[0116] Steps S71 to S73 are the process for when the target cache unit prediction fails. In the case of a target cache unit prediction failure, the HN not only needs to modify the status of the first target data requested to be read by the first cache unit and the cache unit to which it belongs in Table 2, but also needs to read the first target data from the memory and directly return the first target data to the first cache unit.

[0117] An embodiment of the present disclosure further provides a data processing method, which is applied to a data processing system including a first cache unit, a second cache unit, and a data processing device, and includes the following steps: S81 to S83.

[0118] In step S81 , the first cache unit predicts that the second cache unit is the target cache unit, and sends a first data read request message to the second cache unit.

[0119] Step S82: When the second cache unit determines that the first target data requested by the first data read request message is stored in the second cache unit, it updates the status of the first target data according to the type of the first data read request message and sends the first target data to the first cache unit; when the type of the first data read request message is to read shared status data or read exclusive status data, it sends a status update message to the data processing device.

[0120] In step S83, the data processing device obtains the information, address information and status information of the first cache unit carried in the status update message; updates the status of the corresponding first target data to the status information according to the address information, and updates the cache unit to which the first target data belongs to the first cache unit.

[0121] After the first cache unit predicts that the second cache unit is the target cache unit and sends the first data read request message to the second cache unit (ie step S81 ), the data processing method further includes the following steps S82 ′ and S83 ′.

[0122] Step S82 ′: when the second cache unit determines that the first target data requested by the first data read request message is not stored in the second cache unit, the second cache unit sends the first data read request message to the data processing device.

[0123] In step S83', the data processing device obtains the information, address information and status information of the first cache unit carried in the first data read request message; reads the first target data from the memory according to the address information, updates the status of the first target data to the status information, and updates the cache unit to which the first target data belongs to the first cache unit; and sends the first target data to the first cache unit.

[0124] To clearly illustrate the technical solution of the embodiment of the present disclosure, the RDE process when the target cache unit prediction is successful is described below with reference to Figure 10. As shown in Figure 10, the RDE process includes the following steps S101 to S109.

[0125] Step S101 : L2 - 0 sends an RDE message to HN to request to read data.

[0126] Step S102: After receiving the RDE message, the HN searches Table 2 according to the address information (address A) carried in the RDE message, and finds that the third target data corresponding to the address information is in the E state in L2-1. Then, the HN sends a SNPtoI message to L2-1 to monitor L2-1.

[0127] Step S103 , after receiving the SNPToI message, L2 - 1 changes the third target data from the E / M state to the I state, and returns SNPRSPI_DATA (ie, the third target data requested to be read by L2 - 0 ) to the HN.

[0128] In step S104, after receiving SNPRSPI_DATA, HN modifies the data to point to L2-0 and returns SNPRSPI_DATA (ie, the third target data) to L2-0. SNPRSPI_DATA carries the source of the third target data, ie, L2-1.

[0129] Step S105 , L2 - 0 caches the data and changes the state of the data to E state.

[0130] The above steps 101 to 105 are a process of requesting to read data at address A.

[0131] In step S106, L2-0 carries information of L2-1 in the third target data received in step S104, and therefore predicts that the target cache unit is L2-1, and then sends the RDE message carrying address B directly to L2-1.

[0132] In step S107, after receiving the RDE message carrying address B, L2-1 queries the cache and finds that the first target data is hit. It directly returns a DATE message carrying the first target data to L2-0, updates the status of the first target data from E to I, and sends an UpDir message to HN. The UpDir message carries L2-0 information, address B, and status E, which is used to instruct HN to update the status of the first target data corresponding to address B in Table 2 to E and point the first target data to L2-0.

[0133] Step S108 , after receiving the first target data, L2 - 0 caches the first target data, updates the state of the first target data to the E state, and returns a CmpAck message to L2 - 1 .

[0134] Step S109: After updating Table 2, HN returns an UpCmp message to L2-1.

[0135] After L2-1 receives the UpCmp message and the CmpAck message, it indicates that the RDE processing flow for address B is completed.

[0136] It can be seen from the above steps S101 to S109 that the embodiment of the present disclosure predicts the target cache unit for this data read based on the result of the previous data read request. If the target cache unit prediction is successful, the time for reading data is greatly reduced, and the number of times data flows in the NOC is reduced, thereby improving processing performance and reducing power consumption.

[0137] To clearly illustrate the technical solution of the embodiment of the present disclosure, the RDE process when the target cache unit prediction fails is described below with reference to Figure 11. As shown in Figure 11, the RDE process includes the following steps S201 to S209.

[0138] Steps S201 to S205 are the process of RDE requesting to read data in address A, which are the same as steps S101 to S105 in FIG10 and will not be described in detail.

[0139] In step S206, L2-0 carries information of L2-1 in the third target data received in step S204, and therefore predicts that the target cache unit is L2-1, and then sends the RDE message carrying address B directly to L2-1.

[0140] Step S207 , after receiving the RDE message carrying address B, L2 - 1 searches the cache and finds a miss, that is, the first target data is not found locally, and then sends an RDE message carrying address B to HN.

[0141] Step S208: After receiving the RDE message carrying address B, HN reads the corresponding first target data from the memory according to address B, returns a DATE message to L2-0, and updates the cache unit to which the first target data belongs in Table 2 to L2-0.

[0142] In step S209, after receiving the first target data sent by HN, L2-0 caches the first target data, changes the state of the first target data from I state to E state, and sends a CmpAck message to HN to notify HN that the RDE data reading process for requesting to read the data in address B is completed.

[0143] Steps S206 to S209 above illustrate the RDE process for a target cache unit prediction failure at address B. It should be noted that since the first target data corresponding to address B comes from HN, the next RDE at address C can be initiated directly to HN without predicting the target cache unit (see steps S210 to S212 in FIG. 11 for details). The RDE process for address C is identical to that for address B and will not be further described here.

[0144] To clearly illustrate the technical solution of the embodiment of the present disclosure, the RDS process when the target cache unit prediction is successful is described below with reference to Figure 12. As shown in Figure 12, the RDS processing process includes the following steps S301 to S309.

[0145] Steps S301 to S305 are the process of RDS requesting to read the data in address A, which are the same as steps S101 to S105 in Figure 10, with the following differences: in step S303, after L2-1 receives the SNPToS message, it changes the third target data from the E / M state to the S state; in step S304, after HN receives SNPRSPI_DATA, it updates the state of the third target data to the E state and points the third target data to L2-0 and L2-1; in step S305, after L2-0 receives the third target data, it updates the state of the third target data to the S state.

[0146] In step S306, L2-0 carries information about L2-1 in the third target data received in step S304, and therefore predicts that the target cache unit is L2-1, and directly sends the RDS message carrying address B to L2-1.

[0147] In step S307, after receiving the RDE message carrying address B, L2-1 queries the cache and finds that the first target data is hit. It directly returns a DATS (Date S, shared data read response) message to L2-0, which carries the first target data, and updates the state of the first target data from the E / M state to the S state. At the same time, it sends an UpDir message to the HN. The UpDir message carries the L2-0 and L2-1 information, address B, and state S, which is used to instruct the HN to update the state of the first target data corresponding to address B in Table 2 to the S state and point the first target data to L2-0 and L2-1.

[0148] Step S308: After receiving the first target data, L2-0 caches the first target data, updates the state of the first target data to the S state, and returns a CmpAck message to L2-1.

[0149] Step S309: After updating Table 2, HN returns an UpCmp message to L2-1.

[0150] After L2-1 receives the UpCmp message and the CmpAck message, it indicates that the RDS processing flow for address B is completed.

[0151] It should be noted that the process of successful target cache unit prediction for RDS and RDE is the same, the difference lies in the different data update states of HN and L2-1.

[0152] It can be seen from the above steps S301 to S309 that the embodiment of the present disclosure predicts the target cache unit for this data read based on the result of the previous data read request. If the target cache unit is predicted successfully, the time for reading data is greatly reduced, and the number of times data flows in the NOC is reduced, thereby improving processing performance and reducing power consumption.

[0153] To clearly illustrate the technical solution of the embodiment of the present disclosure, the RDI process when the target cache unit prediction is successful is described below with reference to Figure 13. As shown in Figure 13, the RDI processing process includes the following steps S401 to S408.

[0154] Steps S401 to S405 are the process of RDI requesting to read address A, which are the same as steps S101 to S105 in Figure 10, except that: in step S403, after L2-1 receives the SNPCUR message, it does not update the status of the third target data; in step S404, after HN receives SNPRSPI_DATA, it does not update the status of the third target data; in step S405, after L2-0 receives the third target data, it does not update the status of the third target data.

[0155] Steps S406 to S408 are the process of RDI requesting to read address B.

[0156] In step S406, L2-0 carries information of L2-1 in the third target data received in step S404, and therefore predicts that the target cache unit is L2-1, and directly sends the RDI message carrying address B to L2-1.

[0157] Step S407: After receiving the RDI message carrying address B, L2-1 queries the cache and finds that the first target data is hit, and directly returns a DATI (Date I, invalid data read response) message to L2-0, which carries the first target data.

[0158] Step S408: After receiving the first target data, L2-0 returns a CmpAck message to L2-1.

[0159] It can be seen from the above steps S401 to S408 that the embodiment of the present disclosure predicts the target cache unit for this data read based on the result of the previous data read request. If the target cache unit prediction is successful, the time for reading data is greatly reduced, and the number of times data flows in the NOC is reduced, thereby improving processing performance and reducing power consumption.

[0160] The data processing method provided by the disclosed embodiments improves the transmission process of data read requests in cache coherence systems. It can be applied to systems such as SMP and CC-NUMA, where data access latency is particularly important to system performance. The data processing method provided by the disclosed embodiments can reduce data read latency in the system while also reducing bandwidth overhead and chip power consumption.

[0161] In the data processing method provided by the disclosed embodiments, a data read request is sent to the predicted target cache unit by predicting the target cache unit. If the requested data is found in the target cache unit, a data response is directly returned, without first sending the data read request to the HN and then having the HN monitor and return the data response. If the target cache unit prediction is successful, the data processing method provided by the disclosed embodiments can reduce data read time and the number of data flows within the NOC, thereby improving performance while reducing power consumption.

[0162] The present disclosure also provides a data processing system, wherein the data processing system includes at least one processing chip, wherein the processing chip includes: a first cache unit configured to predict that the second cache unit is a target cache unit, and send a first data read request message to the second cache unit; and receive first target data, and update the state of the first target data according to the type of the first data read request message; the second cache unit is configured to receive the first data read request message sent by the first cache unit, and when it is determined that the first target data requested by the first data read request message is stored in the second cache unit, update the state of the first target data according to the type of the first data read request message, and send the first target data to the first cache unit; data processing The device is configured to receive a status update message sent by the second cache unit, obtain the information, address information and status information of the first cache unit carried in the status update message; update the status of the corresponding first target data to the status information according to the address information, and update the cache unit to which the first target data belongs to the first cache unit; or, receive a first data read request message sent by the second cache unit, obtain the information, address information and status information of the first cache unit carried in the first data read request message; read the first target data from the memory according to the address information, update the status of the first target data to the status information, and update the cache unit to which the first target data belongs to the first cache unit; and send the first target data to the first cache unit.

[0163] In some embodiments, the data processing system further includes memory and at least two levels of cache, each level of cache including at least one cache unit. The data processing device may be a master node (HN), or the data processing device may be one of the cache units at a different level from the first cache unit and the second cache unit. In other words, the data processing system provided by the embodiments of the present disclosure is not limited to a cache unit accessing memory data by interacting with the HN; a cache unit may also access memory data by interacting with cache units at other levels.

[0164] It should be noted that the processing system may further include an on-chip network NOC, and cache units at different levels and the master node may communicate via the NOC.

[0165] As shown in Figure 15 , the processing system includes a second-level cache L2, a third-level cache L3, and a fourth-level cache L4. L2 includes three cache units: L2-0, L2-1, and L2-2. L2-0 is connected to processing core Core0, L2-1 is connected to processing core Core1, and L2-2 is connected to processing core Core2. L3 includes two processing units: L3-1 and L3-2. The data processing device can be a master node HN or a cache unit of L4.

[0166] The data processing system may be a symmetric multi-processor (SMP) system or a cache-coherent non-uniform memory access (CC-NUMA) system.

[0167] In some embodiments, there may be at least two processing chips, each processing chip is connected to at least another processing chip, and the processing chip to which the data processing device belongs is the same as or different from the processing chip to which the first cache unit and the second cache unit belong.

[0168] In some embodiments, the processing chip includes but is not limited to: a central processing unit (CPU), a graphics processing unit (GPU), an embedded neural network processor (NPU), and a data processing unit (DPU).

[0169] In a data processing system that includes multiple processing chips, such as a CC-NUMA system, a cache unit can access memory data of the same processing chip as well as memory data of other processing chips, thus achieving cross-CPU access.

[0170] In a CC-NUMA system, distributed memory is connected to form a single memory. There is no page or data replication between memories, and no software message transmission. Accessing local memory on a processing chip is relatively fast, but accessing remote memory belonging to another processing chip is slower due to the additional latency incurred by the interconnection network. CC-NUMA has only one memory image, and the memory of each processing chip is physically connected using copper cables and certain intelligent hardware. Cache coherence means that software is not required to maintain the consistency of multiple copies of data, nor is software required to implement data transfer between the operating system and application systems. Like SMP systems, CC-NUMA systems manage a single operating system and multiple processors entirely at the hardware level.

[0171] The CC-NUMA system shown in Figure 16 includes four processing chips, each of which is connected in pairs. The cache unit within a processing chip can implement cross-chip memory data access. It should be noted that the embodiments of this disclosure do not limit the connection method of the processing chips in the CC-NUMA system. For example, the processing chips can also be connected in series.

[0172] An embodiment of the present disclosure further provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor, so that the processor implements the data processing method provided above.

[0173] It will be appreciated by those skilled in the art that all or some of the steps in the method disclosed above, and the functional modules / units in the device can be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor (such as a central processing unit, a digital signal processor, or a microprocessor), or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0174] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A data processing method, applied to a first cache unit in a data processing system, comprising: Predicting that the second cache unit is a target cache unit, and sending a first data read request message to the second cache unit; wherein the first data read request message is used to read first target data from the target cache unit; receiving the first target data, and updating the state of the first target data according to the type of the first data read request message; A first data read response message is sent to the node that sent the first target data.

2. The method of claim 1, wherein: The node sending the first target data includes the second cache unit or a data processing device.

3. The method of claim 2, wherein: The node sending the first target data is a data processing device, and the method further includes: After sending the first data read response message to the data processing device, sending a second data read request message to the data processing device, wherein the second data read request message is used to read second target data from the data processing device; The second target data sent by the data processing device is received, and a second data read response message is sent to the data processing device.

4. The method of claim 1, wherein: The updating of the state of the first target data according to the type of the first data read request message comprises: When the type of the first data read request message is to read shared state data, updating the state of the first target data to a shared state; When the type of the first data read request message is to read data in an exclusive state, updating the state of the first target data to an exclusive state; In the case where the type of the first data read request message is to read invalid state data, the state of the first target data is maintained as an invalid state.

5. The method of claim 1, further comprising: After receiving the first target data, in a case where the type of the first data read request message is to read shared state data or to read exclusive state data, the first target data is cached.

6. The method according to any one of claims 1 to 5, further comprising: Before predicting that the second cache unit is the target cache unit, requesting to read the data n times, where n is an integer greater than or equal to 1; The predicting that the second cache unit is a target cache unit comprises: The cache units to which the data requested to be read each time belongs are determined, and the second cache unit is predicted to be the target cache unit based on the cache units.

7. The method of claim 6, wherein: One of the n requests to read data includes: Sending a third data read request message to the data processing device; receiving the third target data and the cache unit information storing the third target data sent by the data processing device, and updating the state of the third target data according to the type of the third data read request message; A third data read response message is sent to the data processing device.

8. The method of claim 6, wherein: The predicting, according to each of the cache units, that the second cache unit is the target cache unit comprises: In each of the cache units, a second cache unit located on a route from the first cache unit to the data processing device is predicted to be a target cache unit.

9. The method of claim 7, wherein: The first data read request message, the second data read request message and the third data read request message include one of the following: a shared state data read request message, an exclusive state data read request message, and an invalid state data read request message.

10. The method as claimed in claims 1 to 5, wherein: The data processing system includes a processing chip, a memory, and at least two levels of cache. The processing chip includes the data processing device. Each level of the cache includes at least one cache unit. The data processing device is a master node, or the data processing device is one of the cache units at a different level from the first cache unit and the second cache unit.

11. A data processing method, applied to a second cache unit in a data processing system, comprising: receiving a first data read request message sent by a first cache unit, where the first data read request message is used to read first target data from the second cache unit; In the case where it is determined that the first target data is stored in the second cache unit, the state of the first target data is updated according to the type of the first data read request message, and the first target data is sent to the first cache unit.

12. The method of claim 11, further comprising: After sending the first target data to the first cache unit, receiving a first data read response message sent by the first cache unit; After updating the state of the first target data according to the type of the first data read request message, in the case where the type of the first data read request message is to read shared state data or to read exclusive state data, sending a state update message to the data processing device, the state update message carrying the information, address information and state information of the first cache unit; wherein the state update message is used to instruct the data processing device to update the state of the first target data according to the state information and the address information, and to update the cache unit to which the first target data belongs according to the information of the first cache unit; Receive a status update response message sent by the data processing device.

13. The method of claim 11, further comprising: After receiving a first data read request message sent by the first cache unit, when it is determined that the first target data is not stored in the second cache unit, the first data read request message is sent to the data processing device, so that the data processing device can read the first target data from the memory and send the first target data to the first cache unit, and update the status of the first target data and the cache unit to which the first target data belongs.

14. The method according to any one of claims 11 to 13, wherein: The updating of the state of the first target data according to the type of the first data read request message comprises: When the type of the first data read request message is to read shared state data, updating the state of the first target data to a shared state; In a case where the type of the first data read request message is to read exclusive state data, updating the state of the first target data to an invalid state; When the type of the first data read request message is to read invalid state data, the state of the first target data is kept unchanged.

15. A data processing method, applied to a data processing device in a data processing system, comprising: Receive a status update message sent by the second cache unit, and obtain information, address information, and status information of the first cache unit carried in the status update message; updating the state of the corresponding first target data to the state information according to the address information, and updating the cache unit to which the first target data belongs to the first cache unit; Sending a status update response message to the second cache unit; or, receiving a first data read request message sent by the second cache unit, and acquiring information, address information, and status information of the first cache unit carried in the first data read request message; Reading first target data from the memory according to the address information, updating the state of the first target data to the state information, and updating the cache unit to which the first target data belongs to to the first cache unit; The first target data is sent to the first cache unit, and a first data read response message sent by the first cache unit is received.

16. A data processing method, applied to a data processing system including a first cache unit, a second cache unit and a data processing device, comprising: The first cache unit predicts that the second cache unit is a target cache unit, and sends a first data read request message to the second cache unit; The second cache unit, when determining that the first target data requested by the first data read request message is stored in the second cache unit, updates the state of the first target data according to the type of the first data read request message, and sends the first target data to the first cache unit; when the type of the first data read request message is to read shared state data or to read exclusive state data, sends a state update message to the data processing device; The data processing device obtains the information, address information and status information of the first cache unit carried in the status update message; updates the status of the corresponding first target data to the status information according to the address information, and updates the cache unit to which the first target data belongs to the first cache unit; or, The second cache unit sends a first data read request message to the data processing device when determining that the first target data requested by the first data read request message is not stored in the second cache unit; The data processing device obtains the information, address information and status information of the first cache unit carried in the first data read request message; reads the first target data from the memory according to the address information, updates the status of the first target data to the status information, and updates the cache unit to which the first target data belongs to the first cache unit; and sends the first target data to the first cache unit.

17. A data processing system, comprising at least one processing chip, wherein the processing chip comprises: A first cache unit is configured to predict that a second cache unit is a target cache unit and send a first data read request message to the second cache unit; and, receiving the first target data, and updating the state of the first target data according to the type of the first data read request message; a second cache unit, configured to receive a first data read request message sent by the first cache unit, and when determining that the first target data requested by the first data read request message is stored in the second cache unit, update the state of the first target data according to the type of the first data read request message, and send the first target data to the first cache unit; a data processing device configured to receive a status update message sent by the second cache unit, obtain information, address information and status information of the first cache unit carried in the status update message; update the status of the corresponding first target data to the status information according to the address information, and update the cache unit to which the first target data belongs to the first cache unit; Alternatively, a first data read request message sent by the second cache unit is received, and the information, address information and status information of the first cache unit carried in the first data read request message are obtained; first target data is read from the memory according to the address information, the status of the first target data is updated to the status information, and the cache unit to which the first target data belongs is updated to the first cache unit; and the first target data is sent to the first cache unit.

18. The data processing system of claim 17, wherein: The processing system includes a memory and at least two levels of cache, each level of the cache includes at least one cache unit, the data processing device is a master node, or the data processing device is one of the cache units at a different level from the first cache unit and the second cache unit.

19. The data processing system of claim 17, wherein: The data processing system is a symmetric multiprocessor system or a cache consistency non-uniform storage access system.

20. The data processing system of claim 19, wherein: There are at least two processing chips, each of which is connected to at least another processing chip. The processing chip to which the data processing device belongs is the same as or different from the processing chip to which the first cache unit and the second cache unit belong.

21. The data processing system according to any one of claims 17 to 20, wherein: The processing chip is one of the following: a central processing unit, a graphics processing unit, an embedded neural network processor, and a data processor.

22. A computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor so that the processor implements the data processing method as described in any one of claims 1 to 10, the data processing method as described in claims 11 to 14, the data processing method as described in claim 15, or the data processing method as described in claim 16.

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