Magnetic integrated conversion circuit

Abstract

Disclosed in the present invention is a magnetic integrated conversion circuit. The magnetic integrated conversion circuit comprises a primary-side circuit, a first secondary-side circuit, and a second secondary-side circuit, which are connected to a transformer, wherein the second secondary-side circuit has a buck switch that is connected to a center tap end of a second secondary-side winding of the transformer, and the second secondary-side circuit comprises a bleeder circuit which comprises a switch tube Qsnu, and a capacitor Csnu, one end of the switch tube Qsnu being connected to the capacitor Csnu in series, and then being connected between the center tap end of the second secondary-side winding and a switch tube Qbuck, and the other end of the switch tube being connected between a synchronous rectifier circuit and a low-voltage battery. Compared with the prior art, the present invention greatly reduces the voltage stress of a synchronous rectifier switch tube, without increasing the hardware costs, effectively reduces the voltage stress of a buck switch, greatly improves the output power of a magnetic integrated conversion circuit during operation, and improves the reliability of a product.

Description

A magnetic integrated conversion circuit Technical Field

[0001] The present invention relates to a vehicle-mounted charger, in particular to a magnetic integrated conversion circuit. Background Art

[0002] Magnetic integration topology is widely used in vehicle-mounted CCUs. Its novel control method realizes a two-in-one OBC / INV+DCDC solution, saving a DCDC transformer and corresponding switching devices.

[0003] The negative impact is that when the magnetic integration topology works in OBC / INV+DCDC, the output voltage on the low-voltage battery side needs to be regulated by the buck switch. At this time, the high current on the low-voltage side is cut off by the buck switch, and the voltage stress generated by the leakage inductance is relatively large.

[0004] On the other hand, the buck switch and the synchronous rectifier switch have strict requirements on the turn-on timing. The buck switch must be turned off during the dead zone of the high-voltage side battery drive. Otherwise, the voltage stress of the synchronous rectifier switch will be superimposed with an additional voltage stress spike of the buck switch.

[0005] Theoretically, the average voltage stress of a synchronous rectifier switch is twice that of a buck switch, making it more likely to reach a bottleneck at high voltages. This limitation significantly limits the output power on the low-voltage battery side when operating in OBC / INV+DCDC mode. Given the increasing demand for low-voltage power and cost sensitivity in electric vehicles, addressing the voltage stress of switches in the low-voltage circuits of magnetic integrated topologies at high currents is a pressing challenge within the industry. Summary of the Invention

[0006] In view of the problem in the prior art that the output power on the low-voltage battery side is significantly reduced due to the voltage stress limitation of the synchronous rectifier switch tube and the buck switch, the present invention proposes a magnetic integrated conversion circuit.

[0007] The technical solution of the present invention is to propose a magnetic integrated conversion circuit, comprising:

[0008] A transformer having a primary winding, a first secondary winding, and a second secondary winding having a center tap;

[0009] a primary circuit connected between the primary winding and the bus capacitor and comprising a first bridge arm and a second bridge arm;

[0010] a first secondary circuit connected between the first secondary winding and the high-voltage battery, and comprising a third bridge arm and a fourth bridge arm;

[0011] a second secondary winding connected between the second secondary winding and a low-voltage battery, and comprising a synchronous rectifier circuit and a power switching circuit having a step-down switch connected to a center tap of the second secondary winding;

[0012] The buck switch is a switch tube Qbuck, and the second secondary circuit includes a discharge circuit, and the discharge circuit is used to reduce the voltage stress on the buck switch;

[0013] The discharge circuit includes: a switch tube Qsnu and a capacitor Csnu;

[0014] Among them, one end of the switch tube Qsnu is connected in series with the capacitor Csnu and then connected between the center tap end of the second secondary winding and the switch tube Qbuck, and the other end is connected between the synchronous rectification circuit and the low-voltage battery.

[0015] Furthermore, the turn-off time of the buck switch is set within the conduction time of the switch tube Qsnu, so as to reduce the voltage stress of the buck switch and realize zero voltage turn-off of the buck switch.

[0016] Furthermore, the switch tube Qsnu is turned on before each state switching of the buck switch, and is turned off after each state switching of the buck switch, so as to realize soft switching of the buck switch.

[0017] Furthermore, the switch tube Qsnu is in a normally closed state, so as to reduce the voltage stress of the step-down switch.

[0018] Furthermore, the turn-on time of the buck switch is set after the switch tube Qsnu is turned on, so as to reduce the voltage stress of the buck switch and realize soft switching of the buck switch.

[0019] Furthermore, a delay time is provided between the control timings of the switch tubes located on the third bridge arm and the fourth bridge arm and at the diagonal positions in the first secondary circuit, and the turn-off moment of the step-down switch is set within the delay time of the turn-off moment of the switch tubes located at the diagonal positions in the first secondary circuit.

[0020] Furthermore, all switching tubes in the primary circuit operate at a fixed duty cycle of 50%, and are located on the first bridge arm and the second bridge arm. The control timing of the switching tubes at opposite corners is the same, and the upper arm switch and the lower arm switch located in the same bridge arm work in a complementary manner.

[0021] Furthermore, all the switches in the first secondary circuit operate at a fixed duty cycle of 50%, and the upper arm switch and the lower arm switch in the same bridge arm are complementary to each other;

[0022] The control timing of the lower arm switch of the fourth bridge arm is later than the control timing of the upper arm switch of the third bridge arm, and the delay time is delayed;

[0023] The control timing of the upper arm switch of the fourth bridge arm is later than the control timing of the lower arm switch of the third bridge arm, and the delay time is delayed.

[0024] Furthermore, the magnetic integrated conversion circuit can operate in three working modes:

[0025] An OBC mode is used for the bus capacitor to charge the high-voltage battery, and the second secondary circuit is in operation;

[0026] INV mode, used for the high-voltage battery to charge the bus capacitor and the second secondary circuit to operate;

[0027] The DCDC mode is used for the high-voltage battery to charge the low-voltage battery.

[0028] Furthermore, the second secondary circuit includes a switch tube QSRA and a switch tube QSRB constituting the synchronous rectification circuit, a switch tube Qbuck, a switch tube Qdsr, an inductor Lk, an inductor Lbuck constituting the power switching circuit, and a capacitor CLO connected to both ends of the low-voltage battery;

[0029] One end of the switch tube Qbuck is connected in series with the inductor Lk and then connected to the center tap end of the second secondary winding. The other end of the switch tube Qbuck is connected in series with the inductor Lbuck and then connected to the first end of the capacitor CLO. One end of the switch tube QSRB is connected to the second end of the second secondary winding, and the other end of the switch tube QSRB is connected to the second end of the capacitor CLO. One end of the switch tube QSRA is connected to the first end of the second secondary winding, and the other end of the switch tube QSRA is connected between the switch tube QSRB and the capacitor CLO. One end of the switch tube Qdsr is connected between the switch tube Qbuck and the inductor Lbuck, and the other end of the switch tube Qdsr is connected between the switch tube QSRB and the capacitor CLO.

[0030] Furthermore, the primary circuit includes: a switch tube Q1, a switch tube Q2, a switch tube Q3, a switch tube Q4, an inductor Lr, and a capacitor Cr;

[0031] The switch tube Q1 and the switch tube Q3 form the first bridge arm, and two ends of the first bridge arm are respectively connected to two ends of the bus capacitor;

[0032] The switch tube Q2 and the switch tube Q4 form the second bridge arm, and two ends of the second bridge arm are respectively connected to two ends of the bus capacitor;

[0033] The first end of the primary winding is connected in series with the capacitor Cr and the inductor Lr and then connected to the midpoint of the first bridge arm, and the second end of the primary winding is connected to the midpoint of the second bridge arm.

[0034] Furthermore, the first secondary circuit includes: a switch tube Q5, a switch tube Q6, a switch tube Q7, a switch tube Q8, a capacitor Cdc, and a capacitor CHO;

[0035] The switch tube Q5 and the switch tube Q7 form the third bridge arm, and two ends of the third bridge arm are respectively connected to two ends of the capacitor CHO;

[0036] The switch tube Q6 and the switch tube Q8 form the fourth bridge arm, and two ends of the fourth bridge arm are respectively connected to two ends of the capacitor CHO;

[0037] The first end of the first secondary winding is connected to the midpoint of the fourth bridge arm, and the second end of the first secondary winding is connected in series with the capacitor Cdc and then connected to the midpoint of the third bridge arm.

[0038] Compared with the prior art, the present invention has at least the following beneficial effects:

[0039] The present invention significantly reduces the voltage stress of the synchronous rectifier switch tube without increasing the hardware cost, effectively reduces the voltage stress of the buck switch, significantly improves the output power of the magnetic integrated conversion circuit during operation, and improves the reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] FIG1 is a circuit topology diagram of a magnetic integrated conversion circuit in a first embodiment of the present invention;

[0042] FIG2 is a control timing diagram of the magnetic integrated conversion circuit in the first embodiment of the present invention;

[0043] 3 is a control timing diagram of a magnetic integrated conversion circuit in a second embodiment of the present invention;

[0044] FIG4 is a control timing diagram of a magnetic integrated conversion circuit in a third embodiment of the present invention;

[0045] 5 is a control timing diagram of a magnetic integrated conversion circuit according to a fourth embodiment of the present invention;

[0046] FIG6 is a circuit topology diagram of a magnetic integrated conversion circuit in a second embodiment of the present invention;

[0047] FIG7 is a circuit topology diagram of a magnetic integrated conversion circuit in a third embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0049] Thus, a feature indicated in this specification is intended to illustrate one of the features of one embodiment of the present invention, rather than to imply that every embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although certain features can be combined together to illustrate possible system designs, these features can also be used in other, not explicitly described, combinations. Thus, unless otherwise noted, the described combinations are not intended to be limiting.

[0050] The principle and structure of the present invention are described in detail below with reference to the accompanying drawings and embodiments.

[0051] In existing magnetic integration topologies, the output voltage on the low-voltage battery side needs to be regulated by a buck switch. At this time, the high current on the low-voltage side is cut off by the buck switch, resulting in high voltage stress due to leakage inductance.

[0052] On the other hand, the buck switch and the synchronous rectifier switch have strict requirements on the turn-on timing. The buck switch must be turned off during the dead zone of the high-voltage side battery drive. Otherwise, the voltage stress of the synchronous rectifier switch will be superimposed with an additional voltage stress spike of the buck switch.

[0053] Theoretically, the average voltage stress of a synchronous rectifier switch is twice that of a buck switch, making it more susceptible to bottlenecks at high voltages, significantly limiting the output power on the low-voltage battery side. The present invention employs phase-shift control of the first secondary circuit, so that after rectification by the synchronous rectifier switch, the voltage at the center tap of the transformer's second secondary winding exhibits a discontinuous interval. The buck switch's turn-off time is set within this discontinuous interval, thereby freeing the synchronous rectifier switch from the voltage stress of the buck switch. Furthermore, the present invention includes a bleeder circuit that prevents the voltage of the leakage inductor Lk from rising toward the buck switch, thereby reducing the voltage stress on the buck switch and achieving soft switching control of the buck switch.

[0054] Specifically, the magnetic integrated conversion circuit proposed in the present invention includes:

[0055] A transformer having a primary winding, a first secondary circuit, and a second secondary winding having a center tap;

[0056] a primary circuit connected between the primary winding and the bus capacitor and comprising a first bridge arm and a second bridge arm;

[0057] a first secondary circuit connected between the first secondary winding and the high-voltage battery, and comprising a third bridge arm and a fourth bridge arm;

[0058] A second secondary winding is connected between the second secondary winding and the low-voltage battery and includes a synchronous rectification circuit and a power switching circuit, wherein the power switching circuit has a step-down switch connected to the center tap end of the second secondary winding.

[0059] The control concept of the present invention is to add a bleeder circuit in the second secondary circuit to prevent the voltage rise of the leakage inductor Lk toward the buck switch, thereby preventing the voltage rise of the buck switch and reducing the voltage stress on the buck switch. The bleeder circuit includes: a switch tube Qsnu, a capacitor Csnu;

[0060] Among them, one end of the switch tube Qsnu is connected in series with the capacitor Csnu and then connected between the center tap end of the second secondary winding and the switch tube Qbuck, and the other end is connected between the synchronous rectification circuit and the low-voltage battery.

[0061] This design can reduce the voltage stress on the buck switch, thereby achieving a soft switching function of the buck switch.

[0062] In addition, the control concept of the present invention also includes: adopting phase-shift control on the first secondary circuit, so that a delay time is provided between the control timing of the switch tubes located on the third bridge arm and the fourth bridge arm and at the diagonal position in the first secondary circuit, and the turn-off time of the step-down switch is set within the delay time of the turn-off time of the switch tubes located at the diagonal position in the first secondary circuit.

[0063] The phrase "setting the turn-off time of the buck switch at the delay time of the turn-off time of the diagonally opposite switch tube" means that for a pair of diagonally opposite switch tubes, after one switch tube is turned off first, the other switch tube is turned off after a delay time, and the turn-off time of the buck switch is set after the switch tube that is turned off first is turned off and before the switch tube that is turned off with delay is turned off.

[0064] By adopting the above-mentioned control method, the present invention can ensure that after the synchronous rectifier switch tube is rectified, a discontinuous interval appears in the voltage at the center tap end of the second secondary winding of the transformer. At the same time, the turn-off moment of the buck switch is set within the discontinuous interval, so that the synchronous rectifier switch tube is no longer subjected to the voltage stress superposition of the buck switch, thereby greatly reducing the voltage stress of the synchronous rectifier switch tube and effectively reducing the voltage stress of the buck switch, thereby greatly improving the output power of the magnetic integrated conversion circuit during operation and improving the reliability of the product.

[0065] Referring to FIG1 , the primary circuit of the present invention includes: a switch tube Q1 , a switch tube Q2 , a switch tube Q3 , a switch tube Q4 , an inductor Lr , and a capacitor Cr;

[0066] The switch tube Q1 and the switch tube Q3 form a first bridge arm, and the two ends of the first bridge arm are respectively connected to the two ends of the bus capacitor;

[0067] The switch tube Q2 and the switch tube Q4 form a second bridge arm, and the two ends of the second bridge arm are respectively connected to the two ends of the bus capacitor;

[0068] The first end of the primary winding is connected in series with the capacitor Cr and the inductor Lr and then connected to the midpoint of the first bridge arm, and the second end of the primary winding is connected to the midpoint of the second bridge arm.

[0069] The first secondary circuit includes: a switch tube Q5, a switch tube Q6, a switch tube Q7, a switch tube Q8, a capacitor Cdc, and a capacitor CHO;

[0070] The switch tube Q5 and the switch tube Q7 form a third bridge arm, and two ends of the third bridge arm are respectively connected to two ends of the capacitor CHO;

[0071] The switch tube Q6 and the switch tube Q8 form a fourth bridge arm, and two ends of the fourth bridge arm are respectively connected to two ends of the capacitor CHO;

[0072] The first end of the first secondary winding is connected to the midpoint of the fourth bridge arm, and the second end of the first secondary winding is connected in series with a capacitor Cdc and then connected to the midpoint of the third bridge arm.

[0073] The second secondary circuit includes the switching tubes QSRA and QSRB that constitute the synchronous rectification circuit, the switching tubes Qbuck and Qdsr that constitute the power switching circuit, the inductor Lk, the inductor Lbuck, and the capacitor CLO connected to both ends of the low-voltage battery;

[0074] One end of the switch tube Qbuck is connected in series with the inductor Lk and then connected to the center tap end of the second secondary winding. The other end of the switch tube Qbuck is connected in series with the inductor Lbuck and then connected to the first end of the capacitor CLO. One end of the switch tube QSRB is connected to the second end of the second secondary winding, and the other end of the switch tube QSRB is connected to the second end of the capacitor CLO. One end of the switch tube QSRA is connected to the first end of the second secondary winding, and the other end of the switch tube QSRA is connected between the switch tube QSRB and the capacitor CLO. One end of the switch tube Qdsr is connected between the switch tube Qbuck and the inductor Lbuck, and the other end of the switch tube Qdsr is connected between the switch tube QSRB and the capacitor CLO.

[0075] The control timing of the primary circuit in the present invention is:

[0076] All switching tubes in the primary circuit operate at a fixed duty cycle of 50% and are located on the first and second bridge arms. The control timing of the switching tubes at opposite corners is the same, and the upper arm switch and the lower arm switch in the same bridge arm work in a complementary manner.

[0077] 1 and 2 , the switch tube Q1 and the switch tube Q3 form a first bridge arm, with the switch tube Q1 being the upper arm switch and the switch tube Q3 being the lower arm switch;

[0078] The switch tube Q2 and the switch tube Q4 form a second bridge arm, with the switch tube Q2 being the upper arm switch and the switch tube Q4 being the lower arm switch;

[0079] Here, the switch tubes Q1 and Q4 are diagonally located switch tubes, and the switch tubes Q2 and Q3 are diagonally located switch tubes;

[0080] From the control timing in Figure 2, it's clear that the control timings for switches Q2 and Q3 are completely consistent, as are the control timings for switches Q1 and Q4. Furthermore, without considering dead time, switches Q1 and Q3 operate in a complementary manner, as do switches Q2 and Q4. The control timing in Figure 2 takes dead time into account, with this dead time being provided between the control timings for switches Q2 and Q3 and the control timings for switches Q1 and Q4 to prevent short circuits caused by simultaneous conduction of the same bridge arm.

[0081] Here, complementary conduction means that the phase difference between the control timings of the two switching tubes is 180 degrees, and when one switching tube is in the on state, the other switching tube is in the off state.

[0082] Furthermore, the control timing of the first secondary circuit in the present invention is:

[0083] All switches in the first secondary circuit operate at a fixed duty cycle of 50%, and the upper arm switch and the lower arm switch in the same bridge arm are complementary to each other.

[0084] The control timing of the lower arm switch of the fourth bridge arm is later than the control timing of the upper arm switch of the third bridge arm, and is delayed by the above delay time;

[0085] The control timing of the upper arm switch of the fourth bridge arm is later than the control timing of the lower arm switch of the third bridge arm, and is delayed by the above delay time.

[0086] 1 and 2 , the switch tube Q5 and the switch tube Q7 form the third bridge arm, with the switch tube Q5 being the upper arm switch and the switch tube Q7 being the lower arm switch;

[0087] The switch tube Q6 and the switch tube Q8 form a fourth bridge arm, with the switch tube Q6 being the upper arm switch and the switch tube Q8 being the lower arm switch;

[0088] Here, the switch tube Q5 and the switch tube Q8 are switch tubes located at opposite corners, and the switch tube Q6 and the switch tube Q7 are switch tubes located at opposite corners.

[0089] From the control sequence in Figure 2, it's clear that, without considering the dead time, switches Q5 and Q7 operate in a complementary manner, and switches Q6 and Q8 operate in a complementary manner. The control sequence shown in Figure 2 takes the dead time into account. This dead time is set between the control sequence of switches Q5 and Q7, and between the control sequence of switches Q6 and Q8, to prevent the problem of simultaneous conduction of the same bridge arm causing a short circuit. As shown in Figure 2, DT represents the dead time. The intervals between the switching between switches Q1 and Q3, Q2 and Q4, Q5 and Q7, and Q6 and Q8 all contain this dead time.

[0090] At the same time, as shown in FIG2 , the control timing of the switch tube Q8 is later than the control timing of the switch tube Q5 , and the delay is a time T, which is also the above-mentioned delay time;

[0091] The control timing of the switch tube Q6 is later than the control timing of the switch tube Q7, and the delayed time is also the above-mentioned time T (not shown in FIG2 ), that is, the above-mentioned delay time.

[0092] By applying the above control method to the switches in the first secondary circuit, after rectification by the synchronous rectifier switches, the voltage at the center tap of the transformer's second secondary winding exhibits a discontinuous interval. As shown in Figure 2, Vn represents the voltage at the center tap of the second secondary winding, which is zero between the time switch Q5 turns off and the time switch Q6 turns on. This period is also referred to as the discontinuous interval. (Similarly, the voltage between the time switch Q7 turns off and the time switch Q8 turns on is also zero, also a discontinuous interval.) In the present invention, the buck switch's turn-off time is set within this discontinuous interval. Because the voltage at the center tap of the second secondary winding is zero during this discontinuous interval, the synchronous rectifier switches are no longer subject to the voltage stress of the buck switch, significantly reducing the voltage stress of the synchronous rectifier switches while also effectively reducing the voltage stress of the buck switch. As shown in Figure 1, the synchronous rectifier switches are switches QSRA and QSRB, and the buck switch is switch Qbuck.

[0093] As shown in FIG2 , DT is the dead time. Without considering the dead time, the turn-off time of the buck switch in the present invention is actually set after the switch tube Q5 is turned off and before the switch tube Q8 is turned off (or after the switch tube Q7 is turned off and before the switch tube Q6 is turned off). That is, as pointed out in the above setting, the turn-off time of the buck switch is set within the delay time of the turn-off time of the diagonally opposite switch tube in the first secondary circuit.

[0094] Furthermore, the present invention further provides a discharge circuit in the second secondary circuit, which includes: a switch tube Qsnu, a capacitor Csnu;

[0095] Among them, one end of the switch tube Qsnu is connected in series with the capacitor Csnu and then connected between the inductor Lk and the switch tube Qbuck.

[0096] The other end of the switch tube Qsnu is connected between the switch tube QSRB and the capacitor CLO.

[0097] That is, as mentioned above, "one end of the switch tube Qsnu is connected in series with the capacitor Csnu and then connected between the center tap end of the second secondary winding and the switch tube Qbuck, and the other end is connected between the synchronous rectification circuit and the low-voltage battery."

[0098] Its working principle is that when the buck switch is turned off, the current in the leakage inductor Lk cannot change suddenly, so it will continue in the direction when the buck switch is turned on. At this time, the current will flow into the capacitor Csnu in the discharge circuit. At this time, the capacitor Csnu will play an absorbing role, preventing the voltage of the leakage inductor Lk from rising toward the buck switch, thereby reducing the voltage stress on the buck switch.

[0099] Here, whether the capacitor Csnu is connected to the second secondary circuit is controlled by the switch tube Qsnu. Only when the switch tube Qsnu is turned on, the capacitor Csnu is connected to the second secondary circuit to absorb the current on the leakage inductor Lk.

[0100] Regarding the control logic of the switch tube Qsnu, the present invention is provided with four control modes. Please refer to Figure 2, which is a control timing diagram of the magnetic integrated conversion circuit in the first embodiment of the present invention. In this embodiment, the switch tube Qsnu is in a normally closed state, which is used to reduce the voltage stress of the buck switch.

[0101] Please refer to Figure 3, which shows a control timing diagram for a magnetically integrated converter circuit according to a second embodiment of the present invention. In this embodiment, the turn-on timing of switch Qsnu is set before each state transition of the buck switch, and the turn-off timing is set after each state transition of the buck switch, thereby achieving soft switching of the buck switch. As shown in Figure 3, the turn-on timing of switch Qsnu is set before the turn-off timing of switch Q5, and the turn-off timing is set after the turn-off timing of switch Q8. Furthermore, the turn-on timing of switch Qsnu precedes the turn-off timing of switch Q5 by a very short period of time, and the turn-off timing of switch Qsnu lags behind the turn-off timing of switch Q8 by a very short period of time, thereby minimizing losses in the magnetically integrated converter circuit.

[0102] It should be noted here that the turn-on moment of the switch tube Qsnu is set before the turn-off moment of the switch tube Q5 and the turn-off moment is set after the turn-off moment of the switch tube Q8 because the turn-off moment of the buck switch is between the turn-off moment of the switch tube Q5 and the turn-off moment of the switch tube Q8. This setting can completely ensure that the turn-on moment of the switch tube Qsnu is before the turn-off moment of the buck switch and the turn-off moment of the switch tube Qsnu is after the turn-off moment of the buck switch.

[0103] It should be noted that FIG3 only shows the action of the switch tube Qsnu when the switch tube Qbuck is turned off for the first time and turned on for the second time. In fact, each time the state of the switch tube Qbuck is switched, the switch tube Qsnu will be switched according to the above control logic.

[0104] Similarly, since the turn-off time of the buck switch is also between the turn-off time of the switch tube Q7 and the turn-off time of the switch tube Q6, the present invention also sets the turn-on time of the switch tube Qsnu to be before the turn-off time of the switch tube Q7 and the turn-off time to be after the turn-off time of the switch tube Q6.

[0105] Please refer to Figure 3. Vn1 is the voltage from the leakage inductor Lk to the switch tube Qbuck. It can be clearly seen from the schematic diagram in Figure 3 that after the switch tube Qsnu is turned on, the voltage drops significantly. In other words, the capacitor Csnu absorbs the current, reducing the voltage. At the same time, it also reduces the voltage stress on the switch tube Qbuck. This can achieve soft switching of the switch tube Qbuck. However, the control timing is relatively complex and requires high computing power of the controller.

[0106] Please refer to Figure 4, which is a control timing diagram of the magnetic integrated conversion circuit in the third embodiment of the present invention. In this embodiment, the buck switch's turn-off time is set within the on-time of the switch tube Qsnu to reduce the voltage stress of the buck switch and achieve zero-voltage shutdown of the buck switch. As shown in Figure 4, the buck switch's turn-off time is set within the on-time of the switch tube Qsnu, and its voltage Vbuck is always 0 when the buck switch is in the off-time, thus achieving zero-voltage shutdown of the buck switch. In this case, there is no specific requirement for the buck switch's on-time, so the controller's computing power requirements are relatively low. However, it can only achieve zero-voltage shutdown and cannot fully achieve soft switching.

[0107] Please refer to Figure 5, which shows a control timing diagram of the magnetic integrated converter circuit in a fourth embodiment of the present invention. In this embodiment, the buck switch is turned on after the switch transistor Qsnu is turned on, which reduces the voltage stress of the buck switch and achieves soft switching of the buck switch. In this embodiment, it is sufficient to ensure that the buck switch is turned on after the switch transistor Qsnu is turned on. This reduces the computing power requirements of the controller and achieves soft switching of the buck switch.

[0108] The present invention proposes that the magnetic integrated conversion circuit can operate in three modes:

[0109] OBC mode is used for the bus capacitor to charge the high-voltage battery, and the second secondary circuit is running;

[0110] INV mode is used for the high-voltage battery to charge the bus capacitor and the second secondary circuit is running;

[0111] DCDC mode is used for high-voltage batteries to charge low-voltage batteries.

[0112] To reduce losses in the magnetic integrated converter circuit, the present invention controls the switch Qsnu to be closed in OBC and INV modes and to be open in DCDC mode. The aforementioned switch Qsnu is normally closed, meaning it is closed in OBC and INV modes. This approach reduces losses caused by the switch Qsnu in DCDC mode.

[0113] Furthermore, in this solution, it is necessary to ensure that the switch tube Qsnu has a strong instantaneous circuit-passing capability. Therefore, in the present invention, the switch tube Qsnu can be set to an NMOS tube. Under this setting, the connection direction of the switch tube Qsnu needs to be reversed. Figure 6 is a topological diagram of the magnetic integrated conversion circuit under this embodiment. Compared with Figure 1, it can be found that since the switch tube Qsnu adopts an NMOS tube, its connection direction in Figure 6 is exactly opposite to the connection direction in Figure 1.

[0114] Furthermore, the above-mentioned control timing of the present invention is not limited to the embodiments of Figures 1 and 6. In other embodiments of the present invention, the positions of the switch tube Qsnu and the capacitor Csnu can also be swapped. As shown in Figure 7, one end of the switch tube Qsnu is connected between the inductor Lk and the switch tube Qbuck, and the other end is connected in series with the capacitor Csnu and then connected between the switch tube QSRB and the capacitor CLO.

[0115] Among them, for the four embodiments of the control timing of the switch tube Qbuck in the discharge circuit, the control timing of the first embodiment can be applied to the embodiment of the magnetic integrated conversion circuit in Figure 1, and the control timing of the second, third, and fourth embodiments can be applied to the embodiments of the magnetic integrated conversion circuit in Figures 6 and 7.

[0116] In summary, compared with the prior art, the present invention significantly reduces the voltage stress of the synchronous rectifier switch tube without increasing the hardware cost, and also effectively reduces the voltage stress of the buck switch, thereby significantly improving the output power of the magnetic integrated conversion circuit during operation and improving the reliability of the product.

[0117] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A magnetic integrated conversion circuit, characterized in that: include: A transformer having a primary winding, a first secondary winding, and a second secondary winding having a center tap; A primary circuit connected between the primary winding and the bus capacitor and comprising a first bridge arm and a second bridge arm; a first secondary circuit connected between the first secondary winding and the high-voltage battery, and comprising a third bridge arm and a fourth bridge arm; a second secondary winding connected between the second secondary winding and the low-voltage battery, and comprising a synchronous rectification circuit and a power switch circuit, wherein the power switch circuit has a step-down switch connected to a center tap end of the second secondary winding; The step-down switch is a switch tube Q buck , the second secondary circuit includes a discharge circuit, and the discharge circuit is used to reduce the voltage stress on the buck switch; The discharge circuit includes: a switch tube Q snu , capacitor C snu ; Among them, the switch tube Q snu One end is connected in series with the capacitor C snu Then connected to the center tap end of the second secondary winding and the switch tube Q buck and the other end is connected between the synchronous rectification circuit and the low-voltage battery.

2. The magnetic integrated conversion circuit according to claim 1, characterized in that: The turn-off time of the step-down switch is set at the switch tube Q snu During the on-time of the buck switch, the voltage stress of the buck switch is reduced to achieve zero voltage shutdown of the buck switch.

3. The magnetic integrated conversion circuit according to claim 1, characterized in that: The switch tube Q snu The on-time is set before each state switching of the buck switch, and the off-time is set after each state switching of the buck switch, so as to realize the soft switching of the buck switch.

4. The magnetic integrated conversion circuit according to claim 1, characterized in that: The switch tube Q snu It is in a normally closed state, and is used to reduce the voltage stress of the step-down switch.

5. The magnetic integrated conversion circuit according to claim 1, characterized in that: The conduction time of the step-down switch is set at the switch tube Q snu After being turned on, it is used to reduce the voltage stress of the buck switch and realize soft switching of the buck switch.

6. The magnetic integrated conversion circuit according to claim 1, characterized in that: A delay time is provided between the control timings of the switch tubes located on the third bridge arm and the fourth bridge arm and at the diagonal positions in the first secondary circuit, and the turn-off time of the step-down switch is provided within the delay time of the turn-off time of the switch tubes located at the diagonal positions in the first secondary circuit.

7. The magnetic integrated conversion circuit according to claim 6, characterized in that: All switch tubes in the primary circuit operate at a fixed duty cycle of 50% and are located on the first bridge arm and the second bridge arm. The control timing of the switch tubes at the diagonal positions is the same, and the upper arm switch and the lower arm switch located on the same bridge arm work in a complementary manner.

8. The magnetic integrated conversion circuit according to claim 6, characterized in that: All the switch tubes in the first secondary circuit operate at a fixed duty cycle of 50%, and the upper arm switch and the lower arm switch located in the same bridge arm operate in a complementary manner; The control timing of the lower arm switch of the fourth bridge arm is later than the control timing of the upper arm switch of the third bridge arm, and the delay time is delayed; The control timing of the upper arm switch of the fourth bridge arm is later than the control timing of the lower arm switch of the third bridge arm, and the delay time is delayed.

9. The magnetic integrated conversion circuit according to any one of claims 1 to 8, characterized in that: The magnetic integrated conversion circuit can work in three working modes, namely: OBC mode, used for the bus capacitor to charge the high-voltage battery, and the second secondary circuit is running; INV mode, used for the high-voltage battery to charge the bus capacitor, and the second secondary circuit is running; The DCDC mode is used for the high voltage battery to charge the low voltage battery.

10. The magnetic integrated conversion circuit according to any one of claims 1 to 8, characterized in that: The second secondary circuit includes a switch tube Q constituting the synchronous rectification circuit. SRA And the switch tube Q SRB , the switch tube Q constituting the power switch circuit buck , switch tube Q dsr 、Inductance L k 、Inductance L buck , and a capacitor C connected to both ends of the low voltage battery LO ; The switch tube Q buck One end is connected in series with the inductor L k Then connected to the center tap end of the second secondary winding, the switch tube Q buck The other end is connected in series with the sensor L buck After connecting to the capacitor C LO The first end of the switch tube Q SRB One end is connected to the second end of the second secondary winding, and the switch tube Q SRB The other end is connected to the capacitor C LO The second end of the switch tube Q SRA One end is connected to the first end of the second secondary winding, and the switch tube Q SRA The other end is connected to the switch tube Q SRB With the capacitor C LO Between the switch tube Q dsr One end is connected to the switch tube Q buck With the inductance L buck Between the switch tube Q dsr The other end is connected to the switch tube Q SRB With the capacitor C LO between.

11. The magnetic integrated conversion circuit according to any one of claims 1 to 8, characterized in that: The primary circuit includes: a switch tube Q1, a switch tube Q2, a switch tube Q3, a switch tube Q4, an inductor L r , capacitor C r ; The switch tube Q1 and the switch tube Q3 form the first bridge arm, and two ends of the first bridge arm are respectively connected to two ends of the bus capacitor; The switch tube Q2 and the switch tube Q4 form the second bridge arm, and two ends of the second bridge arm are respectively connected to two ends of the bus capacitor; The first end of the primary winding is connected in series with the capacitor C r 、Inductance L r The first end of the primary winding is connected to the midpoint of the first bridge arm, and the second end of the primary winding is connected to the midpoint of the second bridge arm.

12. The magnetic integrated conversion circuit according to any one of claims 1 to 8, characterized in that: The first secondary circuit includes: a switch tube Q5, a switch tube Q6, a switch tube Q7, a switch tube Q8, a capacitor C dc , capacitor C HO ; The switch tube Q5 and the switch tube Q7 form the third bridge arm, and the two ends of the third bridge arm are respectively connected to the capacitor C HO at both ends; The switch tube Q6 and the switch tube Q8 form the fourth bridge arm, and the two ends of the fourth bridge arm are respectively connected to the capacitor C HO at both ends; The first end of the first secondary winding is connected to the midpoint of the fourth bridge arm, and the second end of the first secondary winding is connected in series with the capacitor C dc Then connected to the midpoint of the third bridge arm.

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