Switch converter, and control circuit and control method therefor

Abstract

Disclosed in the present invention are a switch converter, a control circuit and control method therefor. The control circuit comprises an error signal generation module, which is used for generating an error signal; a PFM control module, which is used for generating a first control signal according to a magnitude relationship between a first feedback voltage of an output voltage and a first reference voltage, a magnitude relationship between the first feedback voltage and a third reference voltage and the error signal, generating a second control signal according to a magnitude relationship between the first feedback voltage and a second reference voltage and the first control signal, and generating a first set signal according to the second control signal and a clock signal; a reset signal generation module, which is used for generating a ramp voltage and generating a first reset signal by means of the ramp voltage and the error signal; and a logic and driving module, which is used for controlling the on and off of a high-side switch tube according to the first set signal and the first reset signal, wherein the second control signal is related to a load degree of the switch converter, and thus the timing of entering a PFM mode is accurately set.

Description

Switching converter and control circuit and control method thereof

[0001] This application claims priority to a Chinese invention application filed on June 30, 2023, with application number 202310796924.6 and titled “Switching converter, control circuit and control method thereof”, and incorporates the entire specification, claims, drawings and abstract of the above-mentioned Chinese invention application into this application by reference. Technical Field

[0002] The present invention relates to the technical field of electronic circuits, and in particular to a switching converter and a control circuit and a control method thereof. Background Art

[0003] Switching converters have been widely used in various fields and have become an indispensable part of people's lives.

[0004] In traditional voltage-mode controlled switching converters, the switching converter operates in continuous current mode (CCM) when the load is heavy, but in discontinuous current mode (DCM) when the load changes from heavy to light. In discontinuous current mode, the switching converter generally uses PFM modulation (pulse frequency modulation) technology. However, due to the lack of inductor current sampling information in the entire circuit and the slow loop response caused by the voltage-mode circuit structure itself, the load level entering PFM mode is difficult to control. At the same time, the PFM mode responds slowly and generates uneven waves when the load changes, resulting in large ripple and overshoot voltage at the output end, which has obvious limitations in practical applications.

[0005] Therefore, a new switching converter and its control circuit are needed to solve the above problems. Summary of the Invention

[0006] In view of the above problems, an object of the present invention is to provide a switching converter and a control circuit and a control method thereof, which are conducive to accurately setting the timing of entering the PFM mode.

[0007] According to one aspect of the present invention, a control circuit for a switching converter is provided. The switching converter includes a high-side switch and an inductor. The control circuit controls power transfer from an input voltage to an output voltage by controlling the on / off state of the high-side switch. The control circuit includes: an error signal generation module configured to generate an error signal having a voltage negatively correlated with a difference between a first feedback voltage and a first reference voltage of the output voltage of the switching converter based on a difference between the first feedback voltage and the first reference voltage when a first control signal is in an inactive state; and to set the voltage of the error signal to a first preset value when the first control signal is in an active state; a PFM control module configured to generate a first control signal based on a magnitude relationship between the first feedback voltage and the first reference voltage, a magnitude relationship between the first feedback voltage and a third reference voltage, and the error signal; generate a second control signal based on a magnitude relationship between the first feedback voltage and the second reference voltage and the first control signal; and generate a first set signal based on the second control signal and a first clock signal, wherein the second reference voltage is greater than the first reference voltage and less than the third reference voltage; and a reset signal generation module configured to generate a ramp voltage and generate a first reset signal using the ramp voltage and the error signal.

[0008] A logic and drive module is used to control the on and off of the high-side switch tube according to the first set signal and the first reset signal, wherein the second control signal is related to the load level of the switching converter.

[0009] Optionally, the PFM control module is configured as follows: when the first control signal is in an invalid state, if the voltage of the error signal meets a preset condition, then the first control signal is controlled to become a valid state; when the first control signal is in an invalid state, if the first feedback voltage is greater than the third reference voltage, then the first control signal is controlled to become a valid state; when the first control signal is in a valid state, if the first feedback voltage is less than the first reference voltage, then the first control signal is controlled to become an invalid state.

[0010] Optionally, the preset condition includes that the sum of the voltage magnitude of the error signal and the second feedback voltage of the output voltage is less than a second preset value; wherein, when the sum of the voltage magnitude of the error signal and the second feedback voltage of the output voltage is the second preset value, if the switching converter is in DCM mode, then at this time, the equivalent duty cycle of the high-side switching tube of the switching converter and the equivalent duty cycle of the high-side switching tube when the switching converter is in CCM mode reach a preset ratio, and the preset ratio is less than 1.

[0011] Optionally, the PFM control module includes: a first comparator, whose positive input terminal receives the first reference voltage, whose negative input terminal receives the first feedback voltage, and whose output terminal is used to provide a first comparison signal; a first buffer, whose positive input terminal receives the second feedback voltage of the output voltage, whose negative input terminal is grounded, whose first output terminal receives the error signal, and whose second output terminal is used to provide a duty cycle signal, wherein the duty cycle signal is obtained by superimposing the second feedback voltage of the output voltage and the error signal, and the second feedback voltage of the output voltage is greater than the first feedback voltage of the output voltage; a second comparator, whose positive input terminal receives the second preset value, and whose negative input terminal receives the duty cycle signal. a duty cycle signal, the output end of which is used to provide a second comparison signal; a third comparator, the positive input end of which receives the first feedback voltage, the negative input end of which receives the third reference voltage, and the output end of which is used to provide a third comparison signal; an OR gate, the first input end of which receives the third comparison signal, the second input end of which receives the second comparison signal, and the output end of which is used to provide a first logic signal; a first AND gate, the first input end of which receives the first logic signal, the second input end of which receives the clock signal, and the output end of which is used to provide a second set signal; a first flip-flop, the reset end of which receives the first comparison signal, the set end of which receives the second set signal, and the output end of which is used to provide the first control signal;

[0012] a fourth comparator, wherein the positive input terminal receives the first feedback voltage, the negative input terminal receives the second reference voltage, and the output terminal is used to provide the fourth comparison signal; a second AND gate, wherein the first input terminal receives the fourth comparison signal, the second input terminal receives the first control signal, and the output terminal is used to provide the second control signal; and a NOR gate, wherein the first input terminal receives the clock signal, the second input terminal receives the second control signal, and the output terminal is used to provide the first set signal.

[0013] Optionally, the error signal generating module includes: a first transconductance amplifier, whose positive input terminal receives the first feedback voltage of the output voltage, and whose negative input terminal receives the first reference voltage, and the first transconductance amplifier is used to differentially amplify the first feedback voltage of the output voltage and the first reference voltage; an amplification module, used to amplify the output of the first transconductance amplifier; a compensation module, used to compensate the output of the amplification module; an output module, including: a second transconductance amplifier, whose positive input terminal receives a fourth reference voltage, and whose negative input terminal is connected to the compensation module; a first switch, connected between the positive and negative input terminals of the second transconductance amplifier; and a first reference voltage source and a second switch, which are sequentially connected between the output terminal of the second transconductance amplifier and ground, and the first reference voltage source is used to provide the first preset value.

[0014] Optionally, the reset signal generating module is configured to: generate a ramp voltage with a first slope according to the second clock signal when the first control signal is in an invalid state; and generate a ramp voltage with a second slope according to the second clock signal when the first control signal is in a valid state, wherein the first slope is smaller than the second slope.

[0015] Optionally, the reset signal generating module includes: a third switch, a first end receiving a first feedback voltage of the input voltage, a second end connected to the first node, and a control end receiving the first control signal; a fourth switch, a first end receiving a second feedback voltage of the input voltage, a second end connected to the first node, the second feedback voltage of the input voltage being greater than the first feedback voltage of the input voltage; an inverter connected between the first control signal and the control end of the fourth switch; a third transconductance amplifier, a positive input end connected to the first node, a negative input end grounded, for differentially amplifying the voltage of the first node and the ground voltage to obtain a differential signal; a first capacitor, a first end connected to the output end of the third transconductance amplifier, a second end grounded; a fifth switch, a first end connected to the first end of the first capacitor, a second end grounded, and a control end connected to the second a clock signal, a common node between the first end of the fifth switch and the first end of the first capacitor is used to provide the ramp voltage; a second buffer, a positive input end receiving the first end of the fifth switch, a negative input end being grounded, a first output end being grounded through a second reference voltage source, and a second output end being used to superimpose the voltage of the first end of the fifth switch with the voltage provided by the second reference voltage source and output the second superimposed signal; a third buffer, a positive input end being connected to the output voltage, a negative input end being grounded, a first output end receiving the error signal, and a second output end being used to superimpose the output voltage with the error signal and output the first superimposed signal; a fifth comparator, a positive input end receiving the second output end of the second buffer, a negative input end being connected to the second output end of the third buffer, and an output end being used to provide the first reset signal.

[0016] Optionally, the logic and drive module includes: a second trigger, a set end receiving the first set signal, a reset end receiving the first reset signal, and an output end for providing a pulse width modulation signal; a drive circuit, used to provide the drive signal according to the pulse width modulation signal to control the conduction and shutdown of the high-side switch tube.

[0017] According to a second aspect of the present invention, a switching converter is provided, comprising a control circuit as described above; and a power stage circuit comprising: a high-side switch tube and an inductor, wherein the power stage circuit controls the transmission of electrical energy from the input voltage to the output voltage by turning on and off the high-side switch tube.

[0018] According to a third aspect of the present invention, a control method for a switching converter is provided, wherein the switching converter includes a high-side switch tube and an inductor, and the control circuit controls the transmission of electric energy from an input voltage to an output voltage by controlling the conduction and shutdown of the high-side switch tube. The control method comprises: when a first control signal is in an invalid state, generating an error signal whose voltage is negatively correlated with the difference between a first feedback voltage of the output voltage of the switching converter and a first reference voltage; when the first control signal is in an effective state, setting the voltage of the error signal to a first preset value; and according to the relationship between the first feedback voltage and the first reference voltage, the first feedback voltage, ... feedback voltage, the first reference voltage, the first feedback voltage, the first reference voltage, the first feedback voltage, the first reference voltage, the first feedback voltage, the first reference voltage, the first feedback voltage, the first reference voltage, the first feedback voltage, the first reference voltage, the first The first control signal is generated according to the magnitude relationship between the first feedback voltage and the second reference voltage and the error signal, and a second control signal is generated according to the magnitude relationship between the first feedback voltage and the second reference voltage and the first control signal, and a first set signal is generated according to the second control signal and the first clock signal, wherein the second reference voltage is greater than the first reference voltage and less than the third reference voltage; a ramp voltage is generated, and a first reset signal is generated using the ramp voltage and the error signal; the conduction and shutdown of the high-side switch tube are controlled according to the first set signal and the first reset signal, wherein the second control signal is related to the load degree of the switching converter.

[0019] The switching converter and its control circuit and control method provided by the present invention can determine the timing of entering the PFM mode based on the speed of the load change after the load changes from heavy to light and the inductor current switches from the CCM mode to the DCM mode. When the load changes slowly, the PFM mode can be entered by utilizing the change of the error signal. When the load changes suddenly, the PFM mode can be entered by utilizing the magnitude relationship between the first feedback voltage and the third reference voltage. This facilitates more accurate setting of the load level for entering the PFM mode and ensures that the switching converter has a faster response when the load changes quickly. In addition, when entering the PFM mode, the first control signal changes synchronously with the first clock signal, which facilitates uniform output voltage fluctuation.

[0020] In a preferred embodiment, the switching converter and its control circuit also set the operating voltage of the error signal according to the level state of the first control signal to make the output voltage have smaller ripple in PFM mode and have a faster response speed when exiting PFM mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0022] FIG1 shows a schematic structural diagram of a switching converter according to an embodiment of the present invention;

[0023] FIG2 shows a schematic structural diagram of a control circuit of a switching converter according to an embodiment of the present invention;

[0024] FIG3 shows a circuit diagram of an error signal generating module according to an embodiment of the present invention;

[0025] FIG4 shows a circuit diagram of a PFM control module according to an embodiment of the present invention;

[0026] FIG5 shows a circuit diagram of a reset signal generating module according to an embodiment of the present invention;

[0027] FIG6 shows a circuit diagram of a logic and driver module according to an embodiment of the present invention;

[0028] FIG7 shows a timing diagram of a switching converter according to an embodiment of the present invention;

[0029] FIG8 shows a flow chart of a method for controlling a switching converter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical components or modules are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0031] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0032] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will appreciate that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in their functionality.

[0033] In this application, the term "semiconductor structure" refers collectively to the entire semiconductor structure formed during the various steps of manufacturing a memory device, including all formed layers or regions. Numerous specific details of the present invention, such as device structure, materials, dimensions, processing techniques, and technologies, are described below to facilitate a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without adherence to these specific details.

[0034] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0035] FIG1 shows a circuit diagram of a switching converter according to an embodiment of the present invention. As shown in FIG1 , the switching converter includes a power stage circuit 100 and a control circuit 200 .

[0036] The power stage circuit 100 includes a high-side switch MH and a low-side switch ML connected sequentially between an input voltage VIN and ground; an inductor L connected between the common node of the high-side switch MH and the low-side switch ML and the output voltage VOUT; an equivalent series resistor Reser and a load capacitor Cload connected sequentially between the output voltage VOUT and ground; and a current source Iload connected between the output voltage VOUT and ground. The power stage circuit 100 is used to control the transmission of electrical energy from the input voltage VIN to the output voltage VOUT by alternatingly turning on the high-side switch MH and the low-side switch ML. Furthermore, the present invention does not specifically limit the structure of the power stage circuit 100; the low-side switch ML of the power stage circuit 100 may also be replaced by a rectifier diode.

[0037] Figure 2 shows a structural schematic diagram of a control circuit of a switching converter according to an embodiment of the present invention. As shown in Figure 2, the control circuit 200 includes an error signal generating module 210, a PFM control module (pulse frequency modulation control module) 220, a reset signal generating module 230, and a logic and driving module 240.

[0038] The error signal generation module 210 is configured to generate an error signal eao, whose voltage is negatively correlated with the difference between the first feedback voltage VOUT*0.125 of the output voltage VOUT of the switching converter and the reference voltage Vref1, based on the difference between the first feedback voltage VOUT*0.125 and the reference voltage Vref1 when the control signal PFM is in an inactive state, and to set the voltage of the error signal eao to a first preset value when the control signal PFM is in an active state. When the control signal PFM is in an inactive state, the error signal eao can reflect the equivalent duty cycle of the high-side switch MH. For example, the control signal PFM is active when the level is 1 and inactive when the level is 0. The first preset value is, for example, 1.1V.

[0039] The PFM control module 220 is configured to generate a control signal PFM based on a magnitude relationship between the first feedback voltage VOUT*0.125 and a reference voltage Vref1, a magnitude relationship between the first feedback voltage VOUT*0.125 and a reference voltage Vref4 (e.g., Vref1+30mV), and an error signal eao, and to generate a control signal PFM_OSC_D based on a magnitude relationship between the first feedback voltage VOUT*0.125 and a reference voltage Vref3 (e.g., Vref1+10mV) and the control signal PFM, and to generate a set signal V1 based on the control signal PFM_OSC_D and a clock signal clk1.

[0040] When the control signal PFM is in the inactive state, the PFM control module 220 is configured to activate the control signal PFM if the voltage of the error signal eao satisfies a preset condition, ie, control the switching converter to enter the PFM mode.

[0041] The preset condition includes the sum of the voltage of the error signal eao and the second feedback voltage VOUT*0.5 of the output voltage VOUT being less than a second preset value (e.g., 1.1V). When the sum of the voltage of the error signal eao and the second feedback voltage VOUT*0.5 of the output voltage VOUT is equal to the second preset value, if the switching converter is in DCM mode (discontinuous inductor current mode), the equivalent duty cycle of the high-side switch MH of the switching converter at this time and the equivalent duty cycle of the high-side switch MH when the switching converter is in CCM mode (continuous inductor current mode) reach a preset ratio. The preset ratio is less than 1. In this embodiment, since the second feedback voltage of the output voltage VOUT is VOUT*0.5, the preset ratio is 1:2. However, in actual applications, the preset ratio can be set to any value between 40% and 60%, and the preset ratio can be adjusted by adjusting the second feedback voltage of the output voltage VOUT.

[0042] When the control signal PFM is in the inactive state, the PFM control module 220 is further configured to activate the control signal PFM if the first feedback voltage VOUT*0.125 of the output voltage VOUT is greater than the reference voltage Vref4, ie, control the switching converter to enter the PFM mode.

[0043] When the control signal PFM is active, the PFM control module 220 is configured to deactivate the control signal PFM if the first feedback voltage VOUT*0.125 of the output voltage VOUT is less than the reference voltage Vref1 , ie, control the switching converter to exit the PFM mode.

[0044] The reset signal generating module 230 is used to generate a ramp voltage RAMP_BK, and generate a reset signal BK_c using the ramp voltage RAMP_BK and the error signal eao.

[0045] Furthermore, the reset signal generating module 230 can be regarded as generating the reset signal BK_c by comparing the equivalent ramp RAMP and the error signal eao, wherein the equivalent ramp RAMP is related to the input voltage VIN and the output voltage VOUT, and the initial value of the equivalent ramp RAMP is 1.1Vk*VOUT / fsw (k is the coefficient of VOUT after passing through the buffer 2213, and fsw is the switching frequency of the high-side switch tube MH).

[0046] The logic and driving module 240 is used to control the on and off of the high-side switch MH and the low-side switch ML according to the set signal V1 and the reset signal BK_c.

[0047] After entering the PFM mode, the PFM control module 220 controls the logic and driving module 240 according to the load level of the switching converter, thereby controlling the conduction of the high-side switch MH.

[0048] When the first feedback voltage VOUT*0.125 of the output voltage VOUT is lower than the reference voltage Vref3, meaning the switching converter is relatively overloaded, the control signal PFM_OSC_D is zero, the set signal V1 changes with the clock signal clk1, and the clock signal clk is immediately reset, turning on the high-side switch MH. When the first feedback voltage VOUT*0.125 of the output voltage VOUT is higher than the reference voltage Vref3, meaning the switching converter is relatively lightly loaded, the control signal PFM_OSC_D is equal to the control signal PFM (i.e., 1). The clock signal clk1 is then blocked, and the set signal V1 is zero. When the clock signal clk1 is blocked, the output voltage VOUT does not ripple. When the set signal V1 changes with the clock signal clk1, upon a falling edge of the clock signal clk1, the set signal V1 becomes 1, turning on the high-side switch MH. Upon a rising edge of the clock signal clk1, the set signal V1 becomes 0. The clock signal clk1 and the clock signal clk are in opposite phases.

[0049] Furthermore, when the control signal PFM is in an invalid state, the reset signal generation module 230 generates a ramp voltage RAMP_BK with a first slope according to the clock signal clk; when the first control signal PFM is in a valid state, the reset signal generation module 230 generates a ramp voltage RAMP_BK with a second slope according to the clock signal clk, and the first slope is smaller than the second slope.

[0050] FIG3 shows a circuit diagram of an error signal generating module according to an embodiment of the present invention. As shown in FIG3 , the error signal generating module 210 includes a transconductance amplifier gm1 , an amplifying module 211 , a compensation module 212 , an output module 213 , a resistor R5 , and a capacitor C4 .

[0051] The transconductance amplifier gm1 has a positive input terminal connected to the first feedback voltage VOUT*0.125 of the output voltage VOUT, and a negative input terminal connected to the reference voltage Vref1 , for differentially amplifying the reference voltage Vref1 and the first feedback voltage VOUT*0.125 of the output voltage VOUT.

[0052] The amplification module 211 includes a bias current source IB1, a resistor R1, and a transistor Q1, which are sequentially connected between the power supply voltage VDD and ground; a transistor Q2, and a bias current source IB2, which are sequentially connected between the power supply voltage VDD and ground. A first terminal and a control terminal of the transistor Q1 are interconnected, and the control terminal of the transistor Q2 is connected to the output terminal of the transconductance amplifier gm1. The amplification module 211 is used to amplify the output signal of the transconductance amplifier gm1.

[0053] The compensation module 212 includes a resistor R2, a capacitor C1, and a capacitor C2 connected in series between the second end of the transistor Q2 and the output end of the transconductance amplifier gm2, and a resistor R3, a resistor R4, and a capacitor C3 connected in series between the second end of the transistor Q2 and the output end of the transconductance amplifier gm2. The compensation module 212 is used to compensate for the output signal of the amplification module 211.

[0054] The resistor R5 and the capacitor C4 are connected in parallel between the output terminal of the transconductance amplifier gm2 and the ground.

[0055] Output module 213 includes a transconductance amplifier gm2, a switch S1, a switch S2, and a reference voltage source 2131. The positive input of transconductance amplifier gm2 receives a reference voltage Vref2, and the negative input is connected to the common node of capacitors C1 and C2 and the common node of resistors R3 and R4. Switch S1 is connected between the positive and negative inputs of transconductance amplifier gm2. Switch S2 and reference voltage source 2131 are connected, in sequence, between the output of transconductance amplifier gm2 and ground. The on / off states of switches S1 and S2 are controlled by a control signal PFM.

[0056] The output module 213 is used to set the operating voltage of the error signal eao according to the level state of the control signal PFM. Its operating principle is as follows: when PFM=1, both switches S1 and S2 are turned on, and the operating voltage of the error signal eao is set to a first preset value (for example, 1.1V) by the reference voltage source 2131, so that the output voltage VOUT has a smaller ripple in the DCM mode; when PFM=0, both switches S1 and S2 are turned off, and the operating voltage of the error signal eao is set to the static operating voltage in the CCM mode by the reference voltage Vref2.

[0057] Figure 4 shows a circuit diagram of a PFM control module according to an embodiment of the present invention. As shown in Figure 4, the PFM control module 220 includes a comparator 2211, a comparator 2212, a buffer 2213, a comparator 2214, an OR gate 2215, an AND gate 2216, an RS trigger 2217, a comparator 2221, an AND gate 2222 and a NOR gate 2223.

[0058] The comparator 2211 receives a reference voltage Vref1 at its positive input and a first feedback voltage VOUT*0.125 of the output voltage VOUT at its negative input. The comparator 2211 outputs a comparison signal VC1 based on a comparison result between the reference voltage Vref1 and the first feedback voltage VOUT*0.125 of the output voltage VOUT to determine the operating mode of the inductor current IL. When the comparison signal VC1 = 1, it indicates that the load is heavy and the inductor current IL operates in CCM mode. When the comparison signal VC1 = 0, it indicates that the load is light and the inductor current IL operates in DCM mode.

[0059] The comparator 2212 receives the first feedback voltage VOUT*0.125 of the output voltage VOUT at its positive input terminal and the reference voltage Vref4 at its negative input terminal for outputting a comparison signal VC2 according to a comparison result between the reference voltage Vref4 and the first feedback voltage VOUT*0.125 of the output voltage VOUT.

[0060] The positive input terminal of the buffer 2213 receives the second feedback voltage VOUT*0.5 of the output voltage VOUT, the negative input terminal is grounded, the first output terminal receives the error signal eao, and the second output terminal is used to superimpose the second feedback voltage VOUT*0.5 of the output voltage VOUT with the error signal eao to generate a duty cycle signal duty.

[0061] The comparator 2214 receives the second preset value V11 (eg, 1.1V) at its positive input and the duty cycle signal duty at its negative input for outputting a comparison signal VC3 based on a comparison result between the first reference voltage V11 and the duty cycle signal duty.

[0062] The OR gate 2215 receives the comparison signal VC2 at a first input terminal and receives the comparison signal VC3 at a second input terminal, and is configured to output a first logic signal according to the comparison signal VC2 and the comparison signal VC3.

[0063] A first input terminal of the AND gate 2216 is connected to the first logic signal, and a second input terminal of the AND gate 2216 is connected to the clock signal clk1 , and the AND gate 2216 is configured to output a second set signal according to the first logic signal and the clock signal clk1 .

[0064] The reset terminal R of RS flip-flop 2217 is connected to the comparison signal VC1, the set terminal S is connected to the second set signal, and the output terminal Q provides the control signal PFM. When R = 1, PFM = 0. When R = 0, if S = 1, PFM = 1. When S switches from 1 to 0, the PFM level remains unchanged.

[0065] The comparator 2221 receives the first feedback voltage VOUT*0.125 of the output voltage VOUT at its positive input terminal and the reference voltage Vref3 at its negative input terminal for outputting a comparison signal VC4 according to a comparison result between the reference voltage Vref3 and the first feedback voltage VOUT*0.125 of the output voltage VOUT.

[0066] The AND gate 2222 receives the comparison signal VC4 at a first input terminal and the control signal PFM at a second input terminal, and is configured to output the control signal PFM_OSC_D according to the comparison signal VC4 and the control signal PFM.

[0067] A first input terminal of the NOR gate 2223 receives the clock signal clk1 , a second input terminal receives the control signal PFM_OSC_D, and an output terminal of the NOR gate 243 provides a set signal V1 .

[0068] Among them, comparator 2212 is used to determine the timing of the switching converter entering the PFM mode when the switching converter quickly jumps from heavy load to light load, and buffer 2213 and comparator 2214 are used to determine the timing of the switching converter entering the PFM mode when the switching converter slowly changes from heavy load to light load.

[0069] Furthermore, the switching converter enters the PFM mode in synchronization with the clock signal clk1 , which is beneficial for uniform ripple of the output voltage VOUT.

[0070] FIG5 shows a circuit diagram of a reset signal generating module according to an embodiment of the present invention. As shown in FIG5 , the reset signal generating module 230 includes a switch S3, a switch S4, an inverter 231, a transconductance amplifier gm3, a capacitor C5, a switch S5, a buffer 232, a reference voltage source 233, a buffer 234, and a comparator 235. The reference voltage source 232 is used to provide a reference voltage, and the reference voltage is, for example, 1.1V.

[0071] A first terminal of switch S3 is connected to a feedback voltage VIN*0.8 of the input voltage VIN, a second terminal is connected to node A, and a control terminal receives a control signal PFM. A first terminal of switch S4 is connected to a feedback voltage VIN*0.5 of the input voltage VIN, a second terminal is connected to node A, and a control terminal receives the control signal PFM after passing through inverter 231. Switches S3, S4, and inverter 231 are configured to switch the feedback voltage of input signal VIN input to transconductance amplifier gm3 to either feedback voltage VIN*0.5 or feedback voltage VIN*0.8 according to control signal PFM.

[0072] The positive input of transconductance amplifier gm3 is connected to node A, and its negative input is grounded. It is used to differentially amplify the voltage VA at node A (i.e., the feedback voltage of input signal VIN) and the ground voltage to produce a differential signal. Capacitor C5 has a first terminal connected to the output of transconductance amplifier gm3 and a second terminal connected to ground. Switch S5 has a first terminal connected to the output of transconductance amplifier gm3 and a second terminal connected to ground. Switch S5 is turned on or off by clock signal clk. Buffer 232 has a positive input connected to the first terminal of switch S5 and a negative input connected to ground. Its first output terminal is grounded via reference voltage source 233, and its second output terminal is used to output the voltage at the first terminal of switch S5 superimposed with the reference voltage. Buffer 234 has a positive input terminal that receives the output signal VOUT, a negative input terminal that is grounded, a first output terminal that receives the error signal eao, and a second output terminal that superimposes the output voltage with the error signal eao. The positive input of the comparator 235 is connected to the second output of the buffer 232 , and the negative input of the comparator 235 is connected to the second output of the buffer 234 . The comparator 235 is used to output a reset signal BK_c according to the comparison result between the output signal of the buffer 232 and the output signal of the buffer 234 .

[0073] The ramp voltage RAMP_BK is related to the output voltage provided by the buffer 232. When the clock signal clk switches to a logic low level, the switch S5 is turned off, the transconductance amplifier gm3 charges the capacitor C5 according to the voltage VA at the node A, and the ramp voltage RAMP_BK rises. When the clock signal clk switches to a logic high level, the switch S5 is turned on, the transconductance amplifier gm3 discharges the capacitor C5 according to the voltage VA at the node A, and the ramp voltage RAMP_BK quickly drops to a preset value. The preset value of the ramp voltage RAMP_BK is, for example, zero.

[0074] FIG6 shows a circuit diagram of a logic and driving module according to an embodiment of the present invention. As shown in FIG6 , the logic and driving module 240 includes a D flip-flop 241 and a driving circuit 242 .

[0075] The set terminal Clk of the D flip-flop 241 receives the set signal V1 , the input terminal D is connected to the power supply voltage VDD, the reset terminal reset receives the reset signal BK_c, and the output terminal Q provides a pulse width modulation signal PWM.

[0076] The driving circuit 242 is configured to provide a driving signal hdr and a driving signal ldr according to a pulse width modulation signal PWM.

[0077] The D flip-flop 241 synchronizes the data of the input terminal D to the output terminal Q when the set terminal Clk has a rising edge. When the reset signal BK_c is equal to 1, the output terminal Q is set to 0. The clock signal clk is synchronized with the timing change of the set terminal Clk.

[0078] FIG7 shows a timing diagram of a switching converter according to an embodiment of the present invention. The working principle of the control circuit of the switching converter provided by the present invention will be described below with reference to FIG7 .

[0079] When the load slowly changes from heavy load to light load, the first feedback voltage VOUT*0.125 of the output voltage VOUT is higher than the reference voltage Vref1, and the inductor current IL enters the DCM mode from the CCM mode (that is, VC1 changes from 1 to 0). The equivalent duty cycle of the drive signal hdr decreases, making the error signal eao smaller. When the equivalent duty cycle of the drive signal hdr in the DCM mode is equal to half of the equivalent duty cycle of the drive signal hdr in the CCM mode, the error signal eao1=1.1Vk*VOUT / 2fsw. Then VC3=1, and the RS flip-flop 227 outputs the control signal PFM with a logic level of 1, causing the switching converter to enter the PFM mode. At this time, the voltage input to the transconductance amplifier gm3 is switched from the feedback voltage VIN*0.5 of the input voltage VIN to the feedback voltage VIN*0.8 of the input voltage VIN. At the same time, the switches S1 and S2 are turned on, setting the operating point of the error signal eao to the first preset value (i.e., 1.1V) to shorten the loop recovery time when exiting the PFM mode, thereby reducing the ripple amplitude of the output voltage VOUT. When the load rapidly changes from heavy to light, the first feedback voltage VOUT*0.125 of the output voltage VOUT is higher than the reference voltage Vref1, and the inductor current IL switches from CCM mode to DCM mode (i.e., VC1 changes from 1 to 0). At this time, although the error signal eao changes slowly, the first feedback voltage VOUT*0.125 of the output voltage VOUT is higher than the reference voltage Vref4 (i.e., VC2 = 1), and the RS flip-flop 227 similarly outputs a control signal PFM with a logic level of 1, causing the switching converter to enter PFM mode. Therefore, the control circuit of the switching converter provided by the present invention can accurately set the load level for entering PFM when the load slowly changes from heavy to light, and achieve a faster transient response when the load rapidly changes from heavy to light.

[0080] Furthermore, when the load changes from light to heavy, the first feedback voltage VOUT*0.125 of the output voltage VOUT will fall below the reference voltage Vref1. At this point, the PFM control circuit outputs a control signal PFM with a logic level of 0, causing the switching converter to exit PFM mode. At this point, switches S1 and S2 are turned off, and the error signal eao operates at approximately 1.1V through loop control. The ratio of the ramp voltage RAMP_BK also returns to normal, allowing energy to be directly transferred to the output terminal. This facilitates the switching converter's rapid response and further reduces the voltage ripple of the output voltage VOUT.

[0081] Correspondingly, the present invention also provides a control method for a switching converter.

[0082] FIG8 shows a flow chart of a control method for a switching converter according to an embodiment of the present invention. The control method is applied to the switching converter described above, and the control method includes:

[0083] Step S1: When the first control signal PFM is in an inactive state, an error signal eao is generated based on a difference between a first feedback voltage VOUT*0.125 of the output voltage VOUT of the switching converter and a reference voltage Vref1, and when the control signal PFM is in an active state, the voltage of the error signal eao is set to a first preset value.

[0084] Step S2: Generate a control signal PFM based on the magnitude relationship between the first feedback voltage VOUT*0.125 and the reference voltage Vref1, the magnitude relationship between the first feedback voltage VOUT*0.125 and the reference voltage Vref4 (for example, Vref1+30mV), and the error signal eao; generate a control signal PFM_OSC_D based on the magnitude relationship between the first feedback voltage VOUT*0.125 and the reference voltage Vref3 (for example, Vref1+10mV) and the control signal PFM; and generate a set signal V1 based on the control signal PFM_OSC_D and a clock signal clk1.

[0085] Step S3: generating a ramp voltage RAMP_BK, and generating a reset signal BK_c using the ramp voltage RAMP_BK and the error signal eao;

[0086] Step S4: controlling the on and off of the high-side switch MH according to the set signal V1 and the reset signal BK_c.

[0087] The embodiments of the present invention are as described above, but these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and modify and use it based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A control circuit of a switching converter, the switching converter comprising a high-side switch tube and an inductor, the control circuit controlling the power transmission from an input voltage to an output voltage by controlling the on and off of the high-side switch tube, the control circuit comprising: an error signal generating module, configured to generate an error signal whose voltage magnitude is negatively correlated with the difference between the first feedback voltage and the first reference voltage of the output voltage of the switching converter according to the difference between the first feedback voltage and the first reference voltage when the first control signal is in an invalid state, and to set the voltage magnitude of the error signal to a first preset value when the first control signal is in an effective state; A PFM control module, configured to generate the first control signal according to a magnitude relationship between the first feedback voltage and the first reference voltage, a magnitude relationship between the first feedback voltage and a third reference voltage, and the error signal, generate a second control signal according to a magnitude relationship between the first feedback voltage and the second reference voltage and the first control signal, and generate a first set signal according to the second control signal and a first clock signal, wherein the second reference voltage is greater than the first reference voltage and less than the third reference voltage; A reset signal generating module, used for generating a ramp voltage, and generating a first reset signal by using the ramp voltage and the error signal; a logic and driving module, configured to control the on and off of the high-side switch tube according to the first set signal and the first reset signal, The second control signal is related to the load level of the switching converter.

2. The control circuit according to claim 1, wherein: The PFM control module is configured to: When the first control signal is in an invalid state, if the voltage of the error signal meets a preset condition, the first control signal is controlled to become a valid state; When the first control signal is in an invalid state, if the first feedback voltage is greater than the third reference voltage, the first control signal is controlled to become a valid state; When the first control signal is in a valid state, if the first feedback voltage is less than the first reference voltage, the first control signal is controlled to become an invalid state.

3. The control circuit according to claim 2, wherein: The preset condition includes that the sum of the voltage of the error signal and the second feedback voltage of the output voltage is less than a second preset value; Among them, when the sum of the voltage magnitude of the error signal and the second feedback voltage of the output voltage is the second preset value, if the switching converter is in DCM mode, then at this time, the equivalent duty cycle of the high-side switching tube of the switching converter and the equivalent duty cycle of the high-side switching tube when the switching converter is in CCM mode reach a preset ratio, and the preset ratio is less than 1.

4. The control circuit according to any one of claims 1 to 3, wherein: The PFM control module includes: A first comparator, having a positive input terminal receiving the first reference voltage, a negative input terminal receiving the first feedback voltage, and an output terminal for providing a first comparison signal; a first buffer, wherein the positive input terminal receives the second feedback voltage of the output voltage, the negative input terminal is grounded, the first output terminal receives the error signal, and the second output terminal is used to provide a duty cycle signal, wherein the duty cycle signal is obtained by superimposing the second feedback voltage of the output voltage and the error signal, and the second feedback voltage of the output voltage is greater than the first feedback voltage of the output voltage; A second comparator, wherein the positive input terminal receives the second preset value, the negative input terminal receives the duty cycle signal, and the output terminal is used to provide a second comparison signal; a third comparator, wherein the positive input terminal receives the first feedback voltage, the negative input terminal receives the third reference voltage, and the output terminal is used to provide a third comparison signal; An OR gate, a first input terminal receiving the third comparison signal, a second input terminal receiving the second comparison signal, and an output terminal for providing a first logic signal; A first AND gate, having a first input terminal receiving the first logic signal, a second input terminal receiving the clock signal, and an output terminal for providing a second set signal; A first trigger, a reset terminal receiving the first comparison signal, a set terminal receiving the second set signal, and an output terminal for providing the first control signal; A fourth comparator, a positive input terminal receiving the first feedback voltage, a negative input terminal receiving the second reference voltage, and an output terminal for providing the fourth comparison signal; a second AND gate, having a first input terminal receiving the fourth comparison signal, a second input terminal receiving the first control signal, and an output terminal for providing the second control signal; A NOR gate has a first input terminal receiving the clock signal, a second input terminal receiving the second control signal, and an output terminal for providing the first set signal.

5. The control circuit according to claim 1, wherein: The error signal generating module comprises: a first transconductance amplifier, having a positive input terminal receiving a first feedback voltage of the output voltage and a negative input terminal receiving the first reference voltage, the first transconductance amplifier being used for differentially amplifying the first feedback voltage of the output voltage and the first reference voltage; an amplification module, used for amplifying the output of the first transconductance amplifier; A compensation module, used for compensating the output of the amplification module; Output modules, including: A second transconductance amplifier, wherein the positive input terminal receives a fourth reference voltage and the negative input terminal is connected to the compensation module; A first switch connected between the positive and negative input terminals of the second transconductance amplifier; and a first reference voltage source and a second switch connected in sequence between the output terminal of the second transconductance amplifier and ground, wherein the first reference voltage source is used to provide the first preset value, The first switch and the second switch are controlled by the first control signal.

6. The control circuit according to claim 1, wherein: The reset signal generating module is configured to: generate a ramp voltage with a first slope according to a second clock signal when the first control signal is in an invalid state; and generate a ramp voltage with a second slope according to the second clock signal when the first control signal is in a valid state, wherein the first slope is smaller than the second slope.

7. The control circuit according to claim 1 or 6, wherein: The reset signal generating module comprises: a third switch, a first end receiving a first feedback voltage of the input voltage, a second end connected to the first node, and a control end receiving the first control signal; A fourth switch, a first end of which receives a second feedback voltage of the input voltage, and a second end of which is connected to the first node, wherein the second feedback voltage of the input voltage is greater than the first feedback voltage of the input voltage; an inverter connected between the first control signal and a control terminal of the fourth switch; a third transconductance amplifier, having a positive input terminal connected to the first node and a negative input terminal connected to the ground, and configured to differentially amplify a voltage at the first node and a ground voltage to obtain a differential signal; A first capacitor, a first end of which is connected to the output end of the third transconductance amplifier, and a second end of which is grounded; A fifth switch, a first end of which is connected to the first end of the first capacitor, a second end of which is grounded, and a control end of which is connected to the second clock signal; a second buffer, wherein the positive input terminal is connected to the first terminal of the fifth switch, the negative input terminal is grounded, the first output terminal is grounded through the second reference voltage source, and the second output terminal is used to output the voltage of the first terminal of the fifth switch superimposed with the voltage provided by the second reference voltage source; A third buffer, having a positive input terminal connected to the output voltage, a negative input terminal connected to ground, a first output terminal receiving the error signal, and a second output terminal for outputting the output voltage and the error signal after being superimposed; A fifth comparator has a positive input terminal receiving the second output terminal of the second buffer, a negative input terminal connected to the second output terminal of the third buffer, and an output terminal for providing the first reset signal.

8. The control circuit according to claim 1, wherein: The logic and driver module includes: a second trigger, a set end receiving the first set signal, a reset end receiving the first reset signal, and an output end for providing a pulse width modulation signal; The driving circuit is used to provide a driving signal according to the pulse width modulation signal to control the on and off of the high-side switch tube.

9. A switching converter, comprising: The control circuit according to any one of claims 1 to 8; as well as Power stage circuit, including: High-side switch and inductor, The power stage circuit controls the transmission of electric energy from the input voltage to the output voltage by turning on and off the high-side switch tube.

10. A control method for a switching converter, wherein the switching converter comprises a high-side switch tube and an inductor, wherein the control circuit controls the power transmission from an input voltage to an output voltage by controlling the on and off of the high-side switch tube, and the control method comprises: When the first control signal is in an invalid state, an error signal having a voltage magnitude negatively correlated with the difference is generated according to the difference between the first feedback voltage of the output voltage of the switching converter and the first reference voltage; When the first control signal is in an effective state, setting the voltage magnitude of the error signal to a first preset value; generating the first control signal according to the magnitude relationship between the first feedback voltage and the first reference voltage, the magnitude relationship between the first feedback voltage and the third reference voltage, and the error signal, generating a second control signal according to the magnitude relationship between the first feedback voltage and the second reference voltage and the first control signal, and generating a first set signal according to the second control signal and the first clock signal, wherein the second reference voltage is greater than the first reference voltage and less than the third reference voltage; generating a ramp voltage, and generating a first reset signal using the ramp voltage and the error signal; controlling the on and off of the high-side switch tube according to the first set signal and the first reset signal, The second control signal is related to the load level of the switching converter.

Images