Display substrate and display panel

Abstract

Provided are a display substrate and a display panel. The display substrate comprises a base (410), a plurality of grid lines (110) extending in a first direction (X) and a plurality of data lines (210) extending in a second direction (Y), wherein the plurality of grid lines (110) and the plurality of data lines (210) are arranged on one side of the base (410) and arranged on different layers, and the orthographic projection of the plurality of grid lines (110) on the base intersect with the orthographic projection of the plurality of data lines (210) on the base to define a plurality of pixel units; each pixel unit comprises at least one transistor, the transistor comprising an active layer (300), and the active layer (300) comprising a channel part (310) and a pair of electrical connecting parts (320) connected to two sides of the channel part (310); and the orthographic projection of the channel part (310) on the base (410) overlaps with the orthographic projection of the data lines (210) on the base (410). The orthographic projection of the channel part (310) of the active layer (300) overlaps with the orthographic projection of the data lines (210), and thus the channel part (310) can be shielded together by a black matrix corresponding to the grid lines (110) and a black matrix corresponding to the data lines (210), thereby increasing the aperture ratio.

Description

Display substrate, display panel Technical Field

[0001] The present invention relates to the field of display devices, and in particular, to a display substrate and a display panel including the display substrate. Background Art

[0002] As a prime example of next-generation information technology convergence and innovation, virtual reality (VR) is experiencing increasing maturity in key technologies, rapid market development, and a rapidly growing market. In recent years, the global commercialization of VR has become increasingly diverse. Beyond familiar applications like gaming and entertainment, VR is increasingly finding its way into new sectors like healthcare, education, and manufacturing, with increasing industry penetration.

[0003] Currently, display technology is rapidly developing, and traditional liquid crystal display (LCD) technology has matured. With the rise of VR products, the application of LCD in VR has brought new technological developments and vitality to LCD. LCDs currently typically have a 1T or 2T pixel structure. Their simple pixel circuits allow for ultra-high pixel density (PPI), offering advantages over organic electroluminescence display (OLED) technology. Furthermore, the maturity of LCD technology offers a cost advantage.

[0004] Currently, VR display technology in the LCD display field has achieved mass production at the 1200PPI level and has reserved 1500PPI technology. With the increase in VR market demand, the iteration speed of LCD display technology applied to VR has accelerated. Currently, there is an urgent need for the implementation of 2000+PPI technology, which includes corresponding Real RGB pixel design, optical innovation and more sophisticated process technology.

[0005] At present, the aperture ratio is still the core indicator of LCD display, which determines the power consumption, brightness and contrast of LCD display. In VR products, the display screen size is relatively small (usually around 2.5 inches), but still requires at least 2K or even 4K resolution. As a result, the size of a single pixel in the LCD panel of the VR device is compressed to only a few μm, which greatly reduces the aperture ratio of the display panel and the transmittance drops to 1% or even lower. The light output ratio of the entire pixel is small and the display efficiency is low, which in turn leads to increased display power consumption and reduced display effect.

[0006] Therefore, how to ensure the aperture ratio of the display panel has become a technical problem that needs to be solved urgently in this field.

[0007] Summary of the Invention

[0008] The present invention aims to provide a display substrate and a display panel, wherein the display substrate can avoid affecting the aperture ratio while ensuring the characteristics of thin film transistors, reduce the display power consumption of the display substrate, and improve the display effect of the display substrate.

[0009] To achieve the above-mentioned objectives, as a first aspect of the present invention, a display substrate is provided, comprising a substrate, and a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction arranged on one side of the substrate, the plurality of gate lines and the plurality of data lines being arranged in different layers, and the orthographic projections of the plurality of gate lines on the substrate intersect with the orthographic projections of the plurality of data lines on the substrate and define a plurality of pixel units; each of the pixel units comprises at least one transistor, the transistor comprises an active layer, the active layer comprises a channel portion and a pair of electrical connection portions connected on both sides of the channel portion; the orthographic projection of the channel portion on the substrate overlaps with the orthographic projection of the data line on the substrate.

[0010] Optionally, the display substrate further includes a plurality of transparent electrode strips, the plurality of transparent electrode strips extending along the first direction, and the positions of the transparent electrode strips corresponding one-to-one to the positions of the plurality of gate lines; the orthographic projections of the transparent electrode strips on the substrate cover the orthographic projections of the gate lines on the substrate.

[0011] Optionally, the pixel unit includes a pixel electrode, one of the electrical connection parts is electrically connected to the data line, and the other electrical connection part is electrically connected to the pixel electrode; the channel part can change its own conductive state in response to the potential change of the gate line and the transparent electrode strip to selectively connect the data line and the pixel electrode.

[0012] Optionally, in a plane parallel to the substrate and perpendicular to the first direction, the width of the transparent electrode strip is d1, and the width of the gate line is d2, wherein 1≤|d1 / d2|≤4.

[0013] Optionally, the transparent electrode strips are electrically connected to the gate lines, and the transparent electrode strips and the gate lines are located on one side of the active layer relative to the substrate, or on both sides of the active layer relative to the substrate.

[0014] Optionally, the display substrate further includes a gate insulating layer, the gate insulating layer is located on a side of the active layer away from the substrate, and the transparent electrode strips and the gate lines are sequentially located on a side of the gate insulating layer away from the substrate.

[0015] Optionally, the display substrate further includes a gate insulating layer and a first insulating layer, the gate insulating layer is located between the gate line and the active layer, the first insulating layer is located on a side of the gate insulating layer away from the substrate, the transparent electrode strip is located on a side of the first insulating layer away from the substrate, and the gate line and the transparent electrode strip are electrically connected through a connecting via that passes through the first insulating layer and the gate insulating layer.

[0016] Optionally, the orthographic projection of the connecting via on the substrate is located between the orthographic projections of two adjacent channel portions on the substrate.

[0017] Optionally, the width of the orthographic projection of the connecting via on the substrate is 1.5 μm to 2.5 μm.

[0018] Optionally, the distance between the connecting via and the adjacent channel portion is greater than or equal to 1.2 μm.

[0019] Optionally, in the multiple active layers on both sides of each connecting via, a length of the channel portion corresponding to an end of the channel portion away from the connecting via extending along the second direction gradually decreases along the side away from the connecting via.

[0020] Optionally, the electrical connection portion is connected to the pixel electrode through a first via hole, and the electrical connection portion is electrically connected to the data line through a second via hole, and the orthographic projection of the first via hole on the substrate falls within the orthographic projection of the corresponding pixel unit on the substrate.

[0021] Optionally, the gap width between the first via hole and the transparent electrode strip is 0.4 μm-0.75 μm.

[0022] Optionally, the gap width between the second via hole and the transparent electrode strip is 0.4 μm-0.75 μm.

[0023] Optionally, an extension direction of the channel portion of the active layer forms a first preset angle with the second direction, and the angle range of the first preset angle is 30-90°.

[0024] Optionally, a central axis of the channel portion of the active layer overlaps with a central axis of the electrical connection portion.

[0025] Optionally, the central axis of the channel portion of the active layer and the central axis of the electrical connection portion do not overlap, and an angle between the central axis of the channel portion and the central axis of the electrical connection portion is in the range of 30-90°.

[0026] Optionally, the extension direction of the channel portion forms a second preset angle with the first direction, and the two adjacent active layers connected to the same data line are respectively located on opposite sides of the data line, so that the multiple pixel units connected to each data line are staggered on both sides of the corresponding data line.

[0027] Optionally, a ratio of a size of the pixel unit along the first direction to a size of the pixel unit along the second direction is 3 / 4 to 4 / 3.

[0028] Optionally, the material of the channel portion includes any one of metal oxide, polysilicon, and low-temperature polysilicon.

[0029] As a second aspect of the present invention, a display panel is provided. The display panel includes the display substrate provided by the present invention.

[0030] In the display substrate and display panel provided by the present invention, the display substrate includes intersecting gate lines and data lines. The data lines are connected to the corresponding pixel electrodes through the active layer of each pixel unit. A channel portion is provided at the center of the active layer where it intersects with the gate lines. The channel portion can change its electrical properties in response to changes in the signal in the gate lines, thereby selectively connecting the pixel electrodes to the data lines, thereby controlling the light emission of each pixel unit. Furthermore, the orthographic projection of the channel portion on the substrate overlaps with the orthographic projection of the data lines on the substrate, so that the channel portion can be jointly shielded by the black matrix corresponding to the gate lines and the black matrix corresponding to the data lines, thereby increasing the aperture ratio of the pixel units, reducing the display power consumption of the display substrate, and improving the display effect of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0032] FIG1 is a schematic cross-sectional view of a display substrate according to an embodiment of the present invention;

[0033] FIG2 is a schematic top plan view of a display substrate provided by an embodiment of the present invention;

[0034] FIG3 is a schematic top plan view of a display substrate provided by an embodiment of the present invention;

[0035] 4 is a schematic diagram showing the positional relationship between data lines and pixel units in a display substrate provided by an embodiment of the present invention;

[0036] FIG5 is a schematic top plan view of a display substrate provided by an embodiment of the present invention;

[0037] 6 is a schematic diagram showing the positional relationship between data lines and pixel units in a display substrate provided by another embodiment of the present invention;

[0038] 7 is a schematic top plan view of a display substrate provided by another embodiment of the present invention;

[0039] FIG8 is a schematic diagram of an arrangement of pixel units in a display substrate provided in an embodiment of the present invention;

[0040] 9 is a schematic top plan view of a display substrate provided in an embodiment of the present invention;

[0041] 10 is a schematic diagram showing how the pixel structure in a display substrate varies with the offset distance provided by an embodiment of the present invention;

[0042] 11 is a schematic cross-sectional view of a display substrate according to an embodiment of the present invention;

[0043] FIG12 is a schematic top plan view of a display substrate provided in an embodiment of the present invention;

[0044] FIG13 is a schematic cross-sectional view taken along line BB of the structure in FIG12 ;

[0045] FIG14 is a schematic top plan view of a display substrate provided in an embodiment of the present invention;

[0046] 15 to 18 are schematic diagrams showing changes in pixel unit arrangement corresponding to different offset distances in a display substrate provided by an embodiment of the present invention;

[0047] FIG19 is a schematic diagram showing a comparison of the values ​​of the dimensions marked in FIG15 to FIG18;

[0048] FIG20 is a schematic diagram of characteristic dimensions of a pixel unit in a display substrate provided by an embodiment of the present invention;

[0049] FIG21 is a schematic diagram of characteristic dimensions of a pixel unit in a display substrate provided by another embodiment of the present invention;

[0050] FIG. 22 is a schematic diagram illustrating characteristic dimensions of a pixel unit in a display substrate according to another embodiment of the present invention.

[0051] Explanation of reference numerals: 110: gate line 210: data line 220: source electrode 120: transparent electrode strip 130: connection via 300: active layer 310: channel portion 320: electrical connection portion 410: substrate 420: gate insulating layer 430: first insulating layer 440: second insulating layer 450: third insulating layer 510: first interlayer dielectric layer 520: second interlayer dielectric layer 600: pixel electrode DETAILED DESCRIPTION

[0052] The following describes specific embodiments of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are intended only to illustrate and explain the present invention and are not intended to limit the present invention. The numerical ranges defined by "about" in the present invention refer to a range of ±20% of a given specific value.

[0053] In liquid crystal display panels, the thin film transistor (TFT) structure is an important factor affecting the aperture ratio. Due to its own characteristics, the oxide thin film transistor (Oxide TFT) used in liquid crystal display panels must ensure that its channel length L is long enough, at least 3.5μm is required to ensure the thin film transistor characteristics. In pixels above 2000PPI, the channel length L is determined by the width of the gate line (Gate). When the channel length L is large, the gate line width must also be kept large. However, in display panels above 2000PPI, the width of the black matrix (BM) corresponding to the gate line is only 2.4μm, and considering the process deviation, the gate line width must be at least less than 0.9μm under the requirement that the aperture ratio will not be affected after the deviation. Referring to the above analysis, if the width of the channel corresponding to the gate line width is as low as 0.9μm, the channel length L will obviously not meet the requirements, and the thin film transistor characteristics cannot be guaranteed.

[0054] To solve the above technical problems, as a first aspect of the present invention, a display substrate is provided, as shown in Figures 1 to 3 and Figures 13 to 14, wherein the display substrate includes a substrate, and a plurality of gate lines 110 (Gate) extending along a first direction (i.e., the x direction shown in the figure) and a plurality of data lines 210 (Data) extending along a second direction (i.e., the y direction shown in the figure) arranged on one side of the substrate 410, wherein the plurality of gate lines 110 and the plurality of data lines 210 are arranged in different layers, and the orthographic projections of the plurality of gate lines 110 on the substrate 410 intersect with the orthographic projections of the plurality of data lines 210 on the substrate 410 and define a plurality of pixel units; each of the pixel units includes at least one transistor, and the transistor includes an active layer 300, and the active layer 300 includes a channel portion 310 and a pair of electrical connection portions 320 connected to both sides of the channel portion; the orthographic projection of the channel portion 310 on the substrate 410 overlaps with the orthographic projection of the data line 210 on the substrate 410.

[0055] Optionally, the display substrate also includes a liquid crystal layer, and the pixel electrode is used to drive the liquid crystal molecules in the liquid crystal layer to flip through an electric field to change the transmittance of the pixel unit corresponding to the pixel electrode, thereby adjusting the grayscale corresponding to each pixel unit to achieve image display function.

[0056] In the present invention, the display substrate includes intersecting gate lines 110 and data lines 210. The data lines 210 are connected to the corresponding pixel electrodes through the active layer 300 of each pixel unit. The center of the active layer 300 intersecting with the gate line 110 has a channel portion 310. The channel portion 310 can change its electrical properties as the signal in the gate line 110 changes, thereby selectively connecting the pixel electrode and the data line 210, thereby controlling the light emission of each pixel unit. In addition, the orthographic projection of the channel portion 310 on the substrate 410 also overlaps with the orthographic projection of the data line 210 on the substrate 410. Therefore, the channel portion 310 can be shielded by the black matrix corresponding to the gate line 110 and the black matrix corresponding to the data line 210. This improves the aperture ratio of the pixel unit, reduces the display power consumption of the display substrate, and improves the display effect of the display substrate.

[0057] In order to further improve the display effect of the display substrate, as a preferred embodiment of the present invention, as shown in Figures 1 to 3 and Figures 13 to 14, the display substrate also includes a plurality of transparent electrode strips 120, the plurality of transparent electrode strips 120 extend along the first direction, and the positions of the transparent electrode strips 120 correspond one-to-one to the positions of the plurality of gate lines 110; the orthographic projection of the transparent electrode strips 120 on the substrate 410 covers the orthographic projection of the gate lines 210 on the substrate.

[0058] As an optional embodiment of the present invention, the pixel unit further includes a pixel electrode, one of the electrical connection portions 320 is electrically connected to the data line 210, and the other of the electrical connection portions 320 is electrically connected to the pixel electrode; the channel portion 310 can change its own conductive state in response to changes in the potential of the gate line 110 and the transparent electrode strip 120 to selectively connect the data line 210 and the pixel electrode.

[0059] As an optional embodiment of the present invention, as shown in FIG2 , in a plane parallel to the substrate 410 and perpendicular to the first direction, the width of the transparent electrode strip 120 is d1, and the width of the gate line 110 is d2, wherein 1≤|d1 / d2|≤4.

[0060] As an optional embodiment of the present invention, the width d1 of the transparent electrode strip 120 may be 3 μm, and the width d2 of the gate line 110 may be 1 μm.

[0061] As an optional embodiment of the present invention, as shown in FIG. 13 , the width W of the channel portion 310 is approximately 2.8 μm.

[0062] As a preferred embodiment of the present invention, the transparent electrode strips 120 are electrically connected to the gate lines 110, and the transparent electrode strips 120 and the gate lines 110 are located on one side of the active layer 300 relative to the substrate 410 (i.e., the situation shown in Figure 1), or on both sides of the active layer 300 relative to the substrate 410 (i.e., the situation shown in Figure 11).

[0063] In the embodiment of the present invention, the transparent electrode strips 120 correspond to and are electrically connected to the gate lines 110. Since the transparent electrode strips 120 are electrically connected to the gate lines 110, they have the same potential as the gate lines 110. Therefore, the transparent electrode strips 120 can also provide gate signals for controlling the switching of the thin film transistors to the channel portion 310. The transparent transparent electrode strips 120 are used to enlarge the size of the gate, thereby increasing the length L of the channel without increasing the area blocked by the gate lines. This ensures the characteristics of the thin film transistors while avoiding affecting the aperture ratio, thereby reducing the display power consumption of the display substrate and improving the display effect of the display substrate.

[0064] To further increase the aperture ratio, as a preferred embodiment of the present invention, the ratio of the size of the pixel unit along the first direction (i.e., the width of the pixel unit) to the size of the pixel unit along the second direction (i.e., the length of the pixel unit) is 3 / 4 to 4 / 3.

[0065] In existing display substrates with specifications above 2000 PPI, the characteristic size (pitch) of the pixel unit is typically 4μm*12μm. However, in the embodiments of the present invention, the ratio of the width to the length (i.e., the aspect ratio) of the pixel unit is 3 / 4 to 4 / 3, thereby further increasing the aperture ratio while maintaining the pixel PPI unchanged. For example, as an optional embodiment of the present invention, as shown in Figure 20, when the pixel unit has an aspect ratio of 3 / 4, the characteristic size of the pixel unit is 6μm*8μm, that is, the width n1 of the pixel unit is 6μm and the length l1 of the pixel unit is 8μm. The PPI of the entire display substrate remains unchanged at approximately 2000. Under the condition that the horizontal and vertical black matrix (BM) widths are both 2.4μm, the aperture area of ​​the pixel in the embodiment of the present invention is 5.6μm*3.6μm, and the aperture ratio reaches 42%. In contrast, the aperture area of ​​the existing rapid structure is 9.6μm*1.6μm, and the aperture ratio is only 31%. It can be seen that under the same conditions, the aperture ratio of the pixel provided by the embodiment of the present invention is significantly improved.

[0066] Optionally, when the width-to-length ratio of the pixel unit is 3 / 4, the reserved space s1 between the pixel electrodes 600 is 2 μm.

[0067] As an optional embodiment of the present invention, the material of the pixel electrode 600 may be indium tin oxide (ITO).

[0068] As a preferred embodiment of the present invention, the width-to-length ratio of the pixel unit is 4 / 3. When the PPI of the display substrate is approximately 2000PPI, as shown in FIG22 , the width n3 of the pixel unit is 8μm, and the length l3 of the pixel unit is 6μm. Considering the current process limitations, the minimum width of the pixel electrode 600 made of indium tin oxide is 1.5μm, and the minimum reserved space s3 between the pixel electrodes 600 is 2μm. Therefore, in the case of a pixel unit width of 6μm in the previous embodiment, the pixel electrode 600 cannot penetrate the entire opening area. As shown in FIG20 , a 0.85μm gap is required between the top of the pixel electrode 600 and the edge of the black matrix above it. Since there is no pixel electrode 600 in this area, the electric field will not drive the liquid crystal to move in the specified direction, thereby losing a certain amount of light efficiency. In the embodiment of the present invention, the horizontal width of the pixel unit is enlarged to 8μm, so that the pixel electrode 600 can not only cover the entire vertical length of the pixel unit, but also further increase the width of the pixel electrode 600, so that the liquid crystal efficiency of the pixel is higher and the display effect is further improved.

[0069] Optionally, when the width-to-length ratio of the pixel unit is 3 / 4, the reserved space s3 between the pixel electrodes 600 is 2.5 μm.

[0070] As a preferred embodiment of the present invention, the aspect ratio of the pixel unit is 7.5 / 6.4. When the PPI of the display substrate is about 2000PPI, as shown in Figure 21, the width n2 of the pixel unit is 7.5μm, and the length l2 of the pixel unit is 6.4μm. In the embodiment of the present invention, not only the lateral space of the pixel unit is 7.5μm, but also the pixel electrode 600 can be allowed to pass through the opening area. Moreover, the opening area size of the pixel unit is 5.1μm*4μm, and the aperture ratio can reach 42.5%, which is higher than the cases with aspect ratios of 3 / 4 and 4 / 3. While ensuring the efficiency of the liquid crystal, the pixel aperture ratio is further increased, thereby further improving the display effect.

[0071] Optionally, when the aspect ratio of the pixel unit is 7.5 / 6.4, the reserved space s2 between the pixel electrodes 600 is 2.25 μm.

[0072] As an optional embodiment of the present invention, as shown in FIG8 , the pixel units in the display substrate provided by the present invention may adopt a Delta distribution, that is, two adjacent rows of pixel units are staggered along the extension direction (first direction) of the gate line 110 .

[0073] As an optional embodiment of the present invention, as shown in FIG8 , the staggered distance A between two adjacent rows of pixel units along the first direction is 0 μm to 3 μm.

[0074] To simplify the manufacturing process, as a preferred embodiment of the present invention, the transparent electrode strips 120 and the gate lines 110 are stacked to achieve electrical connection. Specifically, as shown in Figures 1 to 3, the display substrate also includes a gate insulating layer 420, and the gate insulating layer 420 is located on the side of the active layer 300 away from the substrate 410. The transparent electrode strips 120 and the gate lines 110 are located in sequence on the side of the gate insulating layer 420 away from the substrate 410.

[0075] As an optional embodiment of the present invention, as shown in FIG1 , the display substrate further includes a first insulating layer 430, a second insulating layer 440, a first interlayer dielectric layer 510 and a second interlayer dielectric layer 520, the second insulating layer 440 is stacked between the gate insulating layer 420 and the substrate 410, the first insulating layer 430 is formed on the gate line 110 and the gate insulating layer 420, the data line 210 and the source 220 are both formed on the first insulating layer 430, and the first interlayer dielectric layer 510 is formed on the data line 210, the source 220 and the second interlayer dielectric layer 520. On an insulating layer 430, a pixel electrode (not shown in the figure) is formed on the first interlayer dielectric layer 510, and a second interlayer dielectric layer 520 is formed on the pixel electrode. The source electrode 220 is electrically connected to an electrical connection portion 320 of the active layer 300 through a via hole penetrating the gate insulating layer 420 and the first insulating layer 430, and the pixel electrode is electrically connected to another electrical connection portion 320 of the active layer 300 through a via hole penetrating the gate insulating layer 420, the first insulating layer 430 and the first interlayer dielectric layer 510 (the "×" icon in the top view represents a via).

[0076] As an optional embodiment of the present invention, the material of the transparent electrode strip 120 can be indium tin oxide (ITO). In the embodiment of the present invention, since the resistance of the transparent electrode strip 120 made of ITO material is too large, the resistance of the transparent electrode strip 120 can reach 1700kΩ when used alone as a gate line at specifications above 2000PPI, which will cause the gate signal delay (Gate delay) to be too high and the remote gate voltage cannot be output. Therefore, it is still necessary to retain the metal material of the gate line 110 to realize the signal transmission function. The width of the gate line 110 can be reduced to 0.9μm (the resistance is 35kΩ, which can still meet the remote gate signal output). Because the gate line 110 does not need to define a channel, after the width of the gate line 110 is reduced to 0.9μm, it can still be guaranteed to be under the black matrix shielding when the assy deviation is 1.5μm, without affecting the aperture ratio, thereby maximizing the aperture ratio.

[0077] As an optional embodiment of the present invention, the material of the channel portion 310 includes any one of metal oxide, polysilicon, and low-temperature polysilicon.

[0078] As an optional embodiment of the present invention, the material of the channel portion 310 includes any one or more of indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and lanthanide-doped metal oxide (Ln-OS).

[0079] As an optional embodiment of the present invention, the electrical connection portion 320 of the active layer 300 is obtained by conducting the active layer material (which may include any one or more of indium gallium zinc oxide, indium gallium oxide, indium gallium zinc tin oxide, indium zinc oxide, and lanthanide-doped metal oxides) through a doping process.

[0080] To ensure the stability of the performance of the thin film transistor, as a preferred embodiment of the present invention, the gate line 110 is located between the substrate 410 and the transparent electrode strips 120 and the active layer 300. Specifically, as shown in Figures 11 and 12, the display substrate also includes a gate insulating layer 420 and a first insulating layer 430. The gate insulating layer 420 is located between the gate line 110 and the active layer 300, and the transparent electrode strips 120 are located on the side of the first insulating layer 430 away from the substrate 410. The gate line 110 and the transparent electrode strips 120 are electrically connected through a connecting via 130 that passes through the first insulating layer 430 and the gate insulating layer 420.

[0081] In an embodiment of the present invention, the metal gate line 110 is positioned below the active layer 300, while the transparent electrode strip 120 remains in position, thereby forming a dual-gate structure. The metal gate line 110 below the active layer 300 can now shield the light, effectively reducing the risk of the thin-film transistor characteristics drifting due to light exposure in the channel portion 310 of the active layer 300. When the width of the transparent electrode strip 120 is 3 μm, the width of the underlying gate line 110 can still be maintained at 0.9 μm, without affecting the aperture ratio. At the same time, the gate line 110 shields the channel from light exposure, protecting the channel while maintaining a switching function, thereby ensuring the stability of the thin-film transistor performance.

[0082] As an optional embodiment of the present invention, as shown in Figures 13 and 12, the display substrate further includes a first insulating layer 430, a second insulating layer 440, a third insulating layer 450, a first interlayer dielectric layer 510 and a second interlayer dielectric layer 520, the second insulating layer 440 is stacked between the gate insulating layer 420 and the substrate 410, the first insulating layer 430 is formed on the active layer 300 and the gate insulating layer 420, the transparent electrode strips 120 are formed on the first insulating layer 430, the third insulating layer 450 is formed on the first insulating layer 430 and the transparent electrode strips 120, and the data lines 210 and the source electrodes 220 are both formed on the third insulating layer. 450, a first interlayer dielectric layer 510 is formed on the data line 210, the source 220 and the third insulating layer 450, a pixel electrode (not shown in the figure) is formed on the first interlayer dielectric layer 510, and a second interlayer dielectric layer 520 is formed on the pixel electrode. The source 220 is electrically connected to an electrical connection portion 320 of the active layer 300 through a via hole penetrating the first insulating layer 430 and the third insulating layer 450, and the pixel electrode is electrically connected to another electrical connection portion 320 of the active layer 300 through a via hole penetrating the first insulating layer 430, the third insulating layer 450 and the first interlayer dielectric layer 510 (the "×" icon in the top view represents a via hole).

[0083] As an optional embodiment of the present invention, as shown in Figure 3, the electrical connection portion 320 is connected to the pixel electrode through a first via (i.e., the drain via), and the electrical connection portion 320 is electrically connected to the data line 210 through a second via (i.e., the source via), and the orthographic projection of the first via on the substrate 410 falls within the orthographic projection of the corresponding pixel unit on the substrate 410.

[0084] As an optional embodiment of the present invention, as shown in FIG1 and FIG11 , the width m1 of the first via hole is approximately 1.5 μm, and the gap width between the first via hole and the transparent electrode strip 120 (i.e., the minimum distance between the first via hole and the transparent electrode strip 120 on the film plane where the transparent electrode strip 120 is located) is approximately 0.65 μm. For example, the width m1 of the first via hole may be 1.3 μm-1.7 μm, and the gap width between the first via hole and the transparent electrode strip 120 may be 0.4 μm-0.75 μm.

[0085] The width m1 of the second via hole is about 1.5 μm, and the gap width between the second via hole and the transparent electrode strip 120 is about 0.65 μm. For example, the width m1 of the second via hole can be 1.3 μm-1.7 μm, and the gap width between the second via hole and the transparent electrode strip 120 can be 0.4 μm-0.75 μm.

[0086] As an optional embodiment of the present invention, the extension direction of the channel portion 310 of the active layer 300 forms a first preset angle with the second direction, and the angle range of the first preset angle is 30-90°.

[0087] As an optional embodiment of the present invention, the central axis of the channel portion 310 of the active layer 300 and the central axis of the electrical connection portion 320 overlap, as shown in FIG. 5 .

[0088] As another optional embodiment of the present invention, the central axis of the channel portion 310 of the active layer 300 does not overlap with the central axis of the electrical connection portion 320, as shown in Figure 7 or Figure 9. Optionally, as shown in Figure 9, the angle β between the central axis of the channel portion 310 and the central axis of the electrical connection portion 320 ranges from 30° to 90°.

[0089] As an optional embodiment of the present invention, under conditions of 2000 PPI or above, the width of the transparent electrode strip 120 is less than or equal to 3μm. Specifically, as shown in Figure 3, a is the distance between the first and second via holes and the channel. It is necessary to ensure that the via holes do not affect the channel and cause a short circuit. a is the process deviation of 0.65μm. c is the size of the via hole. The current process limit is 1.5μm. b is the same-layer spacing distance (space) between adjacent active layers 300. It is necessary to ensure that adjacent active layers 300 can be exposed and etched separately. The minimum value of b is 2μm. Based on the above dimensions and the characteristic size of the pixel unit of 6μm*8μm, the auxiliary channel can be a maximum of 3μm. If it is greater than 3μm, the values ​​of abc cannot be guaranteed, and problems such as the active layer 300 cannot be etched open or the via holes affect the channel. Therefore, the width of the transparent electrode strip 120 must be less than or equal to 3μm.

[0090] In order to further improve the display effect, as a preferred embodiment of the present invention, as shown in Figures 6, 7 and 9, the extension direction of the channel portion 310 of the active layer 300 forms a second preset angle α with the first direction, and the two adjacent active layers 300 connected to the same data line 210 are respectively located on opposite sides of the data line 210, so that the multiple pixel units connected to each data line 210 are staggered and distributed on both sides of the corresponding data line 210.

[0091] Currently, liquid crystal display substrates use two inversion methods: column inversion and Zig-Zag inversion. FIG. 4 and FIG. 5 show a delta arrangement with a column inversion structure. The pixels connected to the upstream and downstream data lines 210 are of different colors, which creates the risk of color crosstalk. Furthermore, this connection method employs a vertical TFT design, meaning that the extension direction of the channel portion 310 is parallel to the second direction. The maximum length L of the channel region is limited to the maximum width of the transparent electrode strip 120, which is 3 μm.

[0092] In the embodiment of the present invention, the channel portion 310 of the active layer 300 extends obliquely, and the inclination directions of the active layers 300 of adjacent rows connected to the same data line 210 are opposite. Therefore, while realizing the Zig-Zag inversion mode shown in Figures 6 and 7, the channel portion 310 obliquely crosses the transparent electrode strips 120. When the width of the transparent electrode strips 120 is limited, the length L of the channel region can be further lengthened, so that the length L of the channel region is greater than 3μm, thereby further improving the display effect.

[0093] As an optional implementation manner of the present invention, the second preset angle α is 30° to 60°.

[0094] As an optional embodiment of the present invention, the display substrate further includes a color filter layer, the color filter layer including a plurality of color filter blocks corresponding one-to-one to the positions of the plurality of pixel units, and the colors of the plurality of color filter blocks corresponding to the plurality of pixel units corresponding to each of the data lines 210 are the same, while the colors of the color filter blocks corresponding to the pixel units corresponding to two adjacent data lines 210 are different.

[0095] As shown in Figure 9 , a is the size of the first via, b is the size of the second via, c is the spacing between adjacent active layers 300, d is the distance from the via to the channel that satisfies process tolerances, e is consistent with d, f is the width of the transparent electrode strip 120, and W / L is the aspect ratio of the thin film transistor. When the lateral dimension of the pixel unit is 6 μm, the maximum offset distance A between adjacent rows of pixel units is 3 μm. Figure 10 illustrates the changes in the above parameters as the offset distance A changes from 0 μm to 3 μm. As can be seen from the table, the length L of the oblique channel increases with the increase in the offset distance, and the minimum channel length L is also greater than 3.5 μm. Therefore, the oblique channel design of the embodiment of the present invention can effectively ensure the characteristics of the oxide thin film transistor (Oxide TFT), thereby improving the display effect.

[0096] As an optional embodiment of the present invention, as shown in FIG. 12 , the orthographic projection of the connecting via 130 on the substrate 410 is located between the orthographic projections of two adjacent channel portions 310 on the substrate 410 .

[0097] The display substrate further includes a substrate 410, a gate insulating layer 420 and a first insulating layer 430. The gate line 110 is formed above the substrate 410, the gate insulating layer 420 is formed above the gate line 110, the active layer 300 is formed on the gate insulating layer 420, the first insulating layer 430 is formed on the gate insulating layer 420 and the active layer 300, the transparent electrode strip 120 is formed on the first insulating layer 430, and the gate line 110 and the transparent electrode strip 120 are connected by penetrating the first insulating layer 430 and the first insulating layer 430. When the connection via 130 of the gate insulation layer 420 is electrically connected (that is, the gate line 110 is advanced to the bottom of the active layer 300 to form a dual-gate structure), in order to reserve sufficient space for setting the via, as a preferred embodiment of the present invention, as shown in Figures 12 and 14, at least one of the two electrical connection portions 320 extends along the second direction, and in the active layer 300 adjacent to both sides of the connection via 130, only the channel portion 310 corresponding to the end of the channel portion 310 away from the connection via 130 extends along the second direction.

[0098] In an embodiment of the present invention, the active layers 300 adjacent to each other on both sides of the connecting via 130 are designed to be centrally symmetrical, and only the channel portions 310 on the side away from the connecting via 130 in the active layers 300 on both sides extend along the second direction, so that the two obliquely extending channel portions 310 are as far away from the connecting via 130 therebetween as possible, providing sufficient design space for the connecting via 130.

[0099] As an optional embodiment of the present invention, as shown in FIG. 12 , the length a of the electrical connection portion 320 along the second direction is approximately 3.03 μm, and the second preset angle α is 45°.

[0100] As an optional embodiment of the present invention, as shown in Figure 12, the width c of the orthographic projection of the connecting via 130 on the substrate 410 is 1.5 μm to 2.5 μm. Optionally, the width c of the orthographic projection of the connecting via 130 on the substrate 410 is 2 μm.

[0101] As an optional embodiment of the present invention, as shown in FIG12 , the distance b between the connecting via 130 and the adjacent channel portion 310 (i.e., the distance between the connecting via 130 and the channel) is greater than or equal to 1.2 μm. Optionally, the distance b between the connecting via 130 and the adjacent channel portion 310 is 2 μm.

[0102] At present, after adopting the oblique symmetric design of the active layer 300, if a connecting via 130 is set for each two adjacent pixel units on the left and right, then as shown in Figure 14, the distance d between the active layers 300 of the left and right units needs to be reduced to 1.5μm, while the current limit of the spacing distance (space) between the active layers 300 in the same layer is 2μm. Therefore, more than two pixel units need to be set between adjacent connecting vias 130, and the channels of multiple pixel units need to be designed with a gradient special shape. Specifically, as shown in Figures 15 to 19, in the multiple active layers 300 on both sides of each connecting via 130, the length of the channel portion 310 corresponding to the end of the channel portion 310 away from the connecting via 130 extending along the second direction gradually decreases along the side away from the connecting via 130 to ensure that the spacing distance d between each two adjacent active layers 300 is not less than 2μm.

[0103] As shown in FIG15 , when the offset distance A between adjacent rows of pixel units is 0 μm, a design with 6 pixel units as a cycle is adopted, and the channel structure of the 7th pixel unit is the same as the channel structure of the 1st pixel unit. In this way, a connecting via 130 can be set between the 7th and 8th pixels to realize a cycle.

[0104] Figures 16 to 18 are structural designs of the active layer 300 when the offset distance A between adjacent rows of pixel units is 0.5μm, 1.0μm, and 1.5, respectively. When the offset distance A is 0.5μm and 1.0μm, a design with 5 pixel units as one cycle is adopted, and when the offset distance A is 1.5μm, a design with 4 pixel units as one cycle is adopted. The values ​​of the marked dimensions in Figures 15 to 18 are approximately the values ​​shown in the table of Figure 19.

[0105] Currently, when the offset distance A between adjacent rows of pixel units exceeds 1.5μm, when the gate line 110 provided by the present invention is advanced to the bottom of the active layer 300 to form a double-gate structure, since the distance between the left and right active layers 300 is too close, the distance b between the connecting via 130 and the channel is less than 0.65μm. Therefore, even if the active layers 300 on the left and right sides of the connecting via 130 adopt a special-shaped design, the design requirement of b>0.65μm cannot be met. Therefore, the double-gate structure provided by the present invention is currently only applicable to the case where the offset distance A between adjacent rows of pixel units is less than or equal to 1.5μm.

[0106] As a second aspect of the present invention, a display panel is provided. The display panel includes the display substrate provided by the present invention.

[0107] In the display panel provided by the present invention, the display substrate includes intersecting gate lines 110 and data lines 210. The data lines 210 are connected to the corresponding pixel electrodes through the active layer 300 of each pixel unit. The center of the active layer 300 intersecting with the gate lines 110 has a channel portion 310. The channel portion 310 can change its electrical properties as the signal in the gate lines 110 changes, thereby selectively connecting the pixel electrodes to the data lines 210, thereby controlling the light emission of each pixel unit. In addition, the orthographic projection of the channel portion 310 on the substrate 410 also overlaps with the orthographic projection of the data lines 210 on the substrate 410, so that the channel portion 310 can be jointly shielded by the black matrix corresponding to the gate lines 110 and the black matrix corresponding to the data lines 210, thereby improving the aperture ratio of the pixel unit, reducing the display power consumption of the display substrate, and improving the display effect of the display substrate.

[0108] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: It includes a substrate, and a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction arranged on one side of the substrate, the plurality of gate lines and the plurality of data lines are arranged in different layers, and the orthographic projections of the plurality of gate lines on the substrate intersect with the orthographic projections of the plurality of data lines on the substrate and define a plurality of pixel units; each of the pixel units includes at least one transistor, the transistor includes an active layer, the active layer includes a channel portion and a pair of electrical connection portions connected to both sides of the channel portion; the orthographic projection of the channel portion on the substrate overlaps with the orthographic projection of the data line on the substrate.

2. The display substrate according to claim 1, characterized in that: The display substrate further includes a plurality of transparent electrode strips, the plurality of transparent electrode strips extend along the first direction, and positions of the transparent electrode strips correspond one-to-one to positions of the plurality of gate lines; the orthographic projections of the transparent electrode strips on the substrate cover the orthographic projections of the gate lines on the substrate.

3. The display substrate according to claim 2, characterized in that: The pixel unit includes a pixel electrode, one of the electrical connection parts is electrically connected to the data line, and the other of the electrical connection parts is electrically connected to the pixel electrode; the channel part can change its own conductive state in response to the potential change of the gate line and the transparent electrode strip to selectively connect the data line and the pixel electrode.

4. The display substrate according to claim 2, characterized in that: In a plane parallel to the substrate and perpendicular to the first direction, the width of the transparent electrode strip is d1, and the width of the gate line is d2, wherein 1≤|d1 / d2|≤4.

5. The display substrate according to claim 4, characterized in that: The transparent electrode strips are electrically connected to the gate lines. The transparent electrode strips and the gate lines are located on one side of the active layer relative to the substrate, or on both sides of the active layer relative to the substrate.

6. The display substrate according to claim 5, characterized in that: The display substrate further comprises a gate insulating layer, which is located on a side of the active layer away from the substrate, and the transparent electrode strips and the gate lines are sequentially located on a side of the gate insulating layer away from the substrate.

7. The display substrate according to claim 5, characterized in that: The display substrate also includes a gate insulating layer and a first insulating layer, the gate insulating layer is located between the gate line and the active layer, the first insulating layer is located on a side of the gate insulating layer away from the substrate, the transparent electrode strips are located on a side of the first insulating layer away from the substrate, and the gate line and the transparent electrode strips are electrically connected through connecting vias that penetrate the first insulating layer and the gate insulating layer.

8. The display substrate according to claim 7, characterized in that: The position of the orthographic projection of the connecting via on the substrate is located between the orthographic projections of two adjacent channel portions on the substrate.

9. The display substrate according to claim 8, characterized in that: The width of the orthographic projection of the connecting via on the substrate is 1.5 μm to 2.5 μm.

10. The display substrate according to claim 8, characterized in that: The distance between the connecting via hole and the adjacent channel portion is greater than or equal to 1.2 μm.

11. The display substrate according to claim 8, characterized in that: In the plurality of active layers on both sides of each of the connecting vias, the length of the channel portion corresponding to the end of the channel portion away from the connecting via along the second direction gradually decreases along the side away from the connecting via.

12. The display substrate according to claim 3, characterized in that: The electrical connection portion is connected to the pixel electrode through a first via hole, and the electrical connection portion is electrically connected to the data line through a second via hole, and the orthographic projection of the first via hole on the substrate falls within the orthographic projection of the corresponding pixel unit on the substrate.

13. The display substrate according to claim 12, characterized in that: The width of the gap between the first via hole and the transparent electrode strip is 0.4 μm-0.75 μm.

14. The display substrate according to claim 12, characterized in that: The width of the gap between the second via hole and the transparent electrode strip is 0.4 μm-0.75 μm.

15. The display substrate according to any one of claims 1 to 3, characterized in that: An extension direction of the channel portion of the active layer forms a first preset angle with the second direction, and an angle range of the first preset angle is 30-90°.

16. The display substrate according to any one of claims 1 to 3, characterized in that: A central axis of the channel portion of the active layer overlaps with a central axis of the electrical connection portion.

17. The display substrate according to any one of claims 1 to 3, characterized in that: The central axis of the channel portion of the active layer and the central axis of the electrical connection portion do not overlap, and the angle between the central axis of the channel portion and the central axis of the electrical connection portion is in the range of 30-90°.

18. The display substrate according to any one of claims 1 to 3, characterized in that: The extension direction of the channel portion forms a second preset angle with the first direction, and the two adjacent active layers connected to the same data line are respectively located on opposite sides of the data line, so that the multiple pixel units connected to each data line are staggered on both sides of the corresponding data line.

19. The display substrate according to any one of claims 1 to 3, characterized in that: The ratio of the size of the pixel unit along the first direction to the size of the pixel unit along the second direction is 3 / 4 to 4 / 3.

20. The display substrate according to any one of claims 1 to 3, characterized in that: The material of the channel portion includes any one of metal oxide, polysilicon, and low-temperature polysilicon.

21. A display panel, characterized in that: The display panel comprises the display substrate according to any one of claims 1 to 20.

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