Array substrate, driving method for pixel circuit, display panel and display apparatus

Abstract

An array substrate. The array substrate comprises a substrate and a plurality of pixel circuits provided on the substrate, the plurality of pixel circuits being arranged in a plurality of rows and columns. Each pixel circuit comprises a first light-emitting control transistor and a second light-emitting control transistor. The array substrate further comprises a first light-emitting control signal line and a second light-emitting control signal line. The first light-emitting control signal line is electrically connected to gates of the first light-emitting control transistors. The second light-emitting control signal line is electrically connected to gates of the second light-emitting control transistors. The array substrate further comprises a plurality of conductive layers. The first light-emitting control signal line and the second light-emitting control signal line are electrically insulated from each other, the first light-emitting control signal line and the second light-emitting control signal line being located on different conductive layers, and the orthographic projections of the first light-emitting control signal line and the second light-emitting control signal line on the substrate not overlapping each other.

Description

Array substrate, pixel circuit driving method, display panel and display device

[0001] This application claims priority to Chinese patent application No. 202310805073.7, filed on June 30, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate, a driving method for a pixel circuit, a display panel, and a display device. Background Art

[0003] With the development of display technology, display devices such as mobile phones, televisions and computers are increasingly used in people's lives. Display devices include pixel circuits and light-emitting devices. The pixel circuit controls the driving current flowing through the light-emitting device, thereby driving the light-emitting device to display different grayscales, thereby realizing image display. Among them, the luminous efficiency of the light-emitting device will decrease as the current density decreases under low current density conditions. In order to improve the luminous efficiency of the light-emitting device, the pixel circuit introduces a pulse width modulation (English: Pulse Width Modulation; PWM for short) dimming method to adjust the brightness of the light-emitting device. PWM dimming controls the light-emitting time of the light-emitting device, adjusts the light-emitting brightness of the light-emitting device, changes the overall brightness of the display screen, and makes the overall brightness of the display screen more stable.

[0004] Summary of the Invention

[0005] In one aspect, an array substrate is provided. The array substrate includes a substrate and a plurality of pixel circuits disposed on the substrate, the plurality of pixel circuits being arranged in multiple rows and columns. The pixel circuits include a first light-emission control transistor and a second light-emission control transistor. The array substrate also includes a first light-emission control signal line and a second light-emission control signal line. The first light-emission control signal line is electrically connected to the gate of the first light-emission control transistor. The second light-emission control signal line is electrically connected to the gate of the second light-emission control transistor. The array substrate also includes multiple conductive layers, the first light-emission control signal line and the second light-emission control signal line being electrically insulated, the first light-emission control signal line and the second light-emission control signal line being located on different conductive layers, and the orthographic projections of the first light-emission control signal line and the second light-emission control signal line on the substrate not overlapping.

[0006] In some embodiments, the multiple conductive layers include a first gate conductive layer and a first source / drain conductive layer. The first gate conductive layer includes a first gate pattern and a second light-emission control signal line. The first gate pattern forms the gate of the first light-emission control transistor. The first source / drain conductive layer is disposed on a side of the first gate conductive layer away from the substrate and includes the first light-emission control signal line. The orthographic projection of the first light-emission control signal line on the substrate partially overlaps with the orthographic projection of the first gate pattern on the substrate, and the first light-emission control signal line is electrically connected to the first gate pattern.

[0007] In some embodiments, the pixel circuit further includes a driving transistor. The array substrate further includes a semiconductor layer disposed between the substrate and the first gate conductive layer. The semiconductor layer includes a first channel region of the first emission control transistor, a second channel region of the second emission control transistor, a third channel region of the driving transistor, a first connection region, and a second connection region. The first connection region and the second connection region are located on opposite sides of the third channel region, respectively, and the first connection region is connected to the third channel region and the second channel region, respectively, and the second connection region is connected to the third channel region and the first channel region, respectively. The orthographic projection of the first gate pattern on the substrate partially overlaps with the orthographic projection of the first channel region on the substrate, but does not overlap with the orthographic projection of the first connection region on the substrate. The orthographic projection of the second emission control signal line on the substrate partially overlaps with the orthographic projection of the second channel region on the substrate.

[0008] In some embodiments, the pixel circuit further includes a first reset transistor. The semiconductor layer further includes a third connection region and a fourth channel region of the first reset transistor. The first gate conductive layer further includes a fourth gate pattern, and the orthographic projection of the fourth gate pattern on the substrate at least partially overlaps with the orthographic projection of the fourth channel region on the substrate. The first source-drain conductive layer further includes a first enable signal line and a first adapter block, the orthographic projection of the first enable signal line on the substrate partially overlaps with the orthographic projection of the fourth gate pattern on the substrate, and the first enable signal line is electrically connected to the fourth gate pattern. The first adapter block is electrically connected to the third connection region and the gate of the driving transistor. The array substrate further includes a second gate conductive layer, the second gate conductive layer is arranged between the first gate conductive layer and the first source-drain conductive layer, and includes a first initialization voltage signal line, and the first initialization voltage signal line is electrically connected to the first electrode of the first reset transistor.

[0009] In some embodiments, the pixel circuit further includes a compensation transistor. The semiconductor layer further includes a fifth channel region of the compensation transistor, one side of the fifth channel region being connected to the first connection region and the other side being connected to the third connection region. The first gate conductive layer further includes a fifth gate pattern, the orthographic projection of the fifth gate pattern on the substrate covering the orthographic projection of the fifth channel region on the substrate. The first source-drain conductive layer further includes a second enable signal line, the orthographic projection of the second enable signal line on the substrate partially overlapping the orthographic projection of the fifth gate pattern on the substrate, and the second enable signal line is electrically connected to the fifth gate pattern.

[0010] In some embodiments, the compensation transistor is a dual-gate transistor, and the fifth channel region includes a first sub-region and a second sub-region spaced apart from each other. The semiconductor layer further includes a fourth connection region, the fourth connection region being located between the first sub-region and the second sub-region and connected to the first sub-region and the second sub-region. The second gate conductive layer further includes a first shielding portion, the orthographic projection of the first shielding portion on the substrate at least partially overlapping with the orthographic projection of the fourth connection region on the substrate.

[0011] In some embodiments, the second gate conductive layer further includes a second blocking portion, and the orthographic projections of the second blocking portion, the third connection region, and the second enable signal line on the substrate at least partially overlap.

[0012] In some embodiments, the pixel circuit further includes a data write transistor. The semiconductor layer further includes a sixth channel region of the data write transistor, and along the first direction, the fifth channel region and the sixth channel region are staggered, and the sixth channel region is connected to the second connection region. The first direction is the column direction in which the multiple pixel circuits are arranged. The first gate conductive layer further includes a sixth gate pattern, and the orthographic projection of the sixth gate pattern on the substrate partially overlaps with the orthographic projection of the sixth channel region on the substrate. The first source and drain conductive layer further includes a first scan signal line, and the orthographic projection of the first scan signal line on the substrate partially overlaps with the orthographic projection of the sixth gate pattern on the substrate, and the first scan signal line is electrically connected to the sixth gate pattern.

[0013] In some embodiments, the pixel circuit further includes a second reset transistor. The semiconductor layer further includes a seventh channel region of the second reset transistor. The first gate conductive layer further includes a seventh gate pattern, the orthographic projection of the seventh gate pattern on the substrate partially overlapping with the orthographic projection of the seventh channel region on the substrate. The second gate conductive layer further includes a second initialization voltage signal line, the second initialization voltage signal line being electrically connected to the first electrode of the second reset transistor. The first source-drain conductive layer further includes a second scan signal line, the orthographic projection of the second scan signal line on the substrate partially overlapping with the orthographic projection of the seventh gate pattern on the substrate, and the second scan signal line is electrically connected to the seventh gate pattern.

[0014] In some embodiments, the array substrate further includes a light shielding layer disposed between the substrate and the semiconductor layer, wherein an orthographic projection of the light shielding layer on the substrate at least partially overlaps with an orthographic projection of the pixel circuit on the substrate.

[0015] In some embodiments, the array substrate has a display area and a peripheral area surrounding the display area. The array substrate includes a plurality of first initialization voltage signal lines, a plurality of second initialization voltage signal lines, and a second voltage signal bus. A row of pixel circuits is electrically connected to a first initialization voltage signal line and a second initialization voltage signal line; the second voltage signal bus is arranged in the peripheral area and at least partially surrounds the display area. The array substrate also includes a second source-drain conductive layer. The second source-drain conductive layer is arranged on a side of the first source-drain conductive layer away from the substrate, and includes a plurality of first connection lines, a plurality of second connection lines, and a plurality of third connection lines extending along a first direction. Each first connection line is electrically connected to the plurality of first initialization voltage signal lines, each second connection line is electrically connected to the plurality of second initialization voltage signal lines, and each third connection line extends to the peripheral area and is electrically connected to the second voltage signal bus.

[0016] In another aspect, a method for controlling a pixel circuit is also provided. The pixel circuit includes a driving transistor, a first light-emission control transistor, and a second light-emission control transistor. The first light-emission control transistor has a gate electrically connected to a first light-emission control signal line, a first electrode electrically connected to a first voltage signal line, and a second electrode electrically connected to the first electrode of the driving transistor. The second light-emission control transistor has a gate electrically connected to a second light-emission control signal line, a first electrode electrically connected to the second electrode of the driving transistor, and a second electrode electrically connected to a light-emitting device. The first light-emission control signal line is configured to transmit a first pulse-width modulated signal, and the second light-emission control signal line is configured to transmit a second pulse-width modulated signal.

[0017] A display cycle includes a light-emitting phase. The driving method includes: during the light-emitting phase, the first pulse width modulation signal has a first operating level period, the second pulse width modulation signal has a second operating level period, the first operating level period is different from the second operating level period, and the first operating level period and the second operating level period partially overlap.

[0018] In some embodiments, the amplitude, frequency, and duty cycle of the first pulse width modulation signal are respectively the same as the amplitude, frequency, and duty cycle of the second pulse width modulation signal. The start and end times of the first working level period lag behind the start and end times of the second working level period.

[0019] In some embodiments, the pixel circuit further includes a first reset transistor, a second reset transistor, a data write transistor, and a compensation transistor. The gate of the first reset transistor is electrically connected to the first enable signal line, the first electrode is electrically connected to the first initialization voltage signal line, and the second electrode is electrically connected to the gate of the drive transistor. The gate of the second reset transistor is electrically connected to the second scan signal line, the first electrode is electrically connected to the second initialization voltage signal line, and the second electrode is electrically connected to the second electrode of the second light-emitting control transistor. The gate of the data write transistor is electrically connected to the first scan signal line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the first electrode of the drive transistor. The gate of the compensation transistor is electrically connected to the second enable signal line, the first electrode is electrically connected to the second electrode of the drive transistor, and the second electrode is electrically connected to the gate of the drive transistor.

[0020] A display cycle also includes a blank period, during which at least one of the first light-emitting control transistor and the second light-emitting control transistor is turned off. The blank period includes a first initialization period, a second initialization period, and a data writing period. The driving method further includes: in the first initialization period, the first reset transistor is turned on under the control of a first enable signal from the first enable signal line, and transmits a first initialization voltage signal from the first initialization voltage signal line to the gate electrode of the driving transistor. In the second initialization period, the first reset transistor remains on, and the compensation transistor is turned on under the control of a second enable signal from the second enable signal line, and transmits the first initialization voltage signal to the second electrode of the driving transistor. In the data writing period, the compensation transistor remains on, and the data writing transistor is turned on under the control of a first scan signal from the first scan signal line, and transmits a data signal from the data line to the first electrode of the driving transistor.

[0021] In some embodiments, the blank phase further includes a bias phase after the data writing phase. The driving method further includes: during the bias phase, the first light emission control transistor is turned off, the second light emission control transistor is turned on, and the second reset transistor is turned on under the control of the second scan signal of the second scan signal line, and the second initialization voltage signal from the second initialization voltage signal terminal is transmitted to the second electrode of the second light emission control transistor and the first electrode of the driving transistor in sequence.

[0022] In some embodiments, during the second initialization phase and the data writing phase, the second reset transistor is turned on under the control of the second scan signal from the second scan signal line, and transmits the second initialization voltage signal from the second initialization voltage signal line to the second electrode of the second light-emitting control transistor.

[0023] In some embodiments, the first operating level period is within the second operating level period, and the start and end times of the first operating level period are spaced apart from the start and end times of the second operating level period. Alternatively, the second operating level period is within the first operating level period, and the start and end times of the first operating level period are spaced apart from the start and end times of the second operating level period.

[0024] In some embodiments, the amplitude, frequency, and duty cycle of the first pulse width modulation signal are respectively the same as the amplitude, frequency, and duty cycle of the second pulse width modulation signal. The start and end times of the first working level period are respectively ahead of the start and end times of the second working level period.

[0025] In another aspect, a display panel is provided, comprising a plurality of light-emitting devices and an array substrate as described in any one of the above embodiments, wherein the plurality of light-emitting devices are disposed on the array substrate, and each light-emitting device is electrically connected to a pixel circuit.

[0026] In another aspect, a display device is provided, comprising a driving circuit board and the display panel described above, wherein the driving circuit board is electrically connected to the display panel and configured to transmit a control signal to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0028] FIG1 is a structural diagram of a display device according to some embodiments;

[0029] FIG2 is a structural diagram of a display panel according to some embodiments;

[0030] FIG3 is a cross-sectional structural diagram of a display panel according to some embodiments;

[0031] FIG4 is a structural diagram of a pixel circuit according to some embodiments;

[0032] FIG5 is a PWM signal diagram in the prior art;

[0033] FIG6 is a structural diagram of an array substrate according to some embodiments;

[0034] FIG7 is another structural diagram of an array substrate according to some embodiments;

[0035] FIG8 is a control timing diagram of a first light emitting control signal line and a second light emitting control signal line according to some embodiments;

[0036] FIG9 is another structural diagram of a pixel circuit according to some embodiments;

[0037] FIG10 is a structural diagram of a semiconductor layer according to some embodiments;

[0038] FIG11 is a diagram illustrating a stacked structure of a semiconductor layer and a light shielding layer according to some embodiments;

[0039] FIG12 is a diagram illustrating a stacked structure of a semiconductor layer and a first gate conductive layer according to some embodiments;

[0040] FIG13 is a diagram of a stacked structure from a semiconductor layer to a second gate conductive layer according to some embodiments;

[0041] FIG14 is a diagram of a stacked structure from a semiconductor layer to a first source-drain conductive layer according to some embodiments;

[0042] FIG15 is a diagram of a stacked structure from a semiconductor layer to a second source-drain conductive layer according to some embodiments;

[0043] FIG16A is a schematic diagram of an array substrate according to some embodiments;

[0044] FIG16B is a structural diagram of an array substrate according to some embodiments;

[0045] FIG17 is another structural diagram of a pixel circuit according to some embodiments;

[0046] FIG18 is another structural diagram of a pixel circuit according to some embodiments;

[0047] FIG19 is another control timing diagram of the first light emitting control signal line and the second light emitting control signal line according to some embodiments;

[0048] FIG20 is a diagram illustrating a connection relationship between a first light emitting control signal line and a second light emitting control signal line and a first shift register according to some embodiments;

[0049] FIG21 is a diagram showing the connection relationship between the first enable signal line, the second enable signal line and the second shift register;

[0050] FIG22 is a control timing diagram of a pixel circuit according to some embodiments;

[0051] FIG23 is another control timing diagram of a pixel circuit according to some embodiments;

[0052] FIG24 is another control timing diagram of a pixel circuit according to some embodiments;

[0053] FIG25 is another control timing diagram of a pixel circuit according to some embodiments;

[0054] FIG26 is another control timing diagram of a pixel circuit according to some embodiments;

[0055] FIG. 27 is yet another control timing diagram of a pixel circuit according to some embodiments. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0057] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0058] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0059] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0060] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0061] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0062] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0063] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0064] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0065] 1 , some embodiments of the present disclosure provide a display device 1000 . The display device 1000 may be any device that displays either moving (eg, video) or fixed (eg, still images), and either text or images.

[0066] For example, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigation system, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, an in-vehicle display, or an aircraft display. For example, as shown in FIG1 , the display device 1000 can be a mobile phone.

[0067] From the perspective of the light-emitting type of the display device 1000, the display device 1000 may be an organic light-emitting diode (OLED) display device, a quantum dot electroluminescent display device (QLED) or a mini / micro light-emitting diode (MLED). From the perspective of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device or a foldable display device. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular. Some embodiments of the present disclosure are schematically described below using a rectangular and planar organic light-emitting diode display device as an example. However, the embodiments of the present disclosure are not limited thereto, and any other display device may also be considered as long as the same technical concept is applied.

[0068] In some embodiments, referring to FIG2 , the display device 1000 includes a display panel 1100 and a driver circuit board 1200 . The driver circuit board 1200 may include, for example, a timing controller (TCON), a DC / DC power management chip, and an adjustable resistor divider circuit (generating Vcom), and other driver circuits. The driver circuit board 1200 may also include other circuit structures, which are not listed here. The driver circuit board 1200 is electrically connected to the display panel 1100 and is configured to transmit control signals to the display panel 1100, thereby driving the display panel 1100 to display images. The control signals may include, for example, clock signals, power supply voltage signals, and data signals, which are not listed here.

[0069] In addition, the display device 1000 may further include an under-screen camera and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as taking pictures, recording videos, fingerprint recognition or face recognition, which are not specifically limited here.

[0070] Referring to FIG. 2 , a display panel 1100 includes a display area AA and a peripheral area BB. Peripheral area BB is located on at least one side of display area AA and, illustratively, surrounds display area AA. Display area AA is the area of ​​display panel 1100 used for displaying images. Display area AA includes a plurality of sub-pixels P, each the smallest light-emitting unit on display panel 1100. Sub-pixels P are used to display images.

[0071] Among them, multiple sub-pixels P can emit light of the same color, such as white light or blue light. Based on this, the display panel also includes a color filter layer arranged on the display side, that is, the display panel adopts a COE (English full name: CF on Encapsulation; Chinese name: color filter layer on encapsulation film) structure. Alternatively, multiple sub-pixels P can emit light of different colors. For example, multiple sub-pixels P include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light. Exemplarily, the multiple sub-pixels P can be divided into multiple pixel units, each pixel unit including a red sub-pixel, a blue sub-pixel, and one (or two) green sub-pixels.

[0072] 3 , the display panel 1100 includes a stacked array substrate 100, a plurality of light-emitting devices 200, and an encapsulation layer 300. Of course, the display panel 1100 may also include a functional stack disposed on the side of the encapsulation layer 300 away from the array substrate 100. The functional stack may include, for example, one or more of a touch function layer, an anti-reflection layer, a hardening layer, a color filter layer (the display panel adopts a COE structure), and an anti-fingerprint layer, so that the display panel 1100 can achieve corresponding functions. The embodiments of the present disclosure do not specifically limit the type and number of the above-mentioned functional stacks.

[0073] Continuing with FIG. 3 , the array substrate 100 may include a substrate 11, a semiconductor layer Poly disposed on the substrate 11, and multiple conductive layers 12 disposed on a side of the semiconductor layer Poly away from the substrate 11. In some embodiments, as shown in FIG. 3 , the multiple conductive layers 12 include a first gate conductive layer Gate1, a second gate conductive layer Gate2, a first source / drain conductive layer SD1, and a second source / drain conductive layer SD2, sequentially disposed along a direction Z away from the substrate 11. The array substrate 100 also includes an insulating layer located between any two adjacent conductive layers. For example, the array substrate further includes a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer dielectric layer ILD, a first planarization layer PLN1, and a second planarization layer PLN2. Of course, the array substrate 100 may also include other conductive or insulating layers, which are not listed here.

[0074] 3 , the light-emitting device 200 may include, for example, a stacked anode 201, a light-emitting functional layer 202, and a cathode layer 203. The display panel 1100 may further include a pixel defining layer (PDL), which is disposed on a side of the anode 201 away from the array substrate 100 and includes a plurality of openings, with each light-emitting device 200 located within an opening region.

[0075] The encapsulation layer 300 is configured to reduce the risk of moisture and oxygen from the external environment entering the light-emitting device 200, thereby increasing the service life of the display panel 1100. The encapsulation layer 300 can be an encapsulation film or an encapsulation substrate. For example, as shown in FIG3 , the encapsulation layer 300 can be an encapsulation film. In this case, the encapsulation layer 300 can include a first inorganic encapsulation layer 301, an organic encapsulation layer 302, and a second inorganic encapsulation layer 303, which are stacked in sequence.

[0076] As shown in FIG2 , the array substrate 100 has a display area AA and a peripheral area BB, with the peripheral area BB surrounding the display area AA. The display area AA of the array substrate 100 and the display area AA of the display panel 1100 are the same area, and the peripheral area BB of the array substrate 100 and the peripheral area BB of the display panel 1100 are the same area.

[0077] The array substrate 100 includes a plurality of pixel circuits 110. The plurality of pixel circuits 110 are disposed within the display area AA and arranged in multiple rows and columns within the display area AA. The rows of pixel circuits 110 are arranged along a first direction Y, and each row includes a plurality of pixel circuits 110 arranged along a second direction X. The columns of pixel circuits 110 are arranged along the second direction X, and each column includes a plurality of pixel circuits 110 arranged along the first direction Y. In other words, the first direction Y is the column direction in which the plurality of pixel circuits 110 are arranged, and the second direction X is the row direction in which the plurality of pixel circuits 110 are arranged. The first direction Y and the second direction X intersect with each other. Exemplarily, the first direction Y and the second direction X are perpendicular to each other.

[0078] Among them, the pixel circuit 110 includes a plurality of thin film transistors (TFT) and at least one capacitor Cst. Exemplarily, the pixel circuit 110 can be a "7T1C" circuit or an "8T1C" circuit, etc., wherein "T" refers to TFT, and the number before "T" refers to the number of TFTs; "C" refers to capacitor Cst, and the number before "C" refers to the number of capacitors Cst. In the following embodiments of the present disclosure, the pixel circuit 110 is a "7T1C" circuit as an example for schematic description, but the embodiments of the present disclosure are not limited thereto, and any other pixel circuit 110 can also be considered as long as the same technical concept is applied.

[0079] The thin film transistor can be a P-type transistor or an N-type transistor. The P-type transistor is turned on under the action of a low level and is turned off under the action of a high level; the N-type transistor is turned on under the action of a high level and is turned off under the action of a low level. The embodiments disclosed herein are all described using a P-type transistor as an example. The first electrode of each thin film transistor used in the pixel circuit is one of the source and drain of the thin film transistor, and the second electrode is the other of the source and drain of the thin film transistor. Exemplarily, the first electrode of the thin film transistor is the source, and the second electrode is the drain.

[0080] In some embodiments, as shown in FIG4 , the plurality of thin film transistors may include a driving transistor T3, a first emission control transistor T1, and a second emission control transistor T2. A first electrode of the first emission control transistor T1 is electrically connected to a first voltage signal line VDD, and a second electrode is electrically connected to a first electrode of the driving transistor T3. A first electrode of the second emission control transistor T2 is electrically connected to a second electrode of the driving transistor T3, and a second electrode is electrically connected to the light-emitting device 200. During the light-emitting phase of a display frame, when the first emission control transistor T1 and the second emission control transistor T2 are simultaneously turned on, the driving current generated by the driving transistor T3 can flow to the light-emitting device 200, driving the light-emitting device 200 to emit light.

[0081] In related art, the first and second emission control transistors T1 and T2 in the same pixel circuit are electrically connected to the same emission control signal line. This allows the first and second emission control transistors T1 and T2 to be turned on or off simultaneously. When the pixel circuit utilizes PWM dimming, PWM dimming adjusts the duration of the first and second emission control transistors T1 and T2 during the light-emitting phase, thereby adjusting the duration of the light-emitting device's illumination, thereby adjusting the device's brightness. As shown in Figure 5, in the PWM signal, the duration of an operating level K is typically an even multiple of the horizontal scan time (1H), typically ranging from 2μs to 20μs. Due to the limitation of the duration of an operating level K, PWM dimming has low accuracy. It should be understood that the operating level refers to the voltage that turns on the first and second emission control transistors T1 and T2. When the first and second emission control transistors T1 and T2 are P-type transistors, the operating level is a low voltage.

[0082] To address the above technical issues, referring to Figures 6 and 7 , embodiments of the present disclosure provide an array substrate 100 comprising a first emission control transistor T1 and a second emission control transistor T2. The array substrate 100 also includes a first emission control signal line EM1 and a second emission control signal line EM2. Figure 7 illustrates the stacked structure of the array substrate's semiconductor layer Poly, first gate conductive layer Gate1, and first source and drain conductive layer SD1.

[0083] The first emission control signal line EM1 is electrically connected to the gate of the first emission control transistor T1, and the second emission control signal line EM2 is electrically connected to the second emission control transistor T2. The first emission control signal line EM1 and the second emission control signal line EM2 are electrically insulated from each other. In this way, the first emission control transistor T1 and the second emission control transistor T2 are independently controlled by the first emission control signal line EM1 and the second emission control signal line EM2, respectively. This provides a more flexible control method for the first emission control transistor T1 and the second emission control transistor T2, and helps improve the PWM dimming accuracy of the pixel circuit 110.

[0084] For example, as shown in FIG8 , the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are respectively used to transmit two different PWM signals, and the signal start and end times of the two PWM signals are different (with a certain phase difference). For example, as shown in FIG8 , the low-level duration W of the two PWM signals transmitted by the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 is equal, and the low-level on time can differ by any value ΔK. Based on this, the duration of the low-level overlap of the two PWM signals can be any value, which is conducive to improving the accuracy of PWM dimming. For the specific control method of the pixel circuit 110, please refer to the following. The signal start and end time of a signal refers to the time when the signal starts and the time when it cuts off (ends).

[0085] The first and second emission control signal lines EM1 and EM2 are located on different conductive layers 12. This helps reduce the spacing between the first and second emission control signal lines EM1 and EM2 along the first direction Y, thereby reducing the space occupied by the pixel circuit 110 and improving the pixel density (PPI) of the display panel 1100. The orthographic projections of the first and second emission control signal lines EM1 and EM2 on the substrate 11 do not overlap, thereby preventing parasitic capacitance from forming between the first and second emission control signal lines EM1 and EM2, and reducing the risk of signal interference between the first and second emission control signal lines EM1 and EM2.

[0086] Of course, in some other embodiments, without considering the space occupied by the pixel circuit 110, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 may also be located in the same conductive layer. In this way, it is sufficient to ensure that there is a sufficient interval between the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 to avoid interference between the signals transmitted therebetween.

[0087] In some embodiments, referring to FIG. 9 , the pixel circuit 110 further includes a driving transistor T3 , a first reset transistor T4 , a compensation transistor T5 , a data writing transistor T6 , a second reset transistor T7 , and a capacitor Cst.

[0088] As shown in FIG9 , the gate of the first reset transistor T4 is electrically connected to the first enable signal line Scan-1, the first electrode is electrically connected to the first initialization voltage signal line Vinit1, and the second electrode is electrically connected to the gate of the drive transistor T3. The gate of the compensation transistor T5 is electrically connected to the second enable signal line Scan2, the first electrode is electrically connected to the second electrode of the drive transistor T3, and the second electrode is electrically connected to the gate of the drive transistor T3. The gate of the data write transistor T6 is electrically connected to the first scan signal line GL1, the first electrode is electrically connected to the data line DL, and the second electrode is electrically connected to the first electrode of the drive transistor T3. The gate of the second reset transistor T7 is electrically connected to the second scan signal line GL2, the first electrode is electrically connected to the second initialization voltage signal line Vinit2, and the second electrode is electrically connected to the second electrode of the second light emission control transistor T2 (the anode of the light emitting device 200). One electrode plate of the capacitor Cst is electrically connected to the first voltage signal line VDD, and the other electrode plate is electrically connected to the gate of the drive transistor T3.

[0089] Compared to scan signals (e.g., the first scan signal transmitted by the first scan signal line and the second scan signal transmitted by the second scan signal line), the pulse width of the enable signal (e.g., the first enable signal transmitted by the first enable signal line Scan-1 and the second enable signal transmitted by the second enable signal line Scan2) is wider. The first reset transistor T4 and the compensation transistor T5 are controlled by the enable signal, which facilitates sufficient writing of signals to corresponding nodes and is more conducive to timing adjustment of the pixel circuit 110. For example, the first enable signal transmitted by the first enable signal line Scan-1 has a longer pulse width, which facilitates sufficient writing of the first initialization voltage signal from the first initial voltage signal line Vinit1 to the gate of the drive transistor T3.

[0090] In some embodiments, the second enable signal line Scan2 is insulated from the first scan signal line GL1, and the two are configured to transmit different voltage signals. In this way, the data write transistor T6 and the compensation transistor T5 are controlled by different signal lines, and the control timing of the data write transistor T6 and the compensation transistor T5 is more flexible, which is conducive to improving the control accuracy of the pixel circuit 110 (see below).

[0091] As shown in FIG10 , the semiconductor layer Poly includes a plurality of semiconductor patterns 20, each of which is used to form a pixel circuit 110. Alternatively, the pixel circuit 110 includes a semiconductor pattern 20. It should be noted that in FIG10 , the semiconductor layer Poly uses different fill shapes to distinguish different regions of the semiconductor pattern 20, and the semiconductor pattern 20 is a continuous, integral structure.

[0092] 10 and 11 , the semiconductor pattern 20 may include a first channel region 21 of a first light emission control transistor T1, a second channel region 22 of a second light emission control transistor T2, a third channel region 23 of a driving transistor T3, a fourth channel region 24 of a first reset transistor T4, a fifth channel region 25 of a compensation transistor T5, a sixth channel region 26 of a data write transistor T6, a seventh channel region 27 of a second reset transistor T7, a first connection region 28, a second connection region 29, a third connection region 210, a fourth connection region 211, and a fifth connection region 212.

[0093] The first channel region 21 is used to form the channel structure of the first emission control transistor T1, and the second channel region 22 is used to form the channel structure of the second emission control transistor T2. The first channel region 21 and the second channel region 22 are staggered along the first direction Y. In other words, the first channel region 21 and the second channel region 22 are spaced apart in the first direction Y, which facilitates the wiring arrangement of the first emission control signal line EM1 and the second emission control signal line EM2.

[0094] The first connection region 28 and the second connection region 29 are located on opposite sides of the third channel region 23 (along the second direction X). The first connection region 28 is connected to the third channel region 23 and the second channel region 22 to electrically connect the first electrode of the second emission control transistor T2 to the second electrode of the drive transistor T3. The first connection region 28 can form the second electrode of the drive transistor T3 and the first electrode of the second emission control transistor T2. As shown in Figure 10, the first connection region 28 is also electrically connected to the fifth channel region 25 of the compensation transistor T5 and forms the first electrode of the compensation transistor T5.

[0095] Along the first direction Y, the fourth channel region 24 and the fifth channel region 25 are staggered, and the fifth channel region 25 and the sixth channel region 26 are staggered, so that the first enable signal line Scan1, the second enable signal line Scan2 and the first scan signal line GL1 are arranged at intervals along the first direction Y, which is beneficial to the spatial arrangement of the first enable signal line Scan1, the second enable signal line Scan2 and the first scan signal line GL1.

[0096] The second connection region 29 is connected to the third channel region 23 and the first channel region 21, thereby electrically connecting the second electrode of the first emission control transistor T1 to the first electrode of the drive transistor T3. In other words, the second connection region 29 can form the first electrode of the drive transistor T3 and the second electrode of the first emission control transistor T1. As shown in Figure 10, the second connection region 29 is also electrically connected to the sixth channel region 26 of the data write transistor T6 and forms the second electrode of the data write transistor T6.

[0097] The fourth channel region 24 of the first reset transistor T4 and the fifth channel region 25 of the compensation transistor T5 are connected via a third connection region 210. The third connection region 210 electrically connects the second electrode of the first reset transistor T4 and the second electrode of the compensation transistor T5. In other words, the third connection region 210 forms the second electrode of the first reset transistor T4 and the second electrode of the compensation transistor T5.

[0098] The second channel region 22 of the second emission control transistor T2 and the seventh channel region 27 of the second reset transistor T7 are connected via a fifth connection region 212. The fifth connection region 212 electrically connects the second electrode of the second emission control transistor T2 and the second electrode of the second reset transistor T7. In other words, the fifth connection region 212 forms the second electrode of the second emission control transistor T2 and the second reset transistor T7.

[0099] In some embodiments, referring again to Figures 10 and 11 , the compensation transistor T5 can be a dual-gate transistor. This helps reduce the leakage current of the compensation transistor T5 and thereby improves the ability to maintain the gate voltage of the driving transistor T3. The fifth channel region 25 includes a first sub-region 251 and a second sub-region 252 spaced apart. The fourth connection region 211 is located between the first sub-region 251 and the second sub-region 252 and is used to connect the first sub-region 251 and the second sub-region 252.

[0100] The semiconductor pattern 20 may further include a sixth connection region 213, a seventh connection region 214, an eighth connection region 215, and a ninth connection region 216. The sixth connection region 213 is located on a side of the seventh channel region 27 away from the fifth connection region 212 and is connected to the seventh channel region 27 to form a first electrode of the second reset transistor T7 and is configured to be electrically connected to a second initialization voltage signal line (not shown).

[0101] The seventh connection region 214 is located on a side of the first channel region 21 away from the second connection region 29 and is connected to the first channel region 21. The seventh connection region 214 is used to form the first electrode of the first light-emitting control transistor T1 and is electrically connected to the first voltage signal line (not shown). The eighth connection region 215 is located on a side of the fourth channel region 24 away from the third connection region 210 and is connected to the fourth channel region 24. The eighth connection region 215 is used to form the first electrode of the first reset transistor T4 and is electrically connected to the first initialization voltage signal line (not shown). The ninth connection region 216 is located on a side of the sixth channel region 26 away from the second connection region 29 and is connected to the sixth channel region 26. The ninth connection region 216 is used to form the first electrode of the data write transistor T6 and is electrically connected to the data line (not shown).

[0102] In some embodiments, referring again to FIG. 10 , the first reset transistor T4 may be a dual-gate transistor. This helps reduce leakage current in the first reset transistor T4 and thereby improves the gate voltage retention capability of the drive transistor T3. The fourth channel region 24 includes a third sub-region 241 and a fourth sub-region 242 spaced apart from each other. The semiconductor layer Poly also includes a tenth connection region 217, which is located between the third sub-region 241 and the fourth sub-region 242 and is used to connect the third sub-region 241 and the fourth sub-region 242.

[0103] 12 , the array substrate 100 further includes a light shielding layer BSM disposed between the substrate 11 and the pixel circuit 110 . The orthographic projection of the light shielding layer BSM on the substrate 11 at least partially overlaps with the orthographic projection of the pixel circuit 110 on the substrate.

[0104] Exemplarily, the light shielding layer BSM is disposed between the substrate 11 and the semiconductor layer Poly, and the orthographic projection of the light shielding layer BSM on the substrate 11 partially overlaps with the orthographic projection of the semiconductor layer Poly on the substrate 11. For example, as shown in FIG12 , the orthographic projections of the third channel region 23, the fourth channel region 24, and the fifth channel region 25 in the semiconductor pattern 20 on the substrate 11 are located within the range of the orthographic projection of the light shielding layer BSM on the substrate 11.

[0105] In some embodiments, referring to Figure 11, the first gate conductive layer Gate1 is arranged on a side of the semiconductor layer Poly away from the substrate 11, including a first gate pattern 31, a second light emitting control signal line EM2, a third gate pattern 33, a fourth gate pattern 34, a fifth gate pattern 35, a sixth gate pattern 36 and a seventh gate pattern 37.

[0106] Referring to both Figures 10 and 11 , the orthographic projection of the first gate pattern 31 on the substrate 11 partially overlaps with the orthographic projection of the first channel region 21 on the substrate 11. For example, the orthographic projection of the first gate pattern 31 on the substrate 11 covers the orthographic projection of the first channel region 21 on the substrate 11, thereby forming the gate of the first emission control transistor T1. Furthermore, the orthographic projection of the first gate pattern 31 on the substrate 11 does not overlap with the orthographic projection of the first connection region 28 on the substrate 11, thereby preventing the formation of a transistor between the first gate pattern 31 and the first connection region 28.

[0107] The orthographic projection of the second emission control signal line EM2 on the substrate 11 partially overlaps with the orthographic projection of the second channel region 22 on the substrate 11. Exemplarily, the second emission control signal line EM2 includes a second gate pattern 221. The orthographic projection of the second gate pattern 221 on the substrate 11 overlaps with the orthographic projection of the second channel region 22 on the substrate 11. The second gate pattern 221 is used to form the gate of the second emission control transistor T2. In other words, the second emission control signal line EM2 is used to transmit the second pulse width modulation signal and also to form the gate of the second emission control transistor T2.

[0108] Referring to Figures 10 and 11 simultaneously, the orthographic projection of the third gate pattern 33 on the substrate 11 overlaps the orthographic projection of the third channel region 23 on the substrate 11, forming the gate of the drive transistor T3. Of course, the third gate pattern 33 also forms one electrode plate of the capacitor Cst. The orthographic projection of the fourth gate pattern 34 on the substrate 11 partially overlaps with the orthographic projection of the fourth channel region 24 on the substrate 11, forming the gate of the first reset transistor T4. Exemplarily, the orthographic projection of the fourth gate pattern 34 on the substrate 11 overlaps the orthographic projection of the fourth channel region 24 on the substrate 11. The orthographic projection of the fifth gate pattern 35 on the substrate 11 overlaps with the orthographic projection of the fifth channel region 25 on the substrate 11, forming the gate of the compensation transistor T5. Exemplarily, the orthographic projection of the fifth gate pattern 35 on the substrate 11 overlaps the orthographic projection of the fifth channel region 25 on the substrate 11. The orthographic projection of the sixth gate pattern 36 on the substrate 11 partially overlaps with the orthographic projection of the sixth channel region 26 on the substrate 11, thereby forming the gate of the data write transistor T6. Exemplarily, the orthographic projection of the sixth gate pattern 36 on the substrate 11 covers the orthographic projection of the sixth channel region 26 on the substrate 11. The orthographic projection of the seventh gate pattern 37 on the substrate 11 partially overlaps with the orthographic projection of the seventh channel region 27 on the substrate 11, thereby forming the gate of the second reset transistor T7. Exemplarily, the orthographic projection of the seventh gate pattern 37 on the substrate 11 covers the orthographic projection of the seventh channel region 27 on the substrate 11.

[0109] Exemplarily, as shown in Figure 11, along the first direction Y, the first gate pattern 31, the second light-emitting control signal line EM2, the gate pattern 32, the third gate pattern 33, the fourth gate pattern 34, the fifth gate pattern 35, the sixth gate pattern 36 and the seventh gate pattern 37 included in the same pixel circuit 110 are staggered, so that the gate of the first light-emitting control transistor T1, the gate of the second light-emitting control transistor T2, the gate of the driving transistor T3, the gate of the first reset transistor T4, the gate of the compensation transistor T5, the gate of the data writing transistor T6 and the gate of the second reset transistor T7 can be connected to different signal lines respectively, which can improve the control accuracy of the pixel circuit 110, and the above-mentioned different signal lines are arranged along the first direction Y, reducing the risk of signal interference between adjacent signal lines.

[0110] In some embodiments, as shown in FIG13 , the second gate conductive layer Gate2 is disposed on a side of the first gate conductive layer Gate1 away from the substrate 11 and may include a first initialization voltage signal line Vinit1, a second initialization signal line Vinit2, a first shielding portion 41, a second shielding portion 42, and a capacitor electrode 43. The first shielding portion 41, the second shielding portion 42, and the capacitor electrode 43 are interconnected to form a whole.

[0111] 13 , the orthographic projection of the capacitor electrode 43 on the substrate 11 partially overlaps with the orthographic projection of the third gate pattern 33 on the substrate 11 , so as to form another electrode of the storage capacitor Cst.

[0112] Referring to Figure 14, the first source and drain conductive layer SD1 is arranged on the side of the second gate conductive layer Gate2 away from the substrate 11, and includes a first light-emitting control signal line EM1, a first enable signal line Scan1, a second enable signal line Scan2, a first scan signal line GL1, a second scan signal line GL2, a first voltage signal line VDD, a first transfer block 51, a second transfer block 52, a third transfer block 53, a fourth transfer block 54 and a fifth transfer block 55.

[0113] Referring to Figures 13 and 14 simultaneously, the orthographic projection of the first light-emitting control signal line EM1 on the substrate 11 partially overlaps with the orthographic projection of the first gate pattern 31 on the substrate 11, and the first light-emitting control signal line EM1 is electrically connected to the first gate pattern 31. During the fabrication of the array substrate 100, the semiconductor layer Poly is doped using the first gate conductive layer Gate1 as a mask layer. The first light-emitting control signal line EM1 and the first gate pattern 31 are located in different conductive layers 12. Positioning the first light-emitting control signal line EM1 in the first source-drain conductive layer SD1 prevents the first light-emitting control signal line EM1 from obstructing the semiconductor layer Poly during the doping process. Furthermore, this helps increase the spacing between the first light-emitting control signal line EM1 and the semiconductor pattern 20, reducing parasitic capacitance formed between the first light-emitting control signal line EM1 and the semiconductor pattern 20, thereby reducing the impact of the signal transmitted by the first light-emitting control signal line EM1 on the semiconductor pattern 20.

[0114] The orthographic projection of the first enable signal line Scan1 on the substrate 11 partially overlaps with the orthographic projection of the fourth gate pattern 34 on the substrate 11, and the first enable signal line Scan1 is electrically connected to the fourth gate pattern 34. The orthographic projection of the first enable signal line Scan1 on the substrate 11 also partially overlaps with the orthographic projection of the semiconductor layer Poly on the substrate 11. The first enable signal line Scan1 and the fourth gate pattern 34 are disposed on different conductive layers 12, and the first enable signal line Scan1 is disposed in the first source-drain conductive layer SD1. This prevents the first enable signal line Scan1 from obstructing the semiconductor layer Poly during the doping process of the semiconductor layer Poly. Furthermore, this helps increase the spacing between the first enable signal line Scan1 and the semiconductor pattern 20, reducing the parasitic capacitance formed between the first enable signal line Scan1 and the semiconductor pattern 20, thereby reducing the impact of the signal transmitted by the first enable signal line Scan1 on the semiconductor pattern 20.

[0115] The orthographic projection of the second enable signal line Scan2 on the substrate 11 partially overlaps with the orthographic projection of the fifth gate pattern 35 on the substrate 11, and the second enable signal line Scan2 is electrically connected to the fifth gate pattern 35. The orthographic projection of the first scan signal line GL1 on the substrate 11 partially overlaps with the orthographic projection of the sixth gate pattern 36 on the substrate 11, and the first scan signal line GL1 is electrically connected to the sixth gate pattern 36. The orthographic projection of the second scan signal line GL2 on the substrate 11 partially overlaps with the orthographic projection of the seventh gate pattern 37 on the substrate 11, and the second scan signal line GL2 is electrically connected to the seventh gate pattern 37. For similar reasons to the first emission control signal line EM1 and the first enable signal line Scan1, disposing the second enable signal line Scan2, the first scan signal line GL1, and the second scan signal line GL2 in the first source-drain conductive layer SD1 can prevent the second enable signal line Scan2, the first scan signal line GL1, and the second scan signal line GL2 from obstructing the semiconductor layer Poly during the doping process of the semiconductor layer Poly. Moreover, it is beneficial to reduce the parasitic capacitance formed between the second enable signal line Scan2, the first scan signal line GL1 and the second scan signal line GL2 and the semiconductor pattern 20 respectively, thereby reducing the impact of the signals transmitted by the second enable signal line Scan2, the first scan signal line GL1 and the second scan signal line GL2 on the semiconductor pattern 20.

[0116] The orthographic projection of the first adapter block 51 on the substrate 11 overlaps with the orthographic projections of the third connection area 210 and the third gate pattern 33 on the substrate 11, respectively, and the two ends of the first adapter block 51 are electrically connected to the third connection area 210 and the third gate pattern 33, respectively, so that the second electrode of the first reset transistor T4 and the second electrode of the compensation transistor T5 are electrically connected to the gate of the driving transistor T3.

[0117] 13 and 14 at the same time, the orthographic projection of the second adapter block 52 on the substrate 11 overlaps with the orthographic projections of the first initialization voltage signal line Vinit1 and the eighth connection area (the first electrode of the first reset transistor T4) on the substrate 11, and the second adapter block 52 is electrically connected to the first initialization voltage signal line Vinit1 and the eighth connection area, respectively, so that the first initialization voltage signal line Vinit1 is electrically connected to the first electrode of the first reset transistor T4.

[0118] The orthographic projection of the third adapter block 53 on the substrate 11 overlaps with the orthographic projection of the second initialization voltage signal line Vinit1 and the sixth connection area (the first electrode of the second reset transistor T7) on the substrate 11, and the third adapter block 53 is electrically connected to the second initialization voltage signal line Vinit2 and the sixth connection area, so that the second initialization voltage signal line Vinit2 is electrically connected to the first electrode of the second reset transistor T7.

[0119] The orthographic projection of the fourth adapter block 54 on the substrate 11 partially overlaps with the orthographic projection of the fifth connection area on the substrate 11, and the fourth adapter block 54 is electrically connected to the fifth connection area 212, so that the fourth adapter block 54 is electrically connected to the second electrode of the second light-emitting control transistor T2 and the second electrode of the second reset transistor T7. The fourth adapter block 54 is also used to be electrically connected to the light-emitting device.

[0120] The orthographic projection of the fifth adapter block 55 on the substrate 11 partially overlaps with the orthographic projection of the ninth connection area 216 on the substrate 11. The fifth adapter block 55 is electrically connected to the ninth connection area 216. The fifth adapter block 55 is also electrically connected to the first electrode of the data write transistor T6. The fifth adapter block 55 is also used to electrically connect to the data line.

[0121] 13 and 14 , the orthographic projection of the first shielding portion 41 on the substrate 11 at least partially overlaps with the orthographic projection of the fourth connection region 211 on the substrate 11. Exemplarily, the orthographic projection of the first shielding portion 41 on the substrate 11 covers the orthographic projection of the fourth connection region 211 on the substrate 11. The first shielding portion 41 is used to shield the upper layer signal line (the signal line on the side of the second gate conductive layer Gate2 away from the substrate 11) from signal interference with the fourth connection region 211.

[0122] The orthographic projection of the second shielding portion 42 on the substrate 11 partially overlaps with the orthographic projection of the third connection area 210 on the substrate 11. Exemplarily, the orthographic projection of the second shielding portion 42 on the substrate 11 covers the orthographic projection of the third connection area 210 on the substrate 11. The orthographic projection of the second shielding portion 42 on the substrate 11 also partially overlaps with the orthographic projections of the first scan signal line GL1 and the second enable signal line Scan2 on the substrate 11. The second shielding portion 42 can reduce signal interference from the first scan signal line GL1 and the second enable signal line Scan2 on the third connection area 210. In some embodiments, referring to Figures 15, 16A, and 16B, the array substrate 100 further includes a second source-drain conductive layer SD2. The second source-drain conductive layer SD2 is disposed on a side of the first source-drain conductive layer SD1 away from the substrate 11 and includes a plurality of data lines DL extending along the first direction Y, a plurality of first voltage signal connection lines VDD', a plurality of first connection lines 61, a plurality of second connection lines 62, and a plurality of third connection lines 63. Figure 16A is a simplified view of the array substrate, illustrating more clearly the connections between the plurality of first connection lines 61, the plurality of second connection lines 62, and the plurality of third connection lines 63, and the first initialization voltage signal line Vinit1, the plurality of second initialization voltage signal lines Vinit2, and the second voltage signal bus VSS. Figure 16B is a structural diagram of a row of nine adjacent pixel circuits within the array substrate.

[0123] Each of the plurality of data lines DL is electrically connected to a column of pixel circuits 110. Each of the plurality of first voltage signal connection lines VDD' is electrically connected to the plurality of first voltage signal lines VDD on the first source-drain conductive layer SD1, thereby connecting the plurality of first voltage signal lines VDD into a mesh structure, thereby reducing the resistance of the plurality of first voltage signal lines VDD. For example, as shown in FIG15 , the plurality of data lines DL and the plurality of first voltage signal connection lines VDD' are alternately arranged along the second direction X.

[0124] As shown in Figures 16A and 16B, multiple columns of pixel circuits 110 can be divided into multiple groups, each group including multiple columns of pixel circuits 110. The multiple pixel circuits 110 located in the same row in a group correspond to the multiple sub-pixels of a pixel unit. For example, if a pixel unit includes a red sub-pixel, a blue sub-pixel, and a green sub-pixel, a group includes three columns of pixel circuits 110. The three pixel circuits located in the same row in a group correspond to the red sub-pixel, the blue sub-pixel, and the green sub-pixel of the pixel unit, respectively.

[0125] The first connection lines 61, the second connection lines 62, and the third connection lines 63 are respectively arranged between two adjacent groups of pixel circuits 110, and only one of the first connection lines 61, the second connection lines 62, and the third connection lines 63 is arranged between each two adjacent groups of pixel circuits 110. In the embodiment of the present disclosure, the arrangement order and arrangement density of the first connection lines 61, the second connection lines 62, and the third connection lines 63 are not specifically limited. For example, the first connection lines 61, the second connection lines 62, and the third connection lines 63 are periodically arranged along the second direction.

[0126] Each first connection line 61 is electrically connected to a plurality of first initialization voltage signal lines Vinit1, and is used to connect the plurality of first initialization voltage signal lines Vinit1 into a mesh structure to reduce the resistance of the plurality of first initialization voltage signal lines Vinit1. Each second connection line 62 is electrically connected to a plurality of second initialization voltage signal lines Vinit2, and is used to connect the plurality of second initialization voltage signal lines Vinit2 into a mesh structure to reduce the resistance of the plurality of second initialization voltage signal lines Vinit2.

[0127] The peripheral area BB also includes a second voltage signal bus VSS, which is used to electrically connect to the cathode layer. Both ends of each third connection line 63 extend to the peripheral area BB and are electrically connected to the second voltage signal bus VSS. The third connection line 63 is connected in parallel with the cathode layer, which is beneficial to reducing the resistance on the cathode layer.

[0128] Exemplarily, as shown in FIG15 , the plurality of second adapter blocks 52 include a second target adapter block 52A, the orthographic projection of the second target adapter block 52A on the substrate partially overlaps with the orthographic projection of the first connection line 61 on the substrate, and the second target adapter block 52A is electrically connected to the first connection line 61. As described above, the second adapter block 52 is also electrically connected to the first initialization voltage signal line Vinit1 and the first electrode (eighth connection area) of the first reset transistor. Based on this, the second target adapter block 52A can electrically connect the first connection line 61 to the first initialization voltage signal line Vinit1, so that the first connection line 61 and the first initialization voltage signal line Vinit1 are connected to form a mesh structure. It is understandable that the specific structure of the pixel circuit 110 can also adopt other pixel circuits. Exemplarily, as shown in FIG17 , the pixel circuit 110 can also include a reset transistor T8, the gate of the reset transistor T8 is electrically connected to the second scanning signal line GL2, the first electrode is electrically connected to the reference voltage signal line Vref, and the second electrode is electrically connected to the first electrode of the driving transistor T3. Alternatively, as shown in Figure 18, the second electrode of the compensation transistor T5 may also be electrically connected to the second electrode of the driving transistor T3. The embodiments of the present disclosure do not limit the specific structure of the pixel circuit 110, as long as the same technical concept is applied.

[0129] In some embodiments, the second source-drain conductive layer SD2 further includes a plurality of seventh adapter blocks 64, which are used to connect the pixel circuit 110 and the light-emitting device 200. As shown in FIG15 , the shapes of the plurality of seventh adapter blocks 64 can be different to connect light-emitting devices 200 at different locations. The orthographic projection of the seventh adapter block 64 on the substrate 11 partially overlaps with the orthographic projection of the fourth adapter block 54 on the substrate 11, and the seventh adapter block 64 is electrically connected to the fourth adapter block 54, and further electrically connected to the drain of the second light-emission control transistor T2 of the pixel circuit. The seventh adapter block 64 is also used to electrically connect to the anode of the light-emitting device, thereby electrically connecting the light-emitting device to the pixel circuit.

[0130] Referring to FIG19 , some embodiments of the present disclosure further provide a method for driving a pixel circuit 110, which can be used to drive the pixel circuit 110 described in any of the above embodiments. In the following embodiments of the present disclosure, the pixel circuit 110 is described as the pixel circuit 110 shown in FIG9 , but the method can also be applied to other pixel circuits (such as the pixel circuits shown in FIG17 and FIG18 ) as long as the same technical concepts are applied.

[0131] The first light emitting control signal line EM1 is configured to transmit a first pulse width modulation signal PWM1 , and the second light emitting control signal line EM2 is configured to transmit a second pulse width modulation signal PWM2 .

[0132] One display cycle includes a blank phase B and a light-emitting phase D. As shown in FIG19 , the driving method includes:

[0133] In the light-emitting phase D, the first pulse-width modulation signal PWM1 has a first operating level period K1, and the second pulse-width modulation signal PWM2 has a second operating level period K2. The first operating level period K1 refers to the period of the first pulse-width modulation signal PWM1 used to drive the first light-emitting control transistor T1 to conduct, and the second operating level period K2 refers to the period of the second pulse-width modulation signal PWM2 used to drive the second light-emitting control transistor T2 to conduct.

[0134] The first working level period K1 is different from the second working level period K2. For example, the start time (start-up time) of the first working level period K1 is different from the start time of the second working level period K2, and / or the end time (end time) of the first working level period K1 is different from the end time of the second working level period K2. In this way, the control flexibility of the first light-emitting control transistor T1 and the second light-emitting control transistor T2 can be increased, which is beneficial to improving the PWM dimming accuracy of the pixel circuit 110.

[0135] The first operating level period K1 partially overlaps with the second operating level period K2. When the first operating level period K1 overlaps with the second operating level period K2, the first light-emission control transistor T1 and the second light-emission control transistor T2 are simultaneously turned on, and the drive current generated by the drive transistor T3 can be transmitted to the light-emitting device 200, driving the light-emitting device to emit light. In the embodiments of the present disclosure, the start and end times of the first operating level period K1 and the second operating level period K2 can be controlled to control the length of time the first operating level period K1 and the second operating level period K2 overlap, thereby improving the dimming accuracy of the pixel circuit 110.

[0136] In some embodiments, the portion where the first operating level period K1 and the second operating level period K2 overlap is a light-emitting period K3. The first operating level period K1 is longer than the light-emitting period K3, and the second operating level period K2 is longer than the light-emitting period K3. This shortens the minimum light-emitting duration of each light-emitting stage in PWM dimming, thereby reducing the total light-emitting duration of the light-emitting device within a display cycle, thereby improving the dimming accuracy of the pixel circuit 110.

[0137] In some embodiments, referring to FIG. 19 , the amplitude (high and low voltage values), frequency, and duty cycle of the first pulse-width modulation signal PWM1 are respectively the same as the amplitude, frequency, and duty cycle of the second pulse-width modulation signal PWM2. This helps reduce the difficulty of controlling the first pulse-width modulation signal PWM1 and the second pulse-width modulation signal PWM2.

[0138] The array substrate further includes a shift register located in the peripheral area BB. The shift register includes multiple cascaded shift register circuits. The first light emitting control signal line EM1 and the second light emitting control signal line EM2 can be electrically connected to the same shift register or to different shift registers.

[0139] Exemplarily, when the amplitude, frequency and duty cycle of the first pulse width modulation signal PWM1 are different from at least one of the amplitude, frequency and duty cycle of the second pulse width modulation signal PWM2, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are electrically connected to two different shift registers respectively.

[0140] For example, when the amplitude, frequency and duty cycle of the first pulse width modulation signal PWM1 are respectively the same as the amplitude, frequency and duty cycle of the second pulse width modulation signal PWM2, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 can be electrically connected to the same shift register or to different shift registers.

[0141] As shown in FIG20 , in an embodiment of the present disclosure, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are electrically connected to the same shift register. This facilitates simplifying the circuit structure of the array substrate 100, reducing the width of the peripheral area BB, and thereby achieving a narrow bezel of the display panel 1100. When the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are electrically connected to the same shift register (EM-GOA), the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 electrically connected to the same row of pixel circuits 110 are electrically connected to different stages of shift register circuits.

[0142] Exemplarily, each row of pixel circuits 110 is electrically connected to a first reflection control signal line EM1 and a second reflection control signal line EM2. The array substrate 100 includes a first shift register 400, which includes a plurality of first shift register circuits EM-GOA cascaded in sequence.

[0143] When the start and end times of the first working level period K1 are respectively delayed (latter) than the start and end times of the second working level period K2, as shown in FIG20 , the first light emission control signal line EM1 electrically connected to the pixel circuit 110 in the Nth row is electrically connected to the first shift register circuit EM-GOA-N in the Nth stage. The second light emission control signal line EM2 electrically connected to the pixel circuit in the Nth row is electrically connected to the first shift register circuit EM-GOA-(N+M) in the (N+M)th stage.

[0144] Alternatively, when the start and end times of the first working level period K1 are respectively earlier than (latter than) the start and end times of the second working level period K2, the second light emission control signal line EM2 electrically connected to the pixel circuits in the Nth row is electrically connected to the first shift register circuit EM-GOA-N of the Nth stage. The first light emission control signal line EM1 electrically connected to the pixel circuits in the Nth row is electrically connected to the first shift register circuit EM-GOA-(N+M) of the (N+M)th stage (not shown in the figure).

[0145] Among them, the amplitude, frequency and duty cycle of the PWM signals output by the N-th level first shift register circuit EM-GOA-N and the (N+M)-th level first shift register circuit EM-GOA-(N+M) are correspondingly equal, and the start and end times differ by MH (M-line scanning time).

[0146] In some embodiments, M≤4. For example, M can be 1, 2, 3, or 4. This, on the one hand, helps reduce the number of first shift register circuits EM-GOA and reduces the space occupied by the first shift register 400 in the peripheral area BB. On the other hand, it can reduce the spacing between the second light-emitting control signal line EM2 and the (N+M)-th stage first shift register circuit EM-GOA-(N+M) along the first direction Y, which helps reduce the difficulty of connecting the second light-emitting control signal line EM2 and the (N+M)-th stage first shift register circuit EM-GOA-(N+M). It will be understood that the value of M in the embodiments of the present disclosure is not limited to this, and any other reasonable value may also be considered, as long as the same technical concept is applied and the driving timing requirements of the pixel circuit are met.

[0147] In some embodiments, the first enable signal line Scan1 and the second enable signal line Scan2 may be electrically connected to the same shift register, or to different shift registers.

[0148] Illustratively, the first enable signal line Scan1 and the second enable signal line Scan2 are electrically connected to different shift registers, so that the timing of the first enable signal line Scan1 and the second enable signal line Scan2 can be better adjusted, which is conducive to improving the control accuracy of the pixel circuit.

[0149] For example, as shown in FIG21 , the first enable signal line Scan1 and the second enable signal line Scan2 are electrically connected to the same shift register. This simplifies the circuit structure of the array substrate, reduces the width of the peripheral area BB, and thereby achieves a narrow bezel on the display panel. When the first enable signal line Scan1 and the second enable signal line Scan2 are electrically connected to the same shift register, the first enable signal line Scan1 and the second enable signal line Scan2 electrically connected to the same row of pixel circuits 110 are electrically connected to different stages of shift register circuits.

[0150] As shown in FIG. 21 , in an embodiment of the present disclosure, description is given by taking an example in which the first enable signal line Scan1 and the second enable signal line Scan2 are electrically connected to the same shift register.

[0151] For example, each row of pixel circuits 110 is connected to a first enable signal line Scan1 and a second enable signal line Scan2. The array substrate 100 includes a second shift register 500, which includes a plurality of second shift register circuits Scan-GOA that are cascaded in sequence.

[0152] As shown in FIG21 , the first enable signal line Scan1 electrically connected to the pixel circuit 110 in the Nth row is electrically connected to the second shift register circuit Scan-GOA-(N-2) in the (NQ)th stage. The second enable signal line Scan2 electrically connected to the pixel circuit 110 in the Nth row is electrically connected to the second shift register circuit Scan-GOA-N in the Nth stage.

[0153] Alternatively, the first enable signal line Scan1 electrically connected to the pixel circuit in the Nth row is electrically connected to the second shift register circuit Scan-GOA-N in the Nth stage. The second enable signal line Scan2 electrically connected to the pixel circuit 110 in the Nth row is electrically connected to the second shift register circuit Scan-GOA-(N+Q) in the (N+Q)th stage.

[0154] The waveforms of the enable signals output by the Nth-stage second shift register circuit Scan-GOA-N and the (N+Q)th-stage second shift register circuit Scan-GOA-(N+Q) are the same, and have a certain phase difference.

[0155] In some embodiments, 3≤Q≤9. For example, Q can be 3, 4, 5, 6, 7, 8 or 9. On the one hand, it is beneficial to reduce the number of the second shift register circuit Scan-GOA and reduce the space of the peripheral area BB occupied by the second shift register 500. On the other hand, the interval between the second enable signal line Scan2 and the (N+Q)-th level second shift register circuit Scan-GOA-(N+Q) along the first direction Y can be reduced, which is beneficial to reducing the connection difficulty between the second enable signal line Scan2 and the (N+Q)-th level second shift register circuit Scan-GOA-(N+Q). It can be understood that the value of Q in the embodiments of the present disclosure is not limited to this, and any other reasonable value can also be considered, as long as the same technical ideas are applied and the driving timing requirements of the pixel circuit are met.

[0156] In some embodiments, referring to FIG. 22 , in the blank phase B, at least one of the first light emission control transistor T1 and the second light emission control transistor T2 is turned off (not conducting), and the light emitting device 200 does not emit light.

[0157] For example, the start and end time of the first working level period K1 are delayed (latter) than the start and end time of the second working level period K2. The blank phase B includes a first sub-segment B11, a second sub-segment B12 and a third sub-segment B13.

[0158] In the first sub-segment B11, the first pulse-width modulation signal PWM1 transmitted by the first emission control signal line EM1 is at an operating level (low level), and the second pulse-width modulation signal PWM1 transmitted by the second emission control signal line EM2 is at an off level (high level). At this time, the first emission control transistor T1 is turned on, and the second emission control transistor T2 is turned off. In the second sub-segment B12, the first pulse-width modulation signal PWM1 transmitted by the first emission control signal line EM1 and the second pulse-width modulation signal PWM2 transmitted by the second emission control signal line EM2 are both at an off level, and both the first emission control transistor T1 and the second emission control transistor T2 are turned off. In the third sub-segment B13, the first pulse-width modulation signal PWM1 transmitted by the first emission control signal line EM1 is at an off level, and the second pulse-width modulation signal is at an operating level. At this time, the first emission control transistor T1 is turned off, and the second emission control transistor T2 is turned on.

[0159] In some embodiments, as shown in FIG21 , the blank phase B includes a first initialization phase B21 , a second initialization phase B22 and a data writing phase B23 . The driving method further includes:

[0160] During the first initialization phase B21, the first emission control transistor T1 is turned on for at least part of the time period, the second emission control transistor T2 is turned off, and the first reset transistor T4 is turned on under the control of the first enable signal from the first enable signal line Scan1, transmitting the first initialization voltage signal from the first initialization voltage signal line Vinit1 to the gate of the drive transistor T3 to initialize the voltage at the gate of the drive transistor T3.

[0161] In the second initialization stage B22, the first reset transistor T4 remains turned on, and the compensation transistor T5 is turned on under the control of the second enable signal from the second enable signal line Scan2, and the first initialization voltage signal from the gate of the driving transistor T3 is transmitted to the second electrode of the driving transistor T3 to perform voltage initialization on the second electrode of the driving transistor T3.

[0162] In the data writing phase B23, the first reset transistor T4 is turned off, the compensation transistor T5 remains on, and the data writing transistor T5 is turned on under the control of the first scanning signal from the first scanning signal line GL1, and the data signal from the data line DL is transmitted to the first electrode of the driving transistor T3. The data signal is sequentially transmitted through the driving transistor T3 and the compensation transistor T5 to transmit the compensated data signal (Vdata+Vth) to the gate of the driving transistor T3.

[0163] The first initialization phase B21 is partially located in the first sub-segment B11 and partially located in the second sub-segment B12. The second initialization phase B22 is located in the second sub-segment B12 to prevent the first initialization voltage signal from being transmitted to the anode of the light-emitting device 200, thereby preventing signal interference with the anode of the light-emitting device 200. The data writing phase B23 is located within the second sub-segment B12. That is, during the data writing phase B23, the first and second light-emitting control transistors T1 and T2 remain off, thereby preventing interference between the first voltage signal line VDD and the light-emitting device 200 and the written data signal.

[0164] During the first initialization phase B21, the gate of the driving transistor T3 is initialized to the Vinit1 voltage, and the first light-emission control transistor T1 is turned on for at least part of the time. The first electrode of the driving transistor T3 is at the VDD voltage, and a large voltage difference (Vinit1-VDD) is formed between the gate and source of the driving transistor T3. This voltage difference (Vinit1-VDD) is greater than the voltage difference between the gate and source of the driving transistor T3 during the light-emission phase D of the previous display cycle. Thus, during the first initialization phase B21 of each frame, the bias state of the driving transistor T3 is the same, namely (Vinit1-VDD).

[0165] In the second initialization phase B22, the first emission control transistor T1 and the second emission control transistor T2 are simultaneously turned off, and the first reset transistor T4 and the compensation transistor T5 are turned on. The voltage of the first initialization signal line Vinit1 is transmitted to the gate and second electrode (drain) of the driving transistor T3. At this time, the first electrode of the driving transistor T3 has a higher voltage (the first voltage VDD maintained during the first initialization phase B21), and the first electrode of the driving transistor T3 acts as a source to leak power to the second electrode of the driving transistor T3, ultimately maintaining Vinit1-Vth. In each display cycle, and before the data writing phase B23, the voltages of the gate, first electrode, and second electrode of the driving transistor T3 are independent of the voltages of the previous display cycle. This can avoid the problem of brightness difference when switching grayscale, thereby improving the problem of afterimage on the display panel. In addition, by increasing the duration of the first initialization phase B21 and the second initialization phase B22, the first initialization voltage Vinit1 can be more fully written into the gate of the driving transistor T3 and the second electrode of the driving transistor T3, and the first electrode voltage of the driving transistor T3 can be fully changed to Vinit1-Vth, thereby enhancing the effect of improving the afterimage.

[0166] It should be noted that when the driving transistor T3 is in a grayscale A screen for a long time, the Vgs voltage of the driving transistor T3 is in a grayscale A gate voltage -VDD for a long time. When the driving transistor T3 is in a grayscale C screen for a long time, the Vgs voltage of the driving transistor T3 is in a grayscale C gate voltage -VDD for a long time. The degree of characteristic offset of the driving transistor at the above-mentioned A and C grayscales is different. When switching from grayscale A and C to grayscale B respectively, the driving transistor T3 is re-offset by the new Vgs voltage. During this process, the brightness of grayscale B gradually changes and tends to be stable. The industry usually uses the brightness contrast of the two switching screens, grayscale A to grayscale B and grayscale C to grayscale B, to characterize the image quality, which is the afterimage referred to above.

[0167] In some embodiments, as shown in Figure 22, in the second initialization stage B22 and the data writing stage B23, the second reset transistor T7 is turned on under the control of the second scan signal from the second scan signal line GL2, and the second initialization voltage signal from the second initialization voltage signal line Vinit2 is transmitted to the second electrode of the second light-emitting control transistor T2, that is, the second initialization voltage signal is transmitted to the anode of the light-emitting device 200 to initialize the anode of the light-emitting device.

[0168] In some embodiments, as shown in FIG. 23 and FIG. 24 , the blank phase B may further include a bias phase B24 located after the data writing phase B23 .

[0169] During bias phase B24, the first emission control signal line EM1 transmits an off-level signal, turning off the first emission control transistor T1. The second emission control signal line EM2 transmits an operating-level signal, turning on the second emission control transistor T2. Controlled by the second scan signal of the second scan signal line GL2, the second reset transistor T7 is turned on, transmitting the second initialization voltage signal from the second initialization voltage signal terminal Vinit2 to the second electrode of the second emission control transistor T2 and the first electrode of the second emission control transistor T2 (the second electrode of the drive transistor).

[0170] During bias phase B24, the first light-emission control transistor T1, the first reset transistor T4, the compensation transistor T5, and the data-writing transistor T6 are turned off, while the second reset transistor T7 and the second light-emission control transistor T2 are turned on simultaneously. The voltage of the second initialization voltage signal line Vinit2 resets the voltage at the anode of the light-emitting device and the second electrode of the driving transistor T3. The voltage at the second electrode of the driving transistor T3 is unaffected by the previously written data signal. If the light-emission phase D includes multiple operating level periods (or if the PWM signal uses multi-pulse dimming), the voltage at the second electrode of the driving transistor T3 remains the same before each first light-emission control transistor T1 is turned on and is unaffected by the written data signal, thus preventing flickering in the light-emitting device.

[0171] It should be noted that in the data writing stage B23, the second pole of the driving transistor T3 will write the compensated data signal, and the compensated data signal of each display cycle may be different. In this way, if the voltage of the second pole of the driving transistor T3 is not reset, and the residual voltage of the second pole of the driving transistor T3 will affect the magnitude of the driving current in the light-emitting stage D, and the residual voltage of the second pole of the driving transistor T3 in each display cycle may have different effects on the driving current, therefore, it may cause visual stroboscopic, which is the flicker mentioned above. The driving method of the pixel circuit provided in the present application resets the voltage of the second pole of the driving transistor T3 through the bias stage B24, thereby reducing or even avoiding the voltage residue of the driving transistor T3, thereby reducing the risk of flickering in the light-emitting device.

[0172] In other embodiments, driving methods for pixel driving circuits are also provided. For example, referring to FIG. 25 , the first operating level period K1 may be within the second operating level period K2, and the start and end times of the first operating level period K1 are spaced apart from the start and end times of the second operating level period K2. Alternatively, referring to FIG. 26 , the second operating level period K2 is within the first operating level period K1, and the start and end times of the first operating level period K1 are spaced apart from the start and end times of the second operating level period K2. Alternatively, referring to FIG. 27 , the amplitude, frequency, and duty cycle of the first pulse-width modulation signal PWM1 are the same as the amplitude, frequency, and duty cycle of the second pulse-width modulation signal PWM2, respectively. Furthermore, the start and end times of the first operating level period K1 are respectively ahead of the start and end times of the second operating level period K2. The embodiments of the present disclosure will not be further described in detail.

[0173] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising a substrate and a plurality of pixel circuits disposed on the substrate, wherein the plurality of pixel circuits are arranged in a plurality of rows and columns; The pixel circuit includes a first light emission control transistor and a second light emission control transistor; The array substrate further includes: a first light emission control signal line, electrically connected to the gate of the first light emission control transistor; a second light emission control signal line electrically connected to the gate of the second light emission control transistor; The array substrate also includes multiple conductive layers, the first light-emitting control signal line and the second light-emitting control signal line are electrically insulated, the first light-emitting control signal line and the second light-emitting control signal line are located in different conductive layers, and the orthographic projections of the first light-emitting control signal line and the second light-emitting control signal line on the substrate do not overlap.

2. The array substrate according to claim 1, wherein: The plurality of conductive layers include: A first gate conductive layer, comprising a first gate pattern and the second light emission control signal line; the first gate pattern forms a gate of the first light emission control transistor; A first source-drain conductive layer is arranged on a side of the first gate conductive layer away from the substrate, and includes the first light-emitting control signal line. The orthographic projection of the first light-emitting control signal line on the substrate partially overlaps with the orthographic projection of the first gate pattern on the substrate, and the first light-emitting control signal line is electrically connected to the first gate pattern.

3. The array substrate according to claim 2, wherein: The pixel circuit also includes a driving transistor; The array substrate further includes a semiconductor layer, which is disposed between the substrate and the first gate conductive layer; the semiconductor layer includes a first channel region of the first light emission control transistor, a second channel region of the second light emission control transistor, a third channel region of the driving transistor, a first connection region and a second connection region; the first connection region and the second connection region are respectively located on two opposite sides of the third channel region, and the first connection region is respectively connected to the third channel region and the second channel region, and the second connection region is respectively connected to the third channel region and the first channel region; Among them, the orthographic projection of the first gate pattern on the substrate partially overlaps with the orthographic projection of the first channel region on the substrate, and does not overlap with the orthographic projection of the first connection region on the substrate; the orthographic projection of the second light-emitting control signal line on the substrate partially overlaps with the orthographic projection of the second channel region on the substrate.

4. The array substrate according to claim 3, wherein: The pixel circuit further includes a first reset transistor; The semiconductor layer further includes a third connection region and a fourth channel region of the first reset transistor; The first gate conductive layer further includes a fourth gate pattern, and an orthographic projection of the fourth gate pattern on the substrate partially overlaps with an orthographic projection of the fourth channel region on the substrate; The first source-drain conductive layer further includes a first enable signal line and a first transfer block; The orthographic projection of the first enable signal line on the substrate overlaps with the orthographic projection of the fourth gate pattern on the substrate, and the first enable signal line is electrically connected to the fourth gate pattern; the first adapter block is connected to the third connection area and the drive crystal The grid of the tube is electrically connected; The array substrate further includes a second gate conductive layer, which is disposed between the first gate conductive layer and the first source-drain conductive layer and includes a first initialization voltage signal line, which is electrically connected to a first electrode of the first reset transistor.

5. The array substrate according to claim 4, wherein: The pixel circuit further includes a compensation transistor; The semiconductor layer further includes a fifth channel region of the compensation transistor, one side of the fifth channel region is connected to the first connection region, and the other side of the fifth channel region is connected to the third connection region; The first gate conductive layer further includes a fifth gate pattern, and an orthographic projection of the fifth gate pattern on the substrate partially overlaps with an orthographic projection of the fifth channel region on the substrate; The first source-drain conductive layer further includes a second enable signal line, an orthographic projection of the second enable signal line on the substrate partially overlaps with an orthographic projection of the fifth gate pattern on the substrate, and the second enable signal line is electrically connected to the fifth gate pattern.

6. The array substrate according to claim 5, wherein: The compensation transistor is a dual-gate transistor, and the fifth channel region includes a first sub-region and a second sub-region which are spaced apart from each other; The semiconductor layer further includes a fourth connection region, wherein the fourth connection region is located between the first sub-region and the second sub-region and is connected to the first sub-region and the second sub-region; The second gate conductive layer further includes a first blocking portion, and an orthographic projection of the first blocking portion on the substrate at least partially overlaps with an orthographic projection of the fourth connection region on the substrate.

7. The array substrate according to any one of claims 4 to 6, wherein: The second gate conductive layer further includes a second shielding portion, and the orthographic projections of the second shielding portion, the third connection region, and the second enable signal line on the substrate at least partially overlap.

8. The array substrate according to any one of claims 4 to 7, wherein: The pixel circuit also includes a data writing transistor; The semiconductor layer further includes a sixth channel region of the data writing transistor, and along a first direction, the fifth channel region and the sixth channel region are staggered, and the sixth channel region is connected to the second connection region; the first direction is a column direction in which the plurality of pixel circuits are arranged; The first gate conductive layer further includes a sixth gate pattern, and an orthographic projection of the sixth gate pattern on the substrate partially overlaps with an orthographic projection of the sixth channel region on the substrate; The first source-drain conductive layer further includes a first scan signal line, an orthographic projection of the first scan signal line on the substrate partially overlaps with an orthographic projection of the sixth gate pattern on the substrate, and the first scan signal line is electrically connected to the sixth gate pattern.

9. The array substrate according to any one of claims 3 to 8, wherein: The pixel circuit further includes a second reset transistor; The semiconductor layer further includes a seventh channel region of the second reset transistor; The first gate conductive layer further includes a seventh gate pattern, and an orthographic projection of the seventh gate pattern on the substrate partially overlaps with an orthographic projection of the seventh channel region on the substrate; The second gate conductive layer further comprises a second initialization voltage signal line, and the second initialization voltage signal line is electrically connected to the first electrode of the second reset transistor; The first source-drain conductive layer further includes a second scan signal line, an orthographic projection of the second scan signal line on the substrate partially overlaps with an orthographic projection of the seventh gate pattern on the substrate, and the second scan signal line is electrically connected to the seventh gate pattern.

10. The array substrate according to any one of claims 3 to 9, further comprising: A light shielding layer is disposed between the substrate and the semiconductor layer, and an orthographic projection of the light shielding layer on the substrate at least partially overlaps with an orthographic projection of the semiconductor layer on the substrate.

11. The array substrate according to any one of claims 1 to 10, wherein: The array substrate comprises a display area and a peripheral area surrounding the display area; The array substrate comprises a plurality of first initialization voltage signal lines, a plurality of second initialization voltage signal lines and a second voltage signal bus; a row of pixel circuits is electrically connected to a first initialization voltage signal line and a second initialization voltage signal line, and the second voltage signal bus is arranged in the peripheral area and at least partially surrounds the display area; The array substrate also includes a second source-drain conductive layer, which is arranged on a side of the first source-drain conductive layer away from the substrate, and includes a plurality of first connecting lines, a plurality of second connecting lines and a plurality of third connecting lines extending along a first direction; each first connecting line is electrically connected to the plurality of first initialization voltage signal lines, each second connecting line is electrically connected to the plurality of second initialization voltage signal lines, and each third connecting line extends to the peripheral area and is electrically connected to the second voltage signal bus.

12. A method for driving a pixel circuit, the pixel circuit comprising a driving transistor, a first light-emitting control transistor and a second light-emitting control transistor; the gate of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line, the first electrode is electrically connected to a first voltage signal line, and the second electrode is electrically connected to the first electrode of the driving transistor; the gate of the second light-emitting control transistor is electrically connected to a second light-emitting control signal line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to a light-emitting device; wherein, The first light emission control signal line is configured to transmit a first pulse width modulation signal, and the second light emission control signal line is configured to transmit a second pulse width modulation signal; A display cycle includes a light-emitting phase, and the driving method includes: In the light emitting stage, the first pulse width modulation signal has a first working level period, and the second pulse width modulation signal has a second working level period. The first working level period is different from the second working level period, and the first working level period partially overlaps with the second working level period.

13. The driving method according to claim 12, wherein: The amplitude, frequency and duty cycle of the first pulse width modulation signal are respectively the same as the amplitude, frequency and duty cycle of the second pulse width modulation signal; The start and end times of the first working level period are both later than the start and end times of the second working level period.

14. The driving method according to claim 13, wherein: The pixel circuit further includes a first reset transistor, a second reset transistor, a data write transistor and a compensation transistor; the gate of the first reset transistor is electrically connected to the first enable signal line, the first electrode is electrically connected to the first initialization voltage signal line, and the second electrode is electrically connected to the gate of the driving transistor; the gate of the second reset transistor is electrically connected to the second scanning signal line, the first electrode is electrically connected to the second initialization voltage signal line, and the second electrode is electrically connected to the second electrode of the second light emitting control transistor; the gate of the data write transistor is electrically connected to the first scanning signal line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the first electrode of the driving transistor; the gate of the compensation transistor is electrically connected to the second enable signal line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the gate of the driving transistor; A display cycle further includes a blank period, during which at least one of the first light emission control transistor and the second light emission control transistor is turned off; The blank phase includes a first initialization phase, a second initialization phase and a data writing phase; The driving method further includes: In the first initialization stage, the first reset transistor is turned on under the control of the first enable signal from the first enable signal line, and transmits the first initialization voltage signal from the first initialization voltage signal line to the gate of the driving transistor; In the second initialization stage, the first reset transistor remains turned on, and the compensation transistor is turned on under the control of the second enable signal from the second enable signal line, and transmits the first initialization voltage signal to the second electrode of the driving transistor; In the data writing phase, the compensation transistor remains turned on, and the data writing transistor is turned on under the control of the first scanning signal from the first scanning signal line to transmit the data signal from the data line to the first electrode of the driving transistor.

15. The driving method according to claim 14, wherein: The blank phase also includes a bias phase after the data writing phase; the driving method also includes: In the bias stage, the first light-emitting control transistor is turned off, the second light-emitting control transistor is turned on, and the second reset transistor is turned on under the control of the second scanning signal of the second scanning signal line, and the second initialization voltage signal from the second initialization voltage signal end is transmitted to the second electrode of the second light-emitting control transistor and the first electrode of the driving transistor in sequence.

16. The driving method according to claim 14 or 15, wherein: In the second initialization phase and the data writing phase, the second reset transistor is The second scanning signal line is turned on under the control of the second scanning signal, and the second initialization voltage signal from the second initialization voltage signal line is transmitted to the second electrode of the second light emitting control transistor.

17. The driving method according to claim 12, wherein: The first working level period is within the second working level period, and the start and end times of the first working level period are spaced apart from the start and end times of the second working level period; Alternatively, the second working level period is located within the first working level period, and the start and end times of the first working level period are spaced apart from the start and end times of the second working level period.

18. The driving method according to claim 12, wherein: The amplitude, frequency and duty cycle of the first pulse width modulation signal are respectively the same as the amplitude, frequency and duty cycle of the second pulse width modulation signal; The start and end times of the first working level period are respectively ahead of the start and end times of the second working level period.

19. A display panel, comprising: The array substrate according to any one of claims 1 to 11; A plurality of light emitting devices are arranged on the array substrate, and each light emitting device is electrically connected to a pixel circuit.

20. A display device, comprising: The display panel according to claim 19, The driving circuit board is electrically connected to the display panel and is configured to transmit a control signal to the display panel.

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