Data processing method, data processing apparatus, data processing system, and readable medium

Abstract

Provided in the present disclosure is a data processing method applied to a data processing apparatus in a data processing system. The method comprises: when a data exchange request message sent by a first cache unit is received, acquiring address information carried in the data exchange request, and determining first target data corresponding to address information in a memory; sending a notification message to the first cache unit; receiving second target data and third data which are sent by the first cache unit, wherein the third data is data that is to be subjected to data exchange with the first target data, and the second target data is data that a second cache unit has requested to read; and when the second target data is not equal to the first target data, returning, to the first cache unit, a data exchange response message that carries the third data.

Description

Data processing method, data processing device, data processing system and readable medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Chinese patent application 202310769533.5 filed with the State Intellectual Property Office of China on June 27, 2023, and the disclosure of this Chinese patent application is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to the field of computer processing technology, and in particular to a data processing method, a data processing device, a data processing system, and a readable medium. Background Art

[0004] An SMP (Symmetric multiprocessing) system is one in which multiple CPUs in a server operate symmetrically, with no primary or secondary relationship between them. Each CPU shares the same physical memory, and each CPU takes the same amount of time to access any memory address. Therefore, SMP is also known as a uniform memory access architecture (UMA).

[0005] Summary of the Invention

[0006] The present disclosure provides a data processing method, a data processing device, a data processing system, and a readable medium.

[0007] In a first aspect, an embodiment of the present disclosure provides a data processing method for a data processing device in a data processing system, comprising: receiving a data exchange request message sent by a first cache unit, obtaining address information carried in the data exchange request, and determining first target data corresponding to the address information in the memory; sending a notification message to the first cache unit; receiving second target data and third data sent by the first cache unit, wherein the third data is data to be exchanged with the first target data, and the second target data is data that the second cache unit has requested to read; and when the second target data is not equal to the first target data, returning a data exchange response message carrying the third data to the first cache unit.

[0008] On the other hand, an embodiment of the present disclosure also provides a data processing device, including: one or more processors; a storage device on which one or more programs are stored; when the one or more programs are executed by the one or more processors, the one or more processors implement the data processing method as described above.

[0009] On the other hand, an embodiment of the present disclosure further provides a data processing system, comprising at least one processing chip, wherein the processing chip comprises the data processing device as described above.

[0010] On the other hand, an embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, wherein the program implements the data processing method as described above when executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a schematic diagram of a flow chart of data processing in related art;

[0012] FIG2 is a first schematic diagram of a data processing flow according to an embodiment of the present disclosure;

[0013] FIG3 is a second schematic diagram of a data processing flow according to an embodiment of the present disclosure;

[0014] FIG4 is a schematic diagram of a process for processing an ATCCOMPARE (AtomicCompare) failure according to an embodiment of the present disclosure;

[0015] FIG5 is a schematic diagram of a successful processing flow of ATCCOMPARE according to an embodiment of the present disclosure;

[0016] FIG6 is a first structural diagram of a data processing system (SMP) according to an embodiment of the present disclosure;

[0017] FIG7 is a second structural diagram of a data processing system according to an embodiment of the present disclosure;

[0018] FIG8 is a third structural diagram of a data processing system (CC-NUMA) according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art.

[0020] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] The terms used herein are used only to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof is not excluded.

[0022] The embodiments described herein may be described with reference to plan views and / or cross-sectional views, with the aid of idealized schematic diagrams of the present disclosure. Thus, the example illustrations may be modified based on manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions of the elements, but are not intended to be limiting.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0024] The data processing method and system according to the embodiments of the present disclosure are applicable to any data processing system involving atomic operations, such as an SMP system, a cache-coherent non-uniform memory access (CC-NUMA) system, and the like. In the following examples, an SMP system is used as an example for description, but the embodiments of the present disclosure are not limited thereto.

[0025] Figure 6 is a structural schematic diagram of a data processing system (SMP) according to an embodiment of the present disclosure. As shown in Figure 6, the SMP system includes: a processing core (Core), a secondary cache (L2), a network-on-chip (NOC), a master node (HN) and a memory (Memory). Both L2 and HN are connected to the NOC, and the HN is connected to the memory. L2 may include one or more cache units, and each cache unit may be connected to one or more processing cores. In the SMP system shown in Figure 6, L2 includes three cache units L2-0, L2-1 and L2-2, where L2-0 is connected to the processing core Core0, L2-1 is connected to the processing core Core1, and L2-2 is connected to the processing core Core2. In the SMP system, the HN interacts with each cache unit of the L2 to achieve cache consistency. The HN manages the entire memory space in units of cache lines and tracks the access to the memory by each cache unit in the L2.

[0026] MESI represents four states of cache line data. By switching these four states, the purpose of managing cache data is achieved. The states of MESI and their descriptions are shown in Table 1:

[0027] Table 1

[0028] HN can track the access of all cache line data by maintaining a directory table (dir table). The data structure of the directory table (dir table) is shown in Table 2:

[0029] Table 2

[0030] In Table 2, each entry corresponds to a cache line of data. The location of the cache line data can be determined based on the address information. An entry includes a state field (State) and a bit width field (VEC). The state field records the state of the data read by the cache unit. The bit width field corresponds to the number of cache units n in the L2. Each bit corresponds to a cache unit in the L2, indicating which cache unit in the L2 stores the data.

[0031] The state field in Table 2 only records the three states of ESI. Because after the cache unit in L2 obtains the data in E state, the action of modifying the data will not notify the HN, so the HN does not know whether the state of the data stored in the L2 cache unit is E state or M state. For example, dir.state = E, VEC = 'b001 means that the data in this cache line in L2-0 may be in M ​​state, E state, S state (downgraded from E state to S state without notifying the HN), or I state (data replaced from the cache unit without notifying the HN); dir.state = S, VEC = 'b011 means that the data in this cache line in L2-0 and L2-1 may be in S state or I state (data replaced from the cache unit without notifying the HN); dir.state = I means that no L2 cache unit stores the cache line data.

[0032] Figure 1 is a schematic diagram of the data processing process in the related art, namely, the atomic lock operation process of AtomicCompare in the SMP system. As shown in Figure 1, the process includes steps S1 to S7.

[0033] In step S1, L2-0 sends an RDS (Read Date S, shared state data read request) message to HN, requesting to read data. After receiving the RDS message, HN returns a DATS (Date S, shared data read response) message and records the requested data as S state. After receiving the DATS message, L2-0 stores the requested data and changes the data state from I state to S state. Initially, the data state of each cache unit is I state.

[0034] In step S2, L2-1 sends an ATCCOMPARE (Atomic Compare) message to HN to perform an atomic compare operation. The ATCCOMPARE message carries address information, and HN queries its memory to obtain the data corresponding to the address information. HN also returns a DBIDRESP (Date Buffer ID Response) message to L2-1. Furthermore, HN sends a SNPtoI (Snoop to Invalid) message to L2-0 to snoop on L2-0.

[0035] In step S3, after receiving the DBIDRESP message, L2-1 sends ATCCOMPARE_DAT (Atomic Compare Data) to HN. ATCCOMPARE_DAT includes exchange data and comparison data.

[0036] In step S4, after receiving ATCCOMPARE_DAT, the HN compares the data corresponding to the address information with the comparison data and confirms that the comparison fails (Compare FAIL).

[0037] In step S5, after receiving the SNPtoI message, L2-0 invalidates the data corresponding to the address information and returns a SNPRSPI (Snoop Response Invalid) message to the HN.

[0038] In step S6, after receiving the SNPRSPI message, the HN records the data corresponding to the address information as state I, and returns a DATI (Date I, invalid state data response) message to L2-1.

[0039] If the processing core Core0 corresponding to L2-0 still needs to use the data corresponding to the address information, it needs to resend the RDS message to the HN to read the data, that is, it needs to execute step 7.

[0040] In step S7, L2-0 sends an RDS message to HN to request to read data. After receiving the RDS message, HN returns a DATS message and records the requested data as S state. After receiving the DATS message, L2-0 stores the requested data and changes the state of the data from I state to S state.

[0041] It should be noted that in step 4, if the comparison data in ATCCOMPARE_DAT successfully compares with the data corresponding to the address information, the HN modifies the data corresponding to the address information in memory to the swap data in ATCCOMPARE_DAT and continues with the subsequent steps. If the processing core Core0 corresponding to L2-0 still needs to access the data corresponding to the address information, the data corresponding to the address information in memory has been modified to the swap data. L2-0 needs to resend an RDS message to the HN to obtain the modified data (i.e., the swap data), and then execute step S7.

[0042] The defect of the relevant technical solution is that if the data comparison fails, the data corresponding to the address information in the memory is not actually modified, that is, no data exchange operation is performed, but the data in L2-0 is still invalidated. If the subsequent processing core Core0 still needs to access this data, it must re-initiate RDS to read the data, which will reduce the processing performance of the processing core.

[0043] To solve the above technical problems, an embodiment of the present disclosure provides a data processing method, which is applied to a data processing system in which lock performance is particularly important. The data processing system can be an SMP system or a cache-coherent non-uniform memory access (CC-NUMA) system. In the embodiment of the present disclosure, the data processing system (SMP) shown in Figure 6 is used as an example for explanation, where L2-1 is the first cache unit, L2-0 is the second cache unit, and the data processing device that interacts with L2-1 and L2-0 is an HN.

[0044] Figure 2 is a first schematic diagram of a data processing flow according to an embodiment of the present disclosure. As shown in Figure 2 , the data processing method may be executed by a data processing device in a data processing system, and includes steps S11 to S14.

[0045] In step S11 , a data exchange request message sent by the first cache unit is received, address information carried in the data exchange request is acquired, and first target data corresponding to the address information in the memory is determined.

[0046] In this step, L2-1 (i.e., the first cache unit) sends an ATCCOMPARE message (i.e., a data exchange request message) carrying address information to the HN (i.e., the data processing device), requesting the HN to modify the data corresponding to the address information in memory. The HN searches the memory based on the address information carried in the ATCCOMPARE message and obtains the first target data corresponding to the address information.

[0047] In step S12, a notification message is sent to the first cache unit.

[0048] In this step, the HN allocates local data buffer space, which is used to store data subsequently sent by the L2-1. The notification message is a Data Buffer Identification Response (DBIDRESP) message. After the HN allocates data buffer space, it returns a DBIDRESP message to the L2-1, indicating that the data buffer space has been allocated and that exchange and comparison data can be sent to the HN.

[0049] In step S13, the atomic comparison data notification message sent by the first cache unit is received, and the second target data and third data carried in the atomic comparison data notification message are obtained, wherein the third data is the data to be exchanged with the first target data (i.e., the exchange data), and the second target data is the data that the second cache unit has requested to read.

[0050] The second target data is the comparison data, which the second cache unit has previously requested from the HN and recorded as shared. The second cache unit and the first cache unit are cache units at the same level. In the disclosed embodiment, the second cache unit L2-0 and the first cache unit L2-1 are both cache units of the second-level cache L2.

[0051] In this step, L2-1 sends an ATCCOMPARE_DAT (i.e., atomic comparison data notification message) to the HN. The ATCCOMPARE_DAT includes the second target data and the third data, which can be stored in the cache space allocated in step S12. The third data is the data to be exchanged with the first target data, the data to be modified by L2-1, and is the modified data (i.e., the exchanged data) at the location corresponding to the address information in the memory. The second target data is the data that other cache units have previously requested to be read from the HN, that is, the data that L2-0 has previously accessed. The state of this data recorded in L2-0 is S state.

[0052] In step S14, when the second target data is not equal to the first target data, a data exchange response message carrying the third data is returned to the first cache unit.

[0053] In this step, the HN compares the second target data with the first target data. If they are unequal, indicating that the data L2-1 wants to modify is different from the data L2-0 previously requested to read, the HN returns a DATI message (i.e., a data exchange response message) to L2-1. The DATI message is a response to the ATCCOMPARE message. It should be noted that if the second target data is unequal to the first target data, the DATI message contains the third data, indicating that the HN has not written the third data to memory.

[0054] The data processing method provided by the disclosed embodiment, upon receiving a data exchange request message sent by a first cache unit, determines the corresponding first target data in the memory based on the address information carried therein, and sends a notification message to the first cache unit for the first cache unit to send second target data and third data, wherein the third data is the data to be exchanged with the first target data, and the second target data is the data that the second cache unit has requested to obtain; if the second target data is not equal to the first target data, a data exchange response message carrying the third data is returned to the first cache unit. The disclosed embodiment first performs a data comparison and then determines whether to initiate data monitoring of other cache units. If the data comparison is unsuccessful, data monitoring of other cache units is no longer initiated and the corresponding data is no longer invalidated by other cache units. This does not affect the use of the data by other processing cores, thereby reducing bus bandwidth overhead and chip power consumption. In addition, when other processing cores access the data, they can directly read the data from the cache unit of the other processing core without re-accessing the memory to read the data, which can further reduce bus bandwidth overhead and chip power consumption.

[0055] Figure 3 is a second schematic diagram of the data processing flow according to an embodiment of the present disclosure. The data processing method can be executed by a data processing device in a data processing system. As shown in Figure 3, after receiving the second target data and the third data sent by the first cache unit (i.e., step S13), the data processing method can also include steps S21 to S24.

[0056] In step S21 , when the second target data is equal to the first target data, a data monitoring message is sent to the second cache unit so that the second cache unit modifies the state of the second target data to an invalid state.

[0057] In this step, HN compares the second target data with the first target data. If the second target data is equal to the first target data, it means that the data to be modified by L2-1 is the same as the data previously requested to be read by L2-0. In this case, HN initiates data monitoring of L2-0 by sending an SNPtoI message (i.e., data monitoring message) to L2-0, so that L2-0 invalidates the second target data, that is, L2-0 changes the status of the second target data from the state to the I state.

[0058] In step S22, a data monitoring response message sent by the second cache unit is received.

[0059] In this step, after L2-0 changes the state of the second target data from S state to I state, it returns a SNPRSPI message (i.e., data monitoring response message) to HN. The SNPRSPI message is a response message to the SNPtoI message, used to inform HN that the second target data has changed to I state.

[0060] In step S23, the third data is written into the memory according to the address information, and the state of the data corresponding to the address information (ie, the third data) is modified to an invalid state.

[0061] In this step, the HN writes the third data into the location corresponding to the address information in the memory, ie, updates the first target data with the third data, and changes the state of the corresponding data in Table 2 to the 1 state.

[0062] In step S24, a data exchange response message carrying the first target data is returned to the first cache unit.

[0063] In this step, the HN returns a DATI message (i.e., Data Exchange Response message) to L2-1. The DATI message is a response to the ATCCOMPARE message. It should be noted that if the second target data is equal to the first target data, the DATI message carries the first target data, indicating that the HN has modified the first target data in memory to the third data, effectively invalidating the first target data. In this way, L2-1 uses the third data to exchange data with the first target data in memory, thereby modifying the memory data that has already been accessed by L2-0.

[0064] In some embodiments, before receiving the data exchange request message sent by the first cache unit (ie, step S11 ), the data processing method further includes steps S31 and S32 .

[0065] In step S31 , a data read request message sent by the second cache unit is received, and the state of the requested second target data in the second cache unit is modified to a shared state.

[0066] In this step, L2-0 sends an RDS message (ie, a data read request message) to HN to request to read the second target data. HN modifies the state of the second target data to the S state in Table 2.

[0067] In step S32 , a shared state data read response message carrying the second target data is returned to the second cache unit, so that the second cache unit can store the second target data and modify the state of the second target data to a shared state.

[0068] In this step, HN sends a DATS message (i.e., shared state data read response message) to L2-0. The DATS message is a response message to the RDS message and carries the second target data. L2-0 stores the second target data and changes the state of the second target data from I state to S state.

[0069] It should be noted that after executing step S24, if the processing core Core0 corresponding to L2-0 still needs to access the data corresponding to the address information, and the data corresponding to the address information in the memory has been modified to the third data, L2-0 needs to resend the RDS message to HN to read the modified data (i.e., the third data), that is, it needs to execute steps S31 and S32 again.

[0070] In order to clearly illustrate the technical solution of the embodiment of the present disclosure, the processing flow of ATCCOMPARE failure and the processing flow of ATCCOMPARE success are described below with reference to FIG. 4 and FIG. 5 respectively.

[0071] FIG4 is a schematic diagram of a process flow for processing an ATCCOMPARE (AtomicCompare) failure according to an embodiment of the present disclosure. As shown in FIG4 , the process flow for processing an ATCCOMPARE failure includes steps S101 to S104 .

[0072] In step S101, L2-0 needs to access the second target data. It sends an RDS message to the HN and receives a DATS message, thereby obtaining the second target data. L2-0 caches the second target data and records its state as S. After receiving the RDS message, the HN changes the state of the corresponding data in Table 2 to S.

[0073] In step S102, L2-1 sends an ATCCOMPARE message carrying address information to HN. After allocating data cache space, HN returns a DBIDRESP message to L2-1 to inform L2-1 that it can send data.

[0074] In step S103, after receiving the DBIDRESP message, L2-1 sends ATCCOMPARE_DAT to HN. ATCCOMPARE_DAT includes the second target data and the third data.

[0075] In step S104, after receiving ATCCOMPARE_DAT, the HN compares the second target data with the first target data corresponding to the address information. If the two are not equal, it is determined that the data comparison fails (Compare FAIL).

[0076] In step S105 , the HN directly returns a DATI message to the L2 - 1 , where the DATI message carries the third data.

[0077] As can be seen from the above steps S101 to S105, the embodiment of the present disclosure does not initiate data monitoring on L2-0 before performing data comparison. Accordingly, L2-0 does not modify the state of the second target data (it remains in the S state). In this way, a data comparison failure does not affect the data cached in L2-0. The processing core Core0 corresponding to L2-0 can continue to access the data from L2-0 without having to re-initiate an RDS request to the HN as in the existing solution.

[0078] In the embodiment of the present disclosure, when Atomic Compare fails in data comparison, no monitoring message will be sent to other cache units (i.e., L2-0). In this way, other cache units will not invalidate the data, and therefore will not affect the use of the data by other processing cores (Core0). Other processing cores (Core0) do not need to reaccess the memory when accessing the data, thereby reducing bus bandwidth overhead and reducing chip power consumption.

[0079] FIG5 is a schematic diagram of a process flow of successfully processing ATCCOMPARE according to an embodiment of the present disclosure. As shown in FIG5 , the process flow of successfully processing ATCCOMPARE includes steps S201 to S207 .

[0080] In step S201, L2-0 needs to access the second target data. It sends an RDS message to the HN and receives a DATS message, thereby obtaining the second target data. L2-0 caches the second target data and records its state as S. After receiving the RDS message, the HN changes the state of the corresponding data in Table 2 to S.

[0081] In step S202, L2-1 sends an ATCCOMPARE message carrying address information to HN. After allocating data cache space, HN returns a DBIDRESP message to L2-1.

[0082] In step S203, after receiving the DBIDRESP message, L2-1 sends ATCCOMPARE_DAT to HN. ATCCOMPARE_DAT includes the second target data and the third data.

[0083] In step S204, after receiving ATCCOMPARE_DAT, the HN compares the second target data with the first target data corresponding to the address information. If the two are equal, the data comparison is successful (Compare success).

[0084] In step S205, the HN sends a SNPtoI message to the L2-0 to monitor the L2-0.

[0085] In step S206, L2-0 receives the SNPtoI message, changes the state of the data corresponding to the address information (ie, the third data) from S state to I state, invalidating the data, and returns a SNPRSPI message to the HN to inform the HN that the data has been invalidated and can be modified.

[0086] In step S207, after receiving the SNPRSPI message, the HN writes the third data into the memory according to the address information, changes the state of the data corresponding to the address information to the I state, and returns a DATI message to L2-1. The DATI message carries the first target data, and the Atomic operation is successful.

[0087] As can be seen from steps S201 to S207, only when the data is successfully accessed will it affect the data cached in L2-0. That is, L2-0 needs to invalidate the accessed data. In this way, if the processing core Core0 corresponding to L2-0 needs to access the data again later, since the data cached in L2-0 is invalid, L2-0 needs to re-initiate an RDS request to the HN.

[0088] The disclosed embodiments improve the atomic lock operation process of AtomicCompare and can be applied to systems such as SMP and CC-NUMA. In these systems, the performance of atomic locks is particularly important. The disclosed embodiments can improve the performance of AtomicCompare while reducing bandwidth overhead and chip power consumption.

[0089] In the disclosed embodiment, if a data comparison fails, there is no need to monitor other cache units storing S-state data. This prevents invalidation of data stored in other cache units after a data comparison failure, ensuring that the corresponding processing core can continue to read data from that cache unit. Only if the data comparison is successful is monitoring initiated for other cache units storing S-state data, thereby improving the performance of the processing core. This also reduces the additional bandwidth and power consumption caused by cache unit monitoring and the processing core re-accessing memory.

[0090] An embodiment of the present disclosure also provides a data processing device, which includes: one or more processors and a storage device; wherein one or more programs are stored on the storage device, and when the one or more programs are executed by the one or more processors, the one or more processors implement the data processing method provided in the aforementioned embodiments.

[0091] An embodiment of the present disclosure further provides a data processing system, which includes at least one processing chip, and the processing chip includes the data processing device as described above.

[0092] In some embodiments, the processing system further includes memory and at least two levels of cache, each level of which includes at least one cache unit. The data processing device may be a master node (HN), or the data processing device may be one of the cache units at a different level from the first cache unit and the second cache unit. In other words, the disclosed embodiments are not limited to a cache unit accessing memory data through interaction with the HN; a cache unit may also access memory data through interaction with cache units at other levels.

[0093] It should be noted that the processing system may further include an on-chip network NOC, and cache units at different levels and the master node may communicate via the NOC.

[0094] Figure 7 is a second schematic diagram of the structure of a data processing system according to an embodiment of the present disclosure. As shown in Figure 7, the processing system includes a second-level cache L2, a third-level cache L3, and a fourth-level cache L4. L2 includes three cache units: L2-0, L2-1, and L2-2. L2-0 is connected to processing core Core0, L2-1 is connected to processing core Core1, and L2-2 is connected to processing core Core2. L3 includes two processing units: L3-1 and L3-2. The data processing device can be a master node HN or a cache unit of L4.

[0095] The data processing system may be a symmetric multiprocessor (SMP) system or a cache coherent non-uniform memory access (CC-NUMA) system.

[0096] In some embodiments, there may be at least two processing chips, each processing chip is connected to at least another processing chip, and the processing chip to which the data processing device belongs is the same as or different from the processing chip to which the first cache unit and the second cache unit belong.

[0097] In some embodiments, the processing chip includes but is not limited to: a central processing unit (CPU), a graphics processing unit (GPU), an embedded neural network processor (NPU), and a data processing unit (DPU).

[0098] In a data processing system that includes multiple processing chips, such as a CC-NUMA system, a cache unit can access memory data of the same processing chip as well as memory data of other processing chips, thus achieving cross-CPU access.

[0099] In a CC-NUMA system, distributed memory is connected to form a single memory. There is no page or data replication between memories, and no software message transmission. Accessing local memory from a processing chip is relatively fast, but accessing remote memory belonging to another processing chip is slower due to the additional latency incurred through the interconnection network. CC-NUMA has only one memory image, and the memories of each processing chip are physically connected using copper cables and certain intelligent hardware. Cache coherence means that no software is required to maintain the consistency of multiple copies of data, nor is software required to implement data transmission between the operating system and application systems. Like SMP systems, CC-NUMA systems manage a single operating system and multiple processors entirely at the hardware level.

[0100] Figure 7 is a second structural diagram of a data processing system according to an embodiment of the present disclosure. The CC-NUMA system shown in Figure 8 includes four processing chips, each of which is connected in pairs. A cache unit within one of the processing chips enables cross-chip memory data access. It should be noted that the embodiments of the present disclosure do not limit the connection method of the processing chips in the CC-NUMA system. For example, the processing chips may also be connected in series.

[0101] The embodiments of the present disclosure further provide a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed, implements the data processing method provided in the aforementioned embodiments.

[0102] It will be appreciated by those skilled in the art that all or some of the steps in the method disclosed above, and the functional modules / units in the device can be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0103] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A data processing method, applied to a data processing device in a data processing system, the method comprising: Receiving a data exchange request message sent by the first cache unit, acquiring address information carried in the data exchange request, and determining first target data corresponding to the address information in the memory; Sending a notification message to the first cache unit; receiving second target data and third data sent by the first cache unit, wherein the third data is data to be exchanged with the first target data, and the second target data is data that the second cache unit has requested to read; In a case where the second target data is not equal to the first target data, a data exchange response message carrying the third data is returned to the first cache unit.

2. The method of claim 1, wherein: After receiving the second target data and the third data sent by the first cache unit, the method further includes: When the second target data is equal to the first target data, sending a data monitoring message to the second cache unit so that the second cache unit can modify the state of the second target data to an invalid state; Receiving a data monitoring response message sent by the second cache unit; Writing the third data into the memory according to the address information, and modifying the state of the third data to an invalid state; A data exchange response message carrying the first target data is returned to the first cache unit.

3. The method of claim 2, wherein: The data monitoring message is an invalidation monitoring message, and the data monitoring response message is an invalidation status monitoring response message.

4. The method of claim 1, wherein: Before receiving the data exchange request message sent by the first cache unit, the method further includes: receiving a shared state data read request message sent by the second cache unit, and modifying the state of the requested second target data of the second cache unit to a shared state; A shared state data read response message carrying the second target data is returned to the second cache unit, so that the second cache unit can store the second target data and modify the state of the second target data to a shared state.

5. The method of claim 1, wherein: The data exchange request message is an atomic comparison message, the notification message is a data cache identification response message, and the data exchange response message is an invalid status data response message.

6. The method according to any one of claims 1 to 5, wherein: The data processing system includes a processing chip, a memory, and at least two levels of cache. The processing chip includes the data processing device. Each of the at least two levels of cache includes at least one cache unit. The data processing device is a master node, or the data processing device is one of the cache units at a different level from the first cache unit and the second cache unit.

7. A data processing device, comprising: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the data processing method according to any one of claims 1 to 6.

8. A data processing system comprising at least one processing chip, wherein the processing chip comprises the data processing device according to claim 7.

9. The data processing system of claim 8, wherein: The processing system also includes a memory and at least two levels of cache, each of the at least two levels of cache includes at least one cache unit, the data processing device is a master node, or the data processing device is one of the cache units at a different level from the first cache unit and the second cache unit.

10. The data processing system according to claim 8, wherein: The data processing system is a symmetric multiprocessor system or a cache consistency non-uniform storage access system.

11. The data processing system of claim 10, wherein: There are at least two processing chips, each of which is connected to at least another processing chip, and the processing chip to which the data processing device belongs is the same as or different from the processing chip to which the first cache unit and the second cache unit belong.

12. The data processing system according to any one of claims 8 to 11, wherein: The processing chip is one of the following: a central processing unit, a graphics processing unit, an embedded neural network processor, and a data processor.

13. A computer readable medium having a computer program stored thereon, wherein: When the program is executed, the data processing method according to any one of claims 1 to 6 is implemented.

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