Chip power consumption evaluation method, power consumption model generation method, and computer device

Abstract

The present application relates to a chip power consumption evaluation method, a power consumption model generation method, and a computer device. The chip power consumption evaluation method comprises: determining a static modeling parameter and a dynamic evaluation parameter of a chip under test, wherein the static modeling parameter describes a constant chip design parameter in a power consumption constraint condition of a current power consumption scenario, and the dynamic evaluation parameter is a varying chip design parameter in the power consumption constraint condition of the current power consumption scenario; performing calculation on the basis of the static modeling parameter and a first mapping relationship to obtain an intermediate calculation result, and generating a target power consumption model which stores the intermediate calculation result, wherein the first mapping relationship is at least used for indicating the correspondence between the static modeling parameter and the intermediate calculation result; and obtaining a power consumption evaluation result on the basis of the dynamic evaluation parameter and the target power consumption model. By means of the present application, the problem of low efficiency of the chip power consumption evaluation method is solved, and an efficient and accurate chip power consumption evaluation method is achieved.

Description

Chip power consumption evaluation method, power consumption model generation method and computer device

[0001] This application claims priority to Chinese patent application CN202310773235.3, filed on June 28, 2023, entitled “Chip power consumption evaluation method, power consumption model generation method and computer device,” and all of its contents are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of chip technology, and in particular to a chip power consumption evaluation method, a power consumption model generation method, and a computer device. Background Art

[0003] With the evolution of manufacturing processes and packaging technologies, the integration density (i.e., the number of transistors per unit volume) and power consumption density of integrated circuits (ICs) continue to increase, making power consumption a key consideration in IC design. In related technologies, power consumption assessment techniques are typically used to evaluate IC chips at the register transfer language (RTL) stage, pre-physical implementation, and post-physical implementation stages. These three stages require all relevant chip elements to be input at once before calculating the power consumption of the overall design. This results in a very large amount of input data for power consumption calculations on chips of a certain size, leading to very low overall efficiency in evaluating IC chip power consumption.

[0004] Currently, no effective solution has been proposed for the problem of low efficiency of chip power consumption detection in related technologies. Technical Solutions

[0005] The embodiments of the present application provide a chip power consumption evaluation method, a power consumption model generation method, and a computer device to at least solve the problem of low efficiency of chip power consumption detection in related technologies.

[0006] In a first aspect, an embodiment of the present application provides a chip power consumption evaluation method, the method comprising:

[0007] Determine static modeling parameters and dynamic evaluation parameters of the chip to be tested; wherein the static modeling parameters are fixed chip design parameters in the power consumption constraints describing the current power consumption scenario, and the dynamic evaluation parameters are variable chip design parameters in the power consumption constraints of the current power consumption scenario;

[0008] Obtaining an intermediate calculation result based on the static modeling parameters and the first mapping relationship, and generating a target power consumption model storing the intermediate calculation result; wherein the first mapping relationship is at least used to indicate a correspondence between the static modeling parameters in the power consumption constraint condition and the intermediate calculation result;

[0009] A power consumption evaluation result is obtained according to the dynamic evaluation parameter and the target power consumption model.

[0010] In some embodiments, determining the static modeling parameters of the chip under test includes: acquiring static factor information corresponding to scenario requirement information, and determining the static modeling parameters of the chip under test from the static factor information;

[0011] and / or,

[0012] Determining the dynamic evaluation parameters of the chip under test includes: acquiring dynamic factor information corresponding to scenario requirement information, and determining the dynamic evaluation parameters of the chip under test from the dynamic factor information.

[0013] In some embodiments, generating a target power consumption model storing the intermediate calculation result includes:

[0014] Determine the data template corresponding to the scenario requirement information;

[0015] Obtain the model data required by the data template in the intermediate calculation results;

[0016] A target power consumption model is generated according to the model data and the data template.

[0017] In some embodiments, the target power consumption model includes model detailed data; wherein the model detailed data includes at least chip description data and intermediate calculation results corresponding to the chip description data; and / or,

[0018] The target power consumption model includes model metadata; wherein the model metadata at least includes model description data, and the model description data is used to describe the attributes of the target power consumption model.

[0019] In some embodiments, the static modeling parameters include at least one hierarchical sub-module of the chip to be tested, and the intermediate calculation results include intermediate calculation results corresponding to the hierarchical sub-module.

[0020] In some embodiments, each of the hierarchical sub-modules includes a plurality of component units, and the method further includes:

[0021] For each of the component units, obtaining static modeling parameters corresponding to different power consumption types of the component unit and first mapping relationships corresponding to different power consumption types; wherein the same power consumption type corresponds to the same first mapping relationship;

[0022] Calculating and obtaining intermediate calculation results of different power consumption evaluation types for different component units according to the static modeling parameters of the different power consumption types and the first mapping relationships corresponding to the different power consumption types;

[0023] The intermediate calculation results of the same power consumption type in the same level are merged to generate the intermediate calculation results corresponding to the sub-modules of the level.

[0024] In some embodiments, the method further comprises:

[0025] Obtaining block information for the chip to be tested, determining at least two block chip areas of the chip to be tested based on the block information, and generating at least two target power consumption models corresponding to the block chip areas based on the static modeling parameters;

[0026] The dynamic evaluation parameters of each chip block area are input into the corresponding target power consumption model to obtain a power consumption evaluation result corresponding to the chip block area.

[0027] In a second aspect, an embodiment of the present application provides a chip power consumption evaluation method, the method comprising:

[0028] Responding to a user's power consumption assessment request, obtaining a target power consumption model; wherein the target power consumption model is used to store an intermediate calculation result calculated based on static modeling parameters of the chip under test and a first mapping relationship, wherein the first mapping relationship is used to indicate at least a correspondence between the static modeling parameters in the power consumption constraint condition and the intermediate calculation result;

[0029] Obtaining dynamic evaluation parameters; wherein the static modeling parameters are fixed chip design parameters in the power consumption constraints describing the current power consumption scenario, and the dynamic evaluation parameters are variable chip design parameters in the power consumption constraints of the current power consumption scenario;

[0030] A power consumption evaluation result is obtained according to the dynamic evaluation parameter and the target power consumption model.

[0031] In some embodiments, obtaining a power consumption evaluation result according to the dynamic evaluation parameter and the target power consumption model includes:

[0032] Determine a second mapping relationship; the second mapping relationship is at least used to indicate the correspondence between the dynamic evaluation parameter in the power consumption constraint condition, the intermediate calculation result of the target power consumption model and the power consumption evaluation result;

[0033] A power consumption evaluation result is obtained according to the dynamic evaluation parameter, the intermediate calculation result, and the second mapping relationship.

[0034] In a third aspect, an embodiment of the present application provides a method for generating a power consumption model, the method comprising:

[0035] Determining static modeling parameters of the chip to be tested; wherein the static modeling parameters are fixed chip design parameters in the power consumption constraint conditions that describe the current power consumption scenario;

[0036] An intermediate calculation result is calculated based on the static modeling parameters and the first mapping relationship, and a target power consumption model storing the intermediate calculation result is generated to obtain a power consumption evaluation result of the chip to be tested; wherein, the first mapping relationship is at least used to indicate the correspondence between the static modeling parameters and the intermediate calculation result in the power consumption constraint condition; the power consumption evaluation result is generated based on the dynamic evaluation parameter and the target power consumption model, and the dynamic evaluation parameter is the chip design parameter that changes in the power consumption constraint condition of the current power consumption scenario.

[0037] In some embodiments, the target power consumption model includes model detailed data; wherein the model detailed data includes at least chip description data and intermediate calculation results corresponding to the chip description data; and / or,

[0038] The target power consumption model includes model metadata; wherein the model metadata includes at least model description data, and the model description data is used to describe properties of the target power consumption model.

[0039] In a fourth aspect, an embodiment of the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, it implements the chip power consumption evaluation method described in the first or second aspect, or the power consumption model generation method described in the third aspect.

[0040] Compared with the related art, the chip power consumption evaluation method, power consumption model generation method and computer device provided in the embodiments of the present application determine the static modeling parameters and dynamic evaluation parameters of the chip to be tested; wherein, the static modeling parameters are fixed chip design parameters in the power consumption constraints describing the current power consumption scenario, and the dynamic evaluation parameters are variable chip design parameters in the power consumption constraints of the current power consumption scenario; an intermediate calculation result is calculated based on the static modeling parameters and the first mapping relationship, and a target power consumption model storing the intermediate calculation result is generated; wherein, the first mapping relationship is at least used to indicate the correspondence between the static modeling parameters and the intermediate calculation result; the power consumption evaluation result is obtained according to the dynamic evaluation parameters and the target power consumption model, thereby splitting the chip power consumption analysis process into two parts: power consumption modeling and power consumption evaluation. After the modeling is completed, the subsequent power consumption evaluation steps only need to rely on the generated power consumption model, and multiple power consumption evaluation calculations can be performed by inputting relevant dynamic evaluation parameters. Therefore, the overall efficiency of evaluating the power consumption of the same design chip under different environments and behaviors is improved, the problem of low efficiency of the chip power consumption evaluation method is solved, and an efficient and accurate chip power consumption evaluation method is realized.

[0041] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0043] FIG1 is a diagram illustrating an application environment of a chip power consumption evaluation method according to an embodiment of the present application.

[0044] FIG2 is a flowchart of a chip power consumption evaluation method according to an embodiment of the present application.

[0045] FIG3 is a flowchart of another chip power consumption evaluation method according to an embodiment of the present application.

[0046] FIG4 is a flow chart of a chip power consumption evaluation method according to a preferred embodiment of the present application.

[0047] FIG5 is a structural block diagram of a chip power consumption evaluation device according to an embodiment of the present application.

[0048] FIG6 is a structural block diagram of a chip power consumption evaluation system according to an embodiment of the present application.

[0049] FIG7 is a structural diagram of the interior of a computer device according to an embodiment of the present application.

[0050] Implementation Methods of the Application

[0051] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is described and illustrated below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for ordinary technicians in the field related to the contents disclosed in the present application, some changes such as design, manufacturing or production based on the technical contents disclosed in the present application are only conventional technical means and should not be understood as the contents disclosed in the present application being insufficient.

[0052] References to "embodiments" in this application mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this application may be combined with other embodiments unless there is a conflict.

[0053] Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by persons of ordinary skill in the art to which this application belongs. The terms "a," "an," "an," "the," and similar expressions used herein do not denote limitations on quantity and may refer to either the singular or the plural. The terms "comprise," "include," "have," and any variations thereof, used herein, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or modules (units) is not limited to the listed steps or units but may also include steps or units not listed, or may include other steps or units inherent to the process, method, product, or apparatus. The terms "connected," "connected," "coupled," and similar expressions used herein are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. As used herein, "plurality" means greater than or equal to two. "And / or" describes an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" may mean: A exists alone; A and B exist simultaneously; or B exists alone. The terms "first", "second", "third" and the like involved in this application are merely used to distinguish similar objects and do not represent a specific ordering of the objects.

[0054] The chip power consumption evaluation method provided in the embodiment of the present application can be applied in the application environment shown in Figure 1. The terminal device 12 communicates with the server 14 through the network. The terminal device 12 is used to obtain user operations, and the server 14 obtains the static modeling parameters and dynamic evaluation parameters of the chip to be tested in response to the user operations; the server 14 performs calculations based on the static modeling parameters and the first mapping relationship to obtain intermediate calculation results, and generates a target power consumption model that stores the intermediate calculation results; wherein the first mapping relationship is at least used to indicate the correspondence between the static modeling parameters and the intermediate calculation results; the server 14 obtains the power consumption evaluation results based on the dynamic evaluation results and the target power consumption model, and feeds back the power consumption evaluation results to the user through the terminal device 12. The terminal device 12 can be, but is not limited to, various personal computers, laptops, and tablet computers; the server 14 can be implemented as an independent server or a server cluster consisting of multiple servers.

[0055] This embodiment provides a chip power consumption evaluation method. FIG2 is a flow chart of a chip power consumption evaluation method according to an embodiment of the present application. As shown in FIG2 , the process includes the following steps:

[0056] Step S210, determine the static modeling parameters and dynamic evaluation parameters of the chip to be tested; the static modeling parameters are fixed chip design parameters in the power consumption constraints describing the current power consumption scenario, and the dynamic evaluation parameters are variable chip design parameters in the power consumption constraints of the current power consumption scenario.

[0057] Among them, the above-mentioned chip to be tested refers to a chip at any stage in the integrated circuit design, such as a chip that has not been fully designed in the RTL stage or the stage before physical implementation, but already has certain chip structure data, or it can be a chip that has been completely designed; that is, the power consumption evaluation and analysis of the current chip design can be performed at any design stage of the integrated circuit.

[0058] The above-mentioned static modeling parameters refer to the chip parameters that can affect the chip power consumption in the current power consumption assessment scenario requirements, and will not change during the current chip power consumption assessment process, that is, the parameters that remain in a static state, including at least chip structure information, and also include parameters related to the chip structure itself, such as chip structure, parasitic parameters and chip timing information.

[0059] The above-mentioned dynamic evaluation parameters refer to the chip parameters that can cause power consumption changes due to design changes in the current power consumption evaluation scenario requirements, that is, the parameters that change dynamically during the chip power consumption evaluation process. They are used to quickly evaluate the power consumption changes caused by different design parameter values ​​or value combinations, such as process angle, temperature, voltage, frequency, and chip behavior data.

[0060] Static modeling parameters and dynamic evaluation parameters constitute the complete parameters of the chip under test in the power consumption evaluation for the current power consumption evaluation scenario, that is, all the parameters in the power consumption constraints. Therefore, the power consumption evaluation results cannot be calculated by relying solely on static modeling parameters or dynamic evaluation parameters. All parameters in the power consumption constraints include chip structure parameters, chip behavior parameters, chip environment parameters, etc. Power consumption constraints refer to the rules used to calculate the power consumption of the chip under test, and the same power consumption evaluation type corresponds to the same power consumption constraint. In any power consumption evaluation scenario, when evaluating the power consumption of the chip under test, it is necessary to evaluate different types of power consumption. The power consumption evaluation types can include switching power consumption, internal power consumption, static power consumption, leakage power consumption, etc., all of which have their own power consumption constraints.

[0061] Furthermore, since the power consumption evaluation and analysis of the chip to be tested usually needs to be performed in different scenarios, the corresponding static modeling parameters and dynamic evaluation parameters can be determined according to the requirements of the current evaluation scenario.

[0062] In some embodiments, if the current power consumption evaluation scenario is a scenario for quickly evaluating the power consumption of a chip in different operating environments, then the operating environment needs to be changed in this evaluation scenario, and the chip behavior does not need to be changed, and thus the corresponding static modeling parameters can be determined to include chip behavior parameters in addition to the above-mentioned chip structure parameters, and the corresponding dynamic evaluation parameters can be determined to include environmental parameters; if the current power consumption evaluation scenario is a scenario for quickly evaluating the power consumption of a chip under different behaviors, then the chip behavior needs to be changed in this evaluation scenario, and the operating environment does not need to be changed, and thus the corresponding static modeling parameters can be determined to include environmental parameters in addition to the above-mentioned chip structure parameters, and the corresponding dynamic evaluation parameters can be determined to include chip behavior parameters; if the current power consumption evaluation scenario is a scenario for quickly evaluating the power consumption of a chip in different operating environments and different behaviors, then the operating environment and chip behavior need to be changed in this evaluation scenario, and thus the static modeling parameters can be determined to include chip structure parameters, and the dynamic evaluation parameters can be determined to include environmental parameters and chip behavior parameters.

[0063] Step S220: Calculate an intermediate calculation result based on the static modeling parameters and the first mapping relationship, and generate a target power consumption model that stores the intermediate calculation result; wherein the first mapping relationship is used to indicate the correspondence between the static modeling parameters in the power consumption constraint and the intermediate calculation result, and the target power consumption model is used to form a new power consumption constraint that can indicate the correspondence between the intermediate calculation result and the power consumption assessment result. Specifically, the static modeling parameters and the first mapping relationship can be used to determine a portion of the power consumption calculation result, and the target power consumption model is generated based on the portion of the power consumption calculation result.

[0064] The above-mentioned first mapping relationship is at least used to indicate the correspondence between the static modeling parameters and the intermediate calculation results. The intermediate calculation results can be obtained by calculating the first mapping relationship. The first mapping relationship is determined according to the scenario requirement information. When the scenario requirement is determined, it can be known that the intermediate calculation results can be obtained by which mapping relationship and which static modeling parameters in the current scenario. The intermediate calculation results obtained refer to the power consumption of the chip design parameters that will not change in the current scenario. For example, the intermediate calculation results include power consumption information for a certain chip structure, the intermediate calculation results include the design hierarchy, the power consumption value of the current hierarchy, and can also include the circuit network information of the current hierarchy.

[0065] Furthermore, the target power consumption model, as an intermediate form in the entire power consumption evaluation and analysis process, can utilize the intermediate calculation results stored in the target power consumption model to form power consumption constraints represented by the intermediate calculation results, i.e., to form new power consumption constraints between the intermediate calculation results and the power consumption evaluation results. The new power consumption constraints can represent the relationship between the intermediate calculation results, the dynamic evaluation parameters, and the power consumption evaluation results. The intermediate form established by the target power consumption model serves to store the parameters that do not change in the current power consumption evaluation scenario during the power consumption analysis process, i.e., the power consumption calculation results related to the static modeling parameters. This reduces the time and resources consumed for each subsequent calculation when calculating power consumption based on changing parameters. Furthermore, in subsequent specific power consumption evaluations, the chip evaluation results can be quickly generated based on the dynamic evaluation parameters, thereby facilitating the acceleration of the chip power consumption evaluation process. It should be noted that the target power consumption model can be stored in a format including, but not limited to, an ASCII text file or a binary file, and the model file can be directly stored in a storage space such as a computer memory. Furthermore, for models stored in text file format, the format includes, but is not limited to, YAML, JSON, XML, HTML, other markup languages, or programming languages. It is understandable that the above target power consumption model can be stored in a single file or divided into multiple files.

[0066] Step S230: Obtain a power consumption evaluation result based on the dynamic evaluation parameters and the target power consumption model. After the modeling is completed in step S220, when power consumption evaluation is required, the configuration file and run script required for power consumption evaluation are loaded, the modeling tool software deployed with the target power consumption model is run, and the determined dynamic evaluation parameters are input into the called target power consumption model. The modeling tool software is then used to perform a complete power consumption calculation based on the dynamic evaluation parameters and the intermediate calculation results, ultimately obtaining the power consumption evaluation result of the chip under test.

[0067] Furthermore, in steps S220 to S230, the first mapping relationship between the static modeling parameters and the intermediate calculation results can be composed of one or more power consumption calculation formulas. Different power consumption assessment types have different mapping relationships, and the same power consumption type mapping relationship corresponds to the same mapping relationship. Power consumption assessment types include but are not limited to switching power consumption, internal power consumption, static power consumption, leakage power consumption, etc. For example, the power consumption calculation formula can be set as a calculation expression for the switching power consumption of a single line network. The power consumption calculation formula can be regarded as a power consumption constraint condition, as shown in the following formula 1:

[0068] P s =C×V 2 ×f×TR Formula 1

[0069] In the above formula, P s is the switching power consumption, C is the total capacitance of the line network, including parasitic capacitance and the input pin capacitance of the load unit; V is the supply voltage; f is the operating frequency of the chip, and TR is the flip probability. In some power consumption evaluation scenarios, based on the current power consumption constraint conditions determined by Formula 1, the fixed chip design parameters are C, V, and f, and the variable chip design parameter is TR. The first mapping relationship is C×V 2 ×f, the intermediate calculation result is C×V 2 The calculation result of ×f is obtained, and the new power consumption constraint relationship formed by the target power consumption model is P s = intermediate calculation result × TR. Or in other power consumption evaluation scenarios, the fixed chip design parameters in the power consumption constraint are C and V, and the variable chip design parameters are f and TR. The first mapping relationship is C × V 2 , the intermediate calculation result is C×V 2 The calculation results are obtained, and the new power consumption constraint relationship formed by the target power consumption model is P s =intermediate calculation result×f×TR.

[0070] Alternatively, the power consumption calculation formula can also include an expression for calculating internal power consumption. During the calculation process, the logic gates in the chip can be roughly equivalent to resistors, thereby obtaining the corresponding power consumption value caused by the short-circuit current. This power consumption calculation formula can be regarded as a power consumption constraint condition, as shown in the following formula:

[0071] P I =(V 2 / R)×f×TR Formula 2

[0072] In the above formula, P Iis the internal power consumption, R is the equivalent resistance of the logic gate, V is the supply voltage, f is the operating frequency of the chip, and TR is the flip probability. In some power consumption evaluation scenarios, the fixed chip design parameters in the power consumption constraint are V, R, and f, and the variable chip design parameter is TR. The first mapping relationship is (V 2 / R)×f, the intermediate calculation result is (V 2 / R)×f is calculated to obtain the result, and the power consumption constraint relationship formed by the target power consumption model is P I = intermediate calculation result × TR. Or in other power consumption evaluation scenarios, the fixed chip parameters in the power consumption constraint are V and R, and the variable chip design parameters are f and TR. The first mapping relationship is V 2 / R, the intermediate calculation result is V 2 The result of R calculation is obtained, and the power consumption constraint relationship formed by the target power consumption model is P I =intermediate calculation result×f×TR.

[0073] Alternatively, the power consumption calculation formula may further include a calculation expression for static power consumption / leakage power consumption. This power consumption calculation formula may be considered as a power consumption constraint condition, as shown in the following formula:

[0074] P L =c0×T 2 ×e^(c1 / T) Formula 3

[0075] In some power consumption evaluation scenarios, in the above formula, P L is the static power consumption, c0 and c1 are empirical parameters related to the circuit structure, which are fixed chip parameters in the power consumption constraint conditions, and T is the temperature, which is a variable chip design parameter.

[0076] The above-mentioned power consumption calculation formulas can form at least a first mapping relationship for indicating the static modeling parameters and the intermediate calculation results; for example, for the single-line network switch calculation formula shown in the above formula 1, or for the internal power consumption calculation formula shown in the above formula 2, only the total capacitance C is a static modeling parameter, that is, it does not change in subsequent evaluations, and V, f, and TR can all change. Therefore, for the power consumption of the line network or logic gate, the first mapping relationship between the static modeling parameter C and the intermediate calculation result can be determined based on formulas 1 and 2.

[0077] After obtaining the intermediate calculation result based on the static modeling parameters and the first mapping relationship, a target power consumption model storing the intermediate calculation result is generated. The target power consumption model can be used to form a new power consumption constraint relationship that can indicate the corresponding relationship between the intermediate calculation result and the power consumption evaluation result. The new power consumption constraint relationship represents the calculation rules between the intermediate calculation result, the dynamic evaluation parameter, and the power consumption evaluation result. Next, the power consumption evaluation result can be obtained according to the dynamic evaluation parameter and the target power consumption model; for example, for the single-line network switch power consumption calculation formula shown in Formula 1 above, or for the internal power consumption calculation formula shown in Formula 2 above, the total capacitance C is a static modeling parameter, and V, f, and TR can all change. Therefore, for the power consumption of the line network or logic gate, the value of the total capacitance C and the form of the above expression can be recorded in the power consumption model through the above first mapping relationship, thereby obtaining the intermediate calculation result and generating the target power consumption model. The specific power consumption value is obtained by substituting the specific V, f, and TR values ​​into the calculation in the subsequent power consumption evaluation process. Alternatively, for the static power consumption calculation formula shown in Formula 3 above, c0 and c1 are empirical parameters related to the circuit structure and are static modeling parameters, and T is the temperature and is a dynamic evaluation parameter. Therefore, for the static power consumption of the logic gate, the c0 value, c1 value, and the above expression can be recorded in the target power consumption model. The specific power consumption value is then calculated in the subsequent evaluation process by substituting the specific temperature value of the dynamic evaluation parameter. Furthermore, during the model generation process, this embodiment can also use an interpolation method to calculate power consumption to improve accuracy. For example, linear interpolation can be used to generate switch power consumption, while nonlinear interpolation can be used for internal power consumption and static power consumption.

[0078] It is understandable that the process of performing power consumption evaluation calculations based on dynamic evaluation parameters is similar to the process of generating the above-mentioned power consumption model. It should be noted that the power consumption modeling and evaluation method in this embodiment is not limited to a specific design stage, that is, this method can be used in both the front-end design and the back-end design process, and there is no difference in the use process and method, only the input files are different; similarly, for the aforementioned different application scenarios, the modeling and evaluation methods are the same, only the input content is different. Therefore, by using the target power consumption model as an intermediate form, the variable factors in the power consumption calculation process are converted into a computable model, which is conducive to improving the efficiency of chip power consumption simulation evaluation.

[0079] In related technologies, a complete chip power consumption calculation is performed after all elements of the chip under test, such as the environment, behavior, and structure, are input at once during power consumption analysis. If a parameter in the input information changes, the power consumption evaluation tool needs to recalculate the power consumption completely. For chips of a certain size, the relevant input data for power consumption calculations are usually very large. For example, the size of a standard cell library file can reach 1.5 GB, the size of a parasitic parameter file can reach more than 10 GB, and the VCD file describing the circuit behavior can reach hundreds of GB. Since the parsing and processing of these files takes a lot of time, the additional overhead of repeated calculations is huge, resulting in very low overall efficiency in evaluating the power consumption of the same chip under different environments and behaviors.

[0080] Compared with the power consumption calculation method in the related art that requires all factors to be output at one time, resulting in low efficiency in chip power consumption calculation, the embodiment of the present application, through the above steps S210 to S230, first models the power consumption calculation model based on the fixed static modeling parameters of the chip to be tested, generates a target power consumption model as an intermediate form, and then inputs the dynamic evaluation parameters of the chip to be tested during power consumption evaluation, and finally obtains the power consumption evaluation result of the chip to be tested based on the dynamic evaluation parameters and the target power consumption model, thereby splitting the chip power consumption analysis process into two parts: power consumption modeling and power consumption evaluation. After the modeling is completed, the subsequent power consumption evaluation steps only need to rely on the generated power consumption model, and multiple power consumption evaluation calculations can be performed by inputting relevant dynamic evaluation parameters. Therefore, significant data merging and compression are achieved based on the generated power consumption model, which greatly reduces the parameter processing cost, improves the overall efficiency of evaluating the power consumption of the same design chip under different environments and behaviors, effectively solves the problem of low efficiency of chip power consumption evaluation, and realizes an efficient and accurate chip power consumption evaluation method.

[0081] In some embodiments, determining the static modeling parameters and dynamic evaluation parameters of the chip under test further includes the following steps: obtaining static factor information corresponding to scenario requirement information, and determining the static modeling parameters of the chip under test based on the static factor information; and / or obtaining dynamic factor information corresponding to the scenario requirement information, and determining the dynamic evaluation parameters of the chip under test based on the dynamic factor information. The static factor information may include a file for obtaining static modeling parameters corresponding to the current scenario requirement, or user-entered data for intermediate result calculation; the dynamic factor information may include a file for obtaining dynamic evaluation parameters, or user-entered data that may change the chip design for final power consumption evaluation. The static factor information and dynamic factor information may be in text or binary format. Before generating a target power consumption model, only the static modeling parameters may be obtained to generate the target power consumption model. Alternatively, all parameters may be obtained after confirming the scenario, and only the static modeling parameters may be used during the target model generation phase; the dynamic evaluation parameters may be used during the power consumption evaluation phase. Furthermore, the dynamic evaluation parameters may be quickly replaced during this phase. In some embodiments, obtaining static factor information corresponding to scenario requirement information includes obtaining scenario requirement information, where the user can input the scenario that currently needs to evaluate power consumption, i.e., the scenario requirement information, in the user interface, so that the required static factors can be confirmed based on the scenario requirement information. The confirmation method can be manual determination of the static factors, or the user can select the current scenario requirement information in the user interface, and then the user interface displays a prompt message of the corresponding static factors based on the scenario requirement information selected by the user to remind the user to input the corresponding static factor information based on the prompt information; the static factors include chip structure information, etc.; next, after obtaining the scenario requirement information based on the current power consumption evaluation of the user to determine the static factors required for the current power consumption evaluation, the corresponding static factor information input by the user based on the static factors is obtained, such as a file storing the static factors, or after inputting data related to the static factors, the target power consumption model generation request is responded to, and the static modeling parameters are obtained from the static factor information input by the user.

[0082] In some embodiments, scenario requirement information is obtained, and dynamic factors are determined based on the scenario requirement information; dynamic factor information input by the user based on the dynamic factors is obtained; and in response to a power consumption evaluation request, the dynamic evaluation parameters are obtained from the dynamic factor information input by the user. The above-mentioned scenario requirement information refers to a power consumption evaluation scenario for integrated circuit design chips, and the scenario requirement information can be determined by staff based on actual conditions; for example, the scenario requirement information can be used to indicate the evaluation of chip power consumption under different operating environments, or it can also be used to indicate the evaluation of chip power consumption under different chip behaviors, etc. The method of obtaining dynamic factor information and obtaining dynamic evaluation parameters based on the dynamic factor information in this embodiment is similar to the above-mentioned method of obtaining static factor information and obtaining static modeling parameters based on the static factor information, and will not be repeated here.

[0083] In some embodiments, determining the static modeling parameters and dynamic evaluation parameters of the chip to be tested includes obtaining preset scenario requirement information and the parameters to be processed of the chip to be tested, and classifying and processing the parameters to be processed according to the scenario requirement information to obtain the static modeling parameters and the dynamic evaluation parameters. Before generating the target power consumption model, although the dynamic evaluation parameters are determined, it is still possible to generate the target power consumption model based on the scenario requirements using only the static modeling parameters without using the dynamic evaluation parameters. In the power consumption evaluation stage, the static modeling parameters are locked, and only the dynamic evaluation parameters can be modified, thereby speeding up the power consumption evaluation.

[0084] Specifically, for the chip power consumption analysis scenarios corresponding to different scenario requirement information, the fixed parameters and variable parameters of the chip will also be different, and then the parameters to be processed of the chip to be tested can be classified according to the above scenario requirement information to determine which type of parameters in the processing parameters belong to static modeling parameters and which type of parameters belong to dynamic evaluation parameters; further, the specific values ​​of the dynamic evaluation parameters need to be determined in the subsequent evaluation and input into the above target power consumption model for calculation. Specifically, when the scenario requirement information indicates that it is currently necessary to quickly evaluate the power consumption of the chip to be tested in different operating environments, the determined static modeling parameters may include the chip structure and chip behavior information in the above parameters to be processed, and the dynamic evaluation parameters may include the environmental parameters in the above parameters to be processed; when the scenario requirement information indicates that it is currently necessary to quickly evaluate the power consumption of the chip to be tested under different behaviors, the corresponding static modeling parameters may include the chip structure and environmental parameters, and the dynamic evaluation parameters may include the chip behavior information; when the scenario requirement information indicates that it is currently necessary to quickly evaluate the power consumption of the chip under different operating environments and different behaviors, the static modeling parameters may include the chip structure, and the dynamic evaluation parameters may include the environmental parameters and chip behavior information.

[0085] In some embodiments, the chip structure information may include a design constraint file (syopsys design format, abbreviated as SDC), RTL, Unified Power Format (UPF), design netlist, standard cell library, Library Exchange Format / Design Exchange Format (lef / def), standard parasitic exchange format (spef), timing information, clock tree model, and line load model, etc.; the chip behavior information may include flip rate and static probability, Fast Signal Database (FSDB), Video Compact Disc (VCD), or Switching Activity Interchange Format (SAIF) file and other data used to record chip reversal conditions, etc.; the environmental parameters may include process angle, supply voltage, on-chip temperature and frequency, etc.

[0086] Through the above embodiments, static factor information and dynamic factor information are determined based on different scenario requirement information, and then static modeling parameters and dynamic evaluation parameters are determined, so that the above embodiments can be applied to different power consumption evaluation scenarios, thereby helping to improve the accuracy and efficiency of chip power consumption evaluation.

[0087] In some embodiments, generating a target power consumption model based on the intermediate calculation result includes: obtaining model data required by a data template in the intermediate calculation result; and generating the target power consumption model based on the model data and the data template. The data template specifies the format and content of data storage and can be a visual template that can be displayed to a user upon user request.

[0088] The model data is stored according to the requirements of a data template; this data template refers to a data-free template, such as a formula or chart format, used during model generation. This data template can be pre-set, generated, and stored by the user, or it can be adaptively generated based on user-input parameters. For example, when the number of static modeling parameters currently input exceeds a certain threshold, indicating a large number of input points, a chart template such as a power consumption value-voltage relationship table or a power consumption value-frequency relationship table can be automatically generated during the modeling process. Furthermore, the data template can include a visualization template. For example, using a table template as an example, this table template can be a scalar, a multidimensional table, a function, or a description of a chip's hierarchical design structure. When outputting the power consumption evaluation results, a visualization result can be generated based on the power consumption evaluation results and the visualization template, and the visualization result can be sent to a terminal device for display. That is, after calculating the power consumption evaluation results, the power consumption evaluation result data is substituted into the visualization template, and a visualization result is adaptively generated and displayed by the terminal device. Through the above embodiment, multiple visualization templates are adaptively generated and stored based on the target power consumption model. This allows users to quickly draw and generate visualization results during power consumption analysis using these visualization templates, making it easier for users to query and understand chip power consumption assessments. Furthermore, the visible content consists of two main parts: metadata and detailed data from the target power consumption model.

[0089] In some embodiments, the target power consumption model includes model detailed data, wherein the model detailed data includes at least chip description data and intermediate calculation results corresponding to the chip description data, the chip description data is used to describe chip design information related to the intermediate calculation results, such as the chip's hierarchical structure information, power supply network information, etc., and power consumption description information corresponding to the chip design information, the power consumption description data is used to store intermediate calculation results related to the chip design information, such as the intermediate calculation results of a certain level of chip design. And / or, the target power consumption model includes model metadata; wherein the model metadata includes at least model description data, the model description data is used to describe the properties of the current target power consumption model, and the data can be used to parse the target power consumption model during the power consumption evaluation stage.

[0090] Among them, the model metadata includes but is not limited to the following: model version information, data unit information in the model, model parameters involved, model generation time, input information used when the model is generated, and model description data such as the formula template used in the model. Specifically, the model version information can be generated cumulatively based on the current number of modeling times, and is used to distinguish different model versions. For example, the model version information can be v1.0; the model data unit information and model parameters can be determined based on the static modeling parameters currently input. For example, the model data unit information can be voltage: millivolts, current: milliamperes, etc., which are used to determine the units of the data provided in the model. The model parameters may include parameters such as temperature or voltage; the input information used when the model is generated includes file names, environmental parameters, etc., so that the model can be repeatedly constructed; the above-mentioned model formula template is used to clarify the calculation method of the power consumption involved in the model. It can be understood that the above-mentioned model metadata also includes other data that is not directly related to the specific chip data, but is related to the model itself, which will not be repeated here.

[0091] The detailed data includes, but is not limited to, the following: chip description data, such as the chip top-level module name, chip power supply network information, power consumption information of each chip design level unit, and other information related to specific chip power consumption. Specifically, the chip top-level module name is used to clarify the specific module referred to by the model; the chip power supply network information is used to distinguish different power supply networks during the power consumption assessment phase. For example, the chip power supply network information may include the number and name of the VDD network; the power consumption information of each chip design level unit can be identified in the form of scalars, multidimensional tables, and functions. For example, an overall Top module contains multiple sub-modules such as A, B, and C, and each sub-module can contain its own sub-modules, such as sub-module A contains a and b. In this case, the hierarchical information and power consumption information can be recorded simultaneously, such as the power consumption data of the Top / A / a module is x, the power consumption data of the Top / A / b module is y, the power consumption data of the Top / B module is m, and the power consumption data of the Top / B module is m, so as to calculate the power consumption of modules at each level; data such as x, y, m, and n can be represented in the form of scalars, multidimensional tables, and functions. It should be noted that metadata and detailed data belong to the same model content. During the power consumption assessment process, model metadata such as model description data is mainly used to parse model data, remove duplications, and build the corresponding operation model, while detailed model data such as chip description data is used to calculate the final chip power consumption value during the power consumption assessment stage.

[0092] In some embodiments, for step S230, the above-mentioned generation of power consumption evaluation results based on the dynamic evaluation parameters and the target power consumption model also includes the following steps: determining a second mapping relationship; the second mapping relationship is at least used to indicate the correspondence between the dynamic evaluation parameters in the power consumption constraint conditions, the intermediate calculation results in the target power consumption model and the power consumption evaluation results; obtaining the power consumption evaluation results based on the dynamic evaluation parameters, the intermediate calculation results and the second mapping relationship.

[0093] In some embodiments, the second mapping relationship can be determined based on the scenario requirement information, or the second mapping relationship can be determined from the target power consumption model. In some embodiments, the power consumption constraint conditions of the intermediate calculation results and the power consumption evaluation results formed using the target power consumption model can also be used to describe and indicate the second mapping relationship, and the power consumption constraint conditions are used to represent the dynamic evaluation parameters, the calculation rules of the intermediate calculation results and the power consumption evaluation results in the target power consumption model. Since the power consumption evaluation in the embodiment is related to the scenario requirement, when the scenario requirement information is determined, it has been determined which mapping relationship is used to calculate the intermediate calculation results and the final power consumption evaluation. Alternatively, since the target power consumption model is determined based on the scenario requirement information, the second mapping relationship can also be stored in the target power consumption model, which can be directly obtained from the target power consumption model during the power consumption evaluation. For example, when the current scenario requirement is to quickly evaluate the power consumption of the chip in different operating environments and different behaviors, and determine the first mapping relationship between the static modeling parameter C and the intermediate calculation result based on the above formula 1, the target power consumption model can be established based on the first mapping relationship, and the dynamic evaluation parameters and the second mapping relationship between the intermediate calculation result and the final power consumption evaluation result can be determined based on the scenario requirement information during the power consumption evaluation. Alternatively, when the target power consumption model is generated based on the first mapping relationship, the above second mapping relationship determined according to the scenario requirement information can be stored in the target power consumption model, and the second mapping relationship can be directly obtained from the target power consumption model during the power consumption evaluation to obtain the power consumption evaluation result.

[0094] In some embodiments, the dynamic evaluation parameters may be input into the target power consumption model to obtain a power consumption evaluation result. In another embodiment, an intermediate calculation result may also be obtained from the target power consumption model, and the dynamic evaluation parameters and the intermediate calculation result may be calculated based on the calculation method indicated by the second mapping relationship according to the second mapping relationship to obtain the power consumption evaluation result.

[0095] In some embodiments, during the power consumption evaluation process, the metadata of the target power consumption model is mainly used by the evaluation tool to parse the model data, remove duplications, and build the corresponding operation model, while the detailed data of the target power consumption model is used to calculate the power consumption of the specific chip in the power consumption evaluation stage.

[0096] In some embodiments, the static modeling parameters include at least one hierarchical submodule of the chip under test, and the intermediate calculation results include the intermediate calculation results corresponding to the hierarchical submodule. That is, if the chip under test of the same design includes at least one hierarchical submodule, the static modeling parameters of each hierarchical submodule can be obtained using any of the above method embodiments, and the intermediate calculation results of each hierarchical submodule can be calculated.

[0097] In some embodiments, each of the sub-modules at this level includes multiple component units; the chip power consumption evaluation method further includes the following steps:

[0098] Step S221: For each component unit, obtain static modeling parameters corresponding to different power consumption types of the component unit, as well as first mapping relationships corresponding to different power consumption types; wherein the same power consumption type corresponds to the same first mapping relationship. The above power consumption types include but are not limited to various types such as switching power consumption, internal power consumption, static power consumption, and leakage power consumption.

[0099] Step S222 : calculating and obtaining intermediate calculation results of different power consumption evaluation types for different component units based on the static modeling parameters of the different power consumption types and the first mapping relationships corresponding to the different power consumption types.

[0100] Step S223 , merging intermediate calculation results of the same power consumption type in the same level to generate intermediate calculation results corresponding to the sub-modules of the level.

[0101] In the above steps S221 to S223, the intermediate calculation results of the same power consumption type can be summarized and compressed according to the standard unit data of the same design level in the chip through the above target power consumption model, such as merging the coefficients of multiple polynomials with the same form, so that the data volume of the power consumption model is greatly reduced. Specifically, taking the calculation of the switching power consumption of each component unit as an example, assuming that the hierarchical sub-module includes three logic gates, namely U1, U2 and U3, the switching power consumption calculation values ​​corresponding to each logic gate are calculated using the above formula 1: P S1 =C1×V 2 ×f×TR;P S2 =C2×V 2 ×f×TR;P S3 =C3×V 2 ×f×TR; in some power consumption evaluation scenarios, the static modeling parameter is the capacitor C. Through the capacitance values ​​C1, C2, and C3 corresponding to each logic gate, the intermediate calculation results for the switching power consumption type of each component unit can be obtained. The total switching power consumption calculation value of each logic gate is P S =C1×V 2 ×f×TR+C2×V 2×f×TR+ C3×V 2 ×f×TR=(C1+C2+C3)×V 2 ×f×TR. That is, in the model file, the intermediate calculation results of the three component units can be merged and recorded as a single value after calculation using the values ​​of C1+C2+C3, so as to merge the intermediate settlement results of the same power consumption type in the same hierarchy. If the static modeling parameters are capacitance C and supply voltage V, the intermediate calculation results of the three component units are merged into C1V1+C2V2+C3V3, where V1, V2, and V3 are the supply voltage values ​​corresponding to each logic gate. This allows the intermediate calculation results corresponding to the sub-modules of the aforementioned hierarchy to be obtained, rather than directly storing the three values ​​in the original data. Similarly, similar merging can be performed for power consumption assessment types such as internal power consumption and leakage power consumption, thereby achieving effective data compression.

[0102] Through the above steps S231 to S223, all static calculation values ​​are compressed through the hierarchical sub-modules to obtain compressed power consumption evaluation results, which is beneficial to reducing the data volume of the power consumption model and effectively reducing the memory space occupancy.

[0103] In some embodiments, the chip to be tested includes multiple component units; the chip power consumption detection method further includes the following steps: calculating the sub-power consumption value corresponding to the component unit based on the dynamic evaluation parameter and the target power consumption model; obtaining the identification information corresponding to the component unit, and obtaining the power consumption evaluation result based on the identification information and the sub-power consumption value; detecting the power consumption query instruction for the component unit; searching for the sub-power consumption value in the power consumption evaluation result in response to the detected power consumption query instruction, and determining the corresponding target sub-power consumption value from all the sub-power consumption values ​​based on the identification information; generating a power consumption query result based on the target sub-power consumption value, and sending the power consumption query result to the terminal device for display. Specifically, the power consumption value of each component is stored separately based on the identification information, so that when the user needs to find the power consumption value corresponding to a single component such as a single logic gate, it can be searched based on the identification information corresponding to the component unit, thereby effectively improving the convenience of the user in querying the power consumption value.

[0104] In some embodiments, the chip power consumption evaluation method further includes the following steps: obtaining the block information for the chip to be tested, determining at least two block chip areas of the chip to be tested based on the block information, and generating at least two target power consumption models corresponding to the block chip areas based on the static modeling parameters; inputting the dynamic evaluation parameters of each block chip area into the corresponding target power consumption model to obtain the power consumption evaluation result corresponding to the block chip area. The block information can be set in advance by the staff, for example, it can be set to divide a certain design chip into blocks according to the implemented functions, etc.; then, for different areas of the chip to be tested, the steps in any of the above method embodiments can be adopted to respectively establish a target power consumption model, which is conducive to improving the accuracy and efficiency of the power consumption model calculation. In another embodiment, a unified target power consumption model can also be used for simulation and power consumption evaluation of the same batch of design chips.

[0105] This embodiment further provides a chip power consumption evaluation method. FIG3 is a flow chart of another chip power consumption evaluation method according to an embodiment of the present application. As shown in FIG3 , the process includes the following steps:

[0106] Step S310, responding to the user's power consumption assessment request, obtaining a target power consumption model; wherein, the target power consumption model stores an intermediate calculation result, which is calculated based on the static modeling parameters of the chip to be tested and a first mapping relationship, and the first mapping relationship is at least used to indicate the correspondence between the static modeling parameters and the intermediate calculation result in the power consumption constraint condition, and the target power consumption model is used to form a new power consumption constraint condition that can indicate the correspondence between the intermediate calculation result and the power consumption assessment result.

[0107] Step S320, obtaining the dynamic evaluation parameters; wherein the static modeling parameters are fixed chip design parameters in the power consumption constraints describing the current power consumption scenario, and the dynamic evaluation parameters are variable chip design parameters in the power consumption constraints of the current power consumption scenario.

[0108] Step S330 : obtaining a power consumption evaluation result of the chip to be tested according to the target power consumption model and the dynamic evaluation parameters.

[0109] Through the above steps S310 to S330, during the power consumption analysis and evaluation, the dynamic evaluation parameters of the chip to be tested are input into a target power consumption model that is pre-constructed and stores intermediate calculation results generated by calculation based on the static modeling parameters of the chip to be tested. Then, the final power consumption evaluation result is calculated based on the dynamic evaluation parameters and the intermediate calculation results obtained by partial calculation, which is conducive to greatly improving the efficiency of power consumption evaluation, effectively solving the problem of low efficiency of chip power consumption detection, and realizing an efficient and accurate power consumption calculation method.

[0110] In some embodiments, the above-mentioned obtaining of power consumption evaluation results based on the dynamic evaluation parameters and the target power consumption model also includes the following steps: determining a second mapping relationship; the second mapping relationship is at least used to indicate the correspondence between the dynamic evaluation parameters, the intermediate calculation results of the target power consumption model and the power consumption evaluation results; obtaining the power consumption evaluation results based on the dynamic evaluation parameters, the intermediate calculation results and the second mapping relationship in the power consumption constraint conditions.

[0111] This embodiment also provides a method for generating a power consumption model, which includes the following steps:

[0112] Determine static modeling parameters of the chip to be tested; wherein the static modeling parameters are fixed chip design parameters in the power consumption constraint conditions that describe the current power consumption scenario.

[0113] An intermediate calculation result is calculated based on the static modeling parameter and the first mapping relationship, and a target power consumption model storing the intermediate calculation result is generated to obtain a power consumption evaluation result of the chip to be tested; wherein the first mapping relationship is at least used to indicate the correspondence between the static modeling parameter and the intermediate calculation result in the power consumption constraint condition; the power consumption evaluation result is generated based on the dynamic evaluation parameter and the target power consumption model, and the dynamic evaluation parameter is a chip design parameter that changes in the power consumption constraint condition of the current power consumption scenario.

[0114] Through the above embodiment, a target power consumption model storing intermediate calculation results is pre-constructed based on static modeling parameters and the first mapping relationship, so that in the subsequent chip power consumption simulation evaluation, only dynamic evaluation parameters need to be input, and the generated power consumption model can be relied upon to perform multiple power consumption evaluation calculations to quickly generate chip evaluation results. Therefore, when a certain element of the chip changes, there is no need to re-perform a complete calculation, which effectively improves the overall efficiency of evaluating the power consumption of the same design chip under different environments and behaviors.

[0115] In some embodiments, the target power consumption model includes model detailed data; wherein, the model detailed data includes at least chip description data and intermediate calculation results corresponding to the chip description data; and / or, the target power consumption model includes model metadata; wherein, the model metadata includes at least model description data, and the model description data is used to describe the properties of the target power consumption model.

[0116] The following describes and illustrates the embodiments of the present application through preferred embodiments. FIG4 is a flow chart of a chip power consumption evaluation method according to a preferred embodiment of the present application. As shown in FIG4 , the process includes the following steps:

[0117] Step S401, obtain the input file of the static modeling parameters required for modeling, the input file can be in text form or binary form. Further, prepare the configuration file and running script required by the modeling tool. Among them, for the above-mentioned input file, the input content can also be adaptively checked by the above-mentioned terminal device, or main control device such as server, including the integrity of the input file and the verification of the correctness of the format, so as to avoid problems such as chip power consumption evaluation errors caused by input errors. In addition, the above-mentioned configuration file is used to give configurations such as evaluation mode and log level. The above-mentioned script is used to indicate the running steps of the modeling tool, such as reading the file first, then analyzing it, etc.; examples of the running steps described in the script are: reading the input file; setting the running mode; running timing analysis; running power consumption analysis; outputting the power consumption analysis results; exporting the file.

[0118] Step S402 responds to the user's request to generate a target power consumption model by loading a modeling configuration file and running a modeling script. The modeling configuration file and modeling script are used to obtain the static modeling parameters required for power consumption modeling from the input file, perform power consumption modeling for the fixed portion, and generate intermediate calculation results. The process of loading the configuration file and running the script may not be visible, depending on whether the tool displays the loading process through logs or the interface.

[0119] Step S403: Obtain information required by the target power consumption model from the intermediate calculation results, and generate the target power consumption model.

[0120] Step S404: obtaining an input file of dynamic evaluation parameters required for power consumption evaluation detection.

[0121] Step S405, responding to the user's power consumption evaluation request, loading the power consumption evaluation configuration file, running the power consumption evaluation script, using the power consumption evaluation configuration file and the power consumption evaluation script to obtain the dynamic evaluation parameters and target power consumption model required for power consumption evaluation from the input file, and performing power consumption evaluation.

[0122] Step S406, responding to the user's power consumption evaluation request, checking the input content, the integrity of the input file, whether the input format is correct, etc., to eliminate possible problems as much as possible before formal operation; then obtaining analysis results through calculation, and finally obtaining the power consumption evaluation result.

[0123] It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0124] This embodiment also provides a chip power consumption detection device, which is used to implement the above-mentioned embodiments and preferred implementation methods. The details that have been described will not be repeated here. As used below, the terms "module", "unit", "sub-unit", etc. can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and conceivable.

[0125] Figure 5 is a structural block diagram of a chip power consumption evaluation device according to an embodiment of the present application. As shown in Figure 5, the device includes: a parameter module 52, a modeling module 54 and an evaluation module 56; the parameter module 52 is used to determine the static modeling parameters and dynamic evaluation parameters of the chip to be tested; wherein, the static modeling parameters are fixed chip design parameters in the power consumption constraints describing the current power consumption scenario, and the dynamic evaluation parameters are variable chip design parameters in the power consumption constraints of the current power consumption scenario; the modeling module 54 is used to calculate the intermediate calculation results based on the static modeling parameters and the first mapping relationship, and generate a target power consumption model storing the intermediate calculation results; wherein, the first mapping relationship is at least used to indicate the correspondence between the static modeling parameters in the power consumption constraints and the intermediate calculation results; the evaluation module 56 is used to obtain the power consumption evaluation result of the chip to be tested based on the dynamic evaluation parameters and the target power consumption model.

[0126] Through the above embodiment, the modeling module 54 models the power consumption calculation model based on the fixed static modeling parameters of the chip to be tested, generates a target power consumption model as an intermediate form, and obtains the power consumption evaluation result of the chip to be tested according to the current dynamic evaluation parameters and the target power consumption model through the evaluation module 56 during the power consumption evaluation, thereby splitting the chip power consumption analysis process into two parts: power consumption modeling and power consumption evaluation. After the modeling is completed, the subsequent power consumption evaluation steps only need to rely on the generated power consumption model, and multiple power consumption evaluation calculations can be performed by inputting relevant dynamic evaluation parameters. Therefore, significant data merging and compression are achieved based on the generated power consumption model, which greatly reduces the parameter processing cost, improves the overall efficiency of evaluating the power consumption of the same design chip under different environments and behaviors, effectively solves the problem of low efficiency of chip power consumption evaluation, and realizes an efficient and accurate chip power consumption evaluation device.

[0127] In some embodiments, the above-mentioned parameter module 52 is also used to obtain static factor information corresponding to the scenario requirement information, and determine the static modeling parameters of the chip to be tested from the static factor information; and / or, the parameter module 52 obtains dynamic factor information corresponding to the scenario requirement information, and determines the dynamic evaluation parameters of the chip to be tested from the dynamic factor information.

[0128] In some embodiments, the above-mentioned modeling module 54 is also used to determine the data template corresponding to the scenario requirement information; the modeling module 54 obtains the model data required by the data template in the intermediate calculation results; the modeling module 54 generates the target power consumption model based on the model data and the data template.

[0129] In some embodiments, the target power consumption model includes model detailed data; wherein the model detailed data includes at least chip description data and intermediate calculation results corresponding to the chip description data; and / or, the target power consumption model includes model metadata; wherein the model metadata includes at least model description data, and the model description data is used to describe the properties of the target power consumption model.

[0130] In some embodiments, the above-mentioned evaluation module 56 determines a second mapping relationship; the second mapping relationship is at least used to indicate the correspondence between the dynamic evaluation parameters in the power consumption constraint condition, the intermediate calculation results in the target power consumption model and the power consumption evaluation result; the evaluation module 56 obtains the power consumption evaluation result based on the dynamic evaluation parameters, the intermediate calculation results and the second mapping relationship.

[0131] In some embodiments, the static modeling parameters include at least one hierarchical sub-module of the chip to be tested, and the intermediate calculation results include the intermediate calculation results corresponding to the hierarchical sub-module.

[0132] In some embodiments, each of the hierarchical sub-modules includes multiple component units; the above-mentioned modeling module 54 is also used to obtain, for each of the component units, static modeling parameters corresponding to different power consumption types of the component unit, and first mapping relationships corresponding to different power consumption types; wherein the same power consumption type corresponds to the same first mapping relationship; the modeling module 54 calculates intermediate calculation results of different power consumption evaluation types for different component units based on the static modeling parameters of the different power consumption types and the first mapping relationships corresponding to the different power consumption types; the modeling module 54 merges the intermediate calculation results of the same power consumption type in the same hierarchy to generate the intermediate calculation results corresponding to the hierarchical sub-module.

[0133] In some embodiments, the chip to be tested includes multiple component units; the chip power consumption evaluation device also includes a display module; the evaluation module 56 is also used to use the target power consumption model to calculate the sub-power consumption value corresponding to the component unit according to the dynamic evaluation parameters and the target power consumption model; the evaluation module 56 obtains the identification information corresponding to the component unit, and obtains the power consumption evaluation result according to the identification information and the sub-power consumption value; the display module is also used to detect the power consumption query instruction for the component unit; the display module searches for the sub-power consumption value in the power consumption evaluation result in response to the detected power consumption query instruction, and determines the corresponding target sub-power consumption value from all the sub-power consumption values ​​based on the identification information; the display module generates a power consumption query result according to the target sub-power consumption value, and sends the power consumption query result to the terminal device for display.

[0134] In some embodiments, the chip power consumption detection device further includes a block module; the block module is used to obtain block information for the chip to be tested, and determine at least two block chip areas of the chip to be tested based on the block information; the modeling module 54 generates at least two target power consumption models corresponding to the block chip areas based on the static modeling parameters; the evaluation module 56 inputs the dynamic evaluation parameters of each block chip area into the corresponding target power consumption model to obtain a power consumption evaluation result corresponding to the block chip area.

[0135] It should be noted that the above modules can be functional modules or program modules, and can be implemented through software or hardware. For modules implemented through hardware, the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0136] This embodiment also provides a chip power consumption detection system. FIG6 is a block diagram of a chip power consumption detection system according to an embodiment of the present application. As shown in FIG6 , the system includes: a main control device 62 and a terminal device 12; the terminal device 12 is configured to obtain static modeling parameters and dynamic evaluation parameters of the chip under test and send the static modeling parameters and the dynamic evaluation parameters to the main control device 62; the main control device 62 is configured to execute the steps of any of the above-mentioned method embodiments. The main control device 62 may include, but is not limited to, various computers, servers, server clusters, or other hardware devices used to control the chip power consumption simulation and evaluation process. Furthermore, data transmission between the terminal device 12 and the main control device 62 may be performed via a transmission device. In one embodiment, the transmission device may include a network interface controller (NIC), which may be connected to other network devices via a base station to communicate with the Internet. In another embodiment, the transmission device may be a radio frequency (RF) module, which is configured to communicate with the Internet wirelessly.

[0137] Through the above embodiment, the main control device 62 first models the power consumption calculation model based on the fixed static modeling parameters of the chip to be tested, generates a target power consumption model as an intermediate form, and then inputs the dynamic evaluation parameters of the chip to be tested during power consumption evaluation. Finally, the power consumption evaluation result of the chip to be tested is obtained according to the dynamic evaluation parameters and the target power consumption model, thereby splitting the chip power consumption analysis process into two parts: power consumption modeling and power consumption evaluation. After the modeling is completed, the subsequent power consumption evaluation steps only need to rely on the generated power consumption model, and multiple power consumption evaluation calculations can be performed by inputting relevant dynamic evaluation parameters. Therefore, significant data merging and compression are achieved based on the generated power consumption model, which greatly reduces the parameter processing cost, improves the overall efficiency of evaluating the power consumption of the same design chip under different environments and behaviors, effectively solves the problem of low efficiency of chip power consumption detection, and realizes an efficient and accurate chip power consumption evaluation system.

[0138] In some embodiments, a computer device is provided, which may be a server device. FIG7 is a structural diagram of the internal structure of a computer device according to an embodiment of the present application, as shown in FIG7 . The computer device includes a processor, a memory, a network interface, and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store a target power consumption model. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a chip power consumption evaluation method is implemented.

[0139] Those skilled in the art will understand that the structure shown in FIG7 is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0140] This embodiment further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0141] Optionally, the computer device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0142] Optionally, in this embodiment, the processor may be configured to execute the following steps through a computer program:

[0143] S210, determine the static modeling parameters and dynamic evaluation parameters of the chip to be tested; wherein, the static modeling parameters are fixed chip design parameters in the power consumption constraints describing the current power consumption scenario, and the dynamic evaluation parameters are variable chip design parameters in the power consumption constraints of the current power consumption scenario.

[0144] S220, obtaining an intermediate calculation result based on the static modeling parameter and the first mapping relationship, and generating a target power consumption model storing the intermediate calculation result; wherein the first mapping relationship is at least used to indicate the correspondence between the static modeling parameter and the intermediate calculation result in the power consumption constraint condition.

[0145] S230: Obtain a power consumption evaluation result according to the dynamic evaluation result and the target power consumption model.

[0146] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and this embodiment will not be repeated here.

[0147] In addition, in conjunction with the chip power consumption evaluation method in the above embodiments, the present application embodiment can provide a storage medium for implementation. The storage medium stores a computer program; when the computer program is executed by a processor, it implements any of the chip power consumption evaluation methods in the above embodiments.

[0148] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0149] Those skilled in the art should understand that the various technical features of the above-described embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the various technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0150] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A chip power consumption evaluation method, characterized in that: The method comprises: Determine static modeling parameters and dynamic evaluation parameters of the chip to be tested; wherein the static modeling parameters are fixed chip design parameters in the power consumption constraints describing the current power consumption scenario, and the dynamic evaluation parameters are variable chip design parameters in the power consumption constraints of the current power consumption scenario; Obtaining an intermediate calculation result based on the static modeling parameter and the first mapping relationship, and generating a target power consumption model storing the intermediate calculation result; wherein the first mapping relationship is at least used to indicate a corresponding relationship between the static modeling parameter in the power consumption constraint condition and the intermediate calculation result; The power consumption evaluation result of the chip to be tested is obtained according to the dynamic evaluation parameter and the target power consumption model.

2. The chip power consumption evaluation method according to claim 1, characterized in that: Determining the static modeling parameters of the chip under test includes: acquiring static factor information corresponding to the scenario requirement information, and determining the static modeling parameters of the chip under test from the static factor information; and / or, The determining of the dynamic evaluation parameters of the chip under test includes: acquiring dynamic factor information corresponding to the scenario requirement information, and determining the dynamic evaluation parameters of the chip under test from the dynamic factor information.

3. The chip power consumption evaluation method according to claim 1, characterized in that: The generating a target power consumption model storing the intermediate calculation result comprises: Determine the data template corresponding to the scenario requirement information; Obtain the model data required by the data template in the intermediate calculation results; The target power consumption model is generated according to the model data and the data template.

4. The chip power consumption evaluation method according to claim 1, characterized in that: The target power consumption model includes model detailed data; wherein the model detailed data at least includes chip description data and intermediate calculation results corresponding to the chip description data; and / or, The target power consumption model includes model metadata; wherein the model metadata at least includes model description data, and the model description data is used to describe the attributes of the target power consumption model.

5. The chip power consumption evaluation method according to claim 1, characterized in that: The obtaining of the power consumption evaluation result according to the dynamic evaluation parameter and the target power consumption model comprises: Determine a second mapping relationship; the second mapping relationship is at least used to indicate the correspondence between the dynamic evaluation parameter in the power consumption constraint condition, the intermediate calculation result in the target power consumption model and the power consumption evaluation result; The power consumption evaluation result is obtained according to the dynamic evaluation parameter, the intermediate calculation result and the second mapping relationship.

6. The chip power consumption evaluation method according to claim 1, characterized in that: The static modeling parameters include at least one hierarchical sub-module of the chip to be tested, and the intermediate calculation results in the target power consumption model include the intermediate calculation results corresponding to the hierarchical sub-module.

7. The chip power consumption evaluation method according to claim 6, characterized in that: Each of the hierarchical sub-modules includes a plurality of component units, and an intermediate calculation result of a target power consumption model is calculated based on the static modeling parameters and the first mapping relationship, including: For each of the component units, obtain static modeling parameters corresponding to different power consumption types of the component unit, and first mapping relationships corresponding to different power consumption types; wherein the same power consumption type corresponds to the same first mapping relationship; According to the static modeling parameters of the different power consumption types and the first mapping relationships corresponding to the different power consumption types, intermediate calculation results of different power consumption evaluation types for different component units are calculated; The intermediate calculation results of the same power consumption type in the same level are merged to generate the intermediate calculation results corresponding to the sub-modules of the level.

8. The chip power consumption evaluation method according to any one of claims 1 to 7, characterized in that: The method further comprises: Acquire block information for the chip to be tested, and determine at least two block chip areas of the chip to be tested based on the block information; Obtaining an intermediate calculation result based on the static modeling parameter and the first mapping relationship, and generating a target power consumption model storing the intermediate calculation result, including: At least two target power consumption models corresponding to the chip block regions are generated based on the static modeling parameters, wherein each target power consumption model is used together with the dynamic evaluation parameters of the corresponding chip block region to obtain the power consumption evaluation result of the corresponding chip block region.

9. A chip power consumption evaluation method, characterized in that: The method comprises: In response to a user's request for power consumption assessment, a target power consumption model is obtained; wherein the target power consumption model is used to store an intermediate calculation result calculated based on a static modeling parameter of the chip to be tested and a first mapping relationship, wherein the static modeling parameter is a fixed chip design parameter in a power consumption constraint condition describing a current power consumption scenario, and the first mapping relationship is at least used to indicate a correspondence between the static modeling parameter in the power consumption constraint condition and the intermediate calculation result; Acquire dynamic evaluation parameters; wherein the dynamic evaluation parameters are chip design parameters that change in power consumption constraints of the current power consumption scenario; The power consumption evaluation result of the chip to be tested is obtained according to the dynamic evaluation parameter and the target power consumption model.

10. The chip power consumption evaluation method according to claim 9, characterized in that: The obtaining of the power consumption evaluation result according to the dynamic evaluation parameter and the target power consumption model comprises: Determine a second mapping relationship; the second mapping relationship is at least used to indicate the correspondence between the dynamic evaluation parameter in the power consumption constraint condition, the intermediate calculation result of the target power consumption model and the power consumption evaluation result; A power consumption evaluation result is obtained according to the dynamic evaluation parameter, the intermediate calculation result and the second mapping relationship.

11. A method for generating a power consumption model, characterized in that: The method comprises: Determine static modeling parameters of the chip to be tested; wherein the static modeling parameters are fixed chip design parameters in the power consumption constraint conditions that describe the current power consumption scenario; An intermediate calculation result is calculated based on the static modeling parameters and the first mapping relationship, and a target power consumption model storing the intermediate calculation result is generated to obtain a power consumption evaluation result of the chip to be tested; wherein the first mapping relationship is at least used to indicate the correspondence between the static modeling parameters in the power consumption constraint condition and the intermediate calculation result; the power consumption evaluation result is generated based on dynamic evaluation parameters and the target power consumption model, and the dynamic evaluation parameters are chip design parameters that change in the power consumption constraint condition of the current power consumption scenario.

12. The method for generating a power consumption model according to claim 11, characterized in that: The target power consumption model includes model detailed data; wherein the model detailed data at least includes chip description data and intermediate calculation results corresponding to the chip description data; and / or, The target power consumption model includes model metadata; wherein the model metadata at least includes model description data, and the model description data is used to describe the attributes of the target power consumption model.

13. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the chip power consumption evaluation method according to any one of claims 1 to 10 is implemented, or the power consumption model generation method according to claim 11 or claim 12 is implemented.

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