Data processing system, memory, data read-write method, and device

Abstract

A data processing system, a memory, a data read-write method, and a device. In the present application, a processor sends a read-write request to a memory, wherein the read-write request is used for requesting to perform data read-write on the memory, and the read-write request carries a logic address of data. After receiving the read-write request, the memory maps the logic address to target locations on BANKs of N storage particles of the memory, and performs data read-write on the target locations on the BANKs of the N storage particles, wherein the target locations on the BANKs of the N storage particles are distributed in different areas, and N target locations are not located in the same area any more, so that in the single read-write process for the memory, the error rate of the memory cannot significantly fluctuate due to different logic addresses, ensuring that the error rate of the memory is stable in a small range.

Description

A data processing system, memory, data reading and writing method and device CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the priority of the Chinese patent application filed with the State Intellectual Property Office of China on June 29, 2023, with application number 202310794233.2 and application name “A storage device”, all of which are incorporated by reference into this application; this application claims the priority of the Chinese patent application filed with the State Intellectual Property Office of China on September 15, 2023, with application number 202311199956.4 and application name “A data processing system, memory, data reading and writing method and device”, all of which are incorporated by reference into this application. Technical Field The present application relates to the field of communication technology, and in particular to a data processing system, a memory, a data reading and writing method and a device. Background Art Memory addressing usually refers to locating a certain position of a BANK in a storage particle in the memory according to the logical address sent by the processor. In some memories, the data at the logical address is usually distributed in various storage particles, and the various storage particles share the logical address. That is, in the process of memory addressing, it is necessary to determine a certain position of a BANK in each storage particle, that is, it is necessary to locate multiple positions. In fact, due to the design of the internal circuit of the memory, the BANK of the storage particle may include multiple areas with different error rate ranges. If the multiple locations are all located in the area with the highest error rate range in the BANK to which they belong when the memory is addressed, then the probability of error when reading and writing data at the logical address will double. On the contrary, if the multiple locations are all located in the area with the lowest error rate range in the BANK to which they belong when the memory is addressed, then the probability of error when reading and writing data at the logical address will be greatly reduced. It can be seen that based on the existing memory addressing method, the overall error rate of the memory will change with the change of the logical address, and the overall error rate of the memory is not stable, which also increases the difficulty of subsequently designing the memory as a memory with error correction capability. Summary of the invention The embodiments of the present application provide a data processing system, a memory, a data reading and writing method and a device for stabilizing the error rate of the memory. In a first aspect, an embodiment of the present application provides a data processing system, which includes a processor and a memory. The processor sends a read / write request to the memory, where the read / write request is used to request to read / write data to / from the memory, and the read / write request carries a logical address of the data. After receiving the read / write request, the memory maps the logical address to the target location on the BANK of the N storage particles of the memory, and reads and writes data to the target location on the BANK of the N storage particles; wherein the target locations on the BANK of the N storage particles are distributed in different areas, N is a positive integer, and the areas on the BANK are formed based on the error rate, and the error rates of different areas are different. Through the above system, for the same logical address, the memory maps the logical address to the target location on the BANK of N storage particles, and the N target locations are distributed in different areas. The N target locations are no longer located in the same area, so that in the process of a single read and write to the memory, the error rate of the memory will not fluctuate significantly due to different logical addresses, ensuring that the error rate of the memory is stable within a smaller range. In a possible implementation, the memory has an address remapping function, and the memory provides an option to enable the address remapping function. For example, before sending a read or write request, the processor sends an address remapping instruction to the memory, and the address remapping instruction is used to enable the address remapping function of the memory, so that the processor can enable the address remapping function of the memory according to actual needs. In one possible implementation, the memory includes N first address remapping modules, each storage particle corresponds to a first address remapping module, and after receiving the address remapping instruction, the control circuit controls the M first address remapping modules to be in a working state according to the address remapping instruction, where M is a positive integer and M is not greater than N. Among them, any first address remapping module in working state modifies the physical address converted from the logical address, and the modified physical address points to the target position on the BANK of the storage particle corresponding to the first address remapping module. Through the above system, the first address remapping module in working state can modify the physical address. Since the first address remapping modules corresponding to M storage particles among N storage particles can modify the physical address, the physical addresses obtained by the M storage particles are not exactly the same, further ensuring that the logical address can eventually be mapped to the target position in different areas of the N storage particles. In a possible implementation, when modifying the physical address, the first address remapping module in operation may modify the field in the physical address pointing to the row and / or column in the BANK. Through the above system, the first address remapping module in working state only needs to change some fields in the physical address to ensure that the logical address can eventually be mapped to the target position in different areas of N storage particles, and the implementation method is relatively simple. In a possible implementation, the first address remapping module that is not in working state does not modify the physical address, maintains each field in the physical address unchanged, and the physical address points to the target location on the BANK of the storage particle corresponding to the first address remapping module. Through the above system, the first address remapping module in a working state and the first address remapping module not in a working state process the physical address differently, and ultimately it can be ensured that the N physical addresses obtained by the N storage particles are different, and the target addresses of the BANKs of the N storage particles mapped with different N physical addresses will also belong to different areas. In a possible implementation, any storage particle determines a target location on the BANK of the storage particle according to the physical address obtained from the corresponding first address remapping module, and reads and writes data to the target location. The physical address obtained by the storage particle from the second address remapping module in a working state is a modified physical address, and the physical address obtained by the storage particle from the second address remapping module that is not in a working state is an original physical address. Through the above system, the physical addresses obtained by the N storage particles from the corresponding first address remapping modules are no longer completely the same, and the target positions on the BANKs of the storage particles finally determined are also different. In a possible implementation, in the foregoing description, the address remapping function of the memory is implemented by directly modifying the physical address converted from the logical address. The address remapping function of the memory can also be implemented by modifying the logical address. This implementation is described below. The control circuit includes N second address remapping modules, and each storage particle corresponds to a second address remapping module. The control circuit controls M second address remapping modules to be in a working state according to the address remapping instruction, wherein M is not greater than N. Any second address remapping module in working state modifies the logical address, and the modified logical address is mapped to the target position on the BANK of the storage particle corresponding to the second address remapping module. Through the above system, the second address remapping module in working state can modify the logical address. Since the second address remapping modules corresponding to M storage particles among N storage particles can modify the logical address, the physical addresses converted from the logical address obtained by the M storage particles are not exactly the same, further ensuring that the logical address can eventually be mapped to the target position in different areas of the N storage particles. In a possible implementation, the second address remapping module in working state modifies the field in the logical address pointing to the row and / or column in the BANK. Through the above system, the second address remapping module in working state only needs to change some fields in the logical address to ensure that the logical address can eventually be mapped to the target position in different areas of N storage particles, and the implementation method is relatively simple. In a possible implementation, the second address remapping module that is not in a working state maintains each field in the logical address unchanged. The logical address points to a target location on the BANK of the storage particle corresponding to the first address remapping module. Through the above system, the second address remapping module in a working state and the second address remapping module not in a working state process the logical address differently, and ultimately it can be ensured that the N physical addresses obtained by the N storage particles are different, and the target positions of the BANKs of the N storage particles mapped with different N physical addresses will also belong to different areas. In a possible implementation, the control circuit includes an address conversion module; the address conversion module converts the logical address obtained from the second address remapping module into a physical address; and sends the physical address to the storage particle corresponding to the second address remapping module. The logical address obtained by the address conversion module from the second address remapping module in a working state is a modified logical address, and the logical address obtained by the address conversion module from the second address remapping module that is not in a working state is an original logical address. Through the above system, the address conversion module can realize the conversion from logical address to physical address. Different logical addresses will be converted into different physical addresses, ensuring that the logical address received by the memory can be mapped to the BANKs of N storage particles and the target locations distributed in different areas. In the second aspect, the present application further provides a memory, which has the functions of implementing the first aspect and any possible implementation method, and some beneficial effects can be found in the description of the first aspect and are not repeated here. The memory includes a control circuit and N storage particles, where N is a positive integer. In the memory, the control circuit receives a read / write request sent by the processor, the read request is used to request data reading and writing to the memory, and the read / write request carries the logical address of the data. After receiving the read / write request, the control circuit converts the logical address into a physical address, and sends the physical address converted from the logical address to the N storage particles of the memory respectively, the physical address points to the target position on the BANK of the N storage particles of the memory, and the target position on the BANK of the N storage particles is distributed in different areas, and N is a positive integer. Different areas are formed based on the error rate division within the BANK, and the error rate range of different areas is different. After receiving the physical address, any storage particle reads and writes data to the target location on the BANK of the storage particle; Through the above memory, the same logical address can be mapped to the target location on the BANK of N storage particles inside the memory. These N target locations are distributed in different areas, ensuring that the error rate of the memory will not fluctuate significantly with the different logical addresses received by the memory. In a possible implementation manner, the control circuit receives an address remapping instruction sent by the processor, where the address remapping instruction is used to enable an address remapping function of the memory. In a possible implementation, the memory includes N first address remapping modules, each storage particle includes a first address remapping module, and the control circuit controls the M first address remapping modules to be in a working state according to the address remapping instruction, where M is a positive integer and M is not greater than N. Any first address remapping module in working state modifies the physical address converted from the logical address, and the modified physical address points to the target position on the BANK of the storage particle corresponding to the first address remapping module. In a possible implementation, the first address remapping module in working state modifies the field pointing to the row and / or column in the BANK in the physical address. In a possible implementation, the first address remapping module that is not in a working state maintains each field in the physical address unchanged, and the physical address points to a target location on the BANK of the storage particle corresponding to the first address remapping module. In a possible implementation, any storage particle determines a target location on the BANK of the storage particle according to the physical address obtained from the corresponding first address remapping module, and reads and writes data to the target location. The physical address obtained by the storage particle from the first address remapping module in a working state is a modified physical address, and the physical address obtained by the storage particle from the first address remapping module not in a working state is an original physical address. In a possible implementation, the control circuit includes N second address remapping modules, each storage particle corresponds to a second address remapping module, and the control circuit controls the M second address remapping modules to be in a working state according to the address remapping instruction, where M is a positive integer and M is not greater than N. Any second address remapping module in working state modifies the logical address, and the modified logical address points to the target position on the BANK of the storage particle corresponding to the second address remapping module. In a possible implementation, the second address remapping module in working state modifies the field in the logical address pointing to the row and / or column in the BANK. In a possible implementation, the second address remapping module that is not in a working state maintains each field in the logical address unchanged. The logical address is mapped to a target location on the BANK of the storage particle corresponding to the second address remapping module. In a possible implementation, the control circuit includes an address conversion module; the address conversion module converts the logical address obtained from the second address remapping module into a physical address; and sends the physical address to the storage particle corresponding to the second address remapping module. The logical address obtained by the address conversion module from the second address remapping module in a working state is a modified logical address, and the logical address obtained by the address conversion module from the second address remapping module that is not in a working state is an original logical address. In the third aspect, the present application also provides a data reading and writing method, in which the memory has the function of implementing the above-mentioned first aspect and any possible implementation method. The beneficial effects can be found in the description of the first aspect and will not be repeated here. The control circuit receives a read / write request sent by the processor, wherein the read request is used to request data reading / writing of the memory, and the read / write request carries the logical address of the data; converts the logical address into a physical address, and sends the physical address converted from the logical address to N storage particles respectively, wherein the physical address points to a target position on the BANK of the N storage particles of the memory, wherein the target positions on the BANK of the N storage particles are distributed in different areas; Any storage particle reads and writes data to a target location on the BANK of the storage particle. In a possible implementation, the control circuit may also receive an address remapping instruction sent by the processor, where the address remapping instruction is used to enable the address remapping function of the method. In a possible implementation, the memory includes N first address remapping modules, each storage particle corresponds to a first address remapping module, and the control circuit controls the M first address remapping modules to be in a working state according to the address remapping instruction, wherein M is not greater than N. Any first address remapping module in working state modifies the physical address converted from the logical address, and the modified physical address points to the target position on the BANK of the storage particle corresponding to the first address remapping module. In a possible implementation, when the working first address remapping module modifies the physical address converted from the logical address, the working first address remapping module modifies the field in the physical address pointing to the row and / or column in the BANK. In a possible implementation, the first address remapping module that is not in a working state maintains each field in the physical address unchanged. The physical address points to a target location on a BANK of a storage particle corresponding to the first address remapping module. In a possible implementation, when any storage particle reads or writes data to a target location on a BANK of the storage particle, any storage particle determines the target location on the BANK of the storage particle according to a physical address obtained from the corresponding first address remapping module, and reads or writes data to the target location. In one possible implementation, the control circuit includes N second address remapping modules, each storage particle corresponds to a second address remapping module, and when the control circuit converts the logical address into a physical address, the control circuit controls the M second address remapping modules to be in a working state according to the address remapping instruction, where M is not greater than N. Any second address remapping module in working state modifies the logical address, and the modified logical address points to the target position on the BANK of the storage particle corresponding to the second address remapping module. In a possible implementation, the second address remapping module that is not in a working state maintains each field in the logical address unchanged, and the logical address points to a target location on the BANK of the storage particle corresponding to the second address remapping module. In a possible implementation, the control circuit includes an address conversion module; the address conversion module converts the logical address obtained from the second address remapping module into a physical address; and sends the physical address to the storage particle corresponding to the second address remapping module. The logical address obtained by the address conversion module from the second address remapping module in a working state is a modified logical address, and the logical address obtained by the address conversion module from the second address remapping module that is not in a working state is an original logical address. In a fourth aspect, the present application further provides a computing device, which includes the memory mentioned in each possible implementation of the second aspect and the first aspect above, and optionally, may also include a processor. In a fifth aspect, the present application also provides a computer-readable storage medium, in which instructions are stored, and when the computer-readable storage medium is run on a computer, the computer executes the method in the third aspect and various possible implementations of the third aspect. In a sixth aspect, the present application also provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method in the third aspect and various possible implementations of the third aspect. In the seventh aspect, the present application also provides a computer chip, which is connected to a memory, and the chip is used to read and execute a software program stored in the memory, and to execute the methods in the above-mentioned third aspect and various possible implementation methods of the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS FIG1 is a schematic diagram of memory addressing in a memory; FIG2 is a schematic diagram of the structure of a data processing system provided in an embodiment of the present application; FIG3 is a schematic diagram of the structure of a memory provided by an embodiment of the present application; FIG4 is a schematic diagram of the structure of a storage particle provided by an embodiment of the present application; FIG5A is a schematic diagram of the distribution of the area within a BANK of a storage particle provided in an embodiment of the present application; 5B to 5D are schematic diagrams of mapping physical addresses within a BANK of a storage particle provided in an embodiment of the present application; 6A-6B are schematic diagrams showing the distribution of a BANK of a storage particle provided in an embodiment of the present application; FIG7 is a schematic diagram of a data reading and writing method provided in an embodiment of the present application; FIG8 is a schematic diagram of the structure of a memory provided by an embodiment of the present application; FIG. 9 is a schematic diagram of a data reading and writing method provided in an embodiment of the present application. DETAILED DESCRIPTION Before introducing the data processing system, memory, data reading and writing method and device mentioned in the embodiments of the present application, the memory addressing method involved in the embodiments of the present application is first explained. Memory addressing mode: Generally, a memory used as a memory may include a plurality of memory chips, and the memory may be a phase change memory (PCM), a dynamic random access memory (DRAM), or other types of memory. From the hardware structure, the storage particle is the smallest physical unit for storing data in the memory. The storage space inside any storage particle can be further divided. Each storage particle includes multiple BANKs. Each BANK can be regarded as a storage matrix, which is like a grid array. This "grid array" has many columns and many rows. When you need to get a certain data in the storage space, you only need to specify the BANK, the row in the BANK, and the column. The size, number of rows, and number of columns of each BANK are relatively fixed, that is, the logical address range covered by each BANK is fixed. In memories such as PCM or DRAM, multiple storage particles included in the memory share the same set of logical addresses. That is, after receiving a read or write request carrying a logical address, the control circuit inside the memory converts the logical address into a physical address and sends the physical address to each storage particle. The address decoding circuit deployed in each storage particle will parse the physical address, parse out the address information pointing to the bank, column, and row, and read and write data to the bank, column, and row pointed to by the address information. As shown in FIG1 , it is a schematic diagram of memory addressing in a memory. FIG1 exemplarily shows the addressing mode of a storage particle in the memory, and an address register is provided in the storage particle. The address register is used to receive a physical address sent from the control circuit of the memory. After receiving the physical address, the address register sends the received physical address to the address decoding circuit in the storage particle. The address decoding circuit can determine the address information pointing to the BANK, column, and row from the received physical address, and then locate the BANK in the storage particle, and the row or column in the BANK. Specifically, the address decoding circuit includes a BANK control logic, a column address decoding logic, and a row address decoding logic. After receiving the physical address, the address register can send the portion of the physical address representing the BANK (such as 4 bits) to the BANK control logic, send the portion of the logical address representing the column (such as 15 bits) to the column address decoding logic, and send the portion of the logical address representing the row (such as 11 bits) to the row address decoding logic. The BANK control logic parses the address information pointing to the BANK based on the received portion of the physical address, the column address decoding logic parses the address information pointing to the column based on the received portion of the physical address, and the row address decoding logic parses the address information pointing to the row based on the received portion of the physical address. When the memory includes 8 storage particles, each storage particle can contribute part of the data, such as each storage particle contributes 8 bytes of data, so that the amount of data read and written in each data read and write operation is the sum of the amount of data contributed by each storage particle, such as the amount of data read and written in a data read and write operation is 64 bytes of data. The data at the logical address is physically distributed in each storage particle of the memory. Since the physical address parsed by the address decoding circuit of each storage particle is converted based on the same logical address, the final parsed address information pointing to the bank, column, and row is usually the same. In other words, the logical address will be mapped to the same position inside each storage particle, or it can be understood that the same physical address will be mapped to the same position inside each storage particle. Due to the influence of factors such as the routing method of the internal circuit of the memory and the design method of the driving voltage inside the memory, the error rates of different areas in the BANK of each storage particle are different, that is, each BANK can be further divided into multiple areas according to the error rate, and the range of the error rate in each area is the same, while the range of the error rate in different areas is different. That is, each BANK of the storage particle includes an area with a high error rate, an area with a low error rate, and an area with a moderate error rate. If the position in the BANK to which the logical address is mapped transmits an area with a high error rate, then the error probability of data reading and writing at this position is high, that is, the data read or written may have errors. If the position in the BANK to which the logical address is mapped transmits an area with a low error rate, then the error probability of data reading and writing at this position is low, that is, the data read or written is not prone to errors. Among them, the error rate indicates the probability of erroneous data appearing when reading and writing data at this position or area. In the embodiments of the present application, the specific method of calculating the error rate is not limited. The error rate of a certain position or a certain area can be equal to the ratio of the number of erroneous bits in data read and write operations performed a set number of times to the total number of bits read and written by the set number of data read and write operations, or it can be equal to the ratio of the number of erroneous bits in multiple data read and write operations performed in a unit time to the total number of bits read and written by the set number of data read and write operations. It can be seen that the same logical address (or the physical address converted from the logical address) will eventually be mapped to the same position of a BANK in each storage particle. Since the positions are the same, the error rate range of the area to which the position belongs will also be the same. If the error rate of the area to which it belongs is high, then the error rate of reading and writing data from the logical address will double. That is, in this memory addressing mode, when reading and writing data to the memory, the overall error rate of the memory will change with the area where the data is located, which is relatively unstable. In addition, in order to reduce the overall error rate of the memory, an error correction circuit will be added to the memory, and the unstable error rate will also increase the difficulty of setting the error correction circuit. To this end, the memory mentioned in the present application has an address remapping function. When the memory with this function maps the logical address, the position of the BANK of each storage particle to which the logical address is mapped may be different, that is, the position in each BANK to which the logical address is mapped no longer belongs to the same area with the same error rate range, and the position in each BANK to which the logical address is mapped may be distributed in multiple areas. In this way, the error rates of the positions in each BANK to which the logical address is mapped are no longer exactly the same. The address remapping function of the memory has two implementation methods. One implementation method is to process the physical address after the received logical address is converted to each storage particle in the memory. The address remapping function of the memory is implemented with the help of a first address remapping module inside the storage particle (the first address remapping module is used to modify the physical address). Another implementation method is that the control circuit in the memory converts the logical address into a non-completely identical physical address, and sends the non-completely identical physical address to each storage particle respectively. The memory The address remapping function is implemented with the help of the second address remapping module inside the control circuit (the second address remapping module is used to modify the logical address). Regardless of which implementation method is adopted, the final effect is that the same logical address is finally mapped to different positions in the BANK of each storage particle. In this way, when reading and writing data to the memory, the overall error rate of the memory will not fluctuate greatly with the area where the data is located, and the overall error rate of the memory is relatively stable. The first implementation method: the address remapping function of the memory is implemented by means of a first address remapping module inside the storage particle. The data processing system provided by the embodiment of the present application is described below in conjunction with the accompanying drawings. As shown in Figure 2, it is a structural diagram of a data processing system provided by the embodiment of the present application. The data processing system 10 includes a processor 100 and a memory 200. The processor 100 is the computing core of the system. The processor 100 can perform major data computing operations. When performing data computing operations, the processor 100 can access the memory 200 to read data or write data in the memory 200. For example, the processor 100 can read data from the memory 200 and perform data computing on the read data; the processor 100 can also store data generated after data computing in the memory 200. When accessing the memory 200 , the processor 100 sends a read / write request to the memory 200 . The read / write request carries a logical address of the data to instruct the memory 200 to read / write the data at the logical address. In the embodiment of the present application, in addition to being able to access the memory 200, the processor 100 can also enable an address remapping function of the memory 200. For example, the processor 100 can send an address remapping instruction to the memory 200, and the address remapping instruction is used to enable the address remapping function of the memory 200. The processor 100 may be a central processing unit (CPU) or other specific integrated circuits. The processor 100 may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The memory 200 has a data storage function. The memory 200 can store data required by the processor 100 for data calculation, and can also store data generated after the processor 100 performs data calculation. Exemplarily, the memory 200 receives and processes read and write requests from the processor 100, reads and writes data to the logical address, writes the data calculated by the processor 100 to the logical address, or reads the data required by the processor 100 for data calculation from the logical address, and feeds the read data back to the processor 100. In the embodiment of the present application, the memory 200 also has an address remapping function. The memory 200 can map the logical address to the target locations of multiple BANKs. The target locations of the multiple BANKs are distributed in multiple areas, where different areas correspond to different error rate ranges. Externally, the memory 200 may provide an option to enable the address remapping function, that is, the memory 200 allows a device outside the memory 200 to enable the address remapping function. When the address remapping function is enabled, the memory 200 may map the received logical address to the target locations of multiple BANKs, and the target locations of the multiple BANKs are distributed in multiple areas. When the address remapping function is not enabled, the memory 200 may map the received logical address to the same location of multiple BANKs. The embodiment of the present application does not limit the manner in which the memory 200 provides the enabling option of the address remapping function. For example, the device of the memory 200 is configured with an enabling switch of the address remapping function, and the user can turn on or off the enabling switch of the address remapping function according to actual needs. For another example, the memory 200 is configured with a parsing function of the address remapping instruction, and a device outside the memory 200 can send an address remapping instruction to the memory 200, and the memory 200 enables the address remapping function by parsing the received address remapping instruction. In addition, in the case of enabling the address remapping function, the memory 200 can also provide a variety of different address remapping strategies. Any address remapping strategy describes part or all of the following information: The number of first address remapping modules 222 in working state; Any modification method of the first address remapping module 222 in working state to the physical address after the logical address is converted. Different address remapping strategies may describe different numbers of first address remapping modules 222 in operation and / or different ways of modifying the physical address after logical address conversion by any first address remapping module 222 in operation. Correspondingly, the embodiments of the present application do not limit the manner in which the memory 200 provides a plurality of different address remapping strategies. For example, a plurality of selection buttons for different address remapping strategies are configured on the memory 200, and the user can select an address remapping strategy through the selection button according to actual needs. For another example, the memory 200 is configured with a parsing function for address remapping instructions. In addition to indicating enabling the address remapping function, the address remapping instructions sent to the memory 200 by a device outside the memory 200 can also indicate a certain address remapping strategy. The memory 200 enables the address remapping function by parsing the received address remapping instructions, and performs address remapping using the address remapping strategy indicated in the address remapping instructions. Of course, in actual applications, the address remapping function can also be enabled before the memory 200 leaves the factory, that is, the memory 200 leaves the factory. After that, the address remapping function is enabled and no additional operation is required. The structure of the memory 200 is described below in conjunction with FIG3 . As shown in FIG3 , a memory 200 provided in an embodiment of the present application includes a control circuit 210 and a plurality of storage particles 220 . The description of the storage particles 220 can be found in the above description and will not be repeated here. In the memory 200, the storage particles 220 are mainly used to store data, and the control circuit 210 is the control center of the memory 200. The control circuit 210 can process the read and write requests received by the memory 200. That is, the control circuit 210 can parse the logical address carried in the read and write request, and read and write data to each storage particle 220 according to the logical address. In the embodiment of the present application, the control circuit 210 can convert the logical address into a physical address, and send the physical address to each storage particle 220. In any storage particle 220, the physical address points to a target location of a BANK of the storage particle 220. When the memory 200 enables the address remapping function, the target locations of the multiple BANKs are distributed in different areas, and different areas correspond to different error rate ranges. When the memory 200 does not enable the address remapping function, the target locations of the multiple BANKs are distributed in the same area. Optionally, when the memory 200 provides an enable option for the address remapping function, the control circuit 210 can detect the enable state of the address remapping function, that is, determine whether the address remapping function is enabled. For example, when the device of the memory 200 is configured with an enable switch for the address remapping function, the control circuit 210 can detect the enable switch for the address remapping function to determine whether the address remapping function is enabled. For another example, when the memory 200 is configured with a parsing function for an address remapping instruction, the parsing function can be implemented by the control circuit 210, and the control circuit 210 can parse the received address remapping instruction to enable the address remapping function. In the subsequent description, only the case where the memory 200 enables the address remapping function is described. For the case where the memory 200 does not enable the address remapping function, the method of reading and writing data on the logical address inside the memory 200 can refer to the method shown in Figure 1, and will not be repeated here. From the memory addressing method shown in Figure 1, it can be seen that when the logical address is mapped to each storage particle 220, the control circuit 210 needs to convert the logical address to obtain the corresponding physical address, and then transmit the physical address to each storage particle 220. Each storage particle 220 parses the physical address to determine the address information pointing to the BANK, row, and column, and then locates the position in the BANK according to the address information pointing to the BANK, row, and column. In the embodiment of the present application, different storage particles 220 may adopt different parsing methods when parsing the physical address, and the address information pointing to the bank, row, and column obtained by adopting different parsing methods is not completely the same. Here, not completely the same means that the address information of the bank, row, and column obtained by adopting different parsing methods is completely different or partially different. Assume that when the same physical address is parsed in two different ways, two sets of address information can be generated, each set of address information includes address information pointing to a bank, a row, and a column. If the address information pointing to the bank in the two sets of address information is the same, and the address information pointing to the row and column is completely different, then the two sets of address information will correspond to two different positions on the bank, and the areas where the two positions are located may also be different. If the address information pointing to the bank and the row in the two sets of address information is the same, and the address information pointing to the column is different, then the two sets of address information will correspond to different positions on a bank, and the areas where the two positions are located may also be different. When the memory 200 enables the address remapping function, in order to ensure that the target locations of multiple BANKs to which the logical address is mapped are distributed in different areas, the storage particles 220 may use completely different parsing methods for the physical address to obtain multiple sets of non-completely identical address information. That is, in multiple storage particles 220, the storage particles 220 may convert the physical address into multiple sets of non-completely identical address information, and the multiple sets of non-completely identical address information correspond to different target locations in multiple BANKs. In this way, the target locations of the multiple BANKs will no longer belong to the same area. In the embodiments of the present application, "not completely the same" means two situations, one is partially the same and partially different, and the other is completely different. The parsing methods adopted by each storage particle 220 for the physical address may be partially different, so as to obtain multiple sets of address information that are not completely the same, that is, for some storage particles 220 in the multiple storage particles 220, one parsing method is used to parse the logical address for the physical address, and finally multiple sets of identical address information are obtained, and for another part of the storage particles 220 in the multiple storage particles 220, another parsing method is used to parse the logical address for the physical address, and finally multiple sets of identical address information are obtained. In this way, for the multiple sets of address information that are not completely the same that are finally obtained, a part of the multiple sets of address information corresponds to the same target location in multiple BANKs, and another part of the multiple sets of address information corresponds to the same another target location in multiple BANKs. For example, each storage particle 220 adopts two different parsing methods for the physical address, wherein the storage particles 220-1, 220-2, 220-3, and 220-4 adopt one parsing method, and the storage particles 220-5, 220-6, Storage particles 220-7 and 220-8 adopt another parsing method, then the four sets of address information obtained by parsing in storage particles 220-1, 220-2, 220-3, and 220-4 are the same, and point to target positions A on a certain BANK in storage particles 220-1, 220-2, 220-3, and 220-4 respectively. The positions of each target position A in the BANK to which it belongs are the same, that is, the same target position in multiple BANKs. The four sets of address information obtained by parsing in storage particles 220-5, 220-6, 220-7, and 220-8 are the same, and point to target positions B on a certain BANK in storage particles 220-5, 220-6, 220-7, and 220-8 respectively. The positions of each target position B in the BANK to which it belongs are the same, that is, the same target position in multiple BANKs. The embodiment of the present application does not limit the specific parsing method adopted by the storage particle 220 for the physical address. Any method that can parse the physical address into address information pointing to BANK, row, and column is applicable to the embodiment of the present application. For example, in the process of parsing the physical address, the storage particle 220 can modify some fields of the physical address, and then analyze the modified physical address based on the first mapping relationship to generate address information pointing to BANK, row, and column. The first mapping relationship records the correspondence between each field in the physical address and BANK, row, and column. The structure and specific functions of the memory 200 are described below. As shown in Figure 4, it is a structural diagram of a memory 200 provided in an embodiment of the present application. The memory 200 includes a control circuit 210 and a plurality of storage particles 220. Each storage particle 220 includes an address register 221, a first address remapping module 222, and an address decoding circuit 223. The address register 221 is a register with a storage function, the first address remapping module 222 and the address decoding circuit 223 can be logic circuits. The embodiment of the present application does not limit the specific internal structure of the first address remapping module 222 and the address decoding circuit 223. Any logic circuit that can implement the corresponding function can be used as the first address remapping module 222 and the address decoding circuit 223. In each storage particle 220, the first address remapping module 222 is set between the address register 221 and the address decoding circuit 223, that is, the physical address sent by the address register 221 to the address decoding circuit 223 will first pass through the first address remapping module 222. After the first address remapping module 222 processes the physical address, it can send the physical address after the processing operation to the address decoding circuit 223. The first address remapping module 222 can perform one of two processing operations on the physical address, one is to modify the physical address, and the other is to maintain the various fields in the physical address unchanged. In particular, the first address remapping module 222 in the working state can modify the physical address, and the first address remapping module 222 in the non-working state maintains the various fields of the physical address unchanged. For any storage particle 220, the address register 221 is used to store the physical address sent by the control circuit 210. Generally, when the control circuit 210 sends the physical address, it needs to go through multiple clock cycles to send the complete physical address to the storage particle 220. That is, the amount of data transmitted by the control circuit 210 in one clock cycle is limited. The control circuit 210 can send the fields included in the physical address to the storage particle 220 in multiple times, and the address register 221 can receive and cache the fields included in the physical address sent by the control circuit 210. For example, the control circuit 210 can send a 6-bit address in each clock cycle, and the total length of the physical address is 48 bits. The control circuit 210 can send the 48-bit physical address to the storage particle 220 through 8 clock cycles. The address register 221 caches the 6 bits every time it receives 6 bits until the cached data amount reaches 48 bits. After the address register 221 receives all addresses included in the physical address, the address register 221 may send the physical address to the first address remapping module 222 . After receiving the physical address sent by the address register 221, the first address remapping module 222 may perform a processing operation on the physical address, and send the physical address after the processing operation to the address decoding circuit 223. The embodiment of the present application does not limit the way in which the first address remapping module 222 modifies the physical address. For example, the first address remapping module 222 may invert some fields in the physical address, or for another example, the first address remapping module 222 may subtract some fields in the physical address from a preset value to obtain a difference, and use the difference to replace the part of the fields in the physical address. After obtaining the physical address from the first address remapping module 222, the address decoding circuit 223 can analyze the physical address based on the first mapping relationship to obtain address information pointing to the BANK, row, and column, and then determine the target location on the BANK in the storage particle 220, and read and write data to the target address. The embodiment of the present application does not limit the specific implementation method of the address decoding circuit 223 obtaining the address information pointing to the BANK, row, and column from the physical address, and any method of analyzing the physical address to obtain the address information pointing to the BANK, row, and column is applicable to the embodiment of the present application. Specifically, the address decoding circuit 223 includes a BANK control logic, a column address decoding logic, and a row address decoding logic. After modifying the physical address, the first address remapping module 222 can send the part of the modified physical address that represents the BANK (such as 4 bits) to the BANK control logic, send the part of the physical address that represents the column (such as 15 bits) to the column address decoding logic, and send the part of the physical address that represents the row (such as 11 bits) to the row address decoding logic. The BANK control logic receives the received The address information pointing to the BANK is obtained according to the partial physical address received, the column address decoding logic obtains the address information pointing to the column according to the partial physical address received, and the row address decoding logic obtains the address information pointing to the column according to the partial physical address received. After obtaining the address information pointing to the bank, row and column, the address decoding circuit 223 can locate the target position of the bank and realize data reading and writing by changing the working voltage of the device in the target position. As can be seen from FIG. 1 , the address register 221 will send the physical address to the address decoding circuit 223, and the address decoding circuit 223 can parse the received physical address to obtain the address information pointing to the bank, row, and column. In the embodiment of the present application, a first address remapping module 222 is added before the address decoding circuit 223, and the first address remapping module 222 added before the address decoding circuit 223 can modify the physical address received by the address decoding circuit 223, so that the address decoding circuit 223 can parse the modified physical address. In this way, the modification method only needs to add part of the circuit logic to the original design of the memory 200, and the modification method is simple and low in cost. Based on the control circuit 210 shown in FIG. 4 , several specific ways in which the memory 200 implements the address remapping function are listed below. Before introducing these specific implementations, it is assumed that after testing the memory 200, it is determined that the BANK of the memory 200 includes three areas, and the error rate range corresponding to each area is different. For the convenience of explanation, these three areas are respectively called AREA1, AREA2, and AREA3. The physical address distribution within these three areas can be shown in Table 1. Table 1 Wherein, ADDR[M] represents the Mth bit of the physical address, and ADDR[M:N] represents the Nth to Mth bits of the physical address. For example, ADDR[1]=0 represents the first bit of the physical address is 0. ADDR[2:8]+ADDR[9:31]>=40 represents that the sum of the second to eighth bits of the physical address and twice the number of bits from the ninth to the 31st bits of the physical address is greater than or equal to 40. As shown in Figure 5A, it is a schematic diagram of the distribution of AREA1, AREA2, and AREA3 in a BANK, where AREA1 is located below the BANK, AREA3 is located above the BANK, and AREA2 is located in the middle of the BANK. After testing, among the three areas, the error rate of AREA1 is the highest, the error rate of AREA2 is in the middle, and the error rate of AREA3 is the lowest. It should be noted that the division of regions with different error rate ranges in the BANK is related to multiple factors such as the routing of the control circuit 210 inside the memory 200 and the design of the driving voltage in the memory 200. The number of regions included in the BANK and the error rate range of each region will be related to the specific design of the memory 200. In addition, during specific tests, the number of regions with different error rate ranges in the BANK and the error rate range of each region will also change due to the setting of test parameters. For example, during specific tests, when a higher accuracy or more error rate gears can be selected, the number of regions included in the BANK may also increase. Table 1 only lists one possible distribution. For any storage granule 220 , the memory 200 can implement address remapping in the following two ways. Method 1: Map the physical address pointing to a location in the AREA1 area in the BANK of the storage particle 220 to the target location in the AREA3 area. The rows of the locations in AREA1 and AREA3 are different, so the mapping from AREA1 to AREA3 requires changing the field representing the row in the physical address. The first address remapping module 222 modifies the fields representing rows and columns in the physical address, so that the address information pointing to BANK, row, and column obtained according to the modified physical address will change from the address information pointing to BANK, row, and column obtained according to the physical address before modification. For example, the field ADDR'[15:12] representing the row in the modified physical address satisfies: ADDR'[15:12]=40-ADDR[15:12] As shown in FIG5B , the address register 221 sends the physical address to the first address remapping module 222. After the first address remapping module 222 modifies the field representing the row of the physical address, the physical address pointing to a location in the AREA1 area of ​​the BANK of the storage particle 220 will be mapped to the target location in the AREA3 area. Method 2: Map the physical address pointing to a certain location in the AREA1 area in the BANK of the storage particle 220 to the target location in the AREA2 area. The simplest way to map from AREA1 to AREA2 is to change the field representing the row, or the field representing the row and column in the physical address. 1) Change the field representing the row in the physical address. The first address remapping module 222 can modify the field representing the row in the physical address, so that the address information pointing to the bank, row, and column obtained according to the modified physical address will change from the address information pointing to the bank, row, and column obtained according to the physical address before modification. That is, the first address remapping module 222 only needs to modify the field representing the row in the physical address. For example, the first address remapping module 222 can invert one or more bits in the field representing the row in the physical address, such as inverting one bit ADDR in the field representing the row in the physical address.

[0016] Invert, that is, the bit ADDR'

[0016] representing the row in the modified physical address satisfies: ADDR'

[0013] =invADDR

[0016] . As shown in FIG5C , in the control circuit 210, the address register 221 sends the row field in the physical address to the first address remapping module 222. After the first address remapping module 222 modifies the row field in the physical address, the physical address pointing to a location in the AREA1 area in the BANK of the storage particle 220 will be mapped to the target location in the AREA2 area. 2) Change the fields representing rows and columns in the physical address. The first address remapping module 222 can modify the fields representing rows and columns in the physical address, so that the address information pointing to the bank, row, and column obtained according to the modified physical address will change from the address information pointing to the bank, row, and column obtained according to the physical address before the modification. That is, the first address remapping module 222 only needs to modify the fields representing rows and columns in the physical address. For example, the first address remapping module 222 can invert one or more bits in the field representing the column in the physical address, such as inverting one bit ADDR

[0023] in the field representing the column in the physical address, that is, one bit ADDR'

[0023] representing the column in the modified physical address, which satisfies: ADDR'

[0023] =invADDR

[0023] . The first address remapping module 222 can invert one or more bits in the field representing the row in the physical address, such as inverting one bit ADDR

[0016] in the field representing the row in the physical address, that is, one bit ADDR'

[0016] representing the row in the modified physical address, which satisfies: ADDR'

[0013] =invADDR

[0016] . As shown in FIG5D , in the control circuit 210, the address register 221 sends the column field in the physical address to the first address remapping module 222. After the first address remapping module 222 modifies the column field in the physical address, the physical address pointing to a location in the AREA1 area in the BANK of the storage particle 220 will be mapped to the target location in the AREA2 area. The specific way in which the first address remapping module 222 modifies the physical address is only an example. In practical applications, the way in which the first address remapping module 222 modifies the physical address can be designed according to the location of the fields representing rows and columns in the physical address and the distribution of areas with different error rate ranges. In addition, in practical applications, in view of the different designs of the storage particles 220, the BANKs inside the storage particles 220 may be arranged in a planar manner, that is, the BANKs included in the storage particles 220 are located in the same plane. The BANKs inside the storage particles 220 may also be arranged in a three-dimensional manner, that is, a certain BANK in the storage particles 220 may include multiple stacked layers. FIG6A is a schematic diagram showing that the BANKs inside the storage particle 220 are arranged in a planar manner, and the BANKs inside the storage particle 220 are in the same plane. In this arrangement, the areas in the BANKs inside the storage particle 220 are all located in the same plane, that is, when performing address remapping, the field representing the row / or column in the physical address can be changed. 6B is a schematic diagram showing that the BANKs in the storage particle 220 are arranged in a three-dimensional manner, and each BANK in the storage particle 220 includes two layers, an upper layer and a lower layer. Here, the BANK includes two layers as an example, but in fact, the BANK may also include three layers or even more layers. Each layer of the BANK may include multiple different areas, and the error rate range corresponding to each area is also different. In addition, due to the internal design of the memory 200 and other factors, the error rate ranges of the relative areas in the upper and lower layers of the BANK may also be different. The relative areas refer to two areas with relative positions in the same BANK. In this arrangement, the physical address usually includes a field representing the middle layer of the bank, in addition to changing the physical address table In addition to implementing address remapping by using row and / or column fields, address remapping can also be implemented by changing the field representing the BANK layer in the physical address. In the above description, only several possible specific ways of implementing address remapping are listed by way of example. In the embodiment of the present application, there is no limitation on the way of modifying each field in the physical address when the control circuit 210 implements address remapping. Any way of modifying the physical address that implements mapping from a physical address pointing to a location in one area to a location in another area is applicable to the embodiment of the present application. In addition, in some scenarios, the error rates at the same row and column positions in different BANKs are also different, that is, the error rates at the same position in different BANKs may also be different. In such scenarios, when the first address remapping module 222 modifies the physical address, it can also modify the bit representing the BANK in the physical address, and the modification method is similar to the method in which the first address remapping module 222 modifies the bit representing the row or column in the physical address, which will not be repeated here. Based on the control circuit 210 shown in FIG4 , when the memory 200 enables the address remapping function, it is not necessary for all first address remapping modules 222 in the memory 200 to be in a working state. That is, when the memory 200 enables the address remapping function, it is only necessary to ensure that some of the first address remapping modules 222 among the multiple first address remapping modules 222 can modify the received physical address. The other first address remapping modules 222 do not need to modify the received physical address, and after receiving the physical address, the physical address can be directly sent to the address decoding circuit 223. For example, if the memory 200 includes N storage particles, the memory 200 will also include N first address remapping modules 222. M first address remapping modules 222 can be enabled in the memory 200 and are in working state, where M is a positive integer less than N. Whether the first address remapping module 222 in the memory 200 is in a working state can be set by the control circuit 210 itself. For example, after receiving an address remapping instruction, the control circuit 210 can control the first address remapping modules 222 among the multiple first address remapping modules 222, whose number is equal to the set value, to be in a working state. Whether the first address remapping modules 222 in the memory 200 are in a working state and which first address remapping modules 222 are in a working state can also be set before the memory 200 leaves the factory, that is, some of the multiple first address remapping modules 222 are set to a working state before leaving the factory. Whether the first address remapping module 222 in the memory 200 is in a working state, and the first address remapping module 222 in a working state may also be indicated by the processor 100. For example, in addition to indicating the enabling of the address remapping function, the address remapping instruction sent by the processor 100 also carries an address remapping strategy, which indicates the number of the first address remapping modules 222 in a working state (such as M). The control circuit 210 can control some of the first address remapping modules 222 in the multiple first address remapping modules 222 to be in a working state, and the number of the first address remapping modules 222 meets the instruction of the address remapping instruction. For another example, the address remapping instruction sent by the processor 100, in addition to indicating enabling the address remapping function, also indicates the working status of the first address remapping module 222, that is, it informs which first address remapping modules 222 need to be in a working state. The control circuit 210 can control some of the multiple first address remapping modules 222 to be in a working state, and these some first address remapping modules 222 are the first address remapping modules 222 indicated by the address remapping instruction. In addition, if the address remapping strategy also indicates how the first address remapping module 222 in working state modifies the physical address, the control circuit 210 can also control the first address remapping module 222 in working state to modify the received physical address using the modification method indicated by the address remapping strategy. Of course, in actual applications, if each first address remapping module 222 in a working state modifies the physical address in a different way, the memory 200 can also control all the first address remapping modules 222 to be in a working state. Since each first address remapping module 222 in a working state modifies the physical address in a different way, the physical address processed by the first address remapping module 222 in each storage particle 220 (that is, the modified physical address) will not be exactly the same. The multiple not exactly the same physical addresses will point to the target position in the BANK of each storage particle 220. In the control circuit 210 shown in FIG4 , a corresponding first address remapping module 222 is provided for each storage particle 220. In practical applications, the memory 200 may also only provide the first address remapping module 222 for some storage particles 220. The first address remapping module 222 may be set to a working state before leaving the factory, or when the processor 100 sends an address remapping instruction indicating enabling the address remapping function, the control circuit 210 controls the included first address remapping module 222 to be in a working state. The data reading and writing method provided by the present application is described below in conjunction with Figure 7. Here, the memory 200 provides an enable option for the address remapping function as an example for description. If the memory 200 does not provide an enable option for the address remapping function, steps 700 to 701 can be omitted. Step 700: The processor 100 sends an address remapping instruction to the memory 200. The address remapping instruction is used to indicate enabling of the address remapping function. The address remapping instruction also indicates the first address remapping module 222 that needs to be in working state. Step 701: The memory 200 receives the address remapping instruction, and controls the first address remapping module 222 indicated by the address remapping instruction to be in a working state according to the address remapping instruction. Step 702: The processor 100 sends a read / write request to the memory 200, where the read / write request carries the logical address of the data. Step 703 : the memory 200 receives the read / write request, and maps the logical address to a target location on the BANK of the storage particle 220 in each storage particle 220 of the memory 200 . Inside the memory 200, after converting the logical address into a physical address, the control circuit 210 sends the physical address to each storage particle 220. The internal address register 221 of each storage particle 220 receives the physical address sent by the control circuit 210, and sends the physical address to the first address remapping module 222 of each storage particle 220. For the first address remapping module 222 in a working state, the first address remapping module 222 modifies the physical address and sends the modified physical address to the address decoding circuit 223 of the storage particle 220. The address decoding circuit 223 analyzes the modified physical address to obtain the address information of the execution bank, row, and column, and then locates the target position on the bank according to the address information. For the first address remapping module 222 that is not in working state, the first address remapping module 222 sends the received physical address to the address decoding circuit 223 of the storage particle 220. The address decoding circuit 223 analyzes the obtained physical address to obtain the address information of the execution bank, row, and column, and then locates the target position on the bank according to the address information. Step 704 : the memory 200 reads and writes data to the target location on the BANK of each storage particle 220 . When the read / write request is a read request for reading data, the memory 200 reads data from the target location on the BANK of each storage particle 220 , aggregates the data read from each storage particle 220 , and feeds it back to the processor 100 . When the read-write request is a write request requesting to write data, the memory 200 writes the data carried by the write request at the target location on the BANK of each storage particle 220, wherein the data written at each target location is part of the data carried by the write request, and the data written at all target locations is the data carried by the write request. Second implementation manner: the address remapping function of the memory 200 is implemented by means of the second address remapping module 211 inside the control circuit 210 . In this implementation, the structure of a data processing system 10 provided in an embodiment of the present application and the functions of the processor 100 and the memory 200 in the data processing system are similar to the data processing system shown in Figure 2. For details, please refer to the above description and will not be repeated here. The difference is that, in this implementation, for the case where the address remapping function is enabled, the memory 200 can also provide a variety of different address remapping strategies to the outside. Any address remapping strategy describes part or all of the following information: The number of second address remapping modules 211 in working state; A method of modifying a logical address by any second address remapping module 211 in working state. Different address remapping strategies may describe different numbers of the second address remapping modules 211 in operation and / or different ways in which any second address remapping module 211 in operation modifies the physical address after the logical address is converted. Correspondingly, the embodiments of the present application do not limit the manner in which the memory 200 provides a plurality of different address remapping strategies. For example, a plurality of selection buttons for different address remapping strategies are configured on the memory 200, and the user can select an address remapping strategy through the selection button according to actual needs. For another example, the memory 200 is configured with a parsing function for address remapping instructions. In addition to indicating enabling the address remapping function, the address remapping instructions sent to the memory 200 by a device outside the memory 200 can also indicate a certain address remapping strategy. The memory 200 enables the address remapping function by parsing the received address remapping instructions, and performs address remapping using the address remapping strategy indicated in the address remapping instructions. The structure of the memory 200 is described below. Similar to the structure of the memory 200 shown in FIG3 , in this implementation, the memory 200 includes a control circuit 210 and a plurality of storage particles 220. However, in this implementation, the structure of the control circuit 210 and the storage particles 220 are different from the structure of the memory 200 shown in FIG3 . The structure of the storage particles 220 is similar to the structure of the storage particles 220 in the embodiment shown in FIG1 , and the details can be referred to the above description, which will not be repeated here. In the memory 200, the storage particles 220 are mainly used to store data, and the control circuit 210 is the control center of the memory 200. The control circuit 210 can process the read and write requests received by the memory 200. That is, the control circuit 210 can parse the logical address carried in the read and write request, and read and write data to each storage particle 220 according to the logical address. In the embodiment of the present application, the control circuit 210 can map the logical address to each storage particle 220. In any storage particle 220, the logical address can be mapped to a target location of a BANK of the storage particle 220. That is, the control circuit 210, The logical address may be mapped to target locations of multiple BANKs respectively. When the memory 200 enables the address remapping function, the target locations of the multiple BANKs are distributed in different areas, and different areas correspond to different error rate ranges. When the memory 200 does not enable the address remapping function, the target locations of the multiple BANKs are distributed in the same area. Optionally, when the memory 200 provides an enable option for the address remapping function, the control circuit 210 can detect the enable state of the address remapping function, that is, determine whether the address remapping function is enabled. For example, when the device of the memory 200 is configured with an enable switch for the address remapping function, the control circuit 210 can detect the enable switch for the address remapping function to determine whether the address remapping function is enabled. For another example, when the memory 200 is configured with a parsing function for an address remapping instruction, the parsing function can be implemented by the control circuit 210, and the control circuit 210 can parse the received address remapping instruction to enable the address remapping function. In the subsequent description, only the case where the memory 200 enables the address remapping function is described. For the case where the memory 200 does not enable the address remapping function, the way in which the control circuit 210 reads and writes the logical address can refer to the method shown in Figure 1, and will not be repeated here. It can be seen from the memory addressing method shown in FIG. 1 that when a logical address is mapped to each storage particle 220 , the control circuit 210 needs to convert the logical address to obtain a corresponding physical address, and then send the physical address to each storage particle 220 . In the embodiment of the present application, when converting the logical address, the control circuit 210 may adopt different conversion methods for different storage particles 220, and adopt different conversion methods to ultimately obtain different physical addresses. The control circuit 210 may use different conversion methods for the logical address for each storage particle 220 to obtain multiple physical addresses that are not completely the same. For example, for some storage particles 220 in the multiple storage particles 220, the control circuit 210 uses one conversion method to convert the logical address, and finally obtains multiple identical physical addresses. For another part of the storage particles 220 in the multiple storage particles 220, the control circuit 210 uses another conversion method to convert the logical address, and finally obtains multiple identical physical addresses. In this way, the multiple physical addresses that are not completely the same are finally obtained, a part of the multiple physical addresses corresponds to the same target location in multiple BANKs, and another part of the multiple physical addresses corresponds to another identical target location in multiple BANKs. For another example, the control circuit 210 uses completely different conversion methods for the logical address for each storage particle 220 to obtain multiple sets of completely different address information. That is, in different storage particles 220, the control circuit 210 uses different conversion methods to convert the logical address, and finally obtains completely different physical addresses. In this way, the multiple physical addresses correspond to different target locations in multiple BANKs. In this way, the target locations of the multiple BANKs will no longer belong to the same area. For example, the control circuit 210 adopts two different conversion methods for the logical address for each storage particle 220, wherein one conversion method is adopted for the storage particles 220-1, 220-2, 220-3, and 220-4, and another conversion method is adopted for the storage particles 220-5, 220-6, 220-7, and 220-8. Then, the physical addresses obtained by the storage particles 220-1, 220-2, 220-3, and 220-4 are the same, and point to the target position A on a certain BANK in the storage particles 220-1, 220-2, 220-3, and 220-4 respectively. The positions of the target positions A in the BANKs to which they belong are the same, that is, the same target positions in multiple BANKs. The physical addresses obtained in the storage particles 220-5, 220-6, 220-7, and 220-8 are the same, and point to the target position B on a certain BANK in the storage particles 220-5, 220-6, 220-7, and 220-8 respectively. The positions of the target positions B in the BANKs to which they belong are the same, that is, the target positions are the same in multiple BANKs. The embodiment of the present application does not limit the specific conversion method adopted by the control circuit 210 for the logical address, and any method that can convert the logical address into a physical address is applicable to the embodiment of the present application. For example, in the process of converting the logical address, the control circuit 210 can modify some or all fields in the logical address, and then analyze the modified logical address based on the preset mapping relationship to generate a physical address. The structure and specific functions of the memory 200 are described below. As shown in FIG8 , it is a schematic diagram of the structure of a memory 200 provided in an embodiment of the present application. The control circuit 210 includes a plurality of second address remapping modules 211 and a plurality of address conversion modules 212. The second address remapping module 211 and the plurality of address conversion modules 212 may be logic circuits. The embodiment of the present application does not limit the specific internal structures of the second address remapping module 211 and the plurality of address conversion modules 212. Any logic circuit that can realize the corresponding functions is applicable to the embodiment of the present application. Each storage particle 220 corresponds to a second address remapping module 211 and an address conversion module 212. The second address remapping module 211 is arranged between the storage particle 220 and the address conversion module 212. That is, the logical address will first pass through the second address remapping module 211. After the second address remapping module 211 processes the logical address, it can convert the logical address after the processing operation into the second address remapping module 211. The address is sent to the address conversion module 212. The address conversion module 212 is used to convert the logical address after the processing operation is performed into a physical address based on the second mapping relationship. The second mapping relationship is a mapping relationship between a physical address and a logical address. The second address remapping module 211 can perform one of two processing operations on the logical address. One is to modify the logical address. The embodiment of the present application does not limit the modification method of the logical address by the second address remapping module 211. For example, the second address remapping module 211 can invert some fields in the logical address. For another example, the second address remapping module 211 can subtract some fields in the logical address from the preset value to obtain the difference, and use the difference to replace the part of the fields in the logical address. The other is to maintain the various fields in the logical address unchanged. Among them, the second address remapping module 211 in the working state can modify the logical address, and the second address remapping module 211 in the non-working state maintains the various fields of the logical address unchanged. After receiving the logical address sent by the second address remapping module 211, the address conversion module 212 can convert the obtained logical address into a corresponding physical address according to the second mapping relationship, and convert the physical address to the storage particle 220. The physical address parsing process inside the storage particle 220 can refer to the relevant description in the embodiment shown in Figure 1 and will not be repeated here. Fig. 8 is only a schematic diagram of a possible structure of the control circuit 210. The embodiment of the present application does not limit the division method of each module in the control circuit 210. The way in which the second address remapping module 211 modifies the logical address is similar to the way in which the first address remapping module 222 modifies the physical address. For details, please refer to the aforementioned content and will not be repeated here. The difference is that the second address remapping module 211 may have different specific values ​​of the fields representing BANK, row, and column in the logical address and the specific operations adopted for each field. Based on the memory 200 shown in FIG8 , when the memory 200 enables the address remapping function, it is not necessary for all the second address remapping modules 211 to be in working state inside the control circuit 210. That is, when the memory 200 enables the address remapping function, it is only necessary to ensure that some of the second address remapping modules 211 among the multiple second address remapping modules 211 can modify the received logical address. The other second address remapping modules 211 do not need to modify the received logical address, and after receiving the logical address, the road base address can be directly sent to the address decoding circuit 223. The configuration method of the second address remapping module 211 in the working state is similar to the configuration method of the first address remapping module 222 in the working state. For details, please refer to the above description and will not be repeated here. The data reading and writing method provided by the present application is described below in conjunction with Figure 9. Here, the memory 200 provides an enable option for the address remapping function as an example for description. If the memory 200 does not provide an enable option for the address remapping function, steps 900 to 901 can be omitted. Step 900: The processor 100 sends an address remapping instruction to the memory 200. The address remapping instruction is used to indicate enabling of the address remapping function. The address remapping instruction also indicates a second address remapping module 211 that needs to be in working state. Step 901: the memory 200 receives the address remapping instruction, and controls the second address remapping module 211 indicated by the address remapping instruction to be in a working state according to the address remapping instruction. Step 902: The processor 100 sends a read / write request to the memory 200, where the read / write request carries a logical address. Step 903 : the memory 200 receives the read / write request, and maps the logical address to a target location on the BANK of the storage particle 220 in each storage particle 220 of the memory 200 . Inside the memory 200, the second address remapping module 211 of each storage particle 220 obtains the logical address and sends it. For the second address remapping module 211 in working state, the second address remapping module 211 modifies the field in the logical address and sends the modified logical address to the address conversion module 212 corresponding to the storage particle 220. The address conversion module 212 converts the modified logical address to obtain a physical address and sends the physical address to the corresponding storage particle 220. For the second address remapping module 211 that is not in working state, the second address remapping module 211 sends the received logical address to the address conversion module 212 of the storage particle 220 , and the address conversion module 212 converts the logical address to obtain a physical address and sends the physical address to the corresponding storage particle 220 . Step 904 : the memory 200 reads and writes data to the target location on the BANK of each storage particle 220 . When the read / write request is a read request for reading data, the memory 200 reads data from the target location on the BANK of each storage particle 220 , aggregates the data read from each storage particle 220 , and feeds it back to the processor 100 . When the read-write request is a write request requesting to write data, the memory 200 writes the data carried by the write request at the target location on the BANK of each storage particle 220, wherein the data written at each target location is part of the data carried by the write request, and the data written at all target locations is the data carried by the write request. It should be noted that, in the second implementation, the second address remapping module 211 directly modifies the logical address as an example. As a possible implementation, the second address remapping module 211 may not directly modify the logical address, but may modify the address conversion module 211 directly modify the logical address. The physical address obtained after the conversion is modified 212, and the modified physical address is sent to the corresponding storage particle 220. It should be noted that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. The functional modules in the embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules. The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD). Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code. The present application is described with reference to the flowchart and / or block diagram of the method, device (system), and computer program product according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the process and / or box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the function specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram. These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A data processing system, characterized in that: The system comprises: The processor is used to send a read / write request to the memory, wherein the read / write request carries a logical address of the data; A memory, used for receiving the read and write request, mapping the logical address to a target location on the BANK of the N storage particles of the memory, and reading and writing data to the target location on the BANK of the N storage particles; The target positions on the BANKs of the N storage particles are distributed in different areas, and N is a positive integer.

2. The system according to claim 1, characterized in that Before sending the read / write request, the processor is further configured to: send an address remapping instruction to the memory, wherein the address remapping instruction is used to enable an address remapping function of the memory.

3. The system according to claim 2, characterized in that The memory includes a control circuit and N first address remapping modules, each storage particle corresponds to a first address remapping module, and the control circuit is used to: Control the M first address remapping modules to be in a working state according to the address remapping instruction, wherein M is not greater than N; Any of the first address remapping modules in working state is used to modify the physical address converted from the logical address, so that the modified physical address points to the target location on the BANK of the storage particle corresponding to the first address remapping module.

4. The system according to claim 3, characterized in that The first address remapping module in working state is used for: The fields in the physical address pointing to the row and / or column in the BANK are modified.

5. The system according to any one of claims 2 to 4, characterized in that: The first address remapping module is located in the corresponding storage particle; The control circuit is further used to receive the read / write request, convert the logical address into a physical address, and send the physical address to each storage particle.

6. The system according to claim 3, characterized in that The first address remapping module that is not in a working state is used to: Each field in the physical address is maintained unchanged, and the physical address points to a target location on the BANK of the storage particle corresponding to the first address remapping module.

7. The system according to any one of claims 2 to 4, characterized in that: Any of the storage particles is used to determine a target location on a BANK of the storage particle according to the physical address obtained from the corresponding first address remapping module, and read and write data to the target location.

8. The system according to claim 2, characterized in that The control circuit includes N second address remapping modules, each storage particle corresponds to a second address remapping module, and the control circuit is used to: Control the M first address remapping modules to be in a working state according to the address remapping instruction, wherein M is not greater than N; Any of the second address remapping modules in working state is used to modify the logical address, and the modified logical address is mapped to a target position on the BANK of the storage particle corresponding to the second address remapping module.

9. The system according to claim 8, characterized in that The second address remapping module in working state is used for: The fields in the logical address pointing to the row and / or column in the BANK are modified.

10. The system according to claim 8, characterized in that The second address remapping module which is not in a working state is used for: Each field in the logical address is maintained unchanged.

11. The system according to any one of claims 2, 8 to 10, characterized in that: The control circuit includes an address conversion module; The address conversion module is used to obtain the logical address from the second address remapping module; convert the logical address obtained from the second address remapping module into a physical address; and send the physical address to the storage particle corresponding to the second address remapping module.

12. A memory, characterized in that: The memory includes a control circuit and N storage particles; A control circuit is configured to receive a read / write request sent by a processor, wherein the read request is used to request data reading / writing of a memory, and the read / write request carries a logical address of the data; convert the logical address into a physical address, and send the physical address converted from the logical address to the N storage particles respectively, wherein the physical address points to a target position on the BANK of the N storage particles of the memory, wherein the target positions on the BANK of the N storage particles are distributed in different areas; Any of the storage particles is used to read and write data at a target location on the BANK of the storage particle.

13. The memory according to claim 12, wherein: The control circuit is further used to: receive an address remapping instruction sent by the processor, where the address remapping instruction is used to enable an address remapping function of the memory.

14. The memory according to claim 13, wherein: The memory includes N first address remapping modules, each storage particle corresponds to one first address remapping module, and the control circuit is used to: Control the M first address remapping modules to be in a working state according to the address remapping instruction, wherein M is not greater than N; Any of the first address remapping modules in working state is used to modify the physical address converted from the logical address, so that the modified physical address points to the target location on the BANK of the storage particle corresponding to the first address remapping module.

15. The memory according to claim 13, wherein: The first address remapping module in working state is used for: The fields in the physical address pointing to the row and / or column in the BANK are modified.

16. The memory according to claim 15, characterized in that The first address remapping module that is not in a working state is used to: Each field in the physical address is maintained unchanged, and the physical address points to a target location on the BANK of the storage particle corresponding to the first address remapping module.

17. The memory according to any one of claims 14 to 16, characterized in that: Any of the storage particles is used to determine a target location on a BANK of the storage particle according to the physical address obtained from the corresponding first address remapping module, and read and write data to the target location.

18. The memory according to claim 13, wherein: The control circuit includes N second address remapping modules, each storage particle corresponds to a second address remapping module, and the control circuit is used to: Control the M second address remapping modules to be in a working state according to the address remapping instruction, wherein M is not greater than N; Any of the second address remapping modules in working state is used to modify the logical address, and the modified logical address is mapped to a target position on the BANK of the storage particle corresponding to the second address remapping module.

19. The memory according to claim 18, wherein: The second address remapping module in working state is used for: The fields in the logical address pointing to the row and / or column in the BANK are modified.

20. The memory according to claim 18, wherein: The second address remapping module which is not in a working state is used for: Each field in the logical address is maintained unchanged, and the logical address is mapped to a target location on the BANK of the storage particle corresponding to the second address remapping module.

21. The memory according to any one of claims 13, 18 to 20, characterized in that: The control circuit includes an address conversion module; The address conversion module is used to convert the logical address obtained from the second address remapping module into a physical address; and send the physical address to the storage particle corresponding to the second address remapping module.

22. A data reading and writing method, characterized in that: The method is applied to a memory, comprising a control circuit and N storage particles, where N is a positive integer, and the method comprises: The control circuit receives a read / write request sent by a processor, wherein the read request is used to request data reading and writing to a memory, and the read / write request carries a logical address of the data; converts the logical address into a physical address, and sends the physical address converted from the logical address to the N storage particles respectively, wherein the physical address points to a target position on the BANK of the N storage particles of the memory, wherein the target positions on the BANK of the N storage particles are distributed in different areas; Any of the storage particles reads and writes data to a target location on the BANK of the storage particle.

23. The method of claim 22, wherein: The method further comprises: The control circuit receives a send address remapping instruction sent by the processor, where the address remapping instruction is used to enable the address remapping function of the method.

24. The method of claim 23, wherein: The memory includes N first address remapping modules, each storage particle corresponds to one first address remapping module, and the method further includes: The control circuit controls the M first address remapping modules to be in a working state according to the address remapping instruction, wherein M is not greater than N; Any of the first address remapping modules in working state modifies the physical address converted from the logical address, and the modified physical address points to the target location on the BANK of the storage particle corresponding to the first address remapping module.

25. The method of claim 24, wherein: The first address remapping module in working state modifies the physical address converted from the logical address, including: The first address remapping module in working state modifies the field pointing to the row and / or column in the BANK in the physical address.

26. The method of claim 24, wherein: The method further comprises: The first address remapping module that is not in working state maintains each field in the physical address unchanged, and the physical address points to The first address remapping module corresponds to a target location on a BANK of a storage particle.

27. The method according to any one of claims 24 to 26, characterized in that: Any of the storage particles reads and writes data to a target location on a BANK of the storage particle, including: Any of the storage particles determines a target location on the BANK of the storage particle according to the physical address obtained from the corresponding first address remapping module, and reads and writes data to the target location.

28. The method of claim 23, wherein: The control circuit includes N second address remapping modules, each storage particle corresponds to a second address remapping module, and the method further includes: The control circuit controls the M second address remapping modules to be in a working state according to the address remapping instruction, wherein M is not greater than N; Any of the second address remapping modules in working state modifies the logical address, and the modified logical address points to the target location on the BANK of the storage particle corresponding to the second address remapping module.

29. The method of claim 28, wherein: The second address remapping module in working state modifies the logical address, including: The second address remapping module in working state modifies part of the fields in the logical address pointing to the rows and / or columns in the BANK.

30. The method of claim 28, wherein: The method further comprises: The second address remapping module that is not in a working state maintains each field in the logical address unchanged, and the logical address points to a target location on the BANK of the storage particle corresponding to the second address remapping module.

31. The method according to any one of claims 23, 28 to 30, characterized in that: The control circuit includes an address conversion module; the control circuit converts the logical address into a physical address, and sends the physical address converted from the logical address to the N storage particles of the memory, including: The address conversion module converts the logical address obtained from the second address remapping module into a physical address; and sends the physical address to a storage particle corresponding to the second address remapping module.

32. A computing device, characterized in that The computing device comprises the memory according to any one of claims 12 to 21.

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