Wiring method and apparatus for multi-layer wiring packaging, and device and storage medium

Abstract

A wiring method and apparatus for multi-layer wiring packaging, and a device and a storage medium. The wiring method for multi-layer wiring package comprises: acquiring a multi-layer theoretical wiring scheme during chip packaging, and arranging multiple layers of wiring in a stacked manner (S11); dividing the multiple layers of wiring into a first connection subsection, a second connection subsection and a third connection subsection according to the multi-layer theoretical wiring scheme (S12); and adjusting at least the poses of the first connection subsection and the third connection subsection according to a movement posture of a chip, so as to obtain an actual wiring scheme (S13).

Description

Wiring method, device, equipment and storage medium for multi-layer wiring package

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 29, 2023, with application number 202310779282.9, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip packaging technology, for example, to a wiring method, device, equipment and storage medium for multi-layer wiring packaging. Background Art

[0003] In fan-out panel-level packages (PLPs), the chip must be reattached to the substrate before being encapsulated and drilled. During the chip placement and encapsulation process, temperature fluctuations and other factors can cause the chip position to shift and rotate. This can cause changes in the routing of chips and circuits on the first layer of multi-layer packaging to drive changes in the routing of chips and circuits on other layers, affecting subsequent circuit layouts and, in turn, the chip's electrical properties.

[0004] Summary of the Invention

[0005] The present application provides a wiring method, device, equipment and storage medium for a multi-layer wiring package to solve the problem that the position of the chip changes during the mounting process, causing the position of other wiring layers to change accordingly, thereby affecting the circuit arrangement and chip electrical properties.

[0006] According to one aspect of the present application, a wiring method for a multi-layer wiring package is provided, comprising:

[0007] Obtain multi-layer theoretical wiring scheme and multi-layer wiring stacking settings during chip packaging;

[0008] According to the multi-layer theoretical wiring scheme, the multi-layer wiring is divided into a first connection sub-section, a second connection sub-section, and a third connection sub-section; the first connection sub-section is connected to an electrode in a chip; the second connection sub-section is connected to an electrode in another chip in a stacked arrangement, or the second connection sub-section is connected to an external pin; the third connection sub-section is connected to the first connection sub-section and the second connection sub-section respectively;

[0009] At least the positions of the first connection section and the third connection section are adjusted according to the movement posture of the chip to obtain an actual wiring plan.

[0010] According to another aspect of the present application, a wiring device of a multi-layer wiring package is provided, comprising:

[0011] A multi-layer wiring acquisition module is configured to acquire a multi-layer theoretical wiring scheme and a multi-layer wiring stacking setting during chip packaging;

[0012] a multi-layer wiring division module configured to divide the multi-layer wiring into a first connection subsection, a second connection subsection, and a third connection subsection according to a multi-layer theoretical wiring scheme; the first connection subsection is connected to an electrode in a chip; the second connection subsection is connected to an electrode in another chip in a stacked arrangement, or the second connection subsection is connected to an external pin; and the third connection subsection is connected to the first connection subsection and the second connection subsection respectively;

[0013] The multi-layer wiring adjustment module is configured to adjust the posture of at least the first connection section and the third connection section according to the movement posture of the chip to obtain an actual wiring plan.

[0014] According to another aspect of the present application, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, a wiring method for a multi-layer wiring package is implemented.

[0015] According to another aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, a wiring method for a multi-layer wiring package is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following will introduce the drawings required for the description of the embodiments. The drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] FIG1 is a flow chart of a first wiring method for a multi-layer wiring package provided according to an embodiment of the present application;

[0018] FIG2 is a flow chart of a second wiring method for a multi-layer wiring package provided according to an embodiment of the present application;

[0019] FIG3 is a schematic diagram of wiring division of a multi-layer wiring package provided according to an embodiment of the present application;

[0020] 4 is a flow chart of a third wiring method for a multi-layer wiring package according to an embodiment of the present application;

[0021] 5 is a flowchart of a fourth wiring method for a multi-layer wiring package according to an embodiment of the present application;

[0022] 6 is a flowchart of a fifth wiring method for a multi-layer wiring package provided according to an embodiment of the present application;

[0023] 7 is a flowchart of a sixth wiring method for a multi-layer wiring package according to an embodiment of the present application;

[0024] FIG8 is a schematic diagram of wiring division of another multi-layer wiring package provided according to an embodiment of the present application;

[0025] 9 is a flowchart of a seventh wiring method for a multi-layer wiring package according to an embodiment of the present application;

[0026] 10 is a flowchart of an eighth wiring method for a multi-layer wiring package according to an embodiment of the present application;

[0027] 11 is a flowchart of a ninth wiring method for a multi-layer wiring package according to an embodiment of the present application;

[0028] 12 is a flowchart of a tenth wiring method for a multi-layer wiring package according to an embodiment of the present application;

[0029] FIG13 is a schematic diagram of a wiring structure of a single-layer chip package provided according to an embodiment of the present application;

[0030] FIG14 is a schematic diagram of a wiring structure of another single-layer chip package provided according to an embodiment of the present application;

[0031] 15 is a flowchart of an eleventh wiring method for a multi-layer wiring package according to an embodiment of the present application;

[0032] FIG16 is a schematic structural diagram of a wiring device of a multi-layer wiring package provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present application in conjunction with the accompanying drawings. The embodiments described are some related embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of this application.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units listed, but may include other steps or units that are not listed or inherent to these processes, methods, products or devices.

[0035] FIG1 is a flow chart of a first wiring method for a multi-layer wiring package according to an embodiment of the present application. This embodiment is applicable to chip packaging. As shown in FIG1 , the method includes:

[0036] S11. Obtain a multi-layer theoretical wiring scheme for chip packaging and a multi-layer wiring stacking setting.

[0037] In some instances, during the chip packaging process, when the distribution density of the electrodes in the chip is large and one layer of wiring does not meet the connection requirements of the chip electrodes, a multi-layer wiring layer can be set according to the position of the chip, and the multi-layer wiring layers are stacked so that the connection between the chip and the pin after wiring meets the chip packaging wiring specifications and the customer's special electrical requirements. This method is the multi-layer packaging wiring of a single chip. In addition, based on the customer's special electrical requirements, a multi-layer chip stacking package can also be adopted, with corresponding chips distributed on each layer, and wiring is performed according to the position of each layer of chips and pins. This method is the multi-layer packaging wiring of a multi-layer chip. The wiring method of the multi-layer wiring package provided in the embodiment of the present application can be applied to the above two different multi-layer packaging wiring schemes. In the embodiment of the present application, the multi-layer theoretical wiring scheme during chip packaging is first obtained, that is, the parameters such as the line connection path, line length, line size, and line area of ​​each layer of the chip are obtained. It should be noted that when the multi-layer wiring is stacked, the actual offset value of each layer needs to be considered, and the corresponding wiring is adjusted according to the actual offset value.

[0038] S12. Divide the multi-layer wiring into a first connection division, a second connection division and a third connection division according to the multi-layer theoretical wiring scheme; the first connection division is connected to the electrode in the chip; the second connection division is connected to the electrode in another stacked chip, or the second connection division is connected to an external pin; the third connection division is connected to the first connection division and the second connection division respectively.

[0039] In some examples, during the wiring adjustment process, the wiring is divided into a first connection subsection, a second connection subsection, and a third connection subsection. The first connection subsection, the second connection subsection, and the third connection subsection collectively connect electrodes and pins of a chip, or collectively connect chips to each other. The second connection subsection can be connected to an electrode in another chip or to an external pin, thus achieving multi-layer wiring division for a single chip or for multiple chips.

[0040] S13 , adjusting the positions of at least the first connection section and the third connection section according to the movement posture of the chip to obtain an actual wiring plan.

[0041] In some instances, the first connection section is adjusted according to the chip's moving posture because during the chip mounting process on the substrate, the chip's posture may change due to the influence of temperature during mounting, that is, the position of the chip electrode changes. In the embodiment of the present application, at least the first connection section is adjusted according to the chip's moving posture so that the first connection section always remains connected to the chip's electrode. In addition, the posture of the third connection section is adjusted so that the third connection section always remains connected to the first connection section and the second connection section, while ensuring the chip packaging wiring specifications and the customer's special electrical requirements.

[0042] In an embodiment of the present application, the multi-layer wiring is divided into a first connection section, a second connection section, and a third connection section. During the chip mounting process, at least the first connection section and the third connection section are adjusted according to the movement posture of the chip. By dividing and adjusting the multi-layer wiring, the changes in the posture of the chip and the line in each layer of wiring are taken into account. The multi-layer wiring is reconstructed according to the position of the chip and the line in each layer, which meets the chip packaging wiring specifications and the customer's special electrical requirements, improves the yield of the chip packaging, and reduces the design difficulty of the redistribution layer.

[0043] As described above, the multi-layer wiring package described in the embodiments of the present application includes a single-chip multi-layer wiring package and a multi-chip multi-layer wiring package. These two cases are described below respectively.

[0044] First, the single-chip multi-layer wiring packaging solution is explained.

[0045] In some examples, based on the above embodiments, FIG2 is a flow chart of a second wiring method for a multi-layer wiring package provided according to an embodiment of the present application, and FIG3 is a schematic diagram of wiring division for a first multi-layer wiring package provided according to an embodiment of the present application. The wiring method shown in FIG2 illustrates how to divide a multi-layer theoretical wiring scheme for a single chip package. In combination with FIG2 and FIG3 , the wiring method for the multi-layer wiring package includes:

[0046] S21. Obtain a multi-layer theoretical wiring scheme for a single chip package and a multi-layer wiring stacking setting.

[0047] In some instances, during the packaging of a single chip, due to the high distribution density of electrodes in the chip or substrate space limitations, the wiring routing path is limited, requiring multi-layer wiring for a single chip. When a single chip is mounted on a substrate, the chip posture may change due to the influence of temperature, and the original wiring scheme may not be able to guarantee a good connection relationship between the chip and the external pins after the posture changes. In the embodiment of the present application, a multi-layer theoretical wiring scheme is first obtained when a single chip is packaged, that is, the position of the single chip on the substrate and the routing path, line length, line area, line width, and line spacing of each layer of the circuit are obtained, so as to facilitate subsequent adjustments based on the posture of the chip.

[0048] S22. Divide each layer of wiring into a first connection section, a second connection section, and a third connection section according to a multi-layer theoretical wiring scheme; the first connection section is connected to an electrode in the chip; the second connection section is connected to an external pin; and the third connection section is connected to the first connection section and the second connection section, respectively.

[0049] In some examples, as shown in Figure 3, each layer of wiring is divided into a first connection section 1, a second connection section 2, and a third connection section 3. The first connection section 1 can be understood as a chip-following section, meaning its position can change with the position of the chip; the second connection section 2 can be understood as an external connection section and is used to electrically connect to external pins; and the third connection section 3 serves as the connection between the first connection section 1 and the second connection section 2. Because the positions of wiring layers affect each other, dividing each layer of wiring separately can reduce mutual interference between wiring layers and facilitate subsequent adjustments to each wiring layer.

[0050] S23 , adjusting the postures of the first connecting section and the third connecting section according to the movement posture of the chip.

[0051] In some instances, the positions of the first connection division and the third connection division on each wiring layer are adjusted according to the movement posture of the chip to achieve reconstruction of each wiring layer and ensure that the wiring adjustment method matches the chip offset method.

[0052] It should be noted that FIG3 is an example of a two-layer wiring solution for a single chip, and the number of wiring layers in the embodiment of the present application can be set according to actual conditions.

[0053] It should also be noted that the wiring in different wiring layers is arranged to overlap. Figure 3 shows two wiring layers in a non-overlapping manner in order to clearly illustrate the wiring in different wiring layers. In the actual design scheme, the two wiring layers are arranged to overlap.

[0054] The embodiment of the present application obtains a multi-layer theoretical wiring scheme when packaging a single chip, divides the wiring scheme of each layer when packaging a single chip, and adjusts each layer of wiring separately, thereby reducing the interference between wiring layers when packaging a single chip. While meeting the chip packaging wiring specifications and the customer's special electrical requirements, the yield of chip packaging is improved.

[0055] In some examples, based on the above embodiments, FIG4 is a flow chart of a third wiring method for a multi-layer wiring package provided according to an embodiment of the present application. The wiring method shown in FIG4 illustrates how to adjust the wiring after the multi-layer theoretical wiring scheme is divided when packaging a single chip. In combination with FIG3 and FIG4 , the wiring method for the multi-layer wiring package includes:

[0056] S31. Obtain a multi-layer theoretical wiring scheme for a single chip package and a multi-layer wiring stacking setting.

[0057] S32. Divide each layer of wiring into a first connection section, a second connection section, and a third connection section according to a multi-layer theoretical wiring scheme; the first connection section is connected to an electrode in the chip; the second connection section is connected to an external pin; and the third connection section is connected to the first connection section and the second connection section, respectively.

[0058] S33 , adjusting the postures of the first connection section and the third connection section of the first layer wiring according to the movement posture of the chip.

[0059] For example, when adjusting each layer of wiring in the multi-layer wiring, the posture of the first connection section and the third connection section 3 of the first layer of wiring is first adjusted according to the movement posture of the chip. The adjustment method of the first layer of wiring serves as a reference basis for subsequent adjustments to the wiring of other film layers.

[0060] S34. Adjust the positions of the first connection section and the third connection section of the i+1th layer wiring according to the setting mode of the i-th layer wiring to avoid short circuit between the i+1th layer wiring and the i-th layer wiring; wherein i is a positive integer.

[0061] In some instances, since multiple layers of wiring are electrically connected to the same chip, when adjusting the position of the first connection section 1 and the third connection section 3 of the i+1th wiring layer, it is necessary to consider the offset mode of the chip and the adjustment mode of the i-th wiring layer to prevent short circuits between adjacent wiring layers. For example, when adjusting the first connection section 1 and the third connection section 3 of the second wiring layer, it is necessary to determine the adjustment mode of the second wiring layer based on the offset mode of the chip and the adjustment mode of the first wiring layer to avoid short circuits between the second wiring layer and the first wiring layer. In the embodiment of the present application, by considering the wiring setting mode between adjacent wiring layers, the wiring adjustment is made more accurate, thereby improving the yield rate of the chip after packaging.

[0062] The above describes the adjustment method for multi-layer wiring of a single chip. Next, the adjustment method for multi-layer wiring of a multi-layer chip will be described.

[0063] In some examples, based on the above embodiments, FIG5 is a flow chart of a fourth wiring method for a multi-layer wiring package provided according to an embodiment of the present application. The wiring method shown in FIG5 illustrates how to divide a multi-layer theoretical wiring scheme for a multi-layer chip stack package. As shown in FIG5 , the wiring method for the multi-layer wiring package includes:

[0064] S41. Obtain a multi-layer theoretical wiring scheme and a multi-layer wiring stacking setting for multi-layer chip stacking packaging.

[0065] In some instances, multi-layer chip stacking packaging can be understood as a multi-layer chip stacking arrangement, and the electrical connection between two adjacent layers of chips is achieved through wiring. When multi-layer chip stacking packaging is performed, the relationship between chip offsets between adjacent wiring layers needs to be considered. In the embodiment of the present application, the multi-layer theoretical wiring scheme for multi-layer chip stacking packaging is first obtained, that is, the position of each layer of chips and the routing path, line area, line length, line width and line spacing of each wiring layer are obtained, so as to facilitate subsequent wiring adjustments based on the posture of each layer of chips.

[0066] S42. Divide the wiring between two adjacent layers of chips into a first connection division, a second connection division, and a third connection division according to a multi-layer wiring scheme; the first connection division is connected to the electrode in the i-th layer chip, the second connection division is connected to the electrode in the i+1-th layer chip, and the third connection division is connected to the first connection division and the second connection division respectively; wherein i is a positive integer.

[0067] In some instances, the wiring between two adjacent layers of chips is divided because the offset relationship between chips needs to be considered during the multi-layer chip stacking packaging process. The wiring between two adjacent layers of chips is divided into a first connection subsection, a second connection subsection, and a third connection subsection. The first connection subsection and the second connection subsection are respectively connected to electrodes in the adjacent chips, and the third connection subsection connects the first connection subsection and the second connection subsection, that is, connects the electrodes in the two layers of chips. In other words, the connection wiring between two adjacent layers of chips is divided into three parts, namely, a first connection subsection connected to the electrodes in the lower layer chip, a second connection subsection connected to the electrodes in the upper layer chip, and a third connection subsection connecting these two parts.

[0068] S43 , adjusting the positions of the first connection section, the second connection section, and the third connection section according to the movement positions of the chips in two adjacent layers.

[0069] In some instances, since two adjacent layers of chips may shift during the attachment process due to temperature or attachment process problems, it is necessary to adjust the positions of the first connection section and the second connection section connected to the two layers of chips accordingly, and adjust the position of the third connection section to ensure that the third connection section is connected to the first connection section and the second connection section respectively.

[0070] In an embodiment of the present application, by obtaining the multi-layer theoretical wiring scheme for multi-layer chip stacking packaging and dividing the wiring schemes of any two adjacent wiring layers, it is ensured that the offset between adjacent layer chips meets the wiring specifications, while meeting the chip packaging wiring specifications and the customer's special electrical requirements, thereby improving the yield of chip packaging.

[0071] In some examples, based on the above embodiments, FIG6 is a flow chart of a fifth wiring method for a multi-layer wiring package provided according to an embodiment of the present application. The wiring method shown in FIG6 illustrates how to adjust the wiring after the multi-layer theoretical wiring scheme is divided in a multi-layer chip stacking package. As shown in FIG6, the wiring method for the multi-layer wiring package includes:

[0072] S51. Obtain a multi-layer theoretical wiring scheme and a multi-layer wiring stacking setting for multi-layer chip stacking packaging.

[0073] S52. Divide the wiring between two adjacent layers of chips into a first connection division, a second connection division, and a third connection division according to a multi-layer wiring scheme; the first connection division is connected to the electrode in the i-th layer chip, the second connection division is connected to the electrode in the i+1-th layer chip, and the third connection division is connected to the first connection division and the second connection division respectively; wherein i is a positive integer.

[0074] S53 , adjusting the position of the first connection branch according to the movement posture of the chip in the i-th layer, and adjusting the position of the second connection branch according to the movement posture of the chip in the (i+1)-th layer.

[0075] In some instances, since both the first connection section and the second connection section are connected to the electrodes of the chip, when the chip posture changes, the first connection section and the second connection section need to change along with the change in the chip posture in order to ensure the connection with the chip electrodes, thereby ensuring the positional relationship between the chip and the first connection section and the positional relationship between the chip and the second connection section.

[0076] S54 , adjusting the posture of the third connection segment according to the position of the first connection segment and the position of the second connection segment, so that the third connection segment is connected to the first connection segment and the second connection segment respectively.

[0077] In some instances, after the first connection division and the second connection division are adjusted according to the movement posture of the chip, the position of the third connection division is adjusted according to the position of the first connection division and the position of the second connection division to ensure the electrical connection between the two adjacent layers of chips and to ensure that the offset between the adjacent layers of chips complies with the wiring specifications. At the same time, the chip packaging wiring specifications and the customer's special electrical requirements are met, thereby improving the yield of chip packaging.

[0078] The above embodiment takes the example of dividing the connection wiring between two adjacent layers of chips into three parts to illustrate how to adjust the wiring layer based on the movement posture of the chip when wiring a multi-layer chip and a multi-layer package. Next, another way of dividing the connection wiring between two adjacent layers of chips is taken as an example to illustrate how to adjust the wiring layer based on the movement posture of the chip when wiring a multi-layer chip and a multi-layer package.

[0079] In some examples, based on the above embodiments, FIG7 is a flow chart of a sixth wiring method for a multi-layer wiring package provided according to an embodiment of the present application, and FIG8 is a schematic diagram of wiring division for another multi-layer wiring package provided according to an embodiment of the present application. The wiring method shown in FIG7 illustrates a method for dividing a multi-layer theoretical wiring scheme for another multi-layer chip stacking package. In combination with FIG7 and FIG8 , the wiring method for the multi-layer wiring package includes:

[0080] S61. Obtain a multi-layer theoretical wiring scheme and a multi-layer wiring stacking setting for multi-layer chip stacking packaging.

[0081] In some instances, multi-layer chip stacking packaging can be understood as a multi-layer chip stacking arrangement, and the electrical connection between two adjacent layers of chips is achieved through wiring. When multi-layer chip stacking packaging is performed, the relationship between chip offsets between adjacent wiring layers needs to be considered. In the embodiment of the present application, the multi-layer theoretical wiring scheme for multi-layer chip stacking packaging is first obtained, that is, the position of each layer of chips and the routing path, line area, line length, line width and line spacing of each wiring layer are obtained, so as to facilitate subsequent wiring adjustments based on the posture of each layer of chips.

[0082] S62. Divide the multi-layer wiring into multiple single-layer wirings according to a multi-layer theoretical wiring scheme.

[0083] In some instances, dividing multi-layer wiring into multiple single-layer wiring can be done by dividing the multi-layer wiring according to wiring layers, which facilitates subsequent individual adjustment of the single-layer wiring, reduces the difficulty of wiring adjustment, and improves chip yield.

[0084] S63. Divide each single-layer wiring into a first connection section, a second connection section, and a third connection section; the first connection section is connected to the electrode in the chip, the second connection section is connected to the second connection section in another adjacent and stacked wiring, and the third connection section is connected to the first connection section and the second connection section respectively.

[0085] In some examples, as shown in Figure 8, each single-layer connection wiring is divided into a first connection subsection 1, a second connection subsection 2, and a third connection subsection 3. The first connection subsection 1 of each single layer is connected to the electrodes in the chip, and the second connection subsections 2 in two adjacent wiring layers are interconnected to achieve electrical connection between chips on different layers. The wiring division method in the embodiments of the present application divides each wiring layer separately, enhancing the anti-interference ability of wiring adjustment.

[0086] S64 , adjusting the posture of the first connection branch and the third connection branch in each single-layer wiring according to the movement posture of each layer of chip.

[0087] In some cases, each wiring layer is individually adjusted. During each chip placement process, the actual chip placement position shifts and rotates due to temperature fluctuations, causing the chip routing to deviate from the theoretical routing plan. As the chip's position changes, the position of the first connection segment 1, which connects to the chip's electrodes, also changes. By adjusting the position of the third connection segment 3, each layer's routing plan is adjusted to meet the chip packaging routing specifications and the customer's specific electrical requirements, ultimately forming an actual routing plan.

[0088] In some examples, based on the above embodiments, FIG9 is a flow chart of a seventh wiring method for a multi-layer wiring package provided according to an embodiment of the present application. The wiring method shown in FIG9 illustrates how to adjust the position of the chip following subsection and the connecting subsection according to the movement posture of the chip. In combination with FIG8 and FIG9, the wiring method of the multi-layer wiring package includes:

[0089] S71. Obtain a multi-layer theoretical wiring scheme and a multi-layer wiring stacking setting for multi-layer chip stacking packaging.

[0090] S72. Divide the multi-layer wiring into multiple single-layer wirings according to a multi-layer theoretical wiring scheme.

[0091] S73. Divide each single-layer wiring into a first connection section, a second connection section, and a third connection section; the first connection section is connected to the electrode in the chip, the second connection section is connected to the second connection section in another adjacent and stacked wiring, and the third connection section is connected to the first connection section and the second connection section respectively.

[0092] S74 , maintaining the shape of the first connecting section unchanged, and adjusting the position of the first connecting section according to the movement posture of each layer of chips.

[0093] In some instances, the unchanged shape of the first connection division 1 means that the shape of the connection between the wiring segment on the first connection division 1 and the electrode of the chip remains unchanged. For example, the shape of the first connection division 1 is V-shaped. After the chip posture changes, the V-shape of the first connection division 1 does not change, and the connection angle between the first connection division 1 and the chip and the angle between the first connection division 1 and the connection division do not change; at the same time, the first connection division 1 adjusts the corresponding position according to the movement posture of the chip. For example, if the chip rotates 5 degrees clockwise with the electrode as the center, the first connection division 1 also rotates 5 degrees clockwise with the chip electrode as the center while keeping its own shape unchanged, so that the first connection division 1 adjusts the corresponding position according to the posture of the chip.

[0094] S75. Maintain the shape and position of the second connection branch unchanged, adjust at least one of the line width of the third connection branch, the extension direction of the third connection branch, the connection angle between the third connection branch and the first connection branch, and the connection angle between the third connection branch and the second connection branch to ensure that the third connection branch is connected to the first connection branch and the second connection branch respectively.

[0095] In some instances, the shape and position of the second connection division 2 are maintained, that is, the fixed connection of the second connection divisions 2 of the two adjacent wiring layers is maintained, and at the same time, the line width, extension direction, connection angle with the first connection division 1, and connection angle with the second connection division 2 of each layer of the third connection division 3 are adjusted to ensure the connection between each layer of chips. Among them, since the electrical signal requirements for the circuits in each chip are different, special requirements are required for the line width and extension direction of the chip circuits. The embodiment of the present application maintains the shape of the first connection division 1 unchanged, so that the first connection division 1 changes according to the change of the chip posture, and at the same time adjusts the third connection division 3. While ensuring the connection relationship between the third connection division 3 and the first connection division 1 and the outside, the third connection division 3 has a line width, extension direction and connection angle that meet the corresponding requirements, thereby ensuring the wiring requirements and electrical requirements of each layer of circuits.

[0096] In some examples, based on the above embodiments, FIG10 is a flow chart of an eighth wiring method for a multi-layer wiring package provided according to an embodiment of the present application. The wiring method shown in FIG10 illustrates how to verify whether the adjusted wiring method meets the wiring requirements. In combination with FIG8 and FIG10 , the wiring method for the multi-layer wiring package includes:

[0097] S81. Obtain a multi-layer theoretical wiring scheme and a multi-layer wiring stacking setting for multi-layer chip stacking packaging.

[0098] S82. Divide the multi-layer wiring into multiple single-layer wirings according to a multi-layer theoretical wiring scheme.

[0099] S83. Divide each single-layer wiring into a first connection section, a second connection section, and a third connection section; the first connection section is connected to the electrode in the chip, the second connection section is connected to the second connection section in another adjacent and stacked wiring, and the third connection section is connected to the first connection section and the second connection section respectively.

[0100] S84. Maintain the shape of the first connecting section unchanged, and adjust the position of the first connecting section according to the movement posture of each layer of chips.

[0101] S85. Maintain the shape and position of the second connection branch unchanged, adjust at least one of the line width of the third connection branch, the extension direction of the third connection branch, the connection angle between the third connection branch and the first connection branch, and the connection angle between the third connection branch and the second connection branch to ensure that the third connection branch is connected to the first connection branch and the second connection branch respectively.

[0102] S86. Determine whether the line width of the third connection branch meets the minimum line width requirement, whether the distance between the third connection branches of two adjacent wirings on the same layer meets the minimum line spacing requirement, and whether the connection angle between the third connection branch and the first connection branch and the connection angle between the third connection branch and the second connection branch meet the corner requirement.

[0103] In some instances, the line width can affect the chip's resistivity and impedance; the distance between two adjacent third connection sections 3 in the same wiring layer can affect the line area and, consequently, the circuit's electrical properties; and uneven connection angles between the third connection section 3 and the first connection section 1, and between the third connection section 3 and the second connection section 2, in the same wiring layer, can lead to charge accumulation and, consequently, tip discharge. In chip-to-pin connection requirements, minimum line width and minimum line spacing can be quantified. During the movement of the third connection section 3, the line width of the third connection section 3 must meet the minimum line width requirement, and the distance between two adjacent third connection sections 3 must meet the minimum line spacing requirement. Furthermore, to prevent charge accumulation from affecting circuit electrical properties, the connection angles between the third connection section 3 and the first connection section 1, and between the third connection section 3 and the second connection section 2, must meet corner requirements. This involves rounding corners or adding a fold to prevent charge accumulation at corners.

[0104] S87. If the line width of the third connection division 3 meets the minimum line width requirement, the distance between two adjacent third connection divisions 3 meets the minimum line distance requirement, the connection angle between the third connection division 3 and the first connection division 1, and the connection angle between the third connection division 3 and the second connection division 2 meet the corner requirement, then retain the division information of the first connection division, the second connection division, and the third connection division, as well as the line width information of the third connection division, the extension direction information of the third connection division, the connection angle information between the third connection division and the first connection division, and the connection angle information between the third connection division and the second connection division.

[0105] In some instances, when the line width of the third connection division 3 meets the minimum line width requirement, the distance between two adjacent third connection divisions 3 meets the minimum line spacing requirement, the connection angle between the third connection division 3 and the first connection division 1, and the connection angle between the third connection division 3 and the second connection division 2 meet the corner requirement, it is determined that the line connection method at this time meets the wiring requirements and the special requirements of the connection between the chip and the pin, and the line connection method at this time is determined to be the actual wiring scheme.

[0106] In the embodiment of the present application, by determining the line width, line spacing and connection angle of the connection section of each wiring layer, the basic requirements for the connection between the chip and the pin are guaranteed, thereby ensuring the electrical requirements of the circuit, reducing the chip scrap rate, and ensuring the yield of the chip packaging.

[0107] In some examples, based on the above embodiments, FIG11 is a flow chart of a ninth wiring method for a multi-layer wiring package provided according to an embodiment of the present application. The wiring method shown in FIG11 illustrates how to adjust the wiring scheme when the adjusted wiring method does not meet the wiring requirements. In combination with FIG8 and FIG11 , the wiring method for the multi-layer wiring package includes:

[0108] S91. Obtain a multi-layer theoretical wiring scheme and multi-layer wiring stacking settings for multi-layer chip stacking packaging.

[0109] S92. Divide the multi-layer wiring into multiple single-layer wirings according to a multi-layer theoretical wiring scheme.

[0110] S93. Divide each single-layer wiring into a first connection section, a second connection section, and a third connection section; the first connection section is connected to the electrode in the chip, the second connection section is connected to the second connection section in another adjacent and stacked wiring, and the third connection section is connected to the first connection section and the second connection section respectively.

[0111] S94 , maintaining the shape of the first connecting section unchanged, and adjusting the position of the first connecting section according to the movement posture of each layer of chips.

[0112] S95. Maintain the shape and position of the second connection branch unchanged, adjust at least one of the line width of the third connection branch, the extension direction of the third connection branch, the connection angle between the third connection branch and the first connection branch, and the connection angle between the third connection branch and the second connection branch to ensure that the third connection branch is connected to the first connection branch and the second connection branch respectively.

[0113] S96. Determine whether the line width of the third connection branch meets the minimum line width requirement, whether the distance between the third connection branches of two adjacent wirings on the same layer meets the minimum line distance requirement, and whether the connection angle between the third connection branch and the first connection branch and the connection angle between the third connection branch and the second connection branch meet the corner requirement.

[0114] S97. If so, that is, retain the division information of the first connection division, the second connection division and the third connection division, as well as the line width information of the third connection division, the extension direction information of the third connection division, the connection angle information between the third connection division and the first connection division, and the connection angle information between the third connection division and the second connection division.

[0115] S98. If not, that is, the line connection method at this time does not meet at least one of the following conditions: the line width of the third connection division 3 does not meet the minimum line width requirement, the distance between two adjacent third connection divisions 3 does not meet the minimum line spacing requirement, the connection angle between the third connection division 3 and the first connection division 1 and the connection angle between the third connection division 3 and the second connection division 2 do not meet the connection corner requirement, then adjust the division method of the single-layer wiring.

[0116] In some instances, in each wiring layer, in response to determining that the line connection method at this time does not meet at least one of the following conditions: the line width of the third connection division 3 does not meet the minimum line width requirement, the distance between two adjacent third connection divisions 3 does not meet the minimum line spacing requirement, the connection angle between the third connection division 3 and the first connection division 1, and the connection angle between the third connection division 3 and the second connection division 2 do not meet the connection corner requirement, the division method of the second connection division 2, the first connection division 1 and the third connection division 3 are adjusted according to the theoretical wiring scheme, so that the third connection division 3 meets the corresponding requirements, thereby improving the fault tolerance of the chip and pin connection and ensuring the electrical requirements of the chip after packaging.

[0117] In some examples, based on the above embodiments, FIG12 is a flow chart of a wiring method for a tenth multi-layer wiring package provided according to an embodiment of the present application, FIG13 is a schematic diagram of a wiring structure for a single-layer chip package provided according to an embodiment of the present application, and FIG14 is a schematic diagram of a wiring structure for another single-layer chip package provided according to an embodiment of the present application. In this embodiment of the present application, two wirings electrically connected to the same chip, arranged on the same layer and adjacent to each other include a first wiring 501 and a second wiring 502. The area of ​​the third connection section 3 in the first wiring 501 is greater than the area of ​​the third connection section 3 in the second wiring 502. The wiring method shown in FIG12 illustrates how to adjust the wiring scheme when the adjusted wiring method does not meet the wiring requirements. In combination with FIG12, FIG13, and FIG14, the wiring method for the multi-layer wiring package includes:

[0118] S101. Obtain a multi-layer theoretical wiring scheme and multi-layer wiring stacking settings for multi-layer chip stacking packaging.

[0119] S102 , dividing the multi-layer wiring into multiple single-layer wirings according to a multi-layer theoretical wiring scheme.

[0120] S103. Divide each single-layer wiring into a first connection section, a second connection section, and a third connection section; the first connection section is connected to the electrode in the chip, the second connection section is connected to the second connection section in another adjacent and stacked wiring, and the third connection section is connected to the first connection section and the second connection section respectively.

[0121] S104 , maintaining the shape of the first connecting section unchanged, and adjusting the position of the first connecting section according to the movement posture of each layer of chips.

[0122] S105. Maintain the shape and position of the second connection branch unchanged, and adjust at least one of the line width of the third connection branch, the extension direction of the third connection branch, the connection angle between the third connection branch and the first connection branch, and the connection angle between the third connection branch and the second connection branch to ensure that the third connection branch is connected to the first connection branch and the second connection branch respectively.

[0123] S106. Determine whether the line width of the third connection branch meets the minimum line width requirement, whether the distance between the third connection branches of two adjacent wirings on the same layer meets the minimum line spacing requirement, and whether the connection angle between the third connection branch and the first connection branch and the connection angle between the third connection branch and the second connection branch meet the corner requirement.

[0124] S107. If yes, retain the division information of the first connection division, the second connection division and the third connection division, as well as the line width information of the third connection division, the extension direction information of the third connection division, the connection angle information between the third connection division and the first connection division, and the connection angle information between the third connection division and the second connection division.

[0125] S108. When the line width of the third connection sub-section in the first wiring cannot meet the minimum line width requirement, reduce the line width of the third connection sub-section in the second wiring to increase the line width of the third connection sub-section in the first wiring to ensure that the line width of the third connection sub-section in the first wiring meets the minimum line width requirement; and / or

[0126] When the distance between the third connection section in the first wiring and the third connection section in the second wiring cannot meet the minimum line distance requirement, the line width of the third connection section in the second wiring is reduced to increase the distance between the third connection section in the first wiring and the third connection section in the second wiring, ensuring that the distance between the third connection section in the first wiring and the third connection section in the second wiring meets the minimum line distance requirement.

[0127] In some examples, in each wiring layer, the line width affects the area of ​​the third connection segment 3 and the spacing between the third connection segments 3. During the chip packaging process, multiple wirings may exist, wherein the first wiring 501 and the second wiring 502 are adjacent wirings. Adjustment of the third connection segment 3 of the first wiring 501 may affect the line width of the second wiring 502, and adjustment of the third connection segment 3 of the second wiring 502 may affect the line width of the first wiring 501. Therefore, when adjusting the wirings, the line widths of all wirings must be met. That is, the line widths of the wirings must be adjusted using the area of ​​the third connection segment 3 so that all wirings meet the corresponding line width requirements.

[0128] When the area of ​​the third connection section 3 in the first wiring 501 is larger than the area of ​​the third connection section 3 in the second wiring 502, the area of ​​the third connection section 3 in the first wiring 501 can be reduced. After the area of ​​the third connection section 3 in the first wiring 501 is reduced, the spacing between the first wiring 501 and the second wiring 502 is increased, so that there is enough space for the third connection section 3 in the second wiring 502 to meet the minimum line requirement; and / or, when the distance between the third connection section 3 in the first wiring 501 and the third connection section 3 in the second wiring 502 does not meet the minimum line spacing requirement, since the third connection section 3 in the first wiring 501 with a larger area has a wider adjustment range, the line width of the third connection section 3 in the first wiring 501 is reduced, so that the spacing between the third connection section 3 in the first wiring 501 and the third connection section 3 in the second wiring 502 is increased to meet the minimum line spacing requirement.

[0129] In the process of adjusting a single wiring line in the embodiment of the present application, in order to ensure the line width and line spacing requirements, the area relationship between two adjacent third connection divisions is utilized to adjust the area of ​​the third connection divisions and increase the spacing between the third connection divisions. While ensuring that the total area requirements of each line are met, each layer of the line meets the corresponding line width and line spacing requirements, thereby ensuring the electrical properties of the chip package.

[0130] In some examples, based on the above embodiments, FIG15 is a flow chart of an eleventh wiring method for a multi-layer wiring package provided according to an embodiment of the present application. The wiring method shown in FIG15 illustrates how to divide the first connection subdivision, the second connection subdivision, and the third connection subdivision according to a theoretical wiring scheme. In combination with FIG8 and FIG15 , the wiring method for the multi-layer wiring package includes:

[0131] S111. Obtain a multi-layer theoretical wiring scheme and a multi-layer wiring stacking setting for multi-layer chip stacking packaging.

[0132] S112. Divide the multi-layer wiring into multiple single-layer wirings according to a multi-layer theoretical wiring scheme.

[0133] S113 , determining the extension direction of the wiring and the distance between two adjacent wirings according to the single-layer wiring.

[0134] In some instances, the extension direction of the wiring may be the routing path of the circuit. Based on the extension direction in the theoretical wiring scheme of each layer and the spacing between two adjacent wirings, each layer of chip circuits may be divided from the inside to the outside, and the required minimum line width, minimum line spacing and other extreme offset values ​​may be achieved.

[0135] S114. Divide the areas of two adjacent wirings with the same extension direction and a larger spacing as the third connection division according to the extension direction of the wiring and the spacing between the two adjacent wirings, select the area connected to the third connection division and used to connect to the electrode of the chip as the first connection division, and select the area connected to the third connection division and connected to the second connection division of another adjacent and stacked wiring as the second connection division.

[0136] In some instances, the areas of two adjacent wirings with the same extension direction and a large spacing are used as the third connection divisions 3, so that the third connection divisions 3 of the parallel lines can be adjusted at the same time while keeping the relative position relationship unchanged, avoiding intersection between the lines and affecting the normal operation of the lines, and ensuring the consistency of the routing direction.

[0137] S115 , adjusting the positions of the first connection division and the third connection division in each single-layer wiring according to the movement posture of each layer of chip to obtain an actual wiring plan.

[0138] In an embodiment of the present application, the multi-layer wiring is divided into a first connection section, a second connection section, and a third connection section. During the chip mounting process, at least the first connection section and the third connection section are adjusted according to the movement posture of the chip. By dividing and adjusting the multi-layer wiring, the changes in the posture of the chip and the line in each layer of wiring are taken into account. The multi-layer wiring is reconstructed according to the position of the chip and the line in each layer, which meets the chip packaging wiring specifications and the customer's special electrical requirements, improves the yield of the chip packaging, and reduces the design difficulty of the redistribution layer.

[0139] An embodiment of the present application provides a wiring device of a multi-layer wiring package. FIG16 is a schematic structural diagram of a wiring device of a multi-layer wiring package provided according to an embodiment of the present application. As shown in FIG16 , the wiring device includes:

[0140] The multi-layer wiring acquisition module 100 is configured to acquire a multi-layer theoretical wiring scheme and a multi-layer wiring stacking setting during chip packaging;

[0141] The multi-layer wiring division module 200 is configured to divide the multi-layer wiring into a first connection sub-section, a second connection sub-section, and a third connection sub-section according to a multi-layer theoretical wiring scheme; the first connection sub-section is connected to an electrode in a chip; the second connection sub-section is connected to an electrode in another chip in a stacked arrangement, or the second connection sub-section is connected to an external pin; and the third connection sub-section is connected to the first connection sub-section and the second connection sub-section respectively;

[0142] The multi-layer wiring adjustment module 300 is configured to adjust the posture of at least the first connection section and the third connection section according to the movement posture of the chip to obtain an actual wiring plan.

[0143] Since the wiring device of the multi-layer wiring package is used to perform the wiring method of the multi-layer wiring package, the wiring device of the multi-layer wiring package also has the advantageous effects of the arrangement method of the multi-layer wiring package in the above-mentioned embodiment.

[0144] An embodiment of the present application also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a wiring method for multi-layer wiring packaging when executing the program.

[0145] In some examples, the number of processors in a computer device may be one or more; the memory, processor, and computer programs stored in the memory and executable on the processor in the computer device may be connected via a bus or other means.

[0146] Memory, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the wiring method for a multi-layer wiring package in the embodiments of this application. The processor executes the computer program stored in the memory to perform various functional applications and data processing of the computer device, namely, the wiring method for a multi-layer wiring package.

[0147] The memory may primarily include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal, etc. Furthermore, the memory may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state memory device. In some instances, the memory may include memory remotely located relative to the processor, and such remote memory may be connected to the computer device via a network. Examples of such networks include the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0148] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon, which implements a wiring method for a multi-layer wiring package when the computer program is executed by a processor.

[0149] An embodiment of the present application provides a computer-readable storage medium, whose computer-executable instructions are not limited to the method operations described above, and can also execute related operations in the wiring method of the multi-layer wiring package provided by any embodiment of the present application.

[0150] The various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the multiple steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of this application can be achieved.

Claims

1. A wiring method for a multi-layer wiring package, comprising: Obtain multi-layer theoretical wiring scheme and multi-layer wiring stacking settings during chip packaging; According to the multi-layer theoretical wiring scheme, the multi-layer wiring is divided into a first connection sub-section, a second connection sub-section and a third connection sub-section; the first connection sub-section is connected to an electrode in the chip; the second connection sub-section is connected to an electrode in another stacked chip, or the second connection sub-section is connected to an external pin; the third connection sub-section is connected to the first connection sub-section and the second connection sub-section respectively; At least the positions of the first connection section and the third connection section are adjusted according to the moving posture of the chip to obtain an actual wiring scheme.

2. The wiring method according to claim 1, wherein: The method of obtaining a multi-layer theoretical wiring scheme for chip packaging includes: Obtaining a multi-layer theoretical wiring scheme when packaging a single chip; The method of dividing the multi-layer wiring into a first connection sub-section, a second connection sub-section and a third connection sub-section according to the multi-layer theoretical wiring scheme includes: According to the multi-layer theoretical wiring scheme, each layer of the wiring is divided into a first connection sub-section, a second connection sub-section and a third connection sub-section; the first connection sub-section is connected to the electrode in the chip; the second connection sub-section is connected to the external pin; the third connection sub-section is connected to the first connection sub-section and the second connection sub-section respectively; The step of adjusting at least the positions of the first connection sub-part and the third connection sub-part according to the movement posture of the chip to obtain an actual wiring scheme includes: The positions and postures of the first connecting section and the third connecting section are adjusted according to the moving posture of the chip.

3. The wiring method according to claim 2, wherein: The adjusting the positions of the first connection section and the third connection section according to the moving posture of the chip includes: Adjusting the postures of the first connection sub-portion and the third connection sub-portion of the first layer wiring according to the movement posture of the chip; The positions of the first connection section and the third connection section of the i+1th layer wiring are adjusted according to the setting mode of the i-th layer wiring to avoid short circuit between the i+1th layer wiring and the i-th layer wiring; wherein i is a positive integer.

4. The wiring method according to claim 1, wherein: The method of obtaining a multi-layer theoretical wiring scheme for chip packaging includes: Obtaining a multi-layer theoretical wiring scheme when the multi-layer chips are stacked and packaged; The method of dividing the multi-layer wiring into a first connection sub-section, a second connection sub-section and a third connection sub-section according to the multi-layer theoretical wiring scheme includes: According to the multi-layer wiring scheme, the wiring between two adjacent layers of the chips is divided into a first connection sub-section, a second connection sub-section and a third connection sub-section; the first connection sub-section is connected to the electrode in the i-th layer of the chip, the second connection sub-section is connected to the electrode in the i+1-th layer of the chip, and the third connection sub-section is connected to the first connection sub-section and the second connection sub-section respectively; wherein i is a positive integer; The adjusting at least the positions of the first connection sub-part and the third connection sub-part according to the moving posture of the chip includes: The positions and postures of the first connection section, the second connection section, and the third connection section are adjusted according to the movement postures of the chips in two adjacent layers.

5. The wiring method according to claim 4, wherein: The adjusting the positions of the first connection sub-division, the second connection sub-division and the third connection sub-division according to the movement postures of the chips in two adjacent layers includes: Adjusting the position of the first connection sub-portion according to the movement posture of the chip in the i-th layer, and adjusting the position of the second connection sub-portion according to the movement posture of the chip in the i+1-th layer; The posture of the third connection segment is adjusted according to the position of the first connection segment and the position of the second connection segment, so that the third connection segment is connected to the first connection segment and the second connection segment respectively.

6. The wiring method according to claim 1, wherein: The method of obtaining a multi-layer theoretical wiring scheme for chip packaging includes: Obtaining a multi-layer theoretical wiring scheme when the multi-layer chips are stacked and packaged; The method of dividing the multi-layer wiring into a first connection sub-section, a second connection sub-section and a third connection sub-section according to the multi-layer theoretical wiring scheme includes: Dividing the multi-layer wiring into a plurality of single-layer wirings according to the multi-layer theoretical wiring scheme; Divide each layer of the single-layer wiring into a first connection sub-section, a second connection sub-section and a third connection sub-section; the first connection sub-section is connected to the electrode in the chip, the second connection sub-section is connected to the second connection sub-section in another adjacent and stacked wiring, and the third connection sub-section is connected to the first connection sub-section and the second connection sub-section respectively; The adjusting at least the positions of the first connection sub-part and the third connection sub-part according to the moving posture of the chip includes: The positions and postures of the first connection sub-portions and the third connection sub-portions in each layer of the single-layer wiring are adjusted according to the movement posture of the chip in each layer.

7. The wiring method according to claim 6, wherein: The adjusting the posture of the first connection sub-portion and the third connection sub-portion in each layer of the single-layer wiring according to the movement posture of each layer of the chip includes: Maintaining the shape of the first connection section unchanged, and adjusting the position of the first connection section according to the movement posture of the chip at each layer; The shape and position of the second connection branch are maintained unchanged, and at least one of the line width of the third connection branch, the extension direction of the third connection branch, the connection angle between the third connection branch and the first connection branch, and the connection angle between the third connection branch and the second connection branch is adjusted to ensure that the third connection branch is connected to the first connection branch and the second connection branch respectively.

8. The wiring method according to claim 7, after adjusting the positions of the first connection sub-portion and the third connection sub-portion in each layer of the single-layer wiring according to the movement posture of the chip in each layer to obtain an actual wiring scheme, the method further comprises: Determine whether the line width of the third connection sub-section meets the minimum line width requirement, whether the distance between two third connection sub-sections of the wirings in the same layer and adjacent to each other meets the minimum line distance requirement, and whether the connection angle between the third connection sub-section and the first connection sub-section and the connection angle between the third connection sub-section and the second connection sub-section meet the corner requirement; In response to the line width of the third connection division satisfying the minimum line width requirement, the distance between the third connection divisions of the two wirings in the same layer and adjacently arranged satisfying the minimum line distance requirement, the connection angle between the third connection division and the first connection division and the connection angle between the third connection division and the second connection division satisfying the corner requirement, the division information of the first connection division, the second connection division and the third connection division, the line width information of the third connection division, the extension direction information of the third connection division, the connection angle information between the third connection division and the first connection division, and the connection angle information between the third connection division and the second connection division are retained.

9. The wiring method according to claim 8, after judging whether the line width of the third connection sub-section meets the minimum line width requirement, whether the distance between two third connection sub-sections of the wiring arranged adjacent to each other in the same layer meets the minimum line distance requirement, and whether the connection angle between the third connection sub-section and the first connection sub-section and the connection angle between the third connection sub-section and the second connection sub-section meets the corner requirement, the method further comprises: In response to determining that at least one of the following conditions is not met: the line width of the third connection division does not meet the minimum line width requirement, the distance between the third connection divisions of two of the wirings that are in the same layer and adjacent to each other does not meet the minimum line distance requirement, the connection angle between the third connection division and the first connection division and the connection angle between the third connection division and the second connection division do not meet the corner requirement, the division method of the single-layer wiring is adjusted.

10. The wiring method according to claim 8, wherein: There are two wirings electrically connected to the same chip, in the same layer and adjacently arranged, including a first wiring and a second wiring, and the area of ​​the third connection subdivision in the first wiring is larger than the area of ​​the third connection subdivision in the second wiring; After determining whether the line width of the third connection sub-portion meets the minimum line width requirement, whether the distance between two adjacent third connection sub-portions of the wiring meets the minimum line distance requirement, and whether the connection angle between the third connection sub-portion and the first connection sub-portion and the connection angle between the third connection sub-portion and the second connection sub-portion meets the corner requirement, the method further includes at least one of the following: In response to the line width of the third connection subdivision in the first wiring failing to meet the minimum line width requirement, reducing the line width of the third connection subdivision in the second wiring to increase the line width of the third connection subdivision in the first wiring to ensure that the line width of the third connection subdivision in the first wiring meets the minimum line width requirement; In response to the fact that the distance between the third connection division in the first wiring and the third connection division in the second wiring cannot meet the minimum line spacing requirement, the line width of the third connection division in the second wiring is reduced to increase the distance between the third connection division in the first wiring and the third connection division in the second wiring to ensure that the distance between the third connection division in the first wiring and the third connection division in the second wiring meets the minimum line spacing requirement.

11. The wiring method according to claim 6, wherein: The step of dividing each single-layer wiring into a first connection sub-section, a second connection sub-section, and a third connection sub-section includes: Determining the extension direction of the wiring and the distance between two adjacent wirings according to the single-layer wiring; According to the extension direction of the wiring and the distance between two adjacent wirings, the areas with the same extension direction and a larger distance between the two adjacent wirings are divided as the third connection division, and the area connected to the third connection division and used to connect to the electrode of the chip is selected as the first connection division, and the area connected to the third connection division and connected to the second connection division in another adjacent and stacked wiring is selected as the second connection division.

12. A wiring device for a multi-layer wiring package, comprising: A multi-layer wiring acquisition module, configured to acquire a multi-layer theoretical wiring scheme and a multi-layer wiring stacking setting during chip packaging; A multi-layer wiring division module is configured to divide the multi-layer wiring into a first connection sub-section, a second connection sub-section and a third connection sub-section according to the multi-layer theoretical wiring scheme; the first connection sub-section is connected to an electrode in the chip; the second connection sub-section is connected to an electrode in another chip in a stacked arrangement, or the second connection sub-section is connected to an external pin; the third connection sub-section is connected to the first connection sub-section and the second connection sub-section respectively; The multi-layer wiring adjustment module is configured to adjust at least the positions of the first connection section and the third connection section according to the movement posture of the chip to obtain an actual wiring plan.

13. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 11 when executing the computer program.

14. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method according to any one of claims 1 to 11.

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