Failure detection device, solid-state imaging device, and failure detection method

Abstract

A failure detection device according to an embodiment of the present disclosure comprises a first resistance voltage dividing circuit, a second resistance voltage dividing circuit, a comparator, and a determination unit. The first resistance voltage dividing circuit is configured to be capable of dividing a Hi voltage applied to a first pixel control line among the plurality of pixel control lines. The second resistance voltage dividing circuit is configured to be capable of dividing a Lo voltage applied to the first pixel control line. The comparator is capable of comparing either one of a first voltage generated by the first resistance voltage dividing circuit or a second voltage generated by the second resistance voltage dividing circuit with a reference voltage. The determination unit is capable of determining, on the basis of a result from the comparator, whether there is a failure in the drive circuit or the pixel control lines.

Description

Fault detection device, solid-state imaging device, and fault detection method

[0001] The present disclosure relates to a fault detection device, a solid-state imaging device, and a fault detection method.

[0002] 2. Description of the Related Art Conventionally, detection of driver failure in a solid-state imaging device is disclosed in, for example, Japanese Patent Application Laid-Open No. 2003-144996.

[0003] JP 2018-520983 A

[0004] In the field of solid-state imaging devices, it is desirable to detect various failure modes in drivers and wiring connected to the drivers. It is also desirable to detect various failure modes in control circuits related to pixel readout and wiring connected to such circuits. It is desirable to provide a failure detection device, a solid-state imaging device, and a failure detection method that can detect various failure modes in solid-state imaging devices.

[0005] A failure detection device according to a first aspect of the present disclosure is a failure detection device for an imaging device including a plurality of pixels, a plurality of pixel control lines, and a drive circuit electrically connected to one end of each pixel control line and driving the plurality of pixels via the plurality of pixel control lines. The failure detection device is electrically connected to the other end of each pixel control line. The failure detection device includes a first resistive voltage divider circuit, a second resistive voltage divider circuit, a comparator, and a determination unit. The first resistive voltage divider circuit is configured to divide a high voltage applied to a first pixel control line among the plurality of pixel control lines. The second resistive voltage divider circuit is configured to divide a low voltage applied to the first pixel control line. The comparator is capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage. The determination unit is capable of determining failures in the drive circuit and each pixel control line based on the result of the comparator.

[0006] A fault detection device according to a second aspect of the present disclosure is a fault detection device for an imaging device including a plurality of pixels, a plurality of control lines, and a control circuit electrically connected to each control line and controlling, via the plurality of control lines, a control circuit that processes pixel signals output from the plurality of pixels. The fault detection device is electrically connected to each control line. The fault detection device includes a first resistive voltage divider circuit, a second resistive voltage divider circuit, a comparator, and a determination unit. The first resistive voltage divider circuit is capable of dividing a high voltage applied to a first control line among the plurality of control lines. The second resistive voltage divider circuit is capable of dividing a low voltage applied to the first control line. The comparator is capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage. The determination unit is capable of determining faults in the control circuit and each control line based on the result of the comparator.

[0007] An imaging device according to a third aspect of the present disclosure includes a plurality of pixels, a plurality of pixel control lines, a drive circuit electrically connected to one end of each pixel control line and driving the plurality of pixels via the plurality of pixel control lines, and a fault detection circuit electrically connected to the other end of each pixel control line. The fault detection circuit includes a first resistive voltage divider circuit, a second resistive voltage divider circuit, a comparator, and a determination unit. The first resistive voltage divider circuit is configured to divide a high voltage applied to a first pixel control line among the plurality of pixel control lines. The second resistive voltage divider circuit is configured to divide a low voltage applied to the first pixel control line. The comparator is capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage. The determination unit is capable of determining faults in the drive circuit and each pixel control line based on the result of the comparator.

[0008] An imaging device according to a fourth aspect of the present disclosure includes a plurality of pixels, a plurality of control lines, a control circuit connected to each of the control lines and controlling the control circuit via the plurality of control lines to process pixel signals output from the plurality of pixels, and a fault detection circuit electrically connected to each of the control lines. The fault detection circuit includes a first resistive voltage divider circuit, a second resistive voltage divider circuit, a comparator, and a determination unit. The first resistive voltage divider circuit is capable of dividing a high voltage applied to a first control line among the plurality of control lines. The second resistive voltage divider circuit is capable of dividing a low voltage applied to the first control line. The comparator is capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage. The determination unit is capable of determining faults in the control circuit and each of the control lines based on the result of the comparator.

[0009] A failure detection method according to a fifth aspect of the present disclosure is a method executed by a failure detection device electrically connected to one end of each pixel control line in an imaging device including a plurality of pixels, a plurality of pixel control lines, and a drive circuit electrically connected to the other end of each pixel control line and driving the plurality of pixels via the plurality of pixel control lines. This failure detection method includes the following four steps: (A1) dividing a high voltage applied to a first pixel control line among the plurality of pixel control lines; (A2) dividing a low voltage applied to the first pixel control line; (A3) comparing either a first voltage generated by a first resistive voltage divider circuit or a second voltage generated by a second resistive voltage divider circuit with a reference voltage; and (A4) determining a failure in the drive circuit and each pixel control line based on the comparison result.

[0010] A failure detection method according to a sixth aspect of the present disclosure is a method executed by a failure detection device electrically connected to each control line in an imaging device including a plurality of pixels, a plurality of control lines, and a control circuit electrically connected to each control line and controlling, via the plurality of control lines, a control circuit that processes pixel signals output from the plurality of pixels. This failure detection method includes the following four steps: (B1) dividing a high voltage applied to a first control line among the plurality of control lines; (B2) dividing a low voltage applied to the first control line; (B3) comparing either a first voltage generated by a first resistive voltage divider circuit or a second voltage generated by a second resistive voltage divider circuit with a reference voltage; and (B4) determining whether there is a failure in the control circuit and each control line based on the comparison result.

[0011] FIG. 1 is a diagram illustrating an example of a schematic configuration of a solid-state imaging device according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of a circuit configuration of a sensor pixel in FIG. 1. FIG. 3 is a diagram illustrating an example of a wiring layout of a pixel array unit in FIG. 1 and an example of a schematic configuration of a failure detection circuit in FIG. 1. FIG. 4 is a diagram illustrating an example of a schematic configuration of the failure detection circuit in FIG. 3. FIG. 5 is a diagram illustrating an example of an operation of the solid-state imaging device in FIG. 1. FIG. 6 is a diagram illustrating an example of an all-row batch transfer in FIG. 5. FIG. 7 is a diagram illustrating an example of a row-by-row readout operation in FIG. 5. FIG. 8 is a diagram illustrating an example of a failure detection target in the operation in FIG. 5. FIG. 9 is a diagram illustrating an example of failure detection during normal operation. FIG. 10 is a diagram illustrating an example of failure detection when a high-level abnormality occurs. FIG. 11 is a diagram illustrating an example of failure detection when a low-level abnormality occurs. FIG. 12 is a diagram illustrating a modified circuit configuration of the vertical drive circuit in FIG. 1. FIG. 13 is a diagram illustrating a modified schematic configuration of the failure detection circuit in FIG. 4. FIG. 14 is a diagram illustrating a modified schematic configuration of the failure detection circuit in FIG. 4. Fig. 15 is a diagram illustrating an example of a schematic configuration of a solid-state imaging device according to a second embodiment of the present disclosure. Fig. 16 is a diagram illustrating an example of a schematic configuration of a column signal processing circuit of Fig. 15. Fig. 17 is a diagram illustrating an example of a schematic configuration of a failure detection circuit of Fig. 16. Fig. 18 is a diagram illustrating a modified example of the schematic configuration of the failure detection circuit of Fig. 17. Fig. 19 is a diagram illustrating a modified example of the schematic configuration of the failure detection circuit of Fig. 17. Fig. 20 is a block diagram illustrating an example of a schematic configuration of a vehicle control system. Fig. 21 is an explanatory diagram illustrating an example of installation positions of an outside vehicle information detection unit and an imaging unit.

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. First embodiment (solid-state imaging device)...FIGS. 1 to 11 2. Modification of the first embodiment (solid-state imaging device)...FIGS. 12 to 14 3. Second embodiment (solid-state imaging device)...FIGS. 15 to 17 4. Modification of the second embodiment (solid-state imaging device)...FIGS. 18 and 19 5. Application example to a moving body...FIGS. 20 and 21

[0013] 1. First Embodiment [Configuration] A solid-state imaging device 1 according to a first embodiment of the present disclosure will be described. The solid-state imaging device 1 is, for example, a global shutter type image sensor formed of a CMOS (Complementary Metal Oxide Semiconductor) image sensor or the like. The solid-state imaging device 1 is capable of capturing an image by receiving light from a subject, photoelectrically converting the light, and generating an image signal. The solid-state imaging device 1 is capable of outputting pixel signals corresponding to the incident light.

[0014] The global shutter method is a method of performing global exposure in which exposure is basically started and ended simultaneously for all pixels. Here, "all pixels" refers to all pixels that appear in an image, excluding dummy pixels and the like. Furthermore, if the time difference and image distortion are small enough to be negligible, the global shutter method also includes a method in which global exposure is performed in units of multiple rows (e.g., several tens of rows) rather than simultaneously for all pixels, while the area in which global exposure is performed is moved. Furthermore, the global shutter method also includes a method in which global exposure is performed on pixels in a predetermined area, rather than on all pixels that appear in an image.

[0015] The image sensor is, for example, a back-illuminated image sensor in which a photoelectric conversion unit such as a photodiode that receives light from the subject and converts it into an electrical signal is provided between a light-receiving surface onto which light from the subject is incident and a wiring layer on which wiring connected to transistors that drive each pixel is provided. Note that the present disclosure is not limited to application to CMOS image sensors.

[0016] 1 illustrates an example of a schematic configuration of a solid-state imaging device 1 according to a first embodiment of the present disclosure. The solid-state imaging device 1 is a stacked chip in which a first chip 100 having a pixel array section 10 and a second chip 200 having a logic circuit 20 are stacked. The top surface of the first chip 100 serves as a light-receiving surface. In the solid-state imaging device 1, for example, the above-mentioned wiring layer is in contact with the top surface of the second chip 200.

[0017] The first chip 100 has a pixel array unit 10 in which a plurality of sensor pixels 11 that perform photoelectric conversion are arranged in a matrix. The sensor pixels 11 correspond to a specific example of a "pixel" according to an embodiment of the present disclosure. FIG. 2 shows an example of a circuit configuration of the sensor pixels 11 and a readout circuit 12 (described later). The plurality of sensor pixels 11 are arranged in a matrix on a semiconductor substrate (e.g., a silicon substrate). The readout circuit 12 is also arranged on the semiconductor substrate (e.g., a silicon substrate). Each readout circuit 12 is capable of outputting a pixel signal based on the charge output from the sensor pixel 11.

[0018] 2, for example, one readout circuit 12 is provided for each four sensor pixels 11. In this case, the four sensor pixels 11 share one readout circuit 12. Here, "shared" means that the outputs of the four sensor pixels 11 are input to a common readout circuit 12. The readout circuit 12 includes, for example, a reset transistor Tr6, a selection transistor Tr7, and an amplification transistor Tr5.

[0019] The first chip 100 has a plurality of pixel control lines extending in the row direction and a plurality of data output lines VSL extending in the column direction. The pixel control lines are wirings to which control signals for controlling the output of electric charges accumulated in the sensor pixels 11 are applied, and extend, for example, in the row direction. The data output lines VSL are wirings that output pixel signals output from each readout circuit 12 to the logic circuit 20, and extend, for example, in the column direction.

[0020] The second chip 200 has a logic circuit 20 for processing pixel signals on a semiconductor substrate (e.g., a silicon substrate). The logic circuit 20 has, for example, a vertical drive circuit 21, a column signal processing circuit 22, a horizontal drive circuit 23, a system control circuit 24, and a fault detection circuit 25, as shown in FIG. 1 . The logic circuit 20 (specifically, the horizontal drive circuit 23) is capable of outputting the output voltage of each sensor pixel 11 to the outside. The fault detection circuit 25 is capable of outputting the results of fault detection of the vertical drive circuit 21 and each pixel control line connected to the vertical drive circuit 21 to the outside.

[0021] 1, the first chip 100 and the second chip 200 are provided with TCVs (Through Chip Vias) 26, 27, and 28, and the first chip 100 and the second chip 200 are electrically connected to each other via the TCVs 26, 27, and 28. The TCV 26 is connected to a plurality of output terminals of a vertical drive circuit 21 provided in the second chip 200 and one end of a plurality of pixel control lines provided in the first chip 100. The TCV 27 is connected to a plurality of input terminals of a column signal processing circuit 22 provided in the second chip 200 and a plurality of data output lines VSL provided in the first chip 100. The TCV 28 is connected to a plurality of input terminals of a failure detection circuit 25 provided in the second chip 200 and the other end of a plurality of pixel control lines provided in the first chip 100. That is, one end of each of the pixel control lines is electrically connected to the vertical drive circuit 21 , and the other end of each of the pixel control lines is electrically connected to the failure detection circuit 25 .

[0022] The vertical drive circuit 21 is capable of, for example, sequentially selecting a plurality of sensor pixels 11 for each predetermined unit pixel row. A "predetermined unit pixel row" refers to a pixel row for which pixels can be selected using the same address. For example, when a plurality of sensor pixels 11 share one readout circuit 12, the layout of the plurality of sensor pixels 11 sharing the readout circuit 12 is assumed to be 2 pixel rows by n pixel columns (n ​​is an integer greater than or equal to 1). In this case, the "predetermined unit pixel row" refers to two pixel rows. Similarly, when the layout of the plurality of sensor pixels 11 sharing the readout circuit 12 is 4 pixel rows by n pixel columns (n ​​is an integer greater than or equal to 1), the "predetermined unit pixel row" refers to four pixel rows.

[0023] The column signal processing circuit 22 is capable of, for example, performing correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 11 in a row selected by the vertical drive circuit 21. For example, by performing CDS processing, the column signal processing circuit 22 is capable of extracting the signal level of the pixel signal and storing pixel data corresponding to the amount of light received by each sensor pixel 11. The column signal processing circuit 22 has, for example, a column signal processing section for each data output line VSL. The column signal processing section includes, for example, a single-slope A / D converter. The single-slope A / D converter includes, for example, a comparator and a counter circuit. The horizontal drive circuit 23, for example, sequentially outputs the pixel data stored in the column signal processing circuit 22 to the outside. The system control circuit 24 is capable of, for example, controlling the driving of each block (the vertical drive circuit 21, the column signal processing circuit 22, the horizontal drive circuit 23, and the fault detection circuit 25) in the logic circuit 20.

[0024] Each sensor pixel 11 has common components. For example, as shown in FIG. 2 , each sensor pixel 11 has a photodiode PD, transfer transistors Tr1, Tr2, and Tr3, charge holding units MEM1 and MEM2, a floating diffusion FD, and a discharge transistor Tr4. The transfer transistors Tr1, Tr2, and Tr3 and the discharge transistor Tr4 are, for example, NMOS (Metal Oxide Semiconductor) transistors.

[0025] The photodiode PD is capable of photoelectrically converting light incident through its light-receiving surface. The photodiode PD performs photoelectric conversion and generates an electric charge corresponding to the amount of light received. The photodiode PD is a PN junction photoelectric conversion element formed by an N-type semiconductor region and a P-type semiconductor region provided in a semiconductor substrate (e.g., a silicon substrate). The cathode of the photodiode PD is electrically connected to the source of the transfer transistor Tr1, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground GND).

[0026] The transfer transistor Tr1 is connected between the photodiode PD and the transfer transistor Tr2, and is capable of transferring charges accumulated in the photodiode PD to the transfer transistor Tr2 in response to a control signal applied to the gate electrode. The transfer transistor Tr1 is capable of transferring charges from the photodiode PD to the charge holding unit MEM1. The transfer transistor Tr1 has, for example, a vertical gate electrode. The drain of the transfer transistor Tr1 is electrically connected to the source of the transfer transistor Tr2, and the gate of the transfer transistor Tr1 is connected to a pixel control line TRY (for example, TRY0 or TRY1).

[0027] The transfer transistor Tr2 is connected between the transfer transistors Tr1 and Tr3, and controls the potential of the charge holding unit MEM1 in response to a control signal applied to its gate electrode. For example, when the transfer transistor Tr2 is turned on, the potential of the charge holding unit MEM becomes deeper, and when the transfer transistor Tr2 is turned off, the potential of the charge holding unit MEM becomes shallower. Then, for example, when the transfer transistor Tr1 is turned on, the charge stored in the charge holding unit MEM1 is transferred to the charge holding unit MEM2 via the transfer transistor Tr2. The drain of the transfer transistor Tr2 is electrically connected to the source of the transfer transistor Tr3, and the gate of the transfer transistor Tr2 is connected to a pixel control line TRX (e.g., TRX0, TRX1, TRX2, or TRX3).

[0028] The charge holding units MEM1 and MEM2 are regions that temporarily hold the charges accumulated in the photodiode PD in order to realize the global shutter function. The charge holding units MEM1 and MEM2 are capable of holding the charges transferred from the photodiode PD.

[0029] The transfer transistor Tr3 is connected between the transfer transistor Tr2 and the floating diffusion FD, and is capable of transferring the charges held in the charge holding unit MEM2 to the floating diffusion FD in response to a control signal applied to the gate electrode. For example, when the transfer transistor Tr2 is turned off and the transfer transistor Tr3 is turned on, the charges held in the charge holding unit MEM2 are transferred to the floating diffusion FD via the transfer transistors Tr2 and Tr3. The drain of the transfer transistor Tr3 is electrically connected to the floating diffusion FD, and the gate of the transfer transistor Tr3 is connected to a pixel control line TRG (e.g., TRG0, TRG1, TRG2, or TRG3).

[0030] The floating diffusion FD is a floating diffusion region that temporarily holds the charge output from the photodiode PD via the transfer transistor Tr3. The floating diffusion FD is connected to, for example, a reset transistor Tr6 and is also connected to a vertical signal line VSL via an amplification transistor Tr5 and a selection transistor Tr7.

[0031] The drain of the discharge transistor Tr4 is connected to the power supply line VDD, and the source is connected between the photodiode PD and the transfer transistor Tr1. The gate of the discharge transistor Tr4 is connected to the pixel control line OFG. The discharge transistor Tr4 initializes (resets) the photodiode PD in response to a control signal applied to the gate electrode. For example, when the discharge transistor Tr4 is turned on, the potential of the photodiode PD is reset to the potential level of the power supply line VDD. In other words, the photodiode PD is initialized.

[0032] The drain of the reset transistor Tr6 is connected to the power supply line VDD, and the source is connected to the floating diffusion FD. The gate of the reset transistor Tr6 is connected to a pixel control line RST. The reset transistor RST initializes (resets) each region from the charge holding unit MEM1 to the floating diffusion FD in response to a control signal applied to the gate electrode. For example, when the transfer transistor Tr3 and the reset transistor Tr6 are turned on, the potentials of the charge holding units MEM1 and MEM2 and the floating diffusion FD are reset to the potential level of the power supply line VDD. In other words, the charge holding units MEM1 and MEM2 and the floating diffusion FD are initialized.

[0033] The amplifier transistor Tr5 has a gate electrode connected to the floating diffusion FD and a drain connected to the power supply line VDD, and serves as an input part of a source follower circuit that reads out the charge obtained by photoelectric conversion in the photodiode PD. That is, the amplifier transistor AMP has a source connected to the vertical signal line VSL via the selection transistor SEL, and thereby forms a source follower circuit together with a constant current source connected to one end of the vertical signal line VSL.

[0034] The selection transistor Tr7 is connected between the source of the amplification transistor Tr5 and the vertical signal line VSL, and a control signal is supplied as a selection signal to the gate electrode of the selection transistor Tr7. The gate of the selection transistor Tr7 is connected to the pixel control line SEL. When the control signal is turned on, the selection transistor Tr7 becomes conductive, and the sensor pixel 11 connected to the selection transistor Tr7 becomes selected. When the sensor pixel 11 becomes selected, the pixel signal output from the amplification transistor Tr5 is read out to the column signal processing circuit 22 via the vertical signal line VSL.

[0035] Next, the wiring layout of the pixel array unit 10 will be described in more detail. Fig. 3 shows an example of the wiring layout of the pixel array unit 10. Fig. 3 illustrates pixel control lines OFG, TRY0, TRY1, TRX0, TRX1, TRX2, TRX3, TRG0, TRG1, TRG2, and TRG3 as pixel control lines connected to four sensor pixels 11 that share a floating diffusion FD. Fig. 3 also illustrates RST and SEL as pixel control lines connected to a readout circuit 12 shared by the four sensor pixels 11.

[0036] Next, the circuit configuration of the failure detection circuit 25 will be described with reference to Figures 3 and 4. Figure 4 shows an example of the circuit configuration of the failure detection circuit 25. As shown in Figures 3 and 4, the failure detection circuit 25 has, for example, a selector 25A, a comparison unit 25B, and a determination unit 25C.

[0037] One ends of a plurality of pixel control lines (OFG, TRY0, TRY1, TRX0, TRX1, TRX2, TRX3, TRG0, TRG1, TRG2, TRG3, RST, SEL) are connected to a plurality of input terminals of the selector 25A. One input terminal of the comparator 25B is connected to one output terminal of the selector 25A. The selector 25A can connect any one of the plurality of pixel control lines selected in accordance with a control signal ctl1 from the system control circuit 24 to the comparator 25B.

[0038] The comparison unit 25B includes, for example, a selector 251, a high-level resistive voltage dividing circuit 252, a low-level resistive voltage dividing circuit 253, a selector 254, and a comparator 255, as shown in FIG.

[0039] Of the two output terminals of the selector 251, one is connected to a high-level resistive voltage divider circuit 252, and the other is connected to a low-level resistive voltage divider circuit 253. The selector 251 is capable of connecting one of the two output terminals selected in accordance with a control signal ctl2 from the system control circuit 24 to its input terminal. When the high-level output terminal of the two output terminals of the selector 251 is selected by the selector 251, the voltage of the high-level output terminal is the voltage VH (high voltage) of the pixel control line selected by the selector 25A. When the low-level output terminal of the two output terminals of the selector 251 is selected by the selector 251, the voltage of the low-level output terminal is the voltage VL (low voltage) of the pixel control line selected by the selector 25A.

[0040] 4, the Hi-level resistive voltage divider circuit 252 is configured by two resistive elements R1 and R2 connected in series to one output terminal of the selector 251. A connection node between the resistive elements R1 and R2 is connected to one of the two input terminals of the selector 254. The end of the resistive element R2 that is not connected to the resistive element R1 is electrically connected to, for example, a reference potential line (e.g., ground GND).

[0041] 4, the Lo level resistive voltage dividing circuit 253 is configured by two resistive elements R3 and R4 connected in series to the other output terminal of the selector 251. The connection node between the resistive elements R3 and R4 is connected to the other of the two input terminals of the selector 254. The end of the resistive element R3 that is not connected to the resistive element R4 is electrically connected to the power supply line VDD, for example.

[0042] Of the two input terminals of the selector 254, one input terminal is connected to the connection node between the resistor elements R1 and R2, and the other input terminal is connected to the connection node between the resistor elements R3 and R4. One input terminal of the comparator 255 is connected to one output terminal of the selector 254. The selector 254 is capable of connecting one of the two input terminals selected in accordance with a control signal ctl3 from the system control circuit 24 to the output terminal. When the selector 254 selects the input terminal on the Hi level side of the two input terminals of the selector 254, the voltage of the output terminal of the selector 254 is VH×(R2 / (R1+R2)). When the selector 254 selects the output terminal on the Lo level side of the two output terminals of the selector 251, the voltage of the output terminal of the selector 254 is (VDD−VL)×(R4 / (R3+R4)).

[0043] An output terminal of the selector 254 is connected to one input terminal of the comparator 255, and a resistive voltage divider circuit is connected to the other input terminal of the comparator 255. The output voltage (voltage Vin) of the selector 254 is input to one input terminal of the comparator 255. The resistive voltage divider circuit connected to the other input terminal of the comparator 255 is composed of two resistive elements R5 and R6 connected in series between the power supply line VDD and a reference potential line (e.g., ground GND). The connection node between the resistive elements R5 and R6 is connected to the other input terminal of the comparator 255. A reference voltage Vref (=(VDD-V_GND)×(R6 / (R5+R6)) is input to the other input terminal of the comparator 255. V_GND indicates, for example, the potential of ground GND. The comparator 255 is capable of outputting a Hi-level voltage when the difference (Vin-Vref) between the voltage at one input terminal (voltage Vin) and the voltage at the other input terminal (reference voltage Vref) is 0 or positive. The comparator 255 is capable of outputting a Lo-level voltage when the difference (Vin-Vref) is negative.

[0044] The determination unit 25C is capable of determining whether there is a failure in the vertical drive circuit 21 and a plurality of pixel control lines connected to the vertical drive circuit 21, based on the output of the comparator 255. The determination unit 25C is configured to include, for example, a CPU (central processing unit).

[0045] The determination unit 25C is capable of determining that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the high level, for example, when the selector 254 selects the high-level input terminal and a high-level voltage is input from the comparator 255. The determination unit 25C is capable of determining that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the low level, for example, when the selector 254 selects the low-level input terminal and a high-level voltage is input from the comparator 255.

[0046] For example, when the selector 254 selects the input terminal on the Hi level side and a Lo level voltage is input from the comparator 255, the determination unit 25C is able to determine that at least one of the vertical drive circuit 21 and the pixel control line selected by the selector 25A is abnormal at the Hi level. For example, when the selector 254 selects the input terminal on the Lo level side and a Lo level voltage is input from the comparator 255, the determination unit 25C is able to determine that at least one of the vertical drive circuit 21 and the pixel control line selected by the selector 25A is abnormal at the Lo level.

[0047] [Operation] Fig. 5 shows an example of the operation of the solid-state imaging device 1. Fig. 6 shows an example of the all-row batch transfer in Fig. 5. Fig. 7 shows an example of the row-by-row readout operation in Fig. 5.

[0048] The solid-state imaging device 1 performs all-row batch transfer, row-by-row readout, and blanking in this order in 1F (one frame period), for example, as shown in Fig. 5. At this time, the solid-state imaging device 1 resets the charge holding units MEM1 and MEM2 and the floating diffusion FD in each sensor pixel 11, and then transfers charges from the photodiode PD to the charge holding units MEM1 and MEM2 in each sensor pixel 11, for example, as shown in Fig. 6.

[0049] 7, the solid-state imaging device 1 sequentially transfers charges accumulated in the charge holding units MEM1 and MEM2 of four sensor pixels 11 that share the floating diffusion FD to the floating diffusion FD. At this time, the solid-state imaging device 1 outputs the charges transferred to the floating diffusion FD to the data output line VSL every time the solid-state imaging device 1 transfers charges to the floating diffusion FD, for example, as shown in FIG. 7. Then, the solid-state imaging device 1 resets the floating diffusion FD before the next charge transfer, for example, as shown in FIG. 7.

[0050] The failure detection circuit 25 detects failures in the vertical drive circuit 21 and all pixel control lines, for example, during a period in which all-row batch transfer is being performed. For example, the failure detection circuit 25 divides all pixel control lines into multiple groups and detects failures in multiple pixel control lines for each group. For example, as shown in FIG. 8 , the failure detection circuit 25 divides all pixel control lines into three groups and detects failures in multiple pixel control lines L(1) to L(N / 3) belonging to the first group during a certain frame period. Then, for example, as shown in FIG. 8 , the failure detection circuit 25 detects failures in multiple pixel control lines L(N / 3+1) to L(2N / 3) belonging to the second group during the next frame period. Then, for example, as shown in FIG. 8 , the failure detection circuit 25 detects failures in multiple pixel control lines L(2N / 3+1) to L(N) belonging to the third group during the next frame period. It should be noted that G in FIG. 8 represents a period during which all-row batch transfer is being performed, R in FIG. 8 represents a period during which row-by-row readout operation is being performed, and B represents a blanking period.

[0051] For example, during the period when the row-by-row readout operation is being performed, the failure detection circuit 25 detects failures in the vertical drive circuit 21 and all pixel control lines. For example, as shown in FIG. 8 , the failure detection circuit 25 detects failures in the pixel control line selected by the row-by-row readout operation every time the pixel control line is selected by the row-by-row readout operation.

[0052] 9, when the selector 254 selects the input terminal on the Hi level side (DET_TRG0=VH) during the period when the all-row batch transfer is being performed, the determination unit 25C determines that it is the timing to detect the Hi level in the all-row batch transfer. At this time, when Vin-Vref is positive and a Hi level voltage is output from the comparator 255 (Cout=Hi), for example, as shown in FIG. 9, the determination unit 25C determines that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Hi level.

[0053] 9, when the input terminal on the Lo level side is selected by the selector 254 (DET_TRG0=VL) during the period when the all-row batch transfer is being performed, the determination unit 25C determines that it is the timing to detect the Lo level during the all-row batch transfer. At this time, when Vin-Vref is positive and a Hi level voltage is output from the comparator 255 (Cout=Hi), for example, as shown in FIG. 9, the determination unit 25C determines that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Lo level.

[0054] 9, when the input terminal on the Hi level side is selected by the selector 254 (DET_TRG0=VH) during the period when the row-by-row readout operation is being performed, the determination unit 25C determines that it is the timing to detect a Hi level in the row-by-row readout operation. At this time, when Vin-Vref is positive and a Hi level voltage is output from the comparator 255 (Cout=Hi), for example, as shown in FIG. 9, the determination unit 25C determines that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Hi level.

[0055] 9, when the input terminal on the Lo level side is selected by the selector 254 (DET_TRG0=VL) during the period when the row-by-row readout operation is being performed, the determination unit 25C determines that it is the timing to detect the Lo level in the row-by-row readout operation. At this time, when Vin-Vref is positive and a Hi level voltage is output from the comparator 255 (Cout=Hi), for example, as shown in FIG. 9, the determination unit 25C determines that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Lo level.

[0056] 10, when the selector 254 selects the input terminal on the Hi level side (DET_TRG0=VH) during the period when the all-row batch transfer is being performed, the determination unit 25C determines that it is the timing to detect the Hi level in the all-row batch transfer. At this time, when Vin-Vref is negative and the comparator 255 outputs a Lo level voltage (Cout=Lo), for example, as shown in FIG. 10, the determination unit 25C determines that at least one of the vertical drive circuit 21 and the pixel control line selected by the selector 25A is abnormal at the Hi level.

[0057] 10, for example, when the input terminal on the Lo level side is selected by the selector 254 (DET_TRG0=VL) during the period when the all-row batch transfer is being performed, the determination unit 25C determines that it is the timing to detect the Lo level in the all-row batch transfer. At this time, for example, as shown in FIG. 10, when Vin-Vref is positive and a Hi level voltage is output from the comparator 255 (Cout=Hi), the determination unit 25C determines that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Lo level.

[0058] 10, when the input terminal on the Hi level side is selected by the selector 254 (DET_TRG0=VH) during the period when the row-by-row readout operation is being performed, the determination unit 25C determines that it is the timing to detect a Hi level in the row-by-row readout operation. At this time, when Vin-Vref is negative and a Lo level voltage is output from the comparator 255 (Cout=Lo), for example, as shown in FIG. 10, the determination unit 25C determines that at least one of the vertical drive circuit 21 and the pixel control line selected by the selector 25A is abnormal at the Hi level.

[0059] 10, for example, when the input terminal on the Lo level side is selected by the selector 254 (DET_TRG0=VL) during the period when the row-by-row readout operation is being performed, the determination unit 25C determines that it is the timing to detect the Lo level in the row-by-row readout operation. At this time, for example, as shown in FIG. 10, when Vin-Vref is positive and a Hi level voltage is output from the comparator 255 (Cout=Hi), the determination unit 25C determines that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Lo level.

[0060] 11, for example, when the selector 254 selects the input terminal on the Hi level side (DET_TRG0=VH) during the period when the all-row batch transfer is being performed, the determination unit 25C determines that it is the timing to detect the Hi level in the all-row batch transfer. At this time, for example, as shown in FIG. 11, when Vin-Vref is positive and a Hi level voltage is output from the comparator 255 (Cout=Hi), the determination unit 25C determines that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Hi level.

[0061] 11, when the input terminal on the Lo level side is selected by the selector 254 (DET_TRG0=VL) during the period when the all-row batch transfer is being performed, the determination unit 25C determines that it is the timing to detect the Lo level in the all-row batch transfer. At this time, when Vin-Vref is negative and a Lo level voltage is output from the comparator 255 (Cout=Lo), for example, as shown in FIG. 11, the determination unit 25C determines that at least one of the vertical drive circuit 21 and the pixel control line selected by the selector 25A is abnormal at the Lo level.

[0062] 11, for example, when the selector 254 selects the input terminal on the Hi level side (DET_TRG0=VH) during the period when the row-by-row readout operation is being performed, the determination unit 25C determines that it is the timing to detect a Hi level in the row-by-row readout operation. At this time, for example, as shown in FIG. 9, when Vin-Vref is positive and a Hi level voltage is output from the comparator 255 (Cout=Hi), the determination unit 25C determines that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Hi level.

[0063] 11, when the input terminal on the Lo level side is selected by the selector 254 (DET_TRG0=VL) during the period when the row-by-row readout operation is being performed, the determination unit 25C determines that it is the timing to detect the Lo level in the row-by-row readout operation. At this time, when Vin-Vref is negative and a Lo level voltage is output from the comparator 255 (Cout=Lo), for example, as shown in FIG. 9, the determination unit 25C determines that at least one of the vertical drive circuit 21 and the pixel control line selected by the selector 25A is abnormal at the Lo level.

[0064] [Effects] Next, the effects of the solid-state imaging device 1 will be described.

[0065] In this embodiment, a failure detection device 25 is electrically connected to the other end of each pixel control line. A high voltage (VH) applied to a selected pixel control line is divided by a resistive voltage divider circuit 252, and a low voltage (VL) applied to a selected pixel control line is divided by a resistive voltage divider circuit 253. A comparator 255 compares a reference voltage Vref with either the voltage Vin generated by the resistive voltage divider circuit 252 or the voltage generated by the resistive voltage divider circuit 253. Then, the failure detection circuit 25 determines a failure of the vertical drive circuit 21 based on the result of the comparator 255. This allows high-level failure detection and low-level failure detection for the vertical drive circuit 21. Furthermore, high-level failure detection and low-level failure detection can also be performed for a selected pixel control line.

[0066] In this embodiment, the failure detection device 25 is provided with selectors 251 and 254. This allows either the voltage Vin generated by the resistive voltage divider circuit 252 or the voltage generated by the resistive voltage divider circuit 253 to be input to the comparator 255. This allows for Hi-level failure detection and Lo-level failure detection for the vertical drive circuit 21. Furthermore, Hi-level failure detection and Lo-level failure detection can also be performed for the selected pixel control line.

[0067] In this embodiment, a selector 25A is provided in the failure detection device 25. This makes it possible to select one pixel control line from among a plurality of pixel control lines when transferring all rows at once, thereby enabling failure detection for each pixel control line when transferring all rows at once.

[0068] 2. Modification of the First Embodiment Next, a modification of the first embodiment will be described.

[0069] [Modification 2-1] Fig. 12 shows a modification of the circuit configuration of the vertical drive circuit 21. In the first embodiment, the vertical drive circuit 21 may have, for example, a drive circuit 21a for transferring all rows at once and a drive circuit 21b for reading out data row by row, as shown in Fig. 12.

[0070] The drive circuit 21a has, for example, one driver DRa(k) for each pixel row 12(k) (1≦k≦N; N is the number of unit pixel rows in the pixel array section 10). In the drive circuit 21a, the drivers DRa(k) are simultaneously driven by a common control line. The drive circuit 21b has, for example, one driver DRb(k) for each pixel row 12(k). In the drive circuit 21b, the drivers DRb(k) are independently driven by a control line assigned to each driver DRb(k).

[0071] In this way, in this modification, separate drivers are provided for all-row batch transfer and row-by-row readout, which makes it possible to separate the drive capabilities of the drivers for all-row batch transfer and row-by-row readout.

[0072] [Variation 2-2] Fig. 13 shows a variation of the circuit configuration of the fault detection circuit 25. In the first embodiment and its variations, the resistive elements R5 and R6 may each be a variable resistor, as shown in Fig. 13, for example. The system control circuit 24 may be able to set the resistance values ​​of the resistive elements R5 and R6 to predetermined resistance values, for example, by inputting a control signal ctl4 that sets the resistance values ​​of the resistive elements R5 and R6.

[0073] Resistor element R5 can be changed to a resistance value, for example, 10% lower than its normal resistance value. Resistor element R6 can be changed to a resistance value, for example, 10% lower than its normal resistance value. For example, suppose the system control circuit 24 inputs a control signal to resistor element R5 to set the resistance value to a value, for example, 10% lower than its normal resistance value, and inputs a control signal to resistor element R6 to set the resistance value to its normal resistance value. In this case, the reference voltage Vref becomes a voltage value slightly higher than when both resistor elements R5 and R6 are at their normal resistance values. Furthermore, suppose the system control circuit 24 inputs a control signal to resistor element R5 to set the resistance value to its normal resistance value, and inputs a control signal to resistor element R6 to set the resistance value to a value, for example, 10% lower than its normal resistance value. In this case, the reference voltage Vref becomes a voltage value slightly lower than when both resistor elements R5 and R6 are at their normal resistance values.

[0074] In this way, in this modification, by using variable resistors for the resistance elements R5 and R6, it is possible to set the reference voltage Vref to a slightly higher or lower value, which makes it possible to detect slight fluctuations in the value of the voltage Vin, and therefore to detect whether there is a problem in at least one of the vertical drive circuit 21 and the pixel control line that causes slight fluctuations in the value of the voltage Vin.

[0075] Note that the failure detection circuit 25 may include a selector 256 and a resistor tap 257 instead of the resistor elements R5 and R6, as shown in FIG. 14 . The resistor tap 257 is a resistor tap in which multiple resistor elements are connected in series. Multiple input terminals of the selector 256 are connected to multiple wirings, one for each connection point between two resistor elements in the resistor tap 257. The output terminal of the selector 256 is connected to one input terminal of the comparator 255. In this case, the system control circuit 24 may input a control signal ctl4 to the selector 256 to cause the selector 256 to select one of the multiple input terminals. Even in this case, the reference voltage Vref can be set to a slightly higher or lower value. This allows for detecting slight fluctuations in the value of the voltage Vin, thereby making it possible to detect whether or not there is a defect in at least one of the vertical drive circuit 21 and the pixel control line that causes slight fluctuations in the value of the voltage Vin.

[0076] 3. Second Embodiment [Configuration] Next, a solid-state imaging device 2 according to a second embodiment of the present disclosure will be described. The solid-state imaging device 2 is, for example, a global shutter type image sensor formed of a CMOS image sensor or the like. The solid-state imaging device 2 is capable of capturing an image by receiving light from a subject, photoelectrically converting the light, and generating an image signal. The solid-state imaging device 2 is capable of outputting pixel signals corresponding to the incident light.

[0077] 15 illustrates an example of a schematic configuration of a solid-state imaging device 2 according to a second embodiment of the present disclosure. The solid-state imaging device 2 is a stacked chip in which a first chip 100 having a pixel array unit 10 and a second chip 300 having a logic circuit 30 are stacked. The top surface of the first chip 100 is a light-receiving surface. In this embodiment, the data output lines VSL are wiring that outputs pixel signals output from each readout circuit 12 to the logic circuit 30, and extend, for example, in the column direction.

[0078] The second chip 300 has a logic circuit 30 for processing pixel signals on a semiconductor substrate (e.g., a silicon substrate). The logic circuit 30 has, for example, a vertical drive circuit 21, a column signal processing circuit 22, a horizontal drive circuit 23, a system control circuit 24, and a fault detection circuit 29, as shown in FIG. 15 . The logic circuit 30 (specifically, the horizontal drive circuit 23) is capable of outputting an output voltage for each sensor pixel 11 to the outside. The fault detection circuit 29 is capable of outputting a fault detection result for the column signal processing circuit 22 and each control line connected to the column signal processing circuit 22 to the outside.

[0079] 15 , the first chip 100 and the second chip 300 are provided with TCVs 26 and 27, and the first chip 100 and the second chip 300 are electrically connected to each other via the TCVs 26 and 27. The TCV 26 is connected to a plurality of output terminals of the vertical drive circuit 21 provided on the second chip 300 and one end of a plurality of pixel control lines provided on the first chip 100. The TCV 27 is connected to a plurality of input terminals of the column signal processing circuit 22 provided on the second chip 300 and a plurality of data output lines VSL provided on the first chip 100.

[0080] 16, the column signal processing circuit 22 includes a DAC 221 and a column signal processing unit 22A for each data output line VSL. The column signal processing unit 22A includes, for example, a single-slope A / D converter. The column signal processing unit 22A includes, for example, a comparator 222, a counter 223, and a buffer 224.

[0081] The comparator 222 is capable of comparing the pixel signal obtained from the sensor pixel 11 via the data output line VSL with the ramp voltage supplied from the DAC 221, based on a comparison control signal supplied from the system control circuit 24. The comparator 222 is further capable of outputting the comparison result as binary data to the counter 223. The comparison control signal is input to the comparator 222 via a control line CTL1 connected to the system control circuit 24.

[0082] The counter 223 is capable of performing a counting operation based on a count control signal supplied from the system control circuit 24. The counter 223 is capable of performing a counting operation until the comparison result (binary data) is inverted, for example, and outputting a digital signal indicating the resulting count value to the buffer 224. The count control signal is input to the counter 223 via a control line CTL2 connected to the system control circuit 24.

[0083] The buffer 224 is used to control the output to the horizontal drive circuit 23, and includes, for example, a latch circuit, and is capable of outputting the digital signal input from the counter 223 to the horizontal drive circuit 23 based on a selection signal from the horizontal drive circuit 23.

[0084] The system control circuit 24 may be connected to, for example, control lines other than the above-mentioned control lines CTL1 and CTL2. If the column signal processing unit 22A has, for example, a selector connected to a plurality of data output lines VSL, the system control circuit 24 may be connected to a control line to which a selection signal for this selector is applied. Also, the system control circuit 24 may be connected to, for example, a control line to which a control signal for controlling the auto-zero of the comparator 222 is applied. In this way, if multiple control lines other than the above-mentioned control lines CTL1 and CTL2 are connected to the system control circuit 24, these control lines may be connected to the selector 29A in the same way as the above-mentioned control lines CTL1 and CTL2.

[0085] Next, the circuit configuration of the failure detection circuit 29 will be described with reference to Fig. 17. Fig. 17 shows an example of the circuit configuration of the failure detection circuit 29. As shown in Fig. 17, the failure detection circuit 29 includes, for example, a selector 29A, a comparison unit 29B, and a determination unit 29C.

[0086] One end of each of a plurality of control lines (CTL1, CTL2, etc.) is connected to a plurality of input terminals of the selector 29A. One input terminal of the comparator 29B is connected to one output terminal of the selector 29A. The selector 29A can connect any one of the plurality of control lines selected in accordance with a control signal ctl1 from the system control circuit 24 to the comparator 29B.

[0087] The comparison unit 29B has, for example, a selector 291, a resistance voltage dividing circuit 292 for a high level, a resistance voltage dividing circuit 293 for a low level, a selector 294, and a comparator 295, as shown in FIG.

[0088] Of the two output terminals of the selector 291, one is connected to a high-level resistive voltage divider circuit 292, and the other is connected to a low-level resistive voltage divider circuit 293. The selector 291 is capable of connecting one of the two output terminals selected in accordance with a control signal ctl2 from the system control circuit 24 to its input terminal. When the high-level output terminal of the two output terminals of the selector 291 is selected by the selector 291, the voltage of the high-level output terminal is the voltage VH of the control line selected by the selector 29A. When the low-level output terminal of the two output terminals of the selector 291 is selected by the selector 291, the voltage of the low-level output terminal is the voltage VL of the control line selected by the selector 29A.

[0089] 17, the Hi-level resistive voltage divider circuit 292 is configured by two resistive elements R1 and R2 connected in series to one output terminal of a selector 291. A connection node between the resistive elements R1 and R2 is connected to one of the two input terminals of a selector 294. The end of the resistive element R2 that is not connected to the resistive element R1 is electrically connected to, for example, a reference potential line (e.g., ground GND).

[0090] 17, the Lo level resistive voltage dividing circuit 293 is configured by two resistive elements R3 and R4 connected in series to the other output terminal of the selector 291. The connection node between the resistive elements R3 and R4 is connected to the other of the two input terminals of the selector 294. The end of the resistive element R3 that is not connected to the resistive element R4 is electrically connected to the power supply line VDD, for example.

[0091] Of the two input terminals of the selector 294, one input terminal is connected to the connection node between the resistor elements R1 and R2, and the other input terminal is connected to the connection node between the resistor elements R3 and R4. One input terminal of the comparator 295 is connected to one output terminal of the selector 294. The selector 294 can connect one of the two input terminals selected in accordance with a control signal ctl3 from the system control circuit 24 to the output terminal. When the selector 294 selects the input terminal on the Hi level side of the two input terminals of the selector 294, the voltage at the output terminal of the selector 294 is VH×(R2 / (R1+R2)). When the selector 294 selects the output terminal on the Lo level side of the two output terminals of the selector 291, the voltage at the output terminal of the selector 294 is (VDD−VL)×(R4 / (R3+R4)).

[0092] The output terminal of the selector 294 is connected to one input terminal of the comparator 295, and a resistive voltage divider circuit is connected to the other input terminal of the comparator 295. The output voltage (voltage Vin) of the selector 294 is input to one input terminal of the comparator 295. The resistive voltage divider circuit connected to the other input terminal of the comparator 295 is composed of two resistive elements R5 and R6 connected in series between the power supply line VDD and a reference potential line (e.g., ground GND). The connection node between the resistive elements R5 and R6 is connected to the other input terminal of the comparator 295. A reference voltage Vref (=(VDD-V_GND)×(R6 / (R5+R6)) is input to the other input terminal of the comparator 295. V_GND indicates, for example, the potential of ground GND. The comparator 295 is capable of outputting a Hi-level voltage when the difference (Vin-Vref) between the voltage at one input terminal (voltage Vin) and the voltage at the other input terminal (reference voltage Vref) is 0 or positive. The comparator 295 is capable of outputting a Lo-level voltage when the difference (Vin-Vref) is negative.

[0093] The determination unit 29C is capable of determining whether or not there is a failure in the system control circuit 24 and in a plurality of control lines (e.g., CTL1, CTL2) connected to the system control circuit 24, based on the output of the comparator 295. The determination unit 29C is configured to include, for example, a CPU.

[0094] For example, when the selector 294 selects the input terminal on the Hi level side and a Hi level voltage is input from the comparator 295, the determination unit 29C can determine that the system control circuit 24 and the control line selected by the selector 29A are normal at the Hi level. For example, when the selector 294 selects the input terminal on the Lo level side and a Hi level voltage is input from the comparator 295, the determination unit 29C can determine that the system control circuit 24 and the control line selected by the selector 29A are normal at the Lo level.

[0095] For example, when the selector 294 selects the input terminal on the Hi level side and a Lo level voltage is input from the comparator 295, the determination unit 29C can determine that at least one of the system control circuit 24 and the control line selected by the selector 29A is abnormal at the Hi level. For example, when the selector 294 selects the input terminal on the Lo level side and a Lo level voltage is input from the comparator 295, the determination unit 29C can determine that at least one of the system control circuit 24 and the control line selected by the selector 29A is abnormal at the Lo level.

[0096] The determination unit 29C has the same functions as the determination unit 25C in the above embodiment. The operation of the solid-state imaging device 2 is the same as the operation of the solid-state imaging device 1 in the above embodiment, except for the fact that the target of failure detection is different.

[0097] [Effects] Next, the effects of the solid-state imaging device 2 will be described.

[0098] In this embodiment, a fault detection device 29 is electrically connected to each control line. A high voltage (VH) applied to a selected control line is divided by a resistive voltage divider circuit 292, and a low voltage (VL) applied to a selected control line is divided by a resistive voltage divider circuit 293. A comparator 295 compares a reference voltage Vref with either the voltage Vin generated by the resistive voltage divider circuit 292 or the voltage generated by the resistive voltage divider circuit 293. Then, based on the result of the comparator 295, the fault detection circuit 29 determines whether or not there is a fault in the system control circuit 24 and in the plurality of control lines connected to the system control circuit 24. This allows high-level fault detection and low-level fault detection to be performed for the system control circuit 24. Furthermore, high-level fault detection and low-level fault detection can be performed for the selected control line.

[0099] In this embodiment, the failure detection device 29 is provided with selectors 291 and 294. This allows either the voltage Vin generated by the resistive voltage divider circuit 292 or the voltage generated by the resistive voltage divider circuit 293 to be input to the comparator 295. This allows for Hi-level failure detection and Lo-level failure detection for the system control circuit 24. Furthermore, Hi-level failure detection and Lo-level failure detection can also be performed for the selected control line.

[0100] In this embodiment, a selector 29A is provided in the failure detection device 29. This makes it possible to select one pixel control line from among a plurality of control lines when all the control lines are used simultaneously, and therefore makes it possible to perform failure detection for each control line when all the control lines are used simultaneously.

[0101] 4. Modification of the Second Embodiment Next, a modification of the second embodiment will be described.

[0102] [Variation 4-1] Fig. 18 shows a variation of the circuit configuration of the fault detection circuit 29. In the second embodiment, the resistive elements R5 and R6 may each be a variable resistor, as shown in Fig. 18. The system control circuit 24 may, for example, input a control signal that sets the resistance value of the resistive elements R5 and R6, thereby making it possible to set the resistance values ​​of the resistive elements R5 and R6 to predetermined resistance values.

[0103] Resistor element R5 can be changed to a resistance value, for example, 10% lower than its normal resistance value. Resistor element R6 can be changed to a resistance value, for example, 10% lower than its normal resistance value. For example, suppose the system control circuit 24 inputs a control signal to resistor element R5 to set the resistance value to a value, for example, 10% lower than its normal resistance value, and inputs a control signal to resistor element R6 to set the resistance value to its normal resistance value. In this case, the reference voltage Vref becomes a voltage value slightly higher than when both resistor elements R5 and R6 are at their normal resistance values. Furthermore, suppose the system control circuit 24 inputs a control signal to resistor element R5 to set the resistance value to its normal resistance value, and inputs a control signal to resistor element R6 to set the resistance value to a value, for example, 10% lower than its normal resistance value. In this case, the reference voltage Vref becomes a voltage value slightly lower than when both resistor elements R5 and R6 are at their normal resistance values.

[0104] In this way, in this modification, by using variable resistors for the resistance elements R5 and R6, it is possible to set the reference voltage Vref to a slightly higher or lower value, which makes it possible to detect slight fluctuations in the value of the voltage Vin, and therefore to detect whether there is a problem in at least one of the system control circuit 24 and the control line that is causing slight fluctuations in the value of the voltage Vin.

[0105] Note that the failure detection circuit 25 may include a selector 296 and a resistor tap 297 instead of the resistor elements R5 and R6, as shown in FIG. 19 . The resistor tap 297 is a resistor tap in which multiple resistor elements are connected in series. Multiple input terminals of the selector 296 are connected to multiple wirings, one for each connection point between two resistor elements in the resistor tap 297. The output terminal of the selector 296 is connected to one input terminal of the comparator 295. In this case, the system control circuit 24 may input a control signal ctl4 to the selector 296 to cause the selector 296 to select one of the multiple input terminals. Even in this case, the reference voltage Vref can be set to a slightly higher or lower value. This allows for detecting slight fluctuations in the value of the voltage Vin, thereby making it possible to detect whether or not there is a defect in at least one of the vertical drive circuit 21 and the pixel control line that causes a slight fluctuation in the value of the voltage Vin.

[0106] 5. Application Examples to Mobile Bodies The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, or agricultural machinery (tractor).

[0107] 20 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010. In the example shown in FIG. 20 , the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside-vehicle information detection unit 7400, an inside-vehicle information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these multiple control units may be an in-vehicle communication network conforming to any standard, such as a Controller Area Network (CAN), a Local Interconnect Network (LIN), a Local Area Network (LAN), or FlexRay (registered trademark).

[0108] Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a memory unit that stores the programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit includes a network I / F for communicating with other control units via a communication network 7010, and a communication I / F for communicating with devices or sensors inside and outside the vehicle via wired or wireless communication. Figure 20 illustrates the functional configuration of the integrated control unit 7600, including a microcomputer 7610, a general-purpose communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, an audio / video output unit 7670, an in-vehicle network I / F 7680, and a memory unit 7690. The other control units also include a microcomputer, a communication I / F, a memory unit, and the like.

[0109] The drivetrain control unit 7100 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 7100 functions as a control device for a drive force generating device for generating drive force for the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device for an ABS (Antilock Brake System) or an ESC (Electronic Stability Control), etc.

[0110] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes at least one of a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor that detects the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine rotation speed, the rotation speed of the wheels, etc. The drivetrain control unit 7100 performs arithmetic processing using signals input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, etc.

[0111] The body system control unit 7200 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 7200. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0112] The battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the drive motor, in accordance with various programs. For example, information such as battery temperature, battery output voltage, or remaining battery capacity is input to the battery control unit 7300 from a battery device equipped with the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals, and controls the temperature regulation of the secondary battery 7310 or a cooling device or the like equipped in the battery device.

[0113] The outside vehicle information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000. For example, at least one of an imaging unit 7410 and an outside vehicle information detection unit 7420 is connected to the outside vehicle information detection unit 7400. The imaging unit 7410 includes at least one of a time-of-flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside vehicle information detection unit 7420 includes at least one of an environmental sensor for detecting the current weather or climate, or a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000.

[0114] The environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects fog, a sunshine sensor that detects the degree of sunshine, and a snow sensor that detects snowfall. The surrounding information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. The imaging unit 7410 and the outside vehicle information detection unit 7420 may each be provided as an independent sensor or device, or may be provided as a device in which multiple sensors or devices are integrated.

[0115] 21 shows an example of the installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are provided, for example, at least one of the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 7900. The imaging unit 7910 provided on the front nose and the imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 provided on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0116] 21 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, and 7916. Imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose, imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided on the side mirrors, respectively, and imaging range d indicates the imaging range of the imaging unit 7916 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.

[0117] The outside vehicle information detection units 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, corners, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, ultrasonic sensors or radar devices. The outside vehicle information detection units 7920, 7926, and 7930 provided on the front nose, rear bumper, back door, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, LIDAR devices. These outside vehicle information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, etc.

[0118] Returning to FIG. 20 , the explanation will be continued. The outside-vehicle information detection unit 7400 causes the imaging unit 7410 to capture an image outside the vehicle and receives the captured image data. The outside-vehicle information detection unit 7400 also receives detection information from the connected outside-vehicle information detection unit 7420. If the outside-vehicle information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. Based on the received information, the outside-vehicle information detection unit 7400 may perform object detection processing or distance detection processing for people, vehicles, obstacles, signs, text on the road, etc. Based on the received information, the outside-vehicle information detection unit 7400 may also perform environment recognition processing for recognizing rainfall, fog, road conditions, etc. Based on the received information, the outside-vehicle information detection unit 7400 may also calculate the distance to an object outside the vehicle.

[0119] The outside vehicle information detection unit 7400 may also perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, or characters on the road surface based on the received image data. The outside vehicle information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and may also generate an overhead image or a panoramic image by combining image data captured by different image capturing units 7410. The outside vehicle information detection unit 7400 may also perform viewpoint conversion processing using image data captured by different image capturing units 7410.

[0120] The interior information detection unit 7500 detects information inside the vehicle. A driver state detection unit 7510 that detects the driver's state is connected to the interior information detection unit 7500, for example. The driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sound from within the vehicle cabin. The biosensor is provided, for example, on the seat or steering wheel, and detects the biometric information of a passenger sitting in the seat or the driver gripping the steering wheel. The interior information detection unit 7500 may calculate the driver's level of fatigue or concentration based on the detection information input from the driver state detection unit 7510, or may determine whether the driver is dozing off. The interior information detection unit 7500 may perform processing such as noise canceling on the collected audio signal.

[0121] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 may be implemented by a device that can be operated by a passenger, such as a touch panel, a button, a microphone, a switch, or a lever. Data obtained by voice recognition of a voice input through a microphone may be input to the integrated control unit 7600. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or a personal digital assistant (PDA) that can operate the vehicle control system 7000. The input unit 7800 may be, for example, a camera, in which case the passenger can input information using gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by the passenger using the input unit 7800 and outputs the input signal to the integrated control unit 7600. Passengers and the like operate this input unit 7800 to input various data to the vehicle control system 7000 and to instruct processing operations.

[0122] The storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, etc. The storage unit 7690 may also be realized by a magnetic storage device such as an HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

[0123] The general-purpose communication I / F 7620 is a general-purpose communication I / F that mediates communication with various devices present in the external environment 7750. The general-purpose communication I / F 7620 may implement a cellular communication protocol such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (Long Term Evolution), or LTE-Advanced (LTE-A), or other wireless communication protocols such as a wireless LAN (also referred to as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication I / F 7620 may connect to a device (e.g., an application server or a control server) present on an external network (e.g., the Internet, a cloud network, or an operator-specific network) via, for example, a base station or an access point. In addition, the general-purpose communication I / F 7620 may connect to a terminal located near the vehicle (e.g., a terminal of a driver, pedestrian, or store, or an MTC (Machine Type Communication) terminal) using, for example, P2P (Peer To Peer) technology.

[0124] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol designed for use in vehicles. The dedicated communication I / F 7630 may implement a standard protocol such as WAVE (Wireless Access in Vehicle Environment), which is a combination of a lower layer IEEE 802.11p and an upper layer IEEE 1609, DSRC (Dedicated Short Range Communications), or a cellular communication protocol. The dedicated communication I / F 7630 typically performs V2X communication, which is a concept including one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0125] The positioning unit 7640 performs positioning by receiving, for example, GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites), and generates position information including the latitude, longitude, and altitude of the vehicle. Note that the positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0126] The beacon receiving unit 7650 receives, for example, radio waves or electromagnetic waves transmitted from radio stations or the like installed on the road, and acquires information such as the current location, congestion, road closures, required travel time, etc. The function of the beacon receiving unit 7650 may be included in the dedicated communication I / F 7630 described above.

[0127] The in-vehicle device I / F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 may establish wireless connections using wireless communication protocols such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB). Furthermore, the in-vehicle device I / F 7660 may establish a wired connection such as USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface), or MHL (Mobile High-Definition Link) via a connection terminal (and a cable, if necessary) not shown. The in-vehicle device 7760 may include, for example, at least one of a mobile device or a wearable device owned by a passenger, or an information device carried into or attached to the vehicle. The in-vehicle device 7760 may also include a navigation device that searches for a route to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0128] The in-vehicle network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals in accordance with a predetermined protocol supported by the communication network 7010.

[0129] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 in accordance with various programs based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the acquired information inside and outside the vehicle, and output control commands to the drivetrain control unit 7100. For example, the microcomputer 7610 may perform cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc. In addition, the microcomputer 7610 may perform cooperative control for the purpose of autonomous driving, in which the vehicle travels autonomously without relying on driver operation, by controlling a driving force generating device, a steering mechanism, a braking device, etc. based on information acquired about the vehicle's surroundings.

[0130] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people, and create local map information including information about the vicinity of the vehicle's current location, based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. Furthermore, the microcomputer 7610 may predict dangers, such as a vehicle collision, the approach of a pedestrian, or entry into a closed road, based on the acquired information, and generate a warning signal. The warning signal may be, for example, a signal for generating a warning sound or turning on a warning lamp.

[0131] The audio / image output unit 7670 transmits at least one audio and / or image output signal to an output device capable of visually or audibly notifying the vehicle occupants or the outside of the vehicle of information. In the example of FIG. 20 , an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as examples of the output devices. The display unit 7720 may include, for example, at least one of an on-board display and a head-up display. The display unit 7720 may have an AR (Augmented Reality) display function. The output device may also be other devices, such as headphones, a wearable device such as an eyeglass-type display worn by the occupant, a projector, or a lamp. When the output device is a display device, the display device visually displays results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats, such as text, images, tables, and graphs. When the output device is an audio output device, the audio output device converts audio signals, such as reproduced audio data or acoustic data, into analog signals and audibly outputs the analog signals.

[0132] In the example shown in FIG. 20 , at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include another control unit not shown. In addition, in the above description, some or all of the functions performed by one of the control units may be assigned to another control unit. In other words, as long as information is transmitted and received via the communication network 7010, predetermined arithmetic processing may be performed by one of the control units. Similarly, a sensor or device connected to one of the control units may be connected to another control unit, and multiple control units may transmit and receive detection information to each other via the communication network 7010.

[0133] The present disclosure has been described above by way of embodiments, their modifications, and application examples, but the present disclosure is not limited to the above embodiments, etc., and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

[0134] The present disclosure may also be configured as follows: (1) In an imaging device including a plurality of pixels, a plurality of pixel control lines, and a drive circuit electrically connected to one end of each of the pixel control lines and configured to drive the plurality of pixels via the plurality of pixel control lines, a failure detection device electrically connected to the other end of each of the pixel control lines, the failure detection device comprising: a first resistive voltage divider circuit capable of dividing a high voltage applied to a first pixel control line of the plurality of pixel control lines, a second resistive voltage divider circuit capable of dividing a low voltage applied to the first pixel control line, a comparator capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage, and a determination unit capable of determining a failure in the drive circuit and each of the pixel control lines based on a result of the comparator. (2) The failure detection device according to (1), further comprising: a first selector having two input terminals electrically connected to the first resistive voltage divider circuit and the second resistive voltage divider circuit and one output terminal electrically connected to one input terminal of the comparator; and a second selector having one input terminal electrically connected to the first pixel control line and two output terminals electrically connected to the first resistive voltage divider circuit and the second resistive voltage divider circuit. (3) The failure detection device according to (2), further comprising: a third selector having a plurality of input terminals electrically connected to the other terminals of the plurality of pixel control lines and one output terminal electrically connected to the input terminal of the second selector. (4) The failure detection device according to any one of (1) to (3), further comprising: a third resistive voltage divider circuit capable of generating the reference voltage, the third resistive voltage divider circuit including a plurality of variable resistors connected in series.(5) In an imaging device having a plurality of pixels, a plurality of control lines, and a control circuit connected to each of the control lines and controlling a control circuit via the plurality of control lines to process pixel signals output from the plurality of pixels, the failure detection device is electrically connected to each of the control lines, and comprises: a first resistive voltage divider circuit capable of dividing a high voltage applied to a first control line of the plurality of control lines; a second resistive voltage divider circuit capable of dividing a low voltage applied to the first control line; a comparator capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and a determination unit capable of determining a failure in the control circuit and each of the control lines based on the result of the comparator. (6) The fault detection device according to (5), further comprising: a first selector having two input terminals electrically connected to the first resistive voltage divider circuit and the second resistive voltage divider circuit and one output terminal electrically connected to one input terminal of the comparator; and a second selector having one input terminal electrically connected to the first control line and two output terminals electrically connected to the first resistive voltage divider circuit and the second resistive voltage divider circuit. (7) The fault detection device according to (6), further comprising: a third selector having a plurality of input terminals electrically connected to the other ends of the plurality of control lines and one output terminal electrically connected to the input terminal of the second selector. (8) The fault detection device according to any one of (5) to (7), further comprising: a third resistive voltage divider circuit capable of generating the reference voltage, the third resistive voltage divider circuit including a plurality of variable resistors connected in series.(9) An imaging device comprising: a plurality of pixels; a plurality of pixel control lines; a drive circuit electrically connected to one end of each of the pixel control lines and driving the plurality of pixels via the plurality of pixel control lines; and a fault detection circuit electrically connected to the other end of each of the pixel control lines, wherein the fault detection circuit comprises: a first resistive voltage divider circuit capable of dividing a high voltage applied to a first pixel control line among the plurality of pixel control lines; a second resistive voltage divider circuit capable of dividing a low voltage applied to the first pixel control line; a comparator capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and a determination unit capable of determining a fault in the drive circuit and each of the pixel control lines based on a result of the comparator. (10) An imaging device comprising: a plurality of pixels; a plurality of control lines; a control circuit connected to each of the control lines and controlling, via the plurality of control lines, a control circuit that processes pixel signals output from the plurality of pixels; and a fault detection circuit electrically connected to each of the control lines, wherein the fault detection circuit has: a first resistive voltage divider circuit capable of dividing a high voltage applied to a first control line of the plurality of control lines; a second resistive voltage divider circuit capable of dividing a low voltage applied to the first control line; a comparator capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and a determination unit capable of determining a fault in the control circuit and each of the control lines based on a result of the comparator.(11) A failure detection method for an imaging device including a plurality of pixels, a plurality of pixel control lines, and a drive circuit electrically connected to one end of each of the pixel control lines and driving the plurality of pixels via the plurality of pixel control lines, the failure detection method being executed by a failure detection device electrically connected to the other end of each of the pixel control lines, the failure detection method including: dividing a high voltage applied to a first pixel control line among the plurality of pixel control lines; dividing a low voltage applied to the first pixel control line; comparing one of a first voltage generated by the first resistive voltage divider circuit and a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and determining whether there is a failure in the drive circuit and each of the pixel control lines based on a comparison result. (12) A failure detection method for an imaging device including a plurality of pixels, a plurality of control lines, and a control circuit connected to each of the control lines and controlling a control circuit via the control lines to process pixel signals output from the plurality of pixels, the failure detection method being executed by a failure detection device electrically connected to each of the control lines, the failure detection device comprising: dividing a high voltage applied to a first control line among the plurality of control lines; dividing a low voltage applied to the first control line; comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and determining whether there is a failure in the control circuit and each of the control lines based on a comparison result.

[0135] This application claims priority based on Japanese Patent Application No. 2023-106350, filed on June 28, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0136] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. In an imaging device having a plurality of pixels, a plurality of pixel control lines, and a drive circuit electrically connected to one end of each of the pixel control lines and driving the plurality of pixels via the plurality of pixel control lines, a failure detection device electrically connected to the other end of each of the pixel control lines, comprising: a first resistive voltage divider circuit capable of dividing a Hi voltage applied to a first pixel control line of the plurality of pixel control lines; a second resistive voltage divider circuit capable of dividing a Lo voltage applied to the first pixel control line; a comparator capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and a judgment unit capable of making a failure judgment of the drive circuit and each of the pixel control lines based on a result of the comparator.

2. The fault detection device according to claim 1, further comprising: a first selector having two input terminals electrically connected to the first resistive voltage divider circuit and the second resistive voltage divider circuit and one output terminal electrically connected to one input terminal of the comparator; and a second selector having one input terminal electrically connected to the first pixel control line and two output terminals electrically connected to the first resistive voltage divider circuit and the second resistive voltage divider circuit.

3. The fault detection device according to claim 2, further comprising a third selector having a plurality of input terminals electrically connected to the other ends of the plurality of pixel control lines and one output terminal electrically connected to the input terminal of the second selector.

4. The fault detection device according to claim 1, further comprising a third resistive voltage divider circuit capable of generating the reference voltage, the third resistive voltage divider circuit including a plurality of variable resistors connected in series.

5. A failure detection device electrically connected to each of the control lines in an imaging device comprising a plurality of pixels, a plurality of control lines, and a control circuit connected to each of the control lines and controlling a control circuit via the plurality of control lines for processing pixel signals output from the plurality of pixels, the failure detection device comprising: a first resistive voltage divider circuit capable of dividing a Hi voltage applied to a first control line of the plurality of control lines; a second resistive voltage divider circuit capable of dividing a Lo voltage applied to the first control line; a comparator capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and a judgment unit capable of making a failure judgment of the control circuit and each of the control lines based on a result of the comparator.

6. The fault detection device according to claim 5, further comprising: a first selector having two input terminals electrically connected to said first resistive voltage divider circuit and said second resistive voltage divider circuit and one output terminal electrically connected to one input terminal of said comparator; and a second selector having one input terminal electrically connected to said first control line and two output terminals electrically connected to said first resistive voltage divider circuit and said second resistive voltage divider circuit.

7. The fault detection device according to claim 6, further comprising a third selector having a plurality of input terminals electrically connected to the other ends of the plurality of control lines and having one output terminal electrically connected to the input terminal of the second selector.

8. The fault detection device according to claim 5, further comprising a third resistive voltage divider circuit capable of generating the reference voltage, the third resistive voltage divider circuit including a plurality of variable resistors connected in series.

9. An imaging device comprising: a plurality of pixels; a plurality of pixel control lines; a drive circuit electrically connected to one end of each of the pixel control lines and driving the plurality of pixels via the plurality of pixel control lines; and a fault detection circuit electrically connected to the other end of each of the pixel control lines, wherein the fault detection circuit has: a first resistive voltage divider circuit capable of dividing a Hi voltage applied to a first pixel control line of the plurality of pixel control lines; a second resistive voltage divider circuit capable of dividing a Lo voltage applied to the first pixel control line; a comparator capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and a determination unit capable of determining a fault in the drive circuit and each of the pixel control lines based on a result of the comparator.

10. An imaging device comprising: a plurality of pixels; a plurality of control lines; a control circuit connected to each of the control lines, the control circuit controlling, via the plurality of control lines, a control circuit processing pixel signals output from the plurality of pixels; and a fault detection circuit electrically connected to each of the control lines, wherein the fault detection circuit has: a first resistive voltage divider circuit capable of dividing a Hi voltage applied to a first control line of the plurality of control lines; a second resistive voltage divider circuit capable of dividing a Lo voltage applied to the first control line; a comparator capable of comparing either one of a first voltage generated by the first resistive voltage divider circuit and a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and a judgment unit capable of making a fault judgment of the control circuit and each of the control lines based on a result of the comparator.

11. A failure detection method for an imaging device comprising a plurality of pixels, a plurality of pixel control lines, and a drive circuit electrically connected to one end of each of the pixel control lines and driving the plurality of pixels via the plurality of pixel control lines, the failure detection method being executed by a failure detection device electrically connected to the other end of each of the pixel control lines, the failure detection method comprising: dividing a high voltage applied to a first pixel control line of the plurality of pixel control lines; dividing a low voltage applied to the first pixel control line; comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and determining whether or not there is a failure in the drive circuit and each of the pixel control lines based on a comparison result.

12. A failure detection method for an imaging device having a plurality of pixels, a plurality of control lines, and a control circuit connected to each of the control lines, the control circuit processing pixel signals output from the plurality of pixels, the failure detection method being executed by a failure detection device electrically connected to each of the control lines, the failure detection device comprising: dividing a high voltage applied to a first control line among the plurality of control lines; dividing a low voltage applied to the first control line; comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and making a failure determination for the control circuit and each of the control lines based on a comparison result.

Images